* [PATCH 0/2] OpenRISC support for virt platform with PCI
@ 2022-07-09 21:15 ` Stafford Horne
0 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-09 21:15 UTC (permalink / raw)
To: LKML; +Cc: Openrisc
Hello,
This is a set of kernel patches which I have been using to support the new QEMU
virt platform [1]. The virt platform supports PCI hence I have a patch here to
add PCI support to OpenRISC.
A defconfig is also included which turns on drivers supported devices include
virt network cards and the goldfish RTC.
[1] https://github.com/stffrdhrn/qemu/tree/or1k-virt-2
Stafford Horne (2):
openrisc: Add pci bus support
openrisc: Add virt defconfig
arch/openrisc/Kconfig | 7 +-
arch/openrisc/configs/virt_defconfig | 108 +++++++++++++++++++++++++++
arch/openrisc/include/asm/Kbuild | 1 +
arch/openrisc/include/asm/io.h | 4 +-
arch/openrisc/include/asm/pci.h | 36 +++++++++
5 files changed, 151 insertions(+), 5 deletions(-)
create mode 100644 arch/openrisc/configs/virt_defconfig
create mode 100644 arch/openrisc/include/asm/pci.h
--
2.36.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/2] OpenRISC support for virt platform with PCI
@ 2022-07-09 21:15 ` Stafford Horne
0 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-09 21:15 UTC (permalink / raw)
To: LKML; +Cc: Openrisc, Stafford Horne
Hello,
This is a set of kernel patches which I have been using to support the new QEMU
virt platform [1]. The virt platform supports PCI hence I have a patch here to
add PCI support to OpenRISC.
A defconfig is also included which turns on drivers supported devices include
virt network cards and the goldfish RTC.
[1] https://github.com/stffrdhrn/qemu/tree/or1k-virt-2
Stafford Horne (2):
openrisc: Add pci bus support
openrisc: Add virt defconfig
arch/openrisc/Kconfig | 7 +-
arch/openrisc/configs/virt_defconfig | 108 +++++++++++++++++++++++++++
arch/openrisc/include/asm/Kbuild | 1 +
arch/openrisc/include/asm/io.h | 4 +-
arch/openrisc/include/asm/pci.h | 36 +++++++++
5 files changed, 151 insertions(+), 5 deletions(-)
create mode 100644 arch/openrisc/configs/virt_defconfig
create mode 100644 arch/openrisc/include/asm/pci.h
--
2.36.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/2] openrisc: Add pci bus support
2022-07-09 21:15 ` Stafford Horne
@ 2022-07-09 21:15 ` Stafford Horne
-1 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-09 21:15 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson,
Peter Zijlstra, Palmer Dabbelt, Arnd Bergmann
This patch adds required definitions to allow for PCI buses on OpenRISC.
This is being in the QEMU virt platform.
OpenRISC does not have IO ports so this defines PCI IO to be allowed in
any range. Keeping PIO_RESERVED defined as 0 allows OpenRISC to use
MMIO for all IO.
Also, since commit 66bcd06099bb ("parport_pc: Also enable driver for PCI
systems") all platforms that support PCI also need to support parallel
port. We add a generic header to support parallel port drivers.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 7 ++++---
arch/openrisc/include/asm/Kbuild | 1 +
arch/openrisc/include/asm/io.h | 4 ++--
arch/openrisc/include/asm/pci.h | 36 ++++++++++++++++++++++++++++++++
4 files changed, 43 insertions(+), 5 deletions(-)
create mode 100644 arch/openrisc/include/asm/pci.h
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index e814df4c483c..327241988819 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -21,7 +21,9 @@ config OPENRISC
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_IOMAP
+ select GENERIC_PCI_IOMAP
select GENERIC_CPU_DEVICES
+ select HAVE_PCI
select HAVE_UID16
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS_BROADCAST
@@ -32,6 +34,8 @@ config OPENRISC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select ARCH_USE_QUEUED_RWLOCKS
select OMPIC if SMP
+ select PCI_DOMAINS_GENERIC if PCI
+ select PCI_MSI if PCI
select ARCH_WANT_FRAME_POINTERS
select GENERIC_IRQ_MULTI_HANDLER
select MMU_GATHER_NO_RANGE if MMU
@@ -46,9 +50,6 @@ config MMU
config GENERIC_HWEIGHT
def_bool y
-config NO_IOPORT_MAP
- def_bool y
-
# For now, use generic checksum functions
#These can be reimplemented in assembly later if so inclined
config GENERIC_CSUM
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 3386b9c1c073..c8c99b554ca4 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
generic-y += extable.h
generic-y += kvm_para.h
+generic-y += parport.h
generic-y += spinlock_types.h
generic-y += spinlock.h
generic-y += qrwlock_types.h
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index c298061c70a7..1595aa69d96d 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -17,9 +17,9 @@
#include <linux/types.h>
/*
- * PCI: can we really do 0 here if we have no port IO?
+ * PCI: All address space can be used for IO
*/
-#define IO_SPACE_LIMIT 0
+#define IO_SPACE_LIMIT ~(0UL)
/* OpenRISC has no port IO */
#define HAVE_ARCH_PIO_SIZE 1
diff --git a/arch/openrisc/include/asm/pci.h b/arch/openrisc/include/asm/pci.h
new file mode 100644
index 000000000000..e0865d2f3f42
--- /dev/null
+++ b/arch/openrisc/include/asm/pci.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ASM_OPENRISC_PCI_H
+#define __ASM_OPENRISC_PCI_H
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+
+#define PCIBIOS_MIN_IO 0
+#define PCIBIOS_MIN_MEM 0
+
+/* OpenRISC bootloaders do not initialize PCI bus */
+#define pcibios_assign_all_busses() 1
+
+#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
+
+extern int isa_dma_bridge_buggy;
+
+#ifdef CONFIG_PCI
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+ /* no legacy IRQs on or1k */
+ return -ENODEV;
+}
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+ /* always show the domain in /proc */
+ return 1;
+}
+#endif /* CONFIG_PCI */
+
+#endif /* __ASM_OPENRISC_PCI_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/2] openrisc: Add pci bus support
@ 2022-07-09 21:15 ` Stafford Horne
0 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-09 21:15 UTC (permalink / raw)
To: LKML; +Cc: Jonas Bonn, Arnd Bergmann, Peter Zijlstra, Palmer Dabbelt, Openrisc
This patch adds required definitions to allow for PCI buses on OpenRISC.
This is being in the QEMU virt platform.
OpenRISC does not have IO ports so this defines PCI IO to be allowed in
any range. Keeping PIO_RESERVED defined as 0 allows OpenRISC to use
MMIO for all IO.
Also, since commit 66bcd06099bb ("parport_pc: Also enable driver for PCI
systems") all platforms that support PCI also need to support parallel
port. We add a generic header to support parallel port drivers.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 7 ++++---
arch/openrisc/include/asm/Kbuild | 1 +
arch/openrisc/include/asm/io.h | 4 ++--
arch/openrisc/include/asm/pci.h | 36 ++++++++++++++++++++++++++++++++
4 files changed, 43 insertions(+), 5 deletions(-)
create mode 100644 arch/openrisc/include/asm/pci.h
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index e814df4c483c..327241988819 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -21,7 +21,9 @@ config OPENRISC
select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select GENERIC_IOMAP
+ select GENERIC_PCI_IOMAP
select GENERIC_CPU_DEVICES
+ select HAVE_PCI
select HAVE_UID16
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS_BROADCAST
@@ -32,6 +34,8 @@ config OPENRISC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select ARCH_USE_QUEUED_RWLOCKS
select OMPIC if SMP
+ select PCI_DOMAINS_GENERIC if PCI
+ select PCI_MSI if PCI
select ARCH_WANT_FRAME_POINTERS
select GENERIC_IRQ_MULTI_HANDLER
select MMU_GATHER_NO_RANGE if MMU
@@ -46,9 +50,6 @@ config MMU
config GENERIC_HWEIGHT
def_bool y
-config NO_IOPORT_MAP
- def_bool y
-
# For now, use generic checksum functions
#These can be reimplemented in assembly later if so inclined
config GENERIC_CSUM
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 3386b9c1c073..c8c99b554ca4 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
generic-y += extable.h
generic-y += kvm_para.h
+generic-y += parport.h
generic-y += spinlock_types.h
generic-y += spinlock.h
generic-y += qrwlock_types.h
diff --git a/arch/openrisc/include/asm/io.h b/arch/openrisc/include/asm/io.h
index c298061c70a7..1595aa69d96d 100644
--- a/arch/openrisc/include/asm/io.h
+++ b/arch/openrisc/include/asm/io.h
@@ -17,9 +17,9 @@
#include <linux/types.h>
/*
- * PCI: can we really do 0 here if we have no port IO?
+ * PCI: All address space can be used for IO
*/
-#define IO_SPACE_LIMIT 0
+#define IO_SPACE_LIMIT ~(0UL)
/* OpenRISC has no port IO */
#define HAVE_ARCH_PIO_SIZE 1
diff --git a/arch/openrisc/include/asm/pci.h b/arch/openrisc/include/asm/pci.h
new file mode 100644
index 000000000000..e0865d2f3f42
--- /dev/null
+++ b/arch/openrisc/include/asm/pci.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __ASM_OPENRISC_PCI_H
+#define __ASM_OPENRISC_PCI_H
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/io.h>
+
+#define PCIBIOS_MIN_IO 0
+#define PCIBIOS_MIN_MEM 0
+
+/* OpenRISC bootloaders do not initialize PCI bus */
+#define pcibios_assign_all_busses() 1
+
+#define ARCH_GENERIC_PCI_MMAP_RESOURCE 1
+
+extern int isa_dma_bridge_buggy;
+
+#ifdef CONFIG_PCI
+static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+{
+ /* no legacy IRQs on or1k */
+ return -ENODEV;
+}
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+ /* always show the domain in /proc */
+ return 1;
+}
+#endif /* CONFIG_PCI */
+
+#endif /* __ASM_OPENRISC_PCI_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] openrisc: Add virt defconfig
2022-07-09 21:15 ` Stafford Horne
@ 2022-07-09 21:15 ` Stafford Horne
-1 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-09 21:15 UTC (permalink / raw)
To: LKML; +Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson
I have been developing a new qemu virt platform to help with more
efficient toolchain and kernel testing [1].
This patch adds the defconfig which is needed to support booting
linux on the platform.
[1] https://lore.kernel.org/qemu-devel/YpwNtowUTxRbh2Uq@antec/T/#m6db180b0d682785fb320e4a05345c12a063e0c47
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/configs/virt_defconfig | 108 +++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 arch/openrisc/configs/virt_defconfig
diff --git a/arch/openrisc/configs/virt_defconfig b/arch/openrisc/configs/virt_defconfig
new file mode 100644
index 000000000000..c1b69166c500
--- /dev/null
+++ b/arch/openrisc/configs/virt_defconfig
@@ -0,0 +1,108 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_OPENRISC_HAVE_INST_CMOV=y
+CONFIG_OPENRISC_HAVE_INST_ROR=y
+CONFIG_OPENRISC_HAVE_INST_RORI=y
+CONFIG_OPENRISC_HAVE_INST_SEXT=y
+CONFIG_NR_CPUS=8
+CONFIG_SMP=y
+CONFIG_HZ_100=y
+# CONFIG_OPENRISC_NO_SPR_SR_DSX is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CUBIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_NETDEVICES=y
+CONFIG_VIRTIO_NET=y
+CONFIG_ETHOC=y
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_SYSCON_REBOOT_MODE=y
+# CONFIG_HWMON is not set
+CONFIG_DRM=y
+# CONFIG_DRM_FBDEV_EMULATION is not set
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_INTEL8X0=y
+CONFIG_SND_INTEL8X0M=y
+CONFIG_SND_SOC=y
+CONFIG_SND_VIRTIO=y
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_REDRAGON is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_GADGET=y
+CONFIG_TYPEC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_PCI=y
+# CONFIG_VIRTIO_PCI_LEGACY is not set
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_EXFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_UNICODE=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_FTRACE=y
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/2] openrisc: Add virt defconfig
@ 2022-07-09 21:15 ` Stafford Horne
0 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-09 21:15 UTC (permalink / raw)
To: LKML; +Cc: Jonas Bonn, Openrisc
I have been developing a new qemu virt platform to help with more
efficient toolchain and kernel testing [1].
This patch adds the defconfig which is needed to support booting
linux on the platform.
[1] https://lore.kernel.org/qemu-devel/YpwNtowUTxRbh2Uq@antec/T/#m6db180b0d682785fb320e4a05345c12a063e0c47
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/configs/virt_defconfig | 108 +++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 arch/openrisc/configs/virt_defconfig
diff --git a/arch/openrisc/configs/virt_defconfig b/arch/openrisc/configs/virt_defconfig
new file mode 100644
index 000000000000..c1b69166c500
--- /dev/null
+++ b/arch/openrisc/configs/virt_defconfig
@@ -0,0 +1,108 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_OPENRISC_HAVE_INST_CMOV=y
+CONFIG_OPENRISC_HAVE_INST_ROR=y
+CONFIG_OPENRISC_HAVE_INST_RORI=y
+CONFIG_OPENRISC_HAVE_INST_SEXT=y
+CONFIG_NR_CPUS=8
+CONFIG_SMP=y
+CONFIG_HZ_100=y
+# CONFIG_OPENRISC_NO_SPR_SR_DSX is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CUBIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_NETDEVICES=y
+CONFIG_VIRTIO_NET=y
+CONFIG_ETHOC=y
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_SYSCON_REBOOT_MODE=y
+# CONFIG_HWMON is not set
+CONFIG_DRM=y
+# CONFIG_DRM_FBDEV_EMULATION is not set
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_INTEL8X0=y
+CONFIG_SND_INTEL8X0M=y
+CONFIG_SND_SOC=y
+CONFIG_SND_VIRTIO=y
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_ITE is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_REDRAGON is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_GADGET=y
+CONFIG_TYPEC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_PCI=y
+# CONFIG_VIRTIO_PCI_LEGACY is not set
+CONFIG_VIRTIO_INPUT=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_EXFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_UNICODE=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_FTRACE=y
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] openrisc: Add pci bus support
2022-07-09 21:15 ` Stafford Horne
@ 2022-07-10 15:54 ` Arnd Bergmann
-1 siblings, 0 replies; 12+ messages in thread
From: Arnd Bergmann @ 2022-07-10 15:54 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Openrisc, Jonas Bonn, Stefan Kristiansson, Peter Zijlstra,
Palmer Dabbelt, Arnd Bergmann
On Sat, Jul 9, 2022 at 11:15 PM Stafford Horne <shorne@gmail.com> wrote:
>
> This patch adds required definitions to allow for PCI buses on OpenRISC.
> This is being in the QEMU virt platform.
>
> OpenRISC does not have IO ports so this defines PCI IO to be allowed in
> any range. Keeping PIO_RESERVED defined as 0 allows OpenRISC to use
> MMIO for all IO.
>
> /*
> - * PCI: can we really do 0 here if we have no port IO?
> + * PCI: All address space can be used for IO
> */
> -#define IO_SPACE_LIMIT 0
> +#define IO_SPACE_LIMIT ~(0UL)
I think '0' is the correct limit here if you don't support PCI controllers
that can map their I/O ports into MMIO space. If you don't define
PCI_IOBASE to a meaningful value and set IO_SPACE_LIMIT as you
do here, every virtual address is treated as an I/O port, so accessing
a low port through /dev/ioport or a PCI driver results in an access to
a NULL pointer, which is either a userspace address or low kernel
memory, both of which are bad.
Most PCI controller are however able to map I/O ports into the
physical address space of the CPU, and in that case you can just
define an otherwise unused address as PCI_IOBASE and map the
ports there from the PCI host bridge driver.
Arnd
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] openrisc: Add pci bus support
@ 2022-07-10 15:54 ` Arnd Bergmann
0 siblings, 0 replies; 12+ messages in thread
From: Arnd Bergmann @ 2022-07-10 15:54 UTC (permalink / raw)
To: Stafford Horne
Cc: Jonas Bonn, Arnd Bergmann, Peter Zijlstra, LKML, Palmer Dabbelt,
Openrisc
On Sat, Jul 9, 2022 at 11:15 PM Stafford Horne <shorne@gmail.com> wrote:
>
> This patch adds required definitions to allow for PCI buses on OpenRISC.
> This is being in the QEMU virt platform.
>
> OpenRISC does not have IO ports so this defines PCI IO to be allowed in
> any range. Keeping PIO_RESERVED defined as 0 allows OpenRISC to use
> MMIO for all IO.
>
> /*
> - * PCI: can we really do 0 here if we have no port IO?
> + * PCI: All address space can be used for IO
> */
> -#define IO_SPACE_LIMIT 0
> +#define IO_SPACE_LIMIT ~(0UL)
I think '0' is the correct limit here if you don't support PCI controllers
that can map their I/O ports into MMIO space. If you don't define
PCI_IOBASE to a meaningful value and set IO_SPACE_LIMIT as you
do here, every virtual address is treated as an I/O port, so accessing
a low port through /dev/ioport or a PCI driver results in an access to
a NULL pointer, which is either a userspace address or low kernel
memory, both of which are bad.
Most PCI controller are however able to map I/O ports into the
physical address space of the CPU, and in that case you can just
define an otherwise unused address as PCI_IOBASE and map the
ports there from the PCI host bridge driver.
Arnd
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] openrisc: Add pci bus support
2022-07-10 15:54 ` Arnd Bergmann
@ 2022-07-10 21:22 ` Stafford Horne
-1 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-10 21:22 UTC (permalink / raw)
To: Arnd Bergmann
Cc: LKML, Openrisc, Jonas Bonn, Stefan Kristiansson, Peter Zijlstra,
Palmer Dabbelt
On Sun, Jul 10, 2022 at 05:54:22PM +0200, Arnd Bergmann wrote:
> On Sat, Jul 9, 2022 at 11:15 PM Stafford Horne <shorne@gmail.com> wrote:
> >
> > This patch adds required definitions to allow for PCI buses on OpenRISC.
> > This is being in the QEMU virt platform.
> >
> > OpenRISC does not have IO ports so this defines PCI IO to be allowed in
> > any range. Keeping PIO_RESERVED defined as 0 allows OpenRISC to use
> > MMIO for all IO.
>
> >
> > /*
> > - * PCI: can we really do 0 here if we have no port IO?
> > + * PCI: All address space can be used for IO
> > */
> > -#define IO_SPACE_LIMIT 0
> > +#define IO_SPACE_LIMIT ~(0UL)
>
> I think '0' is the correct limit here if you don't support PCI controllers
> that can map their I/O ports into MMIO space. If you don't define
> PCI_IOBASE to a meaningful value and set IO_SPACE_LIMIT as you
> do here, every virtual address is treated as an I/O port, so accessing
> a low port through /dev/ioport or a PCI driver results in an access to
> a NULL pointer, which is either a userspace address or low kernel
> memory, both of which are bad.
OK, I see, but I think IO_SPACE_LIMIT needs to be defined as something other
than 0. It is used to define kernel/resource.c's ioport_resource. For example
on risc-v they set it to 16MB.
I will setup a LIMIT smaller than 4GB and add a PCI_IOBASE.
> Most PCI controller are however able to map I/O ports into the
> physical address space of the CPU, and in that case you can just
> define an otherwise unused address as PCI_IOBASE and map the
> ports there from the PCI host bridge driver.
OK, understood, do you think this needs to be documented in a architecture
manual? Maybe it's fine for it to be linux specific.
-Stafford
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] openrisc: Add pci bus support
@ 2022-07-10 21:22 ` Stafford Horne
0 siblings, 0 replies; 12+ messages in thread
From: Stafford Horne @ 2022-07-10 21:22 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: Jonas Bonn, Peter Zijlstra, LKML, Palmer Dabbelt, Openrisc
On Sun, Jul 10, 2022 at 05:54:22PM +0200, Arnd Bergmann wrote:
> On Sat, Jul 9, 2022 at 11:15 PM Stafford Horne <shorne@gmail.com> wrote:
> >
> > This patch adds required definitions to allow for PCI buses on OpenRISC.
> > This is being in the QEMU virt platform.
> >
> > OpenRISC does not have IO ports so this defines PCI IO to be allowed in
> > any range. Keeping PIO_RESERVED defined as 0 allows OpenRISC to use
> > MMIO for all IO.
>
> >
> > /*
> > - * PCI: can we really do 0 here if we have no port IO?
> > + * PCI: All address space can be used for IO
> > */
> > -#define IO_SPACE_LIMIT 0
> > +#define IO_SPACE_LIMIT ~(0UL)
>
> I think '0' is the correct limit here if you don't support PCI controllers
> that can map their I/O ports into MMIO space. If you don't define
> PCI_IOBASE to a meaningful value and set IO_SPACE_LIMIT as you
> do here, every virtual address is treated as an I/O port, so accessing
> a low port through /dev/ioport or a PCI driver results in an access to
> a NULL pointer, which is either a userspace address or low kernel
> memory, both of which are bad.
OK, I see, but I think IO_SPACE_LIMIT needs to be defined as something other
than 0. It is used to define kernel/resource.c's ioport_resource. For example
on risc-v they set it to 16MB.
I will setup a LIMIT smaller than 4GB and add a PCI_IOBASE.
> Most PCI controller are however able to map I/O ports into the
> physical address space of the CPU, and in that case you can just
> define an otherwise unused address as PCI_IOBASE and map the
> ports there from the PCI host bridge driver.
OK, understood, do you think this needs to be documented in a architecture
manual? Maybe it's fine for it to be linux specific.
-Stafford
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] openrisc: Add pci bus support
2022-07-10 21:22 ` Stafford Horne
@ 2022-07-11 6:05 ` Arnd Bergmann
-1 siblings, 0 replies; 12+ messages in thread
From: Arnd Bergmann @ 2022-07-11 6:05 UTC (permalink / raw)
To: Stafford Horne
Cc: Arnd Bergmann, LKML, Openrisc, Jonas Bonn, Stefan Kristiansson,
Peter Zijlstra, Palmer Dabbelt
On Sun, Jul 10, 2022 at 11:22 PM Stafford Horne <shorne@gmail.com> wrote:
> On Sun, Jul 10, 2022 at 05:54:22PM +0200, Arnd Bergmann wrote:
>
> OK, I see, but I think IO_SPACE_LIMIT needs to be defined as something other
> than 0. It is used to define kernel/resource.c's ioport_resource.
I think the kernel/resource.c one is fine, it just means that any attempt to
register an I/O port resource below the 0-length root resource will fail, which
is what you need when inb/outb cannot be used.
> For example on risc-v they set it to 16MB.
>
> I will setup a LIMIT smaller than 4GB and add a PCI_IOBASE.
Do you support multiple PCI domains? Usually you want at most 64KB
per domain, as that is the traditional limit and what the normal
pci_remap_iospace() will assign to a domain. The 16MB limit for riscv
is way more than what one may need on a 32-bit machine, since that
is enough for 4096 domains even with the largest possible I/O space,
and each domain has up to 65536 PCI functions attached to it.
> > Most PCI controller are however able to map I/O ports into the
> > physical address space of the CPU, and in that case you can just
> > define an otherwise unused address as PCI_IOBASE and map the
> > ports there from the PCI host bridge driver.
>
> OK, understood, do you think this needs to be documented in a architecture
> manual? Maybe it's fine for it to be linux specific.
Of course it's Linux specific, but it's also architecture specific since
there are different ways of making I/O space available: Generally you
can leave it out completely, unless you have to support devices from
two decades ago, some architectures that existed back then have custom
instructions, some hardcode part of the virtual address space to access
MMIO registers at a fixed location, some rely on an indirect method
going through a particular MMIO register to access all I/O space, and
some use a per hostbridge window that gets mapped using
pci_remap_iospace().
Do you have a driver for your host bridge available somewhere?
It should be clear from that driver which method you need.
Arnd
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/2] openrisc: Add pci bus support
@ 2022-07-11 6:05 ` Arnd Bergmann
0 siblings, 0 replies; 12+ messages in thread
From: Arnd Bergmann @ 2022-07-11 6:05 UTC (permalink / raw)
To: Stafford Horne
Cc: Jonas Bonn, Arnd Bergmann, Peter Zijlstra, LKML, Palmer Dabbelt,
Openrisc
On Sun, Jul 10, 2022 at 11:22 PM Stafford Horne <shorne@gmail.com> wrote:
> On Sun, Jul 10, 2022 at 05:54:22PM +0200, Arnd Bergmann wrote:
>
> OK, I see, but I think IO_SPACE_LIMIT needs to be defined as something other
> than 0. It is used to define kernel/resource.c's ioport_resource.
I think the kernel/resource.c one is fine, it just means that any attempt to
register an I/O port resource below the 0-length root resource will fail, which
is what you need when inb/outb cannot be used.
> For example on risc-v they set it to 16MB.
>
> I will setup a LIMIT smaller than 4GB and add a PCI_IOBASE.
Do you support multiple PCI domains? Usually you want at most 64KB
per domain, as that is the traditional limit and what the normal
pci_remap_iospace() will assign to a domain. The 16MB limit for riscv
is way more than what one may need on a 32-bit machine, since that
is enough for 4096 domains even with the largest possible I/O space,
and each domain has up to 65536 PCI functions attached to it.
> > Most PCI controller are however able to map I/O ports into the
> > physical address space of the CPU, and in that case you can just
> > define an otherwise unused address as PCI_IOBASE and map the
> > ports there from the PCI host bridge driver.
>
> OK, understood, do you think this needs to be documented in a architecture
> manual? Maybe it's fine for it to be linux specific.
Of course it's Linux specific, but it's also architecture specific since
there are different ways of making I/O space available: Generally you
can leave it out completely, unless you have to support devices from
two decades ago, some architectures that existed back then have custom
instructions, some hardcode part of the virtual address space to access
MMIO registers at a fixed location, some rely on an indirect method
going through a particular MMIO register to access all I/O space, and
some use a per hostbridge window that gets mapped using
pci_remap_iospace().
Do you have a driver for your host bridge available somewhere?
It should be clear from that driver which method you need.
Arnd
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-07-11 6:05 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-09 21:15 [PATCH 0/2] OpenRISC support for virt platform with PCI Stafford Horne
2022-07-09 21:15 ` Stafford Horne
2022-07-09 21:15 ` [PATCH 1/2] openrisc: Add pci bus support Stafford Horne
2022-07-09 21:15 ` Stafford Horne
2022-07-10 15:54 ` Arnd Bergmann
2022-07-10 15:54 ` Arnd Bergmann
2022-07-10 21:22 ` Stafford Horne
2022-07-10 21:22 ` Stafford Horne
2022-07-11 6:05 ` Arnd Bergmann
2022-07-11 6:05 ` Arnd Bergmann
2022-07-09 21:15 ` [PATCH 2/2] openrisc: Add virt defconfig Stafford Horne
2022-07-09 21:15 ` Stafford Horne
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