* [PATCH 0/3] Linux RISC-V AIA Preparatory Series
@ 2023-10-25 14:28 ` Anup Patel
0 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:28 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Anup Patel, devicetree, Conor Dooley, Saravana Kannan,
Marc Zyngier, Anup Patel, linux-kernel, Björn Töpel,
Atish Patra, linux-riscv, Andrew Jones
The first three patches of the v11 Linux RISC-V AIA series can be
merged independently hence sending these patches as an independent
perparatory series.
(Refer, https://www.spinics.net/lists/devicetree/msg643764.html)
These patches can also be found in the riscv_aia_prep_v1 branch at:
https://github.com/avpatel/linux.git
Anup Patel (3):
RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
of: property: Add fw_devlink support for msi-parent
irqchip/sifive-plic: Fix syscore registration for multi-socket systems
arch/riscv/kernel/cpu.c | 11 ++++++-----
drivers/irqchip/irq-sifive-plic.c | 7 ++++---
drivers/of/property.c | 2 ++
3 files changed, 12 insertions(+), 8 deletions(-)
--
2.34.1
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
2023-10-25 14:28 ` Anup Patel
@ 2023-10-25 14:28 ` Anup Patel
-1 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:28 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Conor Dooley, Marc Zyngier, Björn Töpel, Atish Patra,
Andrew Jones, Sunil V L, Saravana Kannan, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel, Atish Patra
The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
for HARTs disabled in the DT. This results in the following warning
thrown by the RISC-V INTC driver for the E-core on SiFive boards:
[ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
The riscv_of_parent_hartid() is only expected to read the hartid from
the DT so we should directly call of_get_cpu_hwid() instead of calling
riscv_of_processor_hartid().
Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpu.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c17dacb1141c..157ace8b262c 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
*/
int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
{
- int rc;
-
for (; node; node = node->parent) {
if (of_device_is_compatible(node, "riscv")) {
- rc = riscv_of_processor_hartid(node, hartid);
- if (!rc)
- return 0;
+ *hartid = (unsigned long)of_get_cpu_hwid(node, 0);
+ if (*hartid == ~0UL) {
+ pr_warn("Found CPU without hart ID\n");
+ return -ENODEV;
+ }
+ return 0;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
@ 2023-10-25 14:28 ` Anup Patel
0 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:28 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Anup Patel, devicetree, Conor Dooley, Saravana Kannan,
Marc Zyngier, Anup Patel, Atish Patra, linux-kernel,
Björn Töpel, Atish Patra, linux-riscv, Andrew Jones
The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
for HARTs disabled in the DT. This results in the following warning
thrown by the RISC-V INTC driver for the E-core on SiFive boards:
[ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
The riscv_of_parent_hartid() is only expected to read the hartid from
the DT so we should directly call of_get_cpu_hwid() instead of calling
riscv_of_processor_hartid().
Fixes: ad635e723e17 ("riscv: cpu: Add 64bit hartid support on RV64")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/kernel/cpu.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index c17dacb1141c..157ace8b262c 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -125,13 +125,14 @@ int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned lo
*/
int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
{
- int rc;
-
for (; node; node = node->parent) {
if (of_device_is_compatible(node, "riscv")) {
- rc = riscv_of_processor_hartid(node, hartid);
- if (!rc)
- return 0;
+ *hartid = (unsigned long)of_get_cpu_hwid(node, 0);
+ if (*hartid == ~0UL) {
+ pr_warn("Found CPU without hart ID\n");
+ return -ENODEV;
+ }
+ return 0;
}
}
--
2.34.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
2023-10-25 14:28 ` Anup Patel
@ 2023-10-27 7:59 ` Thomas Gleixner
-1 siblings, 0 replies; 19+ messages in thread
From: Thomas Gleixner @ 2023-10-27 7:59 UTC (permalink / raw)
To: Anup Patel, Palmer Dabbelt, Paul Walmsley, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Conor Dooley, Marc Zyngier, Björn Töpel, Atish Patra,
Andrew Jones, Sunil V L, Saravana Kannan, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel, Atish Patra
On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
> for HARTs disabled in the DT. This results in the following warning
> thrown by the RISC-V INTC driver for the E-core on SiFive boards:
>
> [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
>
> The riscv_of_parent_hartid() is only expected to read the hartid from
> the DT so we should directly call of_get_cpu_hwid() instead of calling
We should? Or maybe not?
Please write precise changelogs and use imperative wording as documented
in Documentation/process.
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
@ 2023-10-27 7:59 ` Thomas Gleixner
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Gleixner @ 2023-10-27 7:59 UTC (permalink / raw)
To: Anup Patel, Palmer Dabbelt, Paul Walmsley, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Anup Patel, devicetree, Conor Dooley, Saravana Kannan,
Marc Zyngier, Anup Patel, Atish Patra, linux-kernel,
Björn Töpel, Atish Patra, linux-riscv, Andrew Jones
On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
> for HARTs disabled in the DT. This results in the following warning
> thrown by the RISC-V INTC driver for the E-core on SiFive boards:
>
> [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
>
> The riscv_of_parent_hartid() is only expected to read the hartid from
> the DT so we should directly call of_get_cpu_hwid() instead of calling
We should? Or maybe not?
Please write precise changelogs and use imperative wording as documented
in Documentation/process.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/3] RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
2023-10-27 7:59 ` Thomas Gleixner
(?)
@ 2023-10-27 14:38 ` Anup Patel
-1 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-27 14:38 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Palmer Dabbelt, Paul Walmsley, Rob Herring, Krzysztof Kozlowski,
Frank Rowand, Conor Dooley, Marc Zyngier, Björn Töpel,
Atish Patra, Andrew Jones, Sunil V L, Saravana Kannan,
Anup Patel, linux-riscv, linux-kernel, devicetree, Atish Patra
On Fri, Oct 27, 2023 at 1:29 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> > The riscv_of_processor_hartid() used by riscv_of_parent_hartid() fails
> > for HARTs disabled in the DT. This results in the following warning
> > thrown by the RISC-V INTC driver for the E-core on SiFive boards:
> >
> > [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
> >
> > The riscv_of_parent_hartid() is only expected to read the hartid from
> > the DT so we should directly call of_get_cpu_hwid() instead of calling
>
> We should? Or maybe not?
>
> Please write precise changelogs and use imperative wording as documented
> in Documentation/process.
Sure, I will update the wording in the commit description.
Thanks,
Anup
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/3] of: property: Add fw_devlink support for msi-parent
2023-10-25 14:28 ` Anup Patel
@ 2023-10-25 14:28 ` Anup Patel
-1 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:28 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Conor Dooley, Marc Zyngier, Björn Töpel, Atish Patra,
Andrew Jones, Sunil V L, Saravana Kannan, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel, Rob Herring
This allows fw_devlink to create device links between consumers of
a MSI and the supplier of the MSI.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Saravana Kannan <saravanak@google.com>
---
drivers/of/property.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/of/property.c b/drivers/of/property.c
index cf8dacf3e3b8..afdaefbd03f6 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -1267,6 +1267,7 @@ DEFINE_SIMPLE_PROP(resets, "resets", "#reset-cells")
DEFINE_SIMPLE_PROP(leds, "leds", NULL)
DEFINE_SIMPLE_PROP(backlight, "backlight", NULL)
DEFINE_SIMPLE_PROP(panel, "panel", NULL)
+DEFINE_SIMPLE_PROP(msi_parent, "msi-parent", "#msi-cells")
DEFINE_SUFFIX_PROP(regulators, "-supply", NULL)
DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells")
@@ -1356,6 +1357,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_leds, },
{ .parse_prop = parse_backlight, },
{ .parse_prop = parse_panel, },
+ { .parse_prop = parse_msi_parent, },
{ .parse_prop = parse_gpio_compat, },
{ .parse_prop = parse_interrupts, },
{ .parse_prop = parse_regulators, },
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 2/3] of: property: Add fw_devlink support for msi-parent
@ 2023-10-25 14:28 ` Anup Patel
0 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:28 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Anup Patel, devicetree, Conor Dooley, Saravana Kannan,
Rob Herring, Marc Zyngier, Anup Patel, linux-kernel,
Björn Töpel, Atish Patra, linux-riscv, Andrew Jones
This allows fw_devlink to create device links between consumers of
a MSI and the supplier of the MSI.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Saravana Kannan <saravanak@google.com>
---
drivers/of/property.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/of/property.c b/drivers/of/property.c
index cf8dacf3e3b8..afdaefbd03f6 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -1267,6 +1267,7 @@ DEFINE_SIMPLE_PROP(resets, "resets", "#reset-cells")
DEFINE_SIMPLE_PROP(leds, "leds", NULL)
DEFINE_SIMPLE_PROP(backlight, "backlight", NULL)
DEFINE_SIMPLE_PROP(panel, "panel", NULL)
+DEFINE_SIMPLE_PROP(msi_parent, "msi-parent", "#msi-cells")
DEFINE_SUFFIX_PROP(regulators, "-supply", NULL)
DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells")
@@ -1356,6 +1357,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_leds, },
{ .parse_prop = parse_backlight, },
{ .parse_prop = parse_panel, },
+ { .parse_prop = parse_msi_parent, },
{ .parse_prop = parse_gpio_compat, },
{ .parse_prop = parse_interrupts, },
{ .parse_prop = parse_regulators, },
--
2.34.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH 2/3] of: property: Add fw_devlink support for msi-parent
2023-10-25 14:28 ` Anup Patel
@ 2023-10-27 7:57 ` Thomas Gleixner
-1 siblings, 0 replies; 19+ messages in thread
From: Thomas Gleixner @ 2023-10-27 7:57 UTC (permalink / raw)
To: Anup Patel, Palmer Dabbelt, Paul Walmsley, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Conor Dooley, Marc Zyngier, Björn Töpel, Atish Patra,
Andrew Jones, Sunil V L, Saravana Kannan, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel, Rob Herring
On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> This allows fw_devlink to create device links between consumers of
> a MSI and the supplier of the MSI.
How is this related to the two fixes in this series?
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/3] of: property: Add fw_devlink support for msi-parent
@ 2023-10-27 7:57 ` Thomas Gleixner
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Gleixner @ 2023-10-27 7:57 UTC (permalink / raw)
To: Anup Patel, Palmer Dabbelt, Paul Walmsley, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Anup Patel, devicetree, Conor Dooley, Saravana Kannan,
Rob Herring, Marc Zyngier, Anup Patel, linux-kernel,
Björn Töpel, Atish Patra, linux-riscv, Andrew Jones
On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> This allows fw_devlink to create device links between consumers of
> a MSI and the supplier of the MSI.
How is this related to the two fixes in this series?
_______________________________________________
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/3] of: property: Add fw_devlink support for msi-parent
2023-10-27 7:57 ` Thomas Gleixner
(?)
@ 2023-10-27 15:31 ` Anup Patel
2023-10-27 17:29 ` Thomas Gleixner
-1 siblings, 1 reply; 19+ messages in thread
From: Anup Patel @ 2023-10-27 15:31 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Palmer Dabbelt, Paul Walmsley, Rob Herring, Krzysztof Kozlowski,
Frank Rowand, Conor Dooley, Marc Zyngier, Björn Töpel,
Atish Patra, Andrew Jones, Sunil V L, Saravana Kannan,
Anup Patel, linux-riscv, linux-kernel, devicetree, Rob Herring
Hi Thomas,
On Fri, Oct 27, 2023 at 1:27 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
> > This allows fw_devlink to create device links between consumers of
> > a MSI and the supplier of the MSI.
>
> How is this related to the two fixes in this series?
The first three patches of the v11 RISC-V AIA series are all
fixes hence I sent them separately for the 6.7 merge window.
(https://lore.kernel.org/lkml/20231023172800.315343-1-apatel@ventanamicro.com/)
All three fixes are unrelated to each other and were discovered
during AIA driver development.
This patch fixes the probing order for platform devices having
inter-dependency based on "msi-parent" DT property.
For example, the AIA APLIC (wired-to-MSI bridge) platform
device depends on the AIA IMSIC (MSI controller) platform
device.
Are you okay with this patch going through the RISC-V tree ?
Regards,
Anup
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/3] of: property: Add fw_devlink support for msi-parent
2023-10-27 15:31 ` Anup Patel
@ 2023-10-27 17:29 ` Thomas Gleixner
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Gleixner @ 2023-10-27 17:29 UTC (permalink / raw)
To: Anup Patel
Cc: Palmer Dabbelt, Paul Walmsley, Rob Herring, Krzysztof Kozlowski,
Frank Rowand, Conor Dooley, Marc Zyngier, Björn Töpel,
Atish Patra, Andrew Jones, Sunil V L, Saravana Kannan,
Anup Patel, linux-riscv, linux-kernel, devicetree, Rob Herring
On Fri, Oct 27 2023 at 21:01, Anup Patel wrote:
> On Fri, Oct 27, 2023 at 1:27 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>>
>> On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
>> > This allows fw_devlink to create device links between consumers of
>> > a MSI and the supplier of the MSI.
>>
>> How is this related to the two fixes in this series?
>
> The first three patches of the v11 RISC-V AIA series are all
> fixes hence I sent them separately for the 6.7 merge window.
> (https://lore.kernel.org/lkml/20231023172800.315343-1-apatel@ventanamicro.com/)
>
> All three fixes are unrelated to each other and were discovered
> during AIA driver development.
>
> This patch fixes the probing order for platform devices having
> inter-dependency based on "msi-parent" DT property.
> For example, the AIA APLIC (wired-to-MSI bridge) platform
> device depends on the AIA IMSIC (MSI controller) platform
> device.
Well, the changelog should tell that it is a fix and not make the
illusion that this is pure enablement....
> Are you okay with this patch going through the RISC-V tree ?
Fine with me.
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/3] of: property: Add fw_devlink support for msi-parent
@ 2023-10-27 17:29 ` Thomas Gleixner
0 siblings, 0 replies; 19+ messages in thread
From: Thomas Gleixner @ 2023-10-27 17:29 UTC (permalink / raw)
To: Anup Patel
Cc: devicetree, Conor Dooley, Saravana Kannan, Rob Herring,
Marc Zyngier, Anup Patel, Atish Patra, linux-kernel,
Björn Töpel, Rob Herring, Palmer Dabbelt,
Krzysztof Kozlowski, Paul Walmsley, linux-riscv, Frank Rowand,
Andrew Jones
On Fri, Oct 27 2023 at 21:01, Anup Patel wrote:
> On Fri, Oct 27, 2023 at 1:27 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>>
>> On Wed, Oct 25 2023 at 19:58, Anup Patel wrote:
>> > This allows fw_devlink to create device links between consumers of
>> > a MSI and the supplier of the MSI.
>>
>> How is this related to the two fixes in this series?
>
> The first three patches of the v11 RISC-V AIA series are all
> fixes hence I sent them separately for the 6.7 merge window.
> (https://lore.kernel.org/lkml/20231023172800.315343-1-apatel@ventanamicro.com/)
>
> All three fixes are unrelated to each other and were discovered
> during AIA driver development.
>
> This patch fixes the probing order for platform devices having
> inter-dependency based on "msi-parent" DT property.
> For example, the AIA APLIC (wired-to-MSI bridge) platform
> device depends on the AIA IMSIC (MSI controller) platform
> device.
Well, the changelog should tell that it is a fix and not make the
illusion that this is pure enablement....
> Are you okay with this patch going through the RISC-V tree ?
Fine with me.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 3/3] irqchip/sifive-plic: Fix syscore registration for multi-socket systems
2023-10-25 14:28 ` Anup Patel
@ 2023-10-25 14:28 ` Anup Patel
-1 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:28 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Conor Dooley, Marc Zyngier, Björn Töpel, Atish Patra,
Andrew Jones, Sunil V L, Saravana Kannan, Anup Patel,
linux-riscv, linux-kernel, devicetree, Anup Patel
On multi-socket systems, we will have a separate PLIC in each socket
so we should register syscore operation only once for multi-socket
systems.
Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/irqchip/irq-sifive-plic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index e1484905b7bd..5b7bc4fd9517 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -532,17 +532,18 @@ static int __init __plic_init(struct device_node *node,
}
/*
- * We can have multiple PLIC instances so setup cpuhp state only
- * when context handler for current/boot CPU is present.
+ * We can have multiple PLIC instances so setup cpuhp state
+ * and register syscore operations only when context handler
+ * for current/boot CPU is present.
*/
handler = this_cpu_ptr(&plic_handlers);
if (handler->present && !plic_cpuhp_setup_done) {
cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
"irqchip/sifive/plic:starting",
plic_starting_cpu, plic_dying_cpu);
+ register_syscore_ops(&plic_irq_syscore_ops);
plic_cpuhp_setup_done = true;
}
- register_syscore_ops(&plic_irq_syscore_ops);
pr_info("%pOFP: mapped %d interrupts with %d handlers for"
" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
--
2.34.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH 3/3] irqchip/sifive-plic: Fix syscore registration for multi-socket systems
@ 2023-10-25 14:28 ` Anup Patel
0 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:28 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, Thomas Gleixner, Rob Herring,
Krzysztof Kozlowski, Frank Rowand
Cc: Anup Patel, devicetree, Conor Dooley, Saravana Kannan,
Marc Zyngier, Anup Patel, linux-kernel, Björn Töpel,
Atish Patra, linux-riscv, Andrew Jones
On multi-socket systems, we will have a separate PLIC in each socket
so we should register syscore operation only once for multi-socket
systems.
Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/irqchip/irq-sifive-plic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index e1484905b7bd..5b7bc4fd9517 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -532,17 +532,18 @@ static int __init __plic_init(struct device_node *node,
}
/*
- * We can have multiple PLIC instances so setup cpuhp state only
- * when context handler for current/boot CPU is present.
+ * We can have multiple PLIC instances so setup cpuhp state
+ * and register syscore operations only when context handler
+ * for current/boot CPU is present.
*/
handler = this_cpu_ptr(&plic_handlers);
if (handler->present && !plic_cpuhp_setup_done) {
cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
"irqchip/sifive/plic:starting",
plic_starting_cpu, plic_dying_cpu);
+ register_syscore_ops(&plic_irq_syscore_ops);
plic_cpuhp_setup_done = true;
}
- register_syscore_ops(&plic_irq_syscore_ops);
pr_info("%pOFP: mapped %d interrupts with %d handlers for"
" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
--
2.34.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 19+ messages in thread* [tip: irq/core] irqchip/sifive-plic: Fix syscore registration for multi-socket systems
2023-10-25 14:28 ` Anup Patel
(?)
@ 2023-10-27 8:17 ` tip-bot2 for Anup Patel
-1 siblings, 0 replies; 19+ messages in thread
From: tip-bot2 for Anup Patel @ 2023-10-27 8:17 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Anup Patel, Thomas Gleixner, x86, linux-kernel, maz
The following commit has been merged into the irq/core branch of tip:
Commit-ID: f99b926f6543faeadba1b4524d8dc9c102489135
Gitweb: https://git.kernel.org/tip/f99b926f6543faeadba1b4524d8dc9c102489135
Author: Anup Patel <apatel@ventanamicro.com>
AuthorDate: Wed, 25 Oct 2023 19:58:20 +05:30
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 27 Oct 2023 10:09:15 +02:00
irqchip/sifive-plic: Fix syscore registration for multi-socket systems
Multi-socket systems have a separate PLIC in each socket, so __plic_init()
is invoked for each PLIC. __plic_init() registers syscore operations, which
obviously fails on the second invocation.
Move it into the already existing condition for installing the CPU hotplug
state so it is only invoked once when the first PLIC is initialized.
[ tglx: Massaged changelog ]
Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231025142820.390238-4-apatel@ventanamicro.com
---
drivers/irqchip/irq-sifive-plic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index e148490..5b7bc4f 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -532,17 +532,18 @@ done:
}
/*
- * We can have multiple PLIC instances so setup cpuhp state only
- * when context handler for current/boot CPU is present.
+ * We can have multiple PLIC instances so setup cpuhp state
+ * and register syscore operations only when context handler
+ * for current/boot CPU is present.
*/
handler = this_cpu_ptr(&plic_handlers);
if (handler->present && !plic_cpuhp_setup_done) {
cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING,
"irqchip/sifive/plic:starting",
plic_starting_cpu, plic_dying_cpu);
+ register_syscore_ops(&plic_irq_syscore_ops);
plic_cpuhp_setup_done = true;
}
- register_syscore_ops(&plic_irq_syscore_ops);
pr_info("%pOFP: mapped %d interrupts with %d handlers for"
" %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts);
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 0/3] Linux RISC-V AIA Preparatory Series
2023-10-25 14:28 ` Anup Patel
@ 2023-10-25 14:31 ` Anup Patel
-1 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:31 UTC (permalink / raw)
To: Palmer Dabbelt, Palmer Dabbelt
Cc: Conor Dooley, Marc Zyngier, Björn Töpel, Atish Patra,
Andrew Jones, Sunil V L, Saravana Kannan, Anup Patel,
Krzysztof Kozlowski, Rob Herring, linux-riscv, Paul Walmsley,
linux-kernel, devicetree, Thomas Gleixner, Frank Rowand
Hi Palmer,
On Wed, Oct 25, 2023 at 7:58 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The first three patches of the v11 Linux RISC-V AIA series can be
> merged independently hence sending these patches as an independent
> perparatory series.
> (Refer, https://www.spinics.net/lists/devicetree/msg643764.html)
>
> These patches can also be found in the riscv_aia_prep_v1 branch at:
> https://github.com/avpatel/linux.git
>
> Anup Patel (3):
> RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
> of: property: Add fw_devlink support for msi-parent
> irqchip/sifive-plic: Fix syscore registration for multi-socket systems
As mentioned on the patchwork call, these are the first three patches
of the v11 Linux AIA series.
Please consider this for the Linux-6.7 merge window.
>
> arch/riscv/kernel/cpu.c | 11 ++++++-----
> drivers/irqchip/irq-sifive-plic.c | 7 ++++---
> drivers/of/property.c | 2 ++
> 3 files changed, 12 insertions(+), 8 deletions(-)
>
> --
> 2.34.1
>
Regards,
Anup
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 0/3] Linux RISC-V AIA Preparatory Series
@ 2023-10-25 14:31 ` Anup Patel
0 siblings, 0 replies; 19+ messages in thread
From: Anup Patel @ 2023-10-25 14:31 UTC (permalink / raw)
To: Palmer Dabbelt, Palmer Dabbelt
Cc: devicetree, Conor Dooley, Saravana Kannan, Marc Zyngier,
Anup Patel, Paul Walmsley, linux-kernel, Rob Herring,
Björn Töpel, Krzysztof Kozlowski, Atish Patra,
linux-riscv, Frank Rowand, Thomas Gleixner, Andrew Jones
Hi Palmer,
On Wed, Oct 25, 2023 at 7:58 PM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The first three patches of the v11 Linux RISC-V AIA series can be
> merged independently hence sending these patches as an independent
> perparatory series.
> (Refer, https://www.spinics.net/lists/devicetree/msg643764.html)
>
> These patches can also be found in the riscv_aia_prep_v1 branch at:
> https://github.com/avpatel/linux.git
>
> Anup Patel (3):
> RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
> of: property: Add fw_devlink support for msi-parent
> irqchip/sifive-plic: Fix syscore registration for multi-socket systems
As mentioned on the patchwork call, these are the first three patches
of the v11 Linux AIA series.
Please consider this for the Linux-6.7 merge window.
>
> arch/riscv/kernel/cpu.c | 11 ++++++-----
> drivers/irqchip/irq-sifive-plic.c | 7 ++++---
> drivers/of/property.c | 2 ++
> 3 files changed, 12 insertions(+), 8 deletions(-)
>
> --
> 2.34.1
>
Regards,
Anup
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 19+ messages in thread