* [PATCH v4] drm/i915: Document the Virtual Engine uAPI
@ 2021-06-18 15:00 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2021-06-18 15:00 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel, Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
A little bit of documentation covering the topics of engine discovery,
context engine maps and virtual engines. It is not very detailed but
supposed to be a starting point of giving a brief high level overview of
general principles and intended use cases.
v2:
* Have the text in uapi header and link from there.
v4:
* Link from driver-uapi.rst.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
---
Documentation/gpu/driver-uapi.rst | 21 ++++
include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++
2 files changed, 209 insertions(+)
diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst
index 4411e6919a3d..27d0fbe33e87 100644
--- a/Documentation/gpu/driver-uapi.rst
+++ b/Documentation/gpu/driver-uapi.rst
@@ -5,4 +5,25 @@ DRM Driver uAPI
drm/i915 uAPI
=============
+Engine Discovery uAPI
+---------------------
+
+.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :doc: Engine Discovery uAPI
+
+Context Engine Map uAPI
+-----------------------
+
+.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :doc: Context Engine Map uAPI
+
+Virtual Engine uAPI
+-------------------
+
+.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :doc: Virtual Engine uAPI
+
+i915_drm.h
+----------
.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :internal:
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a1cb4aa035a9..2f70c48567c0 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu {
__u32 rsvd;
};
+/**
+ * DOC: Virtual Engine uAPI
+ *
+ * Virtual engine is a concept where userspace is able to configure a set of
+ * physical engines, submit a batch buffer, and let the driver execute it on any
+ * engine from the set as it sees fit.
+ *
+ * This is primarily useful on parts which have multiple instances of a same
+ * class engine, like for example GT3+ Skylake parts with their two VCS engines.
+ *
+ * For instance userspace can enumerate all engines of a certain class using the
+ * previously described `Engine Discovery uAPI`_. After that userspace can
+ * create a GEM context with a placeholder slot for the virtual engine (using
+ * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
+ * and instance respectively) and finally using the
+ * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
+ * the same reserved slot.
+ *
+ * Example of creating a virtual engine and submitting a batch buffer to it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
+ * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
+ * .engine_index = 0, // Place this virtual engine into engine map slot 0
+ * .num_siblings = 2,
+ * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
+ * { I915_ENGINE_CLASS_VIDEO, 1 }, },
+ * };
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ * .engines = { { I915_ENGINE_CLASS_INVALID,
+ * I915_ENGINE_CLASS_INVALID_NONE } },
+ * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // Now we have created a GEM context with its engine map containing a
+ * // single virtual engine. Submissions to this slot can go either to
+ * // vcs0 or vcs1, depending on the load balancing algorithm used inside
+ * // the driver. The load balancing is dynamic from one batch buffer to
+ * // another and transparent to userspace.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
/*
* i915_context_engines_load_balance:
*
@@ -1882,6 +1945,61 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
+/**
+ * DOC: Context Engine Map uAPI
+ *
+ * Context engine map is a new way of addressing engines when submitting batch-
+ * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
+ * inside the flags field of `struct drm_i915_gem_execbuffer2`.
+ *
+ * To use it created GEM contexts need to be configured with a list of engines
+ * the user is intending to submit to. This is accomplished using the
+ * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
+ * i915_context_param_engines`.
+ *
+ * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
+ * configured map.
+ *
+ * Example of creating such context and submitting against it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
+ * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
+ * { I915_ENGINE_CLASS_COPY, 0 } }
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // We have now created a GEM context with two engines in the map:
+ * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
+ * // will not be accessible from this context.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
@@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/**
+ * DOC: Engine Discovery uAPI
+ *
+ * Engine discovery uAPI is a way of enumerating physical engines present in a
+ * GPU associated with an open i915 DRM file descriptor. This supersedes the old
+ * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
+ * `I915_PARAM_HAS_BLT`.
+ *
+ * The need for this interface came starting with Icelake and newer GPUs, which
+ * started to establish a pattern of having multiple engines of a same class,
+ * where not all instances were always completely functionally equivalent.
+ *
+ * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
+ * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
+ *
+ * Example for getting the list of engines:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_engine_info *info;
+ * struct drm_i915_query_item item = {
+ * .query_id = DRM_I915_QUERY_ENGINE_INFO;
+ * };
+ * struct drm_i915_query query = {
+ * .num_items = 1,
+ * .items_ptr = (uintptr_t)&item,
+ * };
+ * int err, i;
+ *
+ * // First query the size of the blob we need, this needs to be large
+ * // enough to hold our array of engines. The kernel will fill out the
+ * // item.length for us, which is the number of bytes we need.
+ * //
+ * // Alternatively a large buffer can be allocated straight away enabling
+ * // querying in one pass, in which case item.length should contain the
+ * // length of the provided buffer.
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * info = calloc(1, item.length);
+ * // Now that we allocated the required number of bytes, we call the ioctl
+ * // again, this time with the data_ptr pointing to our newly allocated
+ * // blob, which the kernel can then populate with info on all engines.
+ * item.data_ptr = (uintptr_t)&info,
+ *
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * // We can now access each engine in the array
+ * for (i = 0; i < info->num_engines; i++) {
+ * struct drm_i915_engine_info einfo = info->engines[i];
+ * u16 class = einfo.engine.class;
+ * u16 instance = einfo.engine.instance;
+ * ....
+ * }
+ *
+ * free(info);
+ *
+ * Each of the enumerated engines, apart from being defined by its class and
+ * instance (see `struct i915_engine_class_instance`), also can have flags and
+ * capabilities defined as documented in i915_drm.h.
+ *
+ * For instance video engines which support HEVC encoding will have the
+ * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
+ *
+ * Engine discovery only fully comes to its own when combined with the new way
+ * of addressing engines when submitting batch buffers using contexts with
+ * engine maps configured.
+ */
+
/**
* struct drm_i915_engine_info
*
--
2.30.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v4] drm/i915: Document the Virtual Engine uAPI
@ 2021-06-18 15:00 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2021-06-18 15:00 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
A little bit of documentation covering the topics of engine discovery,
context engine maps and virtual engines. It is not very detailed but
supposed to be a starting point of giving a brief high level overview of
general principles and intended use cases.
v2:
* Have the text in uapi header and link from there.
v4:
* Link from driver-uapi.rst.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
---
Documentation/gpu/driver-uapi.rst | 21 ++++
include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++
2 files changed, 209 insertions(+)
diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst
index 4411e6919a3d..27d0fbe33e87 100644
--- a/Documentation/gpu/driver-uapi.rst
+++ b/Documentation/gpu/driver-uapi.rst
@@ -5,4 +5,25 @@ DRM Driver uAPI
drm/i915 uAPI
=============
+Engine Discovery uAPI
+---------------------
+
+.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :doc: Engine Discovery uAPI
+
+Context Engine Map uAPI
+-----------------------
+
+.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :doc: Context Engine Map uAPI
+
+Virtual Engine uAPI
+-------------------
+
+.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :doc: Virtual Engine uAPI
+
+i915_drm.h
+----------
.. kernel-doc:: include/uapi/drm/i915_drm.h
+ :internal:
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a1cb4aa035a9..2f70c48567c0 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu {
__u32 rsvd;
};
+/**
+ * DOC: Virtual Engine uAPI
+ *
+ * Virtual engine is a concept where userspace is able to configure a set of
+ * physical engines, submit a batch buffer, and let the driver execute it on any
+ * engine from the set as it sees fit.
+ *
+ * This is primarily useful on parts which have multiple instances of a same
+ * class engine, like for example GT3+ Skylake parts with their two VCS engines.
+ *
+ * For instance userspace can enumerate all engines of a certain class using the
+ * previously described `Engine Discovery uAPI`_. After that userspace can
+ * create a GEM context with a placeholder slot for the virtual engine (using
+ * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
+ * and instance respectively) and finally using the
+ * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
+ * the same reserved slot.
+ *
+ * Example of creating a virtual engine and submitting a batch buffer to it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
+ * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
+ * .engine_index = 0, // Place this virtual engine into engine map slot 0
+ * .num_siblings = 2,
+ * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
+ * { I915_ENGINE_CLASS_VIDEO, 1 }, },
+ * };
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
+ * .engines = { { I915_ENGINE_CLASS_INVALID,
+ * I915_ENGINE_CLASS_INVALID_NONE } },
+ * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // Now we have created a GEM context with its engine map containing a
+ * // single virtual engine. Submissions to this slot can go either to
+ * // vcs0 or vcs1, depending on the load balancing algorithm used inside
+ * // the driver. The load balancing is dynamic from one batch buffer to
+ * // another and transparent to userspace.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
/*
* i915_context_engines_load_balance:
*
@@ -1882,6 +1945,61 @@ struct i915_context_engines_bond {
struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
+/**
+ * DOC: Context Engine Map uAPI
+ *
+ * Context engine map is a new way of addressing engines when submitting batch-
+ * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
+ * inside the flags field of `struct drm_i915_gem_execbuffer2`.
+ *
+ * To use it created GEM contexts need to be configured with a list of engines
+ * the user is intending to submit to. This is accomplished using the
+ * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
+ * i915_context_param_engines`.
+ *
+ * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
+ * configured map.
+ *
+ * Example of creating such context and submitting against it:
+ *
+ * .. code-block:: C
+ *
+ * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
+ * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
+ * { I915_ENGINE_CLASS_COPY, 0 } }
+ * };
+ * struct drm_i915_gem_context_create_ext_setparam p_engines = {
+ * .base = {
+ * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ * },
+ * .param = {
+ * .param = I915_CONTEXT_PARAM_ENGINES,
+ * .value = to_user_pointer(&engines),
+ * .size = sizeof(engines),
+ * },
+ * };
+ * struct drm_i915_gem_context_create_ext create = {
+ * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ * .extensions = to_user_pointer(&p_engines);
+ * };
+ *
+ * ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * // We have now created a GEM context with two engines in the map:
+ * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
+ * // will not be accessible from this context.
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ *
+ * ...
+ * execbuf.rsvd1 = ctx_id;
+ * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
+ * gem_execbuf(drm_fd, &execbuf);
+ */
+
struct i915_context_param_engines {
__u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
@@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info {
__u8 data[];
};
+/**
+ * DOC: Engine Discovery uAPI
+ *
+ * Engine discovery uAPI is a way of enumerating physical engines present in a
+ * GPU associated with an open i915 DRM file descriptor. This supersedes the old
+ * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
+ * `I915_PARAM_HAS_BLT`.
+ *
+ * The need for this interface came starting with Icelake and newer GPUs, which
+ * started to establish a pattern of having multiple engines of a same class,
+ * where not all instances were always completely functionally equivalent.
+ *
+ * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
+ * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
+ *
+ * Example for getting the list of engines:
+ *
+ * .. code-block:: C
+ *
+ * struct drm_i915_query_engine_info *info;
+ * struct drm_i915_query_item item = {
+ * .query_id = DRM_I915_QUERY_ENGINE_INFO;
+ * };
+ * struct drm_i915_query query = {
+ * .num_items = 1,
+ * .items_ptr = (uintptr_t)&item,
+ * };
+ * int err, i;
+ *
+ * // First query the size of the blob we need, this needs to be large
+ * // enough to hold our array of engines. The kernel will fill out the
+ * // item.length for us, which is the number of bytes we need.
+ * //
+ * // Alternatively a large buffer can be allocated straight away enabling
+ * // querying in one pass, in which case item.length should contain the
+ * // length of the provided buffer.
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * info = calloc(1, item.length);
+ * // Now that we allocated the required number of bytes, we call the ioctl
+ * // again, this time with the data_ptr pointing to our newly allocated
+ * // blob, which the kernel can then populate with info on all engines.
+ * item.data_ptr = (uintptr_t)&info,
+ *
+ * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
+ * if (err) ...
+ *
+ * // We can now access each engine in the array
+ * for (i = 0; i < info->num_engines; i++) {
+ * struct drm_i915_engine_info einfo = info->engines[i];
+ * u16 class = einfo.engine.class;
+ * u16 instance = einfo.engine.instance;
+ * ....
+ * }
+ *
+ * free(info);
+ *
+ * Each of the enumerated engines, apart from being defined by its class and
+ * instance (see `struct i915_engine_class_instance`), also can have flags and
+ * capabilities defined as documented in i915_drm.h.
+ *
+ * For instance video engines which support HEVC encoding will have the
+ * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
+ *
+ * Engine discovery only fully comes to its own when combined with the new way
+ * of addressing engines when submitting batch buffers using contexts with
+ * engine maps configured.
+ */
+
/**
* struct drm_i915_engine_info
*
--
2.30.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Document the Virtual Engine uAPI (rev4)
2021-06-18 15:00 ` [Intel-gfx] " Tvrtko Ursulin
(?)
@ 2021-06-18 16:39 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-18 16:39 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Document the Virtual Engine uAPI (rev4)
URL : https://patchwork.freedesktop.org/series/91406/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
043a7f21361b drm/i915: Document the Virtual Engine uAPI
-:80: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#80: FILE: include/uapi/drm/i915_drm.h:1831:
+ * ^II915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {$
-:81: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#81: FILE: include/uapi/drm/i915_drm.h:1832:
+ * ^I^I.base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,$
-:82: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#82: FILE: include/uapi/drm/i915_drm.h:1833:
+ * ^I^I.engine_index = 0, // Place this virtual engine into engine map slot 0$
-:83: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#83: FILE: include/uapi/drm/i915_drm.h:1834:
+ * ^I^I.num_siblings = 2,$
-:84: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#84: FILE: include/uapi/drm/i915_drm.h:1835:
+ * ^I^I.engines = { { I915_ENGINE_CLASS_VIDEO, 0 },$
-:85: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#85: FILE: include/uapi/drm/i915_drm.h:1836:
+ * ^I^I^I { I915_ENGINE_CLASS_VIDEO, 1 }, },$
-:86: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#86: FILE: include/uapi/drm/i915_drm.h:1837:
+ * ^I};$
-:87: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#87: FILE: include/uapi/drm/i915_drm.h:1838:
+ * ^II915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {$
-:88: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#88: FILE: include/uapi/drm/i915_drm.h:1839:
+ * ^I^I.engines = { { I915_ENGINE_CLASS_INVALID,$
-:89: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#89: FILE: include/uapi/drm/i915_drm.h:1840:
+ * ^I^I^I I915_ENGINE_CLASS_INVALID_NONE } },$
-:90: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#90: FILE: include/uapi/drm/i915_drm.h:1841:
+ * ^I^I.extensions = to_user_pointer(&virtual), // Chains after load_balance extension$
-:91: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#91: FILE: include/uapi/drm/i915_drm.h:1842:
+ * ^I};$
-:92: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#92: FILE: include/uapi/drm/i915_drm.h:1843:
+ * ^Istruct drm_i915_gem_context_create_ext_setparam p_engines = {$
-:93: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#93: FILE: include/uapi/drm/i915_drm.h:1844:
+ * ^I^I.base = {$
-:94: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#94: FILE: include/uapi/drm/i915_drm.h:1845:
+ * ^I^I^I.name = I915_CONTEXT_CREATE_EXT_SETPARAM,$
-:95: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#95: FILE: include/uapi/drm/i915_drm.h:1846:
+ * ^I^I},$
-:96: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#96: FILE: include/uapi/drm/i915_drm.h:1847:
+ * ^I^I.param = {$
-:97: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#97: FILE: include/uapi/drm/i915_drm.h:1848:
+ * ^I^I^I.param = I915_CONTEXT_PARAM_ENGINES,$
-:98: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#98: FILE: include/uapi/drm/i915_drm.h:1849:
+ * ^I^I^I.value = to_user_pointer(&engines),$
-:99: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#99: FILE: include/uapi/drm/i915_drm.h:1850:
+ * ^I^I^I.size = sizeof(engines),$
-:100: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#100: FILE: include/uapi/drm/i915_drm.h:1851:
+ * ^I^I},$
-:101: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#101: FILE: include/uapi/drm/i915_drm.h:1852:
+ * ^I};$
-:102: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#102: FILE: include/uapi/drm/i915_drm.h:1853:
+ * ^Istruct drm_i915_gem_context_create_ext create = {$
-:103: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#103: FILE: include/uapi/drm/i915_drm.h:1854:
+ * ^I^I.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,$
-:104: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#104: FILE: include/uapi/drm/i915_drm.h:1855:
+ * ^I^I.extensions = to_user_pointer(&p_engines);$
-:105: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#105: FILE: include/uapi/drm/i915_drm.h:1856:
+ * ^I};$
-:107: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#107: FILE: include/uapi/drm/i915_drm.h:1858:
+ * ^Ictx_id = gem_context_create_ext(drm_fd, &create);$
-:109: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#109: FILE: include/uapi/drm/i915_drm.h:1860:
+ * ^I// Now we have created a GEM context with its engine map containing a$
-:110: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#110: FILE: include/uapi/drm/i915_drm.h:1861:
+ * ^I// single virtual engine. Submissions to this slot can go either to$
-:111: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#111: FILE: include/uapi/drm/i915_drm.h:1862:
+ * ^I// vcs0 or vcs1, depending on the load balancing algorithm used inside$
-:112: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#112: FILE: include/uapi/drm/i915_drm.h:1863:
+ * ^I// the driver. The load balancing is dynamic from one batch buffer to$
-:113: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#113: FILE: include/uapi/drm/i915_drm.h:1864:
+ * ^I// another and transparent to userspace.$
-:115: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#115: FILE: include/uapi/drm/i915_drm.h:1866:
+ * ^I...$
-:116: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#116: FILE: include/uapi/drm/i915_drm.h:1867:
+ * ^Iexecbuf.rsvd1 = ctx_id;$
-:117: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#117: FILE: include/uapi/drm/i915_drm.h:1868:
+ * ^Iexecbuf.flags = 0; // Submits to index 0 which is the virtual engine$
-:118: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#118: FILE: include/uapi/drm/i915_drm.h:1869:
+ * ^Igem_execbuf(drm_fd, &execbuf);$
-:147: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#147: FILE: include/uapi/drm/i915_drm.h:1967:
+ * ^II915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {$
-:148: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#148: FILE: include/uapi/drm/i915_drm.h:1968:
+ * ^I^I.engines = { { I915_ENGINE_CLASS_RENDER, 0 },$
-:149: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#149: FILE: include/uapi/drm/i915_drm.h:1969:
+ * ^I^I^I { I915_ENGINE_CLASS_COPY, 0 } }$
-:150: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#150: FILE: include/uapi/drm/i915_drm.h:1970:
+ * ^I};$
-:151: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#151: FILE: include/uapi/drm/i915_drm.h:1971:
+ * ^Istruct drm_i915_gem_context_create_ext_setparam p_engines = {$
-:152: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#152: FILE: include/uapi/drm/i915_drm.h:1972:
+ * ^I^I.base = {$
-:153: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#153: FILE: include/uapi/drm/i915_drm.h:1973:
+ * ^I^I^I.name = I915_CONTEXT_CREATE_EXT_SETPARAM,$
-:154: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#154: FILE: include/uapi/drm/i915_drm.h:1974:
+ * ^I^I},$
-:155: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#155: FILE: include/uapi/drm/i915_drm.h:1975:
+ * ^I^I.param = {$
-:156: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#156: FILE: include/uapi/drm/i915_drm.h:1976:
+ * ^I^I^I.param = I915_CONTEXT_PARAM_ENGINES,$
-:157: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#157: FILE: include/uapi/drm/i915_drm.h:1977:
+ * ^I^I^I.value = to_user_pointer(&engines),$
-:158: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#158: FILE: include/uapi/drm/i915_drm.h:1978:
+ * ^I^I^I.size = sizeof(engines),$
-:159: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#159: FILE: include/uapi/drm/i915_drm.h:1979:
+ * ^I^I},$
-:160: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#160: FILE: include/uapi/drm/i915_drm.h:1980:
+ * ^I};$
-:161: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#161: FILE: include/uapi/drm/i915_drm.h:1981:
+ * ^Istruct drm_i915_gem_context_create_ext create = {$
-:162: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#162: FILE: include/uapi/drm/i915_drm.h:1982:
+ * ^I^I.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,$
-:163: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#163: FILE: include/uapi/drm/i915_drm.h:1983:
+ * ^I^I.extensions = to_user_pointer(&p_engines);$
-:164: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#164: FILE: include/uapi/drm/i915_drm.h:1984:
+ * ^I};$
-:166: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#166: FILE: include/uapi/drm/i915_drm.h:1986:
+ * ^Ictx_id = gem_context_create_ext(drm_fd, &create);$
-:168: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#168: FILE: include/uapi/drm/i915_drm.h:1988:
+ * ^I// We have now created a GEM context with two engines in the map:$
-:169: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#169: FILE: include/uapi/drm/i915_drm.h:1989:
+ * ^I// Index 0 points to rcs0 while index 1 points to bcs0. Other engines$
-:170: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#170: FILE: include/uapi/drm/i915_drm.h:1990:
+ * ^I// will not be accessible from this context.$
-:172: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#172: FILE: include/uapi/drm/i915_drm.h:1992:
+ * ^I...$
-:173: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#173: FILE: include/uapi/drm/i915_drm.h:1993:
+ * ^Iexecbuf.rsvd1 = ctx_id;$
-:174: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#174: FILE: include/uapi/drm/i915_drm.h:1994:
+ * ^Iexecbuf.flags = 0; // Submits to index 0, which is rcs0 for this context$
-:175: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#175: FILE: include/uapi/drm/i915_drm.h:1995:
+ * ^Igem_execbuf(drm_fd, &execbuf);$
-:177: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#177: FILE: include/uapi/drm/i915_drm.h:1997:
+ * ^I...$
-:178: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#178: FILE: include/uapi/drm/i915_drm.h:1998:
+ * ^Iexecbuf.rsvd1 = ctx_id;$
-:179: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#179: FILE: include/uapi/drm/i915_drm.h:1999:
+ * ^Iexecbuf.flags = 1; // Submits to index 0, which is bcs0 for this context$
-:180: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#180: FILE: include/uapi/drm/i915_drm.h:2000:
+ * ^Igem_execbuf(drm_fd, &execbuf);$
-:209: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#209: FILE: include/uapi/drm/i915_drm.h:2515:
+ * ^Istruct drm_i915_query_engine_info *info;$
-:210: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#210: FILE: include/uapi/drm/i915_drm.h:2516:
+ * ^Istruct drm_i915_query_item item = {$
-:211: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#211: FILE: include/uapi/drm/i915_drm.h:2517:
+ * ^I^I.query_id = DRM_I915_QUERY_ENGINE_INFO;$
-:212: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#212: FILE: include/uapi/drm/i915_drm.h:2518:
+ * ^I};$
-:213: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#213: FILE: include/uapi/drm/i915_drm.h:2519:
+ * ^Istruct drm_i915_query query = {$
-:214: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#214: FILE: include/uapi/drm/i915_drm.h:2520:
+ * ^I^I.num_items = 1,$
-:215: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#215: FILE: include/uapi/drm/i915_drm.h:2521:
+ * ^I^I.items_ptr = (uintptr_t)&item,$
-:216: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#216: FILE: include/uapi/drm/i915_drm.h:2522:
+ * ^I};$
-:217: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#217: FILE: include/uapi/drm/i915_drm.h:2523:
+ * ^Iint err, i;$
-:219: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#219: FILE: include/uapi/drm/i915_drm.h:2525:
+ * ^I// First query the size of the blob we need, this needs to be large$
-:220: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#220: FILE: include/uapi/drm/i915_drm.h:2526:
+ * ^I// enough to hold our array of engines. The kernel will fill out the$
-:221: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#221: FILE: include/uapi/drm/i915_drm.h:2527:
+ * ^I// item.length for us, which is the number of bytes we need.$
-:222: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#222: FILE: include/uapi/drm/i915_drm.h:2528:
+ * ^I//$
-:223: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#223: FILE: include/uapi/drm/i915_drm.h:2529:
+ * ^I// Alternatively a large buffer can be allocated straight away enabling$
-:224: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#224: FILE: include/uapi/drm/i915_drm.h:2530:
+ * ^I// querying in one pass, in which case item.length should contain the$
-:225: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#225: FILE: include/uapi/drm/i915_drm.h:2531:
+ * ^I// length of the provided buffer.$
-:226: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#226: FILE: include/uapi/drm/i915_drm.h:2532:
+ * ^Ierr = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);$
-:227: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#227: FILE: include/uapi/drm/i915_drm.h:2533:
+ * ^Iif (err) ...$
-:229: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#229: FILE: include/uapi/drm/i915_drm.h:2535:
+ * ^Iinfo = calloc(1, item.length);$
-:230: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#230: FILE: include/uapi/drm/i915_drm.h:2536:
+ * ^I// Now that we allocated the required number of bytes, we call the ioctl$
-:231: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#231: FILE: include/uapi/drm/i915_drm.h:2537:
+ * ^I// again, this time with the data_ptr pointing to our newly allocated$
-:232: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#232: FILE: include/uapi/drm/i915_drm.h:2538:
+ * ^I// blob, which the kernel can then populate with info on all engines.$
-:233: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#233: FILE: include/uapi/drm/i915_drm.h:2539:
+ * ^Iitem.data_ptr = (uintptr_t)&info,$
-:235: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#235: FILE: include/uapi/drm/i915_drm.h:2541:
+ * ^Ierr = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);$
-:236: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#236: FILE: include/uapi/drm/i915_drm.h:2542:
+ * ^Iif (err) ...$
-:238: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#238: FILE: include/uapi/drm/i915_drm.h:2544:
+ * ^I// We can now access each engine in the array$
-:239: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#239: FILE: include/uapi/drm/i915_drm.h:2545:
+ * ^Ifor (i = 0; i < info->num_engines; i++) {$
-:240: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#240: FILE: include/uapi/drm/i915_drm.h:2546:
+ * ^I^Istruct drm_i915_engine_info einfo = info->engines[i];$
-:241: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#241: FILE: include/uapi/drm/i915_drm.h:2547:
+ * ^I^Iu16 class = einfo.engine.class;$
-:242: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#242: FILE: include/uapi/drm/i915_drm.h:2548:
+ * ^I^Iu16 instance = einfo.engine.instance;$
-:243: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#243: FILE: include/uapi/drm/i915_drm.h:2549:
+ * ^I^I....$
-:244: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#244: FILE: include/uapi/drm/i915_drm.h:2550:
+ * ^I}$
-:246: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#246: FILE: include/uapi/drm/i915_drm.h:2552:
+ * ^Ifree(info);$
total: 0 errors, 99 warnings, 0 checks, 231 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Document the Virtual Engine uAPI (rev4)
2021-06-18 15:00 ` [Intel-gfx] " Tvrtko Ursulin
(?)
(?)
@ 2021-06-18 17:08 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-18 17:08 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3146 bytes --]
== Series Details ==
Series: drm/i915: Document the Virtual Engine uAPI (rev4)
URL : https://patchwork.freedesktop.org/series/91406/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10242 -> Patchwork_20413
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/index.html
Known issues
------------
Here are the changes found in Patchwork_20413 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [PASS][1] -> [INCOMPLETE][2] ([i915#146] / [i915#198])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][3] -> [INCOMPLETE][4] ([i915#2782])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][5] -> [FAIL][6] ([i915#1372])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
#### Possible fixes ####
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][7] ([i915#2867]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/fi-tgl-dsi/igt@i915_selftest@live@perf.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/fi-tgl-dsi/igt@i915_selftest@live@perf.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
Participating hosts (42 -> 37)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10242 -> Patchwork_20413
CI-20190529: 20190529
CI_DRM_10242: a31069c62e8586aa92907539ab948412c1d5f5a0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6112: a17cc0c5d096fabfd516848c114bc411e11130f4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20413: 043a7f21361bce3ffeaa9182d86a9ba21a157b28 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
043a7f21361b drm/i915: Document the Virtual Engine uAPI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/index.html
[-- Attachment #1.2: Type: text/html, Size: 3840 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Document the Virtual Engine uAPI (rev4)
2021-06-18 15:00 ` [Intel-gfx] " Tvrtko Ursulin
` (2 preceding siblings ...)
(?)
@ 2021-06-18 19:13 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2021-06-18 19:13 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 27810 bytes --]
== Series Details ==
Series: drm/i915: Document the Virtual Engine uAPI (rev4)
URL : https://patchwork.freedesktop.org/series/91406/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10242_full -> Patchwork_20413_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20413_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20413_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20413_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_big_fb@x-tiled-8bpp-rotate-0:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk3/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk9/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
New tests
---------
New tests have been introduced between CI_DRM_10242_full and Patchwork_20413_full:
### New IGT tests (2) ###
* igt@kms_atomic_transition@plane-all-transition@vga-1-pipe-a:
- Statuses : 1 pass(s)
- Exec time: [1.30] s
* igt@kms_atomic_transition@plane-all-transition@vga-1-pipe-b:
- Statuses : 1 pass(s)
- Exec time: [1.37] s
Known issues
------------
Here are the changes found in Patchwork_20413_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@bb-with-allocator:
- shard-skl: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl9/igt@api_intel_bb@bb-with-allocator.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl2/igt@api_intel_bb@bb-with-allocator.html
* igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-snb7/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2410])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-tglb3/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_eio@in-flight-1us:
- shard-skl: [PASS][8] -> [TIMEOUT][9] ([i915#3063])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl2/igt@gem_eio@in-flight-1us.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl6/igt@gem_eio@in-flight-1us.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
- shard-apl: [PASS][12] -> [SKIP][13] ([fdo#109271])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl7/igt@gem_exec_fair@basic-none-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][16] -> [SKIP][17] ([fdo#109271])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][18] -> [FAIL][19] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2842])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-sync@rcs0:
- shard-skl: NOTRUN -> [SKIP][21] ([fdo#109271]) +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl10/igt@gem_exec_fair@basic-sync@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][22] -> [FAIL][23] ([i915#2849])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb4/igt@gem_exec_fair@basic-throttle@rcs0.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_gttfill@all:
- shard-glk: [PASS][24] -> [DMESG-WARN][25] ([i915#118] / [i915#95])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk2/igt@gem_exec_gttfill@all.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk4/igt@gem_exec_gttfill@all.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][26] ([i915#3633])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb4/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_mmap_gtt@big-copy:
- shard-skl: [PASS][27] -> [FAIL][28] ([i915#307])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl8/igt@gem_mmap_gtt@big-copy.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl3/igt@gem_mmap_gtt@big-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][29] ([i915#2658])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl7/igt@gem_pread@exhaustion.html
- shard-snb: NOTRUN -> [WARN][30] ([i915#2658])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-snb7/igt@gem_pread@exhaustion.html
* igt@gem_userptr_blits@input-checking:
- shard-snb: NOTRUN -> [DMESG-WARN][31] ([i915#3002])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-snb6/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][32] -> [DMESG-WARN][33] ([i915#1436] / [i915#716])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl1/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271]) +230 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-snb7/igt@gen9_exec_parse@batch-invalid-length.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-iclb: [PASS][35] -> [FAIL][36] ([i915#3601])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb5/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_chamelium@dp-hpd-storm:
- shard-glk: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk7/igt@kms_chamelium@dp-hpd-storm.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +20 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl1/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-snb: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +10 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-snb7/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][40] ([i915#1319]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [PASS][41] -> [FAIL][42] ([i915#2346])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#533]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl6/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@plain-flip-fb-recreate@c-edp1:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#2122])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#2642])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-glk: NOTRUN -> [SKIP][47] ([fdo#109271]) +51 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [PASS][48] -> [DMESG-WARN][49] ([i915#180]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][50] ([fdo#108145] / [i915#265])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][51] ([fdo#108145] / [i915#265])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][52] ([i915#265])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-glk: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#658]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#658]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl8/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#109441]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb2/igt@kms_psr@psr2_basic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb7/igt@kms_psr@psr2_basic.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][57] ([i915#180])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [PASS][58] -> [INCOMPLETE][59] ([i915#155] / [i915#2828] / [i915#794])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2437])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl3/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-glk: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2437])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk7/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][62] -> [FAIL][63] ([i915#1542])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk2/igt@perf@polling-parameterized.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk3/igt@perf@polling-parameterized.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271]) +205 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl8/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@prime_vgem@sync@rcs0:
- shard-tglb: [PASS][65] -> [INCOMPLETE][66] ([i915#409])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-tglb2/igt@prime_vgem@sync@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-tglb3/igt@prime_vgem@sync@rcs0.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2994])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl7/igt@sysfs_clients@fair-3.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][68] ([i915#2842]) -> [PASS][69] +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [FAIL][70] ([i915#2842]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-tglb7/igt@gem_exec_fair@basic-pace@vecs0.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-tglb1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][72] ([i915#2842]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_mmap_gtt@big-copy-odd:
- shard-skl: [FAIL][74] ([i915#307]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl7/igt@gem_mmap_gtt@big-copy-odd.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl5/igt@gem_mmap_gtt@big-copy-odd.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][76] ([i915#454]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][78] ([i915#180]) -> [PASS][79] +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][80] ([fdo#108145] / [i915#265]) -> [PASS][81] +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-glk: [INCOMPLETE][82] -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk5/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-glk: [FAIL][84] ([i915#43]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk7/igt@kms_vblank@pipe-b-accuracy-idle.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk1/igt@kms_vblank@pipe-b-accuracy-idle.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: [FAIL][86] ([i915#1731]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl6/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl1/igt@sysfs_heartbeat_interval@mixed@vcs0.html
* igt@sysfs_heartbeat_interval@mixed@vecs0:
- shard-glk: [FAIL][88] ([i915#1731]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk2/igt@sysfs_heartbeat_interval@mixed@vecs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk4/igt@sysfs_heartbeat_interval@mixed@vecs0.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][90] ([i915#1804] / [i915#2684]) -> [WARN][91] ([i915#2684])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-glk: [FAIL][92] ([i915#49]) -> [FAIL][93] ([i915#2546] / [i915#49])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-glk6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-glk6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][94] ([i915#2920]) -> [SKIP][95] ([i915#658]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-iclb: [SKIP][96] ([i915#658]) -> [SKIP][97] ([i915#2920]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][98], [FAIL][99]) ([i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][100], [FAIL][101]) ([i915#3002] / [i915#3363])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-kbl4/igt@runner@aborted.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-kbl6/igt@runner@aborted.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-kbl1/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-kbl3/igt@runner@aborted.html
- shard-apl: ([FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl7/igt@runner@aborted.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl1/igt@runner@aborted.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl1/igt@runner@aborted.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl1/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl3/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-apl3/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl3/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl1/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl1/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl2/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-apl3/igt@runner@aborted.html
- shard-tglb: ([FAIL][113], [FAIL][114]) ([i915#3002]) -> ([FAIL][115], [FAIL][116], [FAIL][117]) ([i915#2426] / [i915#3002] / [i915#409])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-tglb5/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-tglb8/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-tglb1/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-tglb8/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-tglb3/igt@runner@aborted.html
- shard-skl: ([FAIL][118], [FAIL][119]) ([i915#3002] / [i915#3363]) -> ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123]) ([i915#1436] / [i915#1814] / [i915#2029] / [i915#3002] / [i915#3363])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl9/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10242/shard-skl10/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl3/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl2/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl1/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/shard-skl7/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2828]: https://gitlab.freedesktop.org/drm/intel/issues/2828
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3601]: https://gitlab.freedesktop.org/drm/intel/issues/3601
[i915#3633]: https://gitlab.freedesktop.org/drm/intel/issues/3633
[i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 10)
------------------------------
Missing (1): pig-snb-2600
Build changes
-------------
* Linux: CI_DRM_10242 -> Patchwork_20413
CI-20190529: 20190529
CI_DRM_10242: a31069c62e8586aa92907539ab948412c1d5f5a0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6112: a17cc0c5d096fabfd516848c114bc411e11130f4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20413: 043a7f21361bce3ffeaa9182d86a9ba21a157b28 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20413/index.html
[-- Attachment #1.2: Type: text/html, Size: 34472 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4] drm/i915: Document the Virtual Engine uAPI
2021-06-18 15:00 ` [Intel-gfx] " Tvrtko Ursulin
@ 2021-06-18 20:46 ` Daniel Vetter
-1 siblings, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2021-06-18 20:46 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx, dri-devel, Tvrtko Ursulin
On Fri, Jun 18, 2021 at 5:00 PM Tvrtko Ursulin
<tvrtko.ursulin@linux.intel.com> wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> A little bit of documentation covering the topics of engine discovery,
> context engine maps and virtual engines. It is not very detailed but
> supposed to be a starting point of giving a brief high level overview of
> general principles and intended use cases.
>
> v2:
> * Have the text in uapi header and link from there.
>
> v4:
> * Link from driver-uapi.rst.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
Apologies for the confusion :-/
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imo just push, it's good stuff at the right place, and it's much
easier to polish&integrate docs better once something is there. I've
read through it and it looks all nice.
-Daniel
> ---
> Documentation/gpu/driver-uapi.rst | 21 ++++
> include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++
> 2 files changed, 209 insertions(+)
>
> diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst
> index 4411e6919a3d..27d0fbe33e87 100644
> --- a/Documentation/gpu/driver-uapi.rst
> +++ b/Documentation/gpu/driver-uapi.rst
> @@ -5,4 +5,25 @@ DRM Driver uAPI
> drm/i915 uAPI
> =============
>
> +Engine Discovery uAPI
> +---------------------
> +
> +.. kernel-doc:: include/uapi/drm/i915_drm.h
> + :doc: Engine Discovery uAPI
> +
> +Context Engine Map uAPI
> +-----------------------
> +
> +.. kernel-doc:: include/uapi/drm/i915_drm.h
> + :doc: Context Engine Map uAPI
> +
> +Virtual Engine uAPI
> +-------------------
> +
> +.. kernel-doc:: include/uapi/drm/i915_drm.h
> + :doc: Virtual Engine uAPI
> +
> +i915_drm.h
> +----------
> .. kernel-doc:: include/uapi/drm/i915_drm.h
> + :internal:
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index a1cb4aa035a9..2f70c48567c0 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu {
> __u32 rsvd;
> };
>
> +/**
> + * DOC: Virtual Engine uAPI
> + *
> + * Virtual engine is a concept where userspace is able to configure a set of
> + * physical engines, submit a batch buffer, and let the driver execute it on any
> + * engine from the set as it sees fit.
> + *
> + * This is primarily useful on parts which have multiple instances of a same
> + * class engine, like for example GT3+ Skylake parts with their two VCS engines.
> + *
> + * For instance userspace can enumerate all engines of a certain class using the
> + * previously described `Engine Discovery uAPI`_. After that userspace can
> + * create a GEM context with a placeholder slot for the virtual engine (using
> + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
> + * and instance respectively) and finally using the
> + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
> + * the same reserved slot.
> + *
> + * Example of creating a virtual engine and submitting a batch buffer to it:
> + *
> + * .. code-block:: C
> + *
> + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
> + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
> + * .engine_index = 0, // Place this virtual engine into engine map slot 0
> + * .num_siblings = 2,
> + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
> + * { I915_ENGINE_CLASS_VIDEO, 1 }, },
> + * };
> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
> + * .engines = { { I915_ENGINE_CLASS_INVALID,
> + * I915_ENGINE_CLASS_INVALID_NONE } },
> + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
> + * };
> + * struct drm_i915_gem_context_create_ext_setparam p_engines = {
> + * .base = {
> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> + * },
> + * .param = {
> + * .param = I915_CONTEXT_PARAM_ENGINES,
> + * .value = to_user_pointer(&engines),
> + * .size = sizeof(engines),
> + * },
> + * };
> + * struct drm_i915_gem_context_create_ext create = {
> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> + * .extensions = to_user_pointer(&p_engines);
> + * };
> + *
> + * ctx_id = gem_context_create_ext(drm_fd, &create);
> + *
> + * // Now we have created a GEM context with its engine map containing a
> + * // single virtual engine. Submissions to this slot can go either to
> + * // vcs0 or vcs1, depending on the load balancing algorithm used inside
> + * // the driver. The load balancing is dynamic from one batch buffer to
> + * // another and transparent to userspace.
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
> + * gem_execbuf(drm_fd, &execbuf);
> + */
> +
> /*
> * i915_context_engines_load_balance:
> *
> @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond {
> struct i915_engine_class_instance engines[N__]; \
> } __attribute__((packed)) name__
>
> +/**
> + * DOC: Context Engine Map uAPI
> + *
> + * Context engine map is a new way of addressing engines when submitting batch-
> + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
> + * inside the flags field of `struct drm_i915_gem_execbuffer2`.
> + *
> + * To use it created GEM contexts need to be configured with a list of engines
> + * the user is intending to submit to. This is accomplished using the
> + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
> + * i915_context_param_engines`.
> + *
> + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
> + * configured map.
> + *
> + * Example of creating such context and submitting against it:
> + *
> + * .. code-block:: C
> + *
> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
> + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
> + * { I915_ENGINE_CLASS_COPY, 0 } }
> + * };
> + * struct drm_i915_gem_context_create_ext_setparam p_engines = {
> + * .base = {
> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> + * },
> + * .param = {
> + * .param = I915_CONTEXT_PARAM_ENGINES,
> + * .value = to_user_pointer(&engines),
> + * .size = sizeof(engines),
> + * },
> + * };
> + * struct drm_i915_gem_context_create_ext create = {
> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> + * .extensions = to_user_pointer(&p_engines);
> + * };
> + *
> + * ctx_id = gem_context_create_ext(drm_fd, &create);
> + *
> + * // We have now created a GEM context with two engines in the map:
> + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
> + * // will not be accessible from this context.
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
> + * gem_execbuf(drm_fd, &execbuf);
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
> + * gem_execbuf(drm_fd, &execbuf);
> + */
> +
> struct i915_context_param_engines {
> __u64 extensions; /* linked chain of extension blocks, 0 terminates */
> #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
> @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info {
> __u8 data[];
> };
>
> +/**
> + * DOC: Engine Discovery uAPI
> + *
> + * Engine discovery uAPI is a way of enumerating physical engines present in a
> + * GPU associated with an open i915 DRM file descriptor. This supersedes the old
> + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
> + * `I915_PARAM_HAS_BLT`.
> + *
> + * The need for this interface came starting with Icelake and newer GPUs, which
> + * started to establish a pattern of having multiple engines of a same class,
> + * where not all instances were always completely functionally equivalent.
> + *
> + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
> + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
> + *
> + * Example for getting the list of engines:
> + *
> + * .. code-block:: C
> + *
> + * struct drm_i915_query_engine_info *info;
> + * struct drm_i915_query_item item = {
> + * .query_id = DRM_I915_QUERY_ENGINE_INFO;
> + * };
> + * struct drm_i915_query query = {
> + * .num_items = 1,
> + * .items_ptr = (uintptr_t)&item,
> + * };
> + * int err, i;
> + *
> + * // First query the size of the blob we need, this needs to be large
> + * // enough to hold our array of engines. The kernel will fill out the
> + * // item.length for us, which is the number of bytes we need.
> + * //
> + * // Alternatively a large buffer can be allocated straight away enabling
> + * // querying in one pass, in which case item.length should contain the
> + * // length of the provided buffer.
> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + * if (err) ...
> + *
> + * info = calloc(1, item.length);
> + * // Now that we allocated the required number of bytes, we call the ioctl
> + * // again, this time with the data_ptr pointing to our newly allocated
> + * // blob, which the kernel can then populate with info on all engines.
> + * item.data_ptr = (uintptr_t)&info,
> + *
> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + * if (err) ...
> + *
> + * // We can now access each engine in the array
> + * for (i = 0; i < info->num_engines; i++) {
> + * struct drm_i915_engine_info einfo = info->engines[i];
> + * u16 class = einfo.engine.class;
> + * u16 instance = einfo.engine.instance;
> + * ....
> + * }
> + *
> + * free(info);
> + *
> + * Each of the enumerated engines, apart from being defined by its class and
> + * instance (see `struct i915_engine_class_instance`), also can have flags and
> + * capabilities defined as documented in i915_drm.h.
> + *
> + * For instance video engines which support HEVC encoding will have the
> + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
> + *
> + * Engine discovery only fully comes to its own when combined with the new way
> + * of addressing engines when submitting batch buffers using contexts with
> + * engine maps configured.
> + */
> +
> /**
> * struct drm_i915_engine_info
> *
> --
> 2.30.2
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915: Document the Virtual Engine uAPI
@ 2021-06-18 20:46 ` Daniel Vetter
0 siblings, 0 replies; 9+ messages in thread
From: Daniel Vetter @ 2021-06-18 20:46 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx, dri-devel
On Fri, Jun 18, 2021 at 5:00 PM Tvrtko Ursulin
<tvrtko.ursulin@linux.intel.com> wrote:
>
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> A little bit of documentation covering the topics of engine discovery,
> context engine maps and virtual engines. It is not very detailed but
> supposed to be a starting point of giving a brief high level overview of
> general principles and intended use cases.
>
> v2:
> * Have the text in uapi header and link from there.
>
> v4:
> * Link from driver-uapi.rst.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniel Vetter <daniel@ffwll.ch>
Apologies for the confusion :-/
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Imo just push, it's good stuff at the right place, and it's much
easier to polish&integrate docs better once something is there. I've
read through it and it looks all nice.
-Daniel
> ---
> Documentation/gpu/driver-uapi.rst | 21 ++++
> include/uapi/drm/i915_drm.h | 188 ++++++++++++++++++++++++++++++
> 2 files changed, 209 insertions(+)
>
> diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst
> index 4411e6919a3d..27d0fbe33e87 100644
> --- a/Documentation/gpu/driver-uapi.rst
> +++ b/Documentation/gpu/driver-uapi.rst
> @@ -5,4 +5,25 @@ DRM Driver uAPI
> drm/i915 uAPI
> =============
>
> +Engine Discovery uAPI
> +---------------------
> +
> +.. kernel-doc:: include/uapi/drm/i915_drm.h
> + :doc: Engine Discovery uAPI
> +
> +Context Engine Map uAPI
> +-----------------------
> +
> +.. kernel-doc:: include/uapi/drm/i915_drm.h
> + :doc: Context Engine Map uAPI
> +
> +Virtual Engine uAPI
> +-------------------
> +
> +.. kernel-doc:: include/uapi/drm/i915_drm.h
> + :doc: Virtual Engine uAPI
> +
> +i915_drm.h
> +----------
> .. kernel-doc:: include/uapi/drm/i915_drm.h
> + :internal:
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index a1cb4aa035a9..2f70c48567c0 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1806,6 +1806,69 @@ struct drm_i915_gem_context_param_sseu {
> __u32 rsvd;
> };
>
> +/**
> + * DOC: Virtual Engine uAPI
> + *
> + * Virtual engine is a concept where userspace is able to configure a set of
> + * physical engines, submit a batch buffer, and let the driver execute it on any
> + * engine from the set as it sees fit.
> + *
> + * This is primarily useful on parts which have multiple instances of a same
> + * class engine, like for example GT3+ Skylake parts with their two VCS engines.
> + *
> + * For instance userspace can enumerate all engines of a certain class using the
> + * previously described `Engine Discovery uAPI`_. After that userspace can
> + * create a GEM context with a placeholder slot for the virtual engine (using
> + * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
> + * and instance respectively) and finally using the
> + * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
> + * the same reserved slot.
> + *
> + * Example of creating a virtual engine and submitting a batch buffer to it:
> + *
> + * .. code-block:: C
> + *
> + * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
> + * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
> + * .engine_index = 0, // Place this virtual engine into engine map slot 0
> + * .num_siblings = 2,
> + * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
> + * { I915_ENGINE_CLASS_VIDEO, 1 }, },
> + * };
> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
> + * .engines = { { I915_ENGINE_CLASS_INVALID,
> + * I915_ENGINE_CLASS_INVALID_NONE } },
> + * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
> + * };
> + * struct drm_i915_gem_context_create_ext_setparam p_engines = {
> + * .base = {
> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> + * },
> + * .param = {
> + * .param = I915_CONTEXT_PARAM_ENGINES,
> + * .value = to_user_pointer(&engines),
> + * .size = sizeof(engines),
> + * },
> + * };
> + * struct drm_i915_gem_context_create_ext create = {
> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> + * .extensions = to_user_pointer(&p_engines);
> + * };
> + *
> + * ctx_id = gem_context_create_ext(drm_fd, &create);
> + *
> + * // Now we have created a GEM context with its engine map containing a
> + * // single virtual engine. Submissions to this slot can go either to
> + * // vcs0 or vcs1, depending on the load balancing algorithm used inside
> + * // the driver. The load balancing is dynamic from one batch buffer to
> + * // another and transparent to userspace.
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
> + * gem_execbuf(drm_fd, &execbuf);
> + */
> +
> /*
> * i915_context_engines_load_balance:
> *
> @@ -1882,6 +1945,61 @@ struct i915_context_engines_bond {
> struct i915_engine_class_instance engines[N__]; \
> } __attribute__((packed)) name__
>
> +/**
> + * DOC: Context Engine Map uAPI
> + *
> + * Context engine map is a new way of addressing engines when submitting batch-
> + * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
> + * inside the flags field of `struct drm_i915_gem_execbuffer2`.
> + *
> + * To use it created GEM contexts need to be configured with a list of engines
> + * the user is intending to submit to. This is accomplished using the
> + * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
> + * i915_context_param_engines`.
> + *
> + * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
> + * configured map.
> + *
> + * Example of creating such context and submitting against it:
> + *
> + * .. code-block:: C
> + *
> + * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
> + * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
> + * { I915_ENGINE_CLASS_COPY, 0 } }
> + * };
> + * struct drm_i915_gem_context_create_ext_setparam p_engines = {
> + * .base = {
> + * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
> + * },
> + * .param = {
> + * .param = I915_CONTEXT_PARAM_ENGINES,
> + * .value = to_user_pointer(&engines),
> + * .size = sizeof(engines),
> + * },
> + * };
> + * struct drm_i915_gem_context_create_ext create = {
> + * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
> + * .extensions = to_user_pointer(&p_engines);
> + * };
> + *
> + * ctx_id = gem_context_create_ext(drm_fd, &create);
> + *
> + * // We have now created a GEM context with two engines in the map:
> + * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
> + * // will not be accessible from this context.
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
> + * gem_execbuf(drm_fd, &execbuf);
> + *
> + * ...
> + * execbuf.rsvd1 = ctx_id;
> + * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
> + * gem_execbuf(drm_fd, &execbuf);
> + */
> +
> struct i915_context_param_engines {
> __u64 extensions; /* linked chain of extension blocks, 0 terminates */
> #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
> @@ -2375,6 +2493,76 @@ struct drm_i915_query_topology_info {
> __u8 data[];
> };
>
> +/**
> + * DOC: Engine Discovery uAPI
> + *
> + * Engine discovery uAPI is a way of enumerating physical engines present in a
> + * GPU associated with an open i915 DRM file descriptor. This supersedes the old
> + * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
> + * `I915_PARAM_HAS_BLT`.
> + *
> + * The need for this interface came starting with Icelake and newer GPUs, which
> + * started to establish a pattern of having multiple engines of a same class,
> + * where not all instances were always completely functionally equivalent.
> + *
> + * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
> + * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
> + *
> + * Example for getting the list of engines:
> + *
> + * .. code-block:: C
> + *
> + * struct drm_i915_query_engine_info *info;
> + * struct drm_i915_query_item item = {
> + * .query_id = DRM_I915_QUERY_ENGINE_INFO;
> + * };
> + * struct drm_i915_query query = {
> + * .num_items = 1,
> + * .items_ptr = (uintptr_t)&item,
> + * };
> + * int err, i;
> + *
> + * // First query the size of the blob we need, this needs to be large
> + * // enough to hold our array of engines. The kernel will fill out the
> + * // item.length for us, which is the number of bytes we need.
> + * //
> + * // Alternatively a large buffer can be allocated straight away enabling
> + * // querying in one pass, in which case item.length should contain the
> + * // length of the provided buffer.
> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + * if (err) ...
> + *
> + * info = calloc(1, item.length);
> + * // Now that we allocated the required number of bytes, we call the ioctl
> + * // again, this time with the data_ptr pointing to our newly allocated
> + * // blob, which the kernel can then populate with info on all engines.
> + * item.data_ptr = (uintptr_t)&info,
> + *
> + * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
> + * if (err) ...
> + *
> + * // We can now access each engine in the array
> + * for (i = 0; i < info->num_engines; i++) {
> + * struct drm_i915_engine_info einfo = info->engines[i];
> + * u16 class = einfo.engine.class;
> + * u16 instance = einfo.engine.instance;
> + * ....
> + * }
> + *
> + * free(info);
> + *
> + * Each of the enumerated engines, apart from being defined by its class and
> + * instance (see `struct i915_engine_class_instance`), also can have flags and
> + * capabilities defined as documented in i915_drm.h.
> + *
> + * For instance video engines which support HEVC encoding will have the
> + * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
> + *
> + * Engine discovery only fully comes to its own when combined with the new way
> + * of addressing engines when submitting batch buffers using contexts with
> + * engine maps configured.
> + */
> +
> /**
> * struct drm_i915_engine_info
> *
> --
> 2.30.2
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v4] drm/i915: Document the Virtual Engine uAPI
2021-06-18 20:46 ` [Intel-gfx] " Daniel Vetter
@ 2021-06-21 8:30 ` Tvrtko Ursulin
-1 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2021-06-21 8:30 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, dri-devel, Tvrtko Ursulin
On 18/06/2021 21:46, Daniel Vetter wrote:
> On Fri, Jun 18, 2021 at 5:00 PM Tvrtko Ursulin
> <tvrtko.ursulin@linux.intel.com> wrote:
>>
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> A little bit of documentation covering the topics of engine discovery,
>> context engine maps and virtual engines. It is not very detailed but
>> supposed to be a starting point of giving a brief high level overview of
>> general principles and intended use cases.
>>
>> v2:
>> * Have the text in uapi header and link from there.
>>
>> v4:
>> * Link from driver-uapi.rst.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Daniel Vetter <daniel@ffwll.ch>
>
> Apologies for the confusion :-/
>
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Imo just push, it's good stuff at the right place, and it's much
> easier to polish&integrate docs better once something is there. I've
> read through it and it looks all nice.
Okay pushed, thanks.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915: Document the Virtual Engine uAPI
@ 2021-06-21 8:30 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2021-06-21 8:30 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, dri-devel
On 18/06/2021 21:46, Daniel Vetter wrote:
> On Fri, Jun 18, 2021 at 5:00 PM Tvrtko Ursulin
> <tvrtko.ursulin@linux.intel.com> wrote:
>>
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> A little bit of documentation covering the topics of engine discovery,
>> context engine maps and virtual engines. It is not very detailed but
>> supposed to be a starting point of giving a brief high level overview of
>> general principles and intended use cases.
>>
>> v2:
>> * Have the text in uapi header and link from there.
>>
>> v4:
>> * Link from driver-uapi.rst.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Daniel Vetter <daniel@ffwll.ch>
>
> Apologies for the confusion :-/
>
> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Imo just push, it's good stuff at the right place, and it's much
> easier to polish&integrate docs better once something is there. I've
> read through it and it looks all nice.
Okay pushed, thanks.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-06-21 8:30 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-18 15:00 [PATCH v4] drm/i915: Document the Virtual Engine uAPI Tvrtko Ursulin
2021-06-18 15:00 ` [Intel-gfx] " Tvrtko Ursulin
2021-06-18 16:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Document the Virtual Engine uAPI (rev4) Patchwork
2021-06-18 17:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-18 19:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-06-18 20:46 ` [PATCH v4] drm/i915: Document the Virtual Engine uAPI Daniel Vetter
2021-06-18 20:46 ` [Intel-gfx] " Daniel Vetter
2021-06-21 8:30 ` Tvrtko Ursulin
2021-06-21 8:30 ` [Intel-gfx] " Tvrtko Ursulin
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.