[PATCH] rockchip: px30: sync serial flash controller bindings with mainline

[PATCH] rockchip: px30: sync serial flash controller bindings with mainline

[Chris Morgan]

From: Chris Morgan <macromorgan@hotmail.com>

The devicetree submitted and approved for the mainline linux kernel is
slightly different than the one present here. This syncs both
devicetrees (for the Rockchip SFC node at least) present on the PX30
and the Odroid Go Advance. Changes include renaming the flash node,
reordering the values in the SFC node for the rk3326-odroid-go2,
changing the name of the cs pinctrl node to cs0, and updating the
u-boot specific tree to utilize the new flash node value.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 arch/arm/dts/px30.dtsi                     | 4 ++--
 arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 2 +-
 arch/arm/dts/rk3326-odroid-go2.dts         | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index aaa8ae2235..ef706486dc 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -967,7 +967,7 @@
 		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
 		clock-names = "clk_sfc", "hclk_sfc";
 		pinctrl-names = "default";
-		pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
+		pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
 		power-domains = <&power PX30_PD_MMC_NAND>;
 		status = "disabled";
 	};
@@ -1953,7 +1953,7 @@
 					<1 RK_PA1 3 &pcfg_pull_none>;
 			};
 
-			sfc_cs: sfc-cs {
+			sfc_cs0: sfc-cs0 {
 				rockchip,pins =
 					<1 RK_PA4 3 &pcfg_pull_none>;
 			};
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 741e8dd935..0990005a15 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -70,7 +70,7 @@
 	u-boot,dm-pre-reloc;
 };
 
-&spi_flash {
+&{/sfc@ff3a0000/flash@0} {
 	u-boot,dm-pre-reloc;
 };
 
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 6f91f5040b..4e3dceecbe 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -618,18 +618,18 @@
 };
 
 &sfc {
+	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+	pinctrl-names = "default";
 	#address-cells = <1>;
 	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
 	status = "okay";
 
-	spi_flash: xt25f128b@0 {
+	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <108000000>;
 		spi-rx-bus-width = <2>;
-		spi-tx-bus-width = <2>;
+		spi-tx-bus-width = <1>;
 	};
 };
 
-- 
2.25.1

Re: [PATCH] rockchip: px30: sync serial flash controller bindings with mainline

[Kever Yang]

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>


Thanks,
- Kever

Chris Morgan <macroalpha82@gmail.com> 于2021年8月21日周六 上午9:47写道：
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> The devicetree submitted and approved for the mainline linux kernel is
> slightly different than the one present here. This syncs both
> devicetrees (for the Rockchip SFC node at least) present on the PX30
> and the Odroid Go Advance. Changes include renaming the flash node,
> reordering the values in the SFC node for the rk3326-odroid-go2,
> changing the name of the cs pinctrl node to cs0, and updating the
> u-boot specific tree to utilize the new flash node value.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> ---
>  arch/arm/dts/px30.dtsi                     | 4 ++--
>  arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 2 +-
>  arch/arm/dts/rk3326-odroid-go2.dts         | 8 ++++----
>  3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
> index aaa8ae2235..ef706486dc 100644
> --- a/arch/arm/dts/px30.dtsi
> +++ b/arch/arm/dts/px30.dtsi
> @@ -967,7 +967,7 @@
>                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
>                 clock-names = "clk_sfc", "hclk_sfc";
>                 pinctrl-names = "default";
> -               pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
> +               pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
>                 power-domains = <&power PX30_PD_MMC_NAND>;
>                 status = "disabled";
>         };
> @@ -1953,7 +1953,7 @@
>                                         <1 RK_PA1 3 &pcfg_pull_none>;
>                         };
>
> -                       sfc_cs: sfc-cs {
> +                       sfc_cs0: sfc-cs0 {
>                                 rockchip,pins =
>                                         <1 RK_PA4 3 &pcfg_pull_none>;
>                         };
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> index 741e8dd935..0990005a15 100644
> --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -70,7 +70,7 @@
>         u-boot,dm-pre-reloc;
>  };
>
> -&spi_flash {
> +&{/sfc@ff3a0000/flash@0} {
>         u-boot,dm-pre-reloc;
>  };
>
> diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
> index 6f91f5040b..4e3dceecbe 100644
> --- a/arch/arm/dts/rk3326-odroid-go2.dts
> +++ b/arch/arm/dts/rk3326-odroid-go2.dts
> @@ -618,18 +618,18 @@
>  };
>
>  &sfc {
> +       pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
> +       pinctrl-names = "default";
>         #address-cells = <1>;
>         #size-cells = <0>;
> -       pinctrl-names = "default";
> -       pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
>         status = "okay";
>
> -       spi_flash: xt25f128b@0 {
> +       flash@0 {
>                 compatible = "jedec,spi-nor";
>                 reg = <0>;
>                 spi-max-frequency = <108000000>;
>                 spi-rx-bus-width = <2>;
> -               spi-tx-bus-width = <2>;
> +               spi-tx-bus-width = <1>;
>         };
>  };
>
> --
> 2.25.1
>