* [PATCH 01/23] nv50: import updated g80_defs.xml.h from rnndb
@ 2016-02-15 5:38 Ben Skeggs
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/g80_defs.xml.h | 279 ++++++++++++++++++++++++
1 file changed, 279 insertions(+)
create mode 100644 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h b/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
new file mode 100644
index 0000000..5d40624
--- /dev/null
+++ b/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
@@ -0,0 +1,279 @@
+#ifndef G80_DEFS_XML
+#define G80_DEFS_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/envytools/envytools/
+git clone https://github.com/envytools/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/skeggsb/git/envytools/rnndb/../rnndb/graph/g80_texture.xml ( 18837 bytes, from 2016-01-14 23:54:22)
+- /home/skeggsb/git/envytools/rnndb/copyright.xml ( 6456 bytes, from 2015-09-10 02:57:40)
+- /home/skeggsb/git/envytools/rnndb/nvchipsets.xml ( 2908 bytes, from 2016-02-02 23:45:00)
+- /home/skeggsb/git/envytools/rnndb/g80_defs.xml ( 21739 bytes, from 2016-02-04 00:29:42)
+- /home/skeggsb/git/envytools/rnndb/nv_defs.xml ( 5388 bytes, from 2016-01-14 23:54:22)
+
+Copyright (C) 2006-2016 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define G80_VSTATUS_IDLE 0x00000000
+#define G80_VSTATUS_BUSY 0x00000001
+#define G80_VSTATUS_UNK2 0x00000002
+#define G80_VSTATUS_WAITING 0x00000003
+#define G80_VSTATUS_BLOCKED 0x00000005
+#define G80_VSTATUS_FAULTED 0x00000006
+#define G80_VSTATUS_PAUSED 0x00000007
+#define G80_TIC_SOURCE_ZERO 0x00000000
+#define G80_TIC_SOURCE_R 0x00000002
+#define G80_TIC_SOURCE_G 0x00000003
+#define G80_TIC_SOURCE_B 0x00000004
+#define G80_TIC_SOURCE_A 0x00000005
+#define G80_TIC_SOURCE_ONE_INT 0x00000006
+#define G80_TIC_SOURCE_ONE_FLOAT 0x00000007
+#define G80_TIC_TYPE_SNORM 0x00000001
+#define G80_TIC_TYPE_UNORM 0x00000002
+#define G80_TIC_TYPE_SINT 0x00000003
+#define G80_TIC_TYPE_UINT 0x00000004
+#define G80_TIC_TYPE_SNORM_FORCE_FP16 0x00000005
+#define G80_TIC_TYPE_UNORM_FORCE_FP16 0x00000006
+#define G80_TIC_TYPE_FLOAT 0x00000007
+#define G80_SURFACE_FORMAT_BITMAP 0x0000001c
+#define G80_SURFACE_FORMAT_UNK1D 0x0000001d
+#define G80_SURFACE_FORMAT_RGBA32_FLOAT 0x000000c0
+#define G80_SURFACE_FORMAT_RGBA32_SINT 0x000000c1
+#define G80_SURFACE_FORMAT_RGBA32_UINT 0x000000c2
+#define G80_SURFACE_FORMAT_RGBX32_FLOAT 0x000000c3
+#define G80_SURFACE_FORMAT_RGBX32_SINT 0x000000c4
+#define G80_SURFACE_FORMAT_RGBX32_UINT 0x000000c5
+#define G80_SURFACE_FORMAT_RGBA16_UNORM 0x000000c6
+#define G80_SURFACE_FORMAT_RGBA16_SNORM 0x000000c7
+#define G80_SURFACE_FORMAT_RGBA16_SINT 0x000000c8
+#define G80_SURFACE_FORMAT_RGBA16_UINT 0x000000c9
+#define G80_SURFACE_FORMAT_RGBA16_FLOAT 0x000000ca
+#define G80_SURFACE_FORMAT_RG32_FLOAT 0x000000cb
+#define G80_SURFACE_FORMAT_RG32_SINT 0x000000cc
+#define G80_SURFACE_FORMAT_RG32_UINT 0x000000cd
+#define G80_SURFACE_FORMAT_RGBX16_FLOAT 0x000000ce
+#define G80_SURFACE_FORMAT_BGRA8_UNORM 0x000000cf
+#define G80_SURFACE_FORMAT_BGRA8_SRGB 0x000000d0
+#define G80_SURFACE_FORMAT_RGB10_A2_UNORM 0x000000d1
+#define G80_SURFACE_FORMAT_RGB10_A2_UINT 0x000000d2
+#define G80_SURFACE_FORMAT_RGBA8_UNORM 0x000000d5
+#define G80_SURFACE_FORMAT_RGBA8_SRGB 0x000000d6
+#define G80_SURFACE_FORMAT_RGBA8_SNORM 0x000000d7
+#define G80_SURFACE_FORMAT_RGBA8_SINT 0x000000d8
+#define G80_SURFACE_FORMAT_RGBA8_UINT 0x000000d9
+#define G80_SURFACE_FORMAT_RG16_UNORM 0x000000da
+#define G80_SURFACE_FORMAT_RG16_SNORM 0x000000db
+#define G80_SURFACE_FORMAT_RG16_SINT 0x000000dc
+#define G80_SURFACE_FORMAT_RG16_UINT 0x000000dd
+#define G80_SURFACE_FORMAT_RG16_FLOAT 0x000000de
+#define G80_SURFACE_FORMAT_BGR10_A2_UNORM 0x000000df
+#define G80_SURFACE_FORMAT_R11G11B10_FLOAT 0x000000e0
+#define G80_SURFACE_FORMAT_R32_SINT 0x000000e3
+#define G80_SURFACE_FORMAT_R32_UINT 0x000000e4
+#define G80_SURFACE_FORMAT_R32_FLOAT 0x000000e5
+#define G80_SURFACE_FORMAT_BGRX8_UNORM 0x000000e6
+#define G80_SURFACE_FORMAT_BGRX8_SRGB 0x000000e7
+#define G80_SURFACE_FORMAT_B5G6R5_UNORM 0x000000e8
+#define G80_SURFACE_FORMAT_BGR5_A1_UNORM 0x000000e9
+#define G80_SURFACE_FORMAT_RG8_UNORM 0x000000ea
+#define G80_SURFACE_FORMAT_RG8_SNORM 0x000000eb
+#define G80_SURFACE_FORMAT_RG8_SINT 0x000000ec
+#define G80_SURFACE_FORMAT_RG8_UINT 0x000000ed
+#define G80_SURFACE_FORMAT_R16_UNORM 0x000000ee
+#define G80_SURFACE_FORMAT_R16_SNORM 0x000000ef
+#define G80_SURFACE_FORMAT_R16_SINT 0x000000f0
+#define G80_SURFACE_FORMAT_R16_UINT 0x000000f1
+#define G80_SURFACE_FORMAT_R16_FLOAT 0x000000f2
+#define G80_SURFACE_FORMAT_R8_UNORM 0x000000f3
+#define G80_SURFACE_FORMAT_R8_SNORM 0x000000f4
+#define G80_SURFACE_FORMAT_R8_SINT 0x000000f5
+#define G80_SURFACE_FORMAT_R8_UINT 0x000000f6
+#define G80_SURFACE_FORMAT_A8_UNORM 0x000000f7
+#define G80_SURFACE_FORMAT_BGR5_X1_UNORM 0x000000f8
+#define G80_SURFACE_FORMAT_RGBX8_UNORM 0x000000f9
+#define G80_SURFACE_FORMAT_RGBX8_SRGB 0x000000fa
+#define G80_SURFACE_FORMAT_BGR5_X1_UNORM_UNKFB 0x000000fb
+#define G80_SURFACE_FORMAT_BGR5_X1_UNORM_UNKFC 0x000000fc
+#define G80_SURFACE_FORMAT_BGRX8_UNORM_UNKFD 0x000000fd
+#define G80_SURFACE_FORMAT_BGRX8_UNORM_UNKFE 0x000000fe
+#define G80_SURFACE_FORMAT_Y32_UINT_UNKFF 0x000000ff
+#define G80_ZETA_FORMAT_Z32_FLOAT 0x0000000a
+#define G80_ZETA_FORMAT_Z16_UNORM 0x00000013
+#define G80_ZETA_FORMAT_S8_Z24_UNORM 0x00000014
+#define G80_ZETA_FORMAT_Z24_X8_UNORM 0x00000015
+#define G80_ZETA_FORMAT_Z24_S8_UNORM 0x00000016
+#define G80_ZETA_FORMAT_Z24_C8_UNORM 0x00000018
+#define G80_ZETA_FORMAT_Z32_S8_X24_FLOAT 0x00000019
+#define G80_ZETA_FORMAT_Z24_X8_S8_C8_X16_UNORM 0x0000001d
+#define G80_ZETA_FORMAT_Z32_X8_C8_X16_FLOAT 0x0000001e
+#define G80_ZETA_FORMAT_Z32_S8_C8_X16_FLOAT 0x0000001f
+#define GK104_IMAGE_FORMAT_RGBA32_FLOAT 0x00000002
+#define GK104_IMAGE_FORMAT_RGBA32_SINT 0x00000003
+#define GK104_IMAGE_FORMAT_RGBA32_UINT 0x00000004
+#define GK104_IMAGE_FORMAT_RGBA16_UNORM 0x00000008
+#define GK104_IMAGE_FORMAT_RGBA16_SNORM 0x00000009
+#define GK104_IMAGE_FORMAT_RGBA16_SINT 0x0000000a
+#define GK104_IMAGE_FORMAT_RGBA16_UINT 0x0000000b
+#define GK104_IMAGE_FORMAT_RGBA16_FLOAT 0x0000000c
+#define GK104_IMAGE_FORMAT_RG32_FLOAT 0x0000000d
+#define GK104_IMAGE_FORMAT_RG32_SINT 0x0000000e
+#define GK104_IMAGE_FORMAT_RG32_UINT 0x0000000f
+#define GK104_IMAGE_FORMAT_RGB10_A2_UNORM 0x00000013
+#define GK104_IMAGE_FORMAT_RGB10_A2_UINT 0x00000015
+#define GK104_IMAGE_FORMAT_RGBA8_UNORM 0x00000018
+#define GK104_IMAGE_FORMAT_RGBA8_SNORM 0x0000001a
+#define GK104_IMAGE_FORMAT_RGBA8_SINT 0x0000001b
+#define GK104_IMAGE_FORMAT_RGBA8_UINT 0x0000001c
+#define GK104_IMAGE_FORMAT_RG16_UNORM 0x0000001d
+#define GK104_IMAGE_FORMAT_RG16_SNORM 0x0000001e
+#define GK104_IMAGE_FORMAT_RG16_SINT 0x0000001f
+#define GK104_IMAGE_FORMAT_RG16_UINT 0x00000020
+#define GK104_IMAGE_FORMAT_RG16_FLOAT 0x00000021
+#define GK104_IMAGE_FORMAT_R11G11B10_FLOAT 0x00000024
+#define GK104_IMAGE_FORMAT_R32_SINT 0x00000027
+#define GK104_IMAGE_FORMAT_R32_UINT 0x00000028
+#define GK104_IMAGE_FORMAT_R32_FLOAT 0x00000029
+#define GK104_IMAGE_FORMAT_RG8_UNORM 0x0000002e
+#define GK104_IMAGE_FORMAT_RG8_SNORM 0x0000002f
+#define GK104_IMAGE_FORMAT_RG8_SINT 0x00000030
+#define GK104_IMAGE_FORMAT_RG8_UINT 0x00000031
+#define GK104_IMAGE_FORMAT_R16_UNORM 0x00000032
+#define GK104_IMAGE_FORMAT_R16_SNORM 0x00000033
+#define GK104_IMAGE_FORMAT_R16_SINT 0x00000034
+#define GK104_IMAGE_FORMAT_R16_UINT 0x00000035
+#define GK104_IMAGE_FORMAT_R16_FLOAT 0x00000036
+#define GK104_IMAGE_FORMAT_R8_UNORM 0x00000037
+#define GK104_IMAGE_FORMAT_R8_SNORM 0x00000038
+#define GK104_IMAGE_FORMAT_R8_SINT 0x00000039
+#define GK104_IMAGE_FORMAT_R8_UINT 0x0000003a
+#define G80_PGRAPH_DATA_ERROR_INVALID_OPERATION 0x00000003
+#define G80_PGRAPH_DATA_ERROR_INVALID_VALUE 0x00000004
+#define G80_PGRAPH_DATA_ERROR_INVALID_ENUM 0x00000005
+#define G80_PGRAPH_DATA_ERROR_INVALID_OBJECT 0x00000008
+#define G80_PGRAPH_DATA_ERROR_READ_ONLY_OBJECT 0x00000009
+#define G80_PGRAPH_DATA_ERROR_SUPERVISOR_OBJECT 0x0000000a
+#define G80_PGRAPH_DATA_ERROR_INVALID_ADDRESS_ALIGNMENT 0x0000000b
+#define G80_PGRAPH_DATA_ERROR_INVALID_BITFIELD 0x0000000c
+#define G80_PGRAPH_DATA_ERROR_BEGIN_END_ACTIVE 0x0000000d
+#define G80_PGRAPH_DATA_ERROR_SEMANTIC_COLOR_BACK_OVER_LIMIT 0x0000000e
+#define G80_PGRAPH_DATA_ERROR_VIEWPORT_ID_NEEDS_GP 0x0000000f
+#define G80_PGRAPH_DATA_ERROR_RT_DOUBLE_BIND 0x00000010
+#define G80_PGRAPH_DATA_ERROR_RT_TYPES_MISMATCH 0x00000011
+#define G80_PGRAPH_DATA_ERROR_RT_PITCH_WITH_ZETA 0x00000012
+#define G80_PGRAPH_DATA_ERROR_FP_TOO_FEW_REGS 0x00000015
+#define G80_PGRAPH_DATA_ERROR_ZETA_FORMAT_CSAA_MISMATCH 0x00000016
+#define G80_PGRAPH_DATA_ERROR_RT_PITCH_WITH_MSAA 0x00000017
+#define G80_PGRAPH_DATA_ERROR_FP_INTERPOLANT_START_OVER_LIMIT 0x00000018
+#define G80_PGRAPH_DATA_ERROR_SEMANTIC_LAYER_OVER_LIMIT 0x00000019
+#define G80_PGRAPH_DATA_ERROR_RT_INVALID_ALIGNMENT 0x0000001a
+#define G80_PGRAPH_DATA_ERROR_SAMPLER_OVER_LIMIT 0x0000001b
+#define G80_PGRAPH_DATA_ERROR_TEXTURE_OVER_LIMIT 0x0000001c
+#define G80_PGRAPH_DATA_ERROR_GP_TOO_MANY_OUTPUTS 0x0000001e
+#define G80_PGRAPH_DATA_ERROR_RT_BPP128_WITH_MS8 0x0000001f
+#define G80_PGRAPH_DATA_ERROR_Z_OUT_OF_BOUNDS 0x00000021
+#define G80_PGRAPH_DATA_ERROR_XY_OUT_OF_BOUNDS 0x00000023
+#define G80_PGRAPH_DATA_ERROR_VP_ZERO_INPUTS 0x00000024
+#define G80_PGRAPH_DATA_ERROR_CP_MORE_PARAMS_THAN_SHARED 0x00000027
+#define G80_PGRAPH_DATA_ERROR_CP_NO_REG_SPACE_STRIPED 0x00000028
+#define G80_PGRAPH_DATA_ERROR_CP_NO_REG_SPACE_PACKED 0x00000029
+#define G80_PGRAPH_DATA_ERROR_CP_NOT_ENOUGH_WARPS 0x0000002a
+#define G80_PGRAPH_DATA_ERROR_CP_BLOCK_SIZE_MISMATCH 0x0000002b
+#define G80_PGRAPH_DATA_ERROR_CP_NOT_ENOUGH_LOCAL_WARPS 0x0000002c
+#define G80_PGRAPH_DATA_ERROR_CP_NOT_ENOUGH_STACK_WARPS 0x0000002d
+#define G80_PGRAPH_DATA_ERROR_CP_NO_BLOCKDIM_LATCH 0x0000002e
+#define G80_PGRAPH_DATA_ERROR_ENG2D_FORMAT_MISMATCH 0x00000031
+#define G80_PGRAPH_DATA_ERROR_ENG2D_OPERATION_ILLEGAL_FOR_DST_FORMAT 0x00000033
+#define G80_PGRAPH_DATA_ERROR_ENG2D_FORMAT_MISMATCH_B 0x00000034
+#define G80_PGRAPH_DATA_ERROR_PRIMITIVE_ID_NEEDS_GP 0x0000003f
+#define G80_PGRAPH_DATA_ERROR_SEMANTIC_VIEWPORT_OVER_LIMIT 0x00000044
+#define G80_PGRAPH_DATA_ERROR_SEMANTIC_COLOR_FRONT_OVER_LIMIT 0x00000045
+#define G80_PGRAPH_DATA_ERROR_LAYER_ID_NEEDS_GP 0x00000046
+#define G80_PGRAPH_DATA_ERROR_SEMANTIC_CLIP_OVER_LIMIT 0x00000047
+#define G80_PGRAPH_DATA_ERROR_SEMANTIC_PTSZ_OVER_LIMIT 0x00000048
+#define G80_PGRAPH_DATA_ERROR_M2MF_LINE_LENGTH_EXCEEDS_PITCH_IN 0x00000051
+#define G80_PGRAPH_DATA_ERROR_M2MF_LINE_LENGTH_EXCEEDS_PITCH_OUT 0x00000053
+#define G80_PGRAPH_DATA_ERROR_RT_PITCH_WITH_ZETA_GF100 0x00000098
+#define G80_PGRAPH_DATA_ERROR_ENG2D_UNALIGNED_PITCH_GF100 0x000000a5
+#define G80_CG_IDLE_TIMEOUT__MASK 0x0000003f
+#define G80_CG_IDLE_TIMEOUT__SHIFT 0
+#define G80_CG_IDLE_TIMEOUT_ENABLE 0x00000040
+#define G80_CG_INTERFACE_REENABLE_TIME__MASK 0x000f0000
+#define G80_CG_INTERFACE_REENABLE_TIME__SHIFT 16
+#define G80_CG_THROTTLE_DUTY_M1__MASK 0x00f00000
+#define G80_CG_THROTTLE_DUTY_M1__SHIFT 20
+#define G80_CG_DELAY__MASK 0x0f000000
+#define G80_CG_DELAY__SHIFT 24
+#define G80_CG_CLOCK_THROTTLE_ENABLE 0x10000000
+#define G80_CG_THROTTLE_MODE__MASK 0x20000000
+#define G80_CG_THROTTLE_MODE__SHIFT 29
+#define G80_CG_THROTTLE_MODE_AUTO 0x00000000
+#define G80_CG_THROTTLE_MODE_MANUAL 0x20000000
+#define G80_CG_INTERFACE_THROTTLE_ENABLE 0x40000000
+#define G80_QUERY__SIZE 0x00000010
+#define G80_QUERY_COUNTER 0x00000000
+
+#define G80_QUERY_RES 0x00000004
+
+#define G80_QUERY_TIME 0x00000008
+
+
+#endif /* G80_DEFS_XML */
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 02/23] nv50: switch nv50_surface.c to updated g80_defs.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 03/23] nv50: switch nv50_tex.c " Ben Skeggs
` (20 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_surface.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index c69fa5a..8080b81 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -37,7 +37,7 @@
#include "nv50/nv50_context.h"
#include "nv50/nv50_resource.h"
-#include "nv50/nv50_defs.xml.h"
+#include "nv50/g80_defs.xml.h"
#include "nv50/nv50_texture.xml.h"
/* these are used in nv50_blit.h */
@@ -64,15 +64,15 @@ nv50_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
switch (util_format_get_blocksize(format)) {
case 1:
- return NV50_SURFACE_FORMAT_R8_UNORM;
+ return G80_SURFACE_FORMAT_R8_UNORM;
case 2:
- return NV50_SURFACE_FORMAT_R16_UNORM;
+ return G80_SURFACE_FORMAT_R16_UNORM;
case 4:
- return NV50_SURFACE_FORMAT_BGRA8_UNORM;
+ return G80_SURFACE_FORMAT_BGRA8_UNORM;
case 8:
- return NV50_SURFACE_FORMAT_RGBA16_FLOAT;
+ return G80_SURFACE_FORMAT_RGBA16_FLOAT;
case 16:
- return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
+ return G80_SURFACE_FORMAT_RGBA32_FLOAT;
default:
return 0;
}
@@ -628,7 +628,7 @@ nv50_clear_buffer_push(struct pipe_context *pipe,
offset &= ~0xff;
BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
- PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+ PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
PUSH_DATA (push, 262144);
@@ -638,7 +638,7 @@ nv50_clear_buffer_push(struct pipe_context *pipe,
PUSH_DATA (push, buf->address + offset);
BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
PUSH_DATA (push, 0);
- PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+ PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
PUSH_DATA (push, size);
PUSH_DATA (push, 1);
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 03/23] nv50: switch nv50_tex.c to updated g80_defs.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-15 5:38 ` [PATCH 02/23] nv50: switch nv50_surface.c to updated g80_defs.xml.h Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 04/23] nv50: switch nv50_transfer.c to g80_defs.xml.h Ben Skeggs
` (19 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_tex.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_tex.c b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
index c3f4336..b53a435 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
@@ -23,7 +23,7 @@
#include "nv50/nv50_context.h"
#include "nv50/nv50_resource.h"
#include "nv50/nv50_texture.xml.h"
-#include "nv50/nv50_defs.xml.h"
+#include "nv50/g80_defs.xml.h"
#include "util/u_format.h"
@@ -265,7 +265,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
tic->id = nv50_screen_tic_alloc(nv50->screen, tic);
BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
- PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+ PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
PUSH_DATA (push, 262144);
@@ -275,7 +275,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
PUSH_DATA (push, txc->offset);
BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
PUSH_DATA (push, 0);
- PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+ PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
PUSH_DATA (push, 32);
PUSH_DATA (push, 1);
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 04/23] nv50: switch nv50_transfer.c to g80_defs.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-15 5:38 ` [PATCH 02/23] nv50: switch nv50_surface.c to updated g80_defs.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 03/23] nv50: switch nv50_tex.c " Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 05/23] nv50: remove unnecessary include Ben Skeggs
` (18 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_transfer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
index 9a3fd1e..86a8c15 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c
@@ -3,7 +3,7 @@
#include "nv50/nv50_context.h"
-#include "nv50/nv50_defs.xml.h"
+#include "nv50/g80_defs.xml.h"
struct nv50_transfer {
struct pipe_transfer base;
@@ -163,7 +163,7 @@ nv50_sifc_linear_u8(struct nouveau_context *nv,
offset &= ~0xff;
BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
- PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+ PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
PUSH_DATA (push, 262144);
@@ -173,7 +173,7 @@ nv50_sifc_linear_u8(struct nouveau_context *nv,
PUSH_DATA (push, dst->offset + offset);
BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
PUSH_DATA (push, 0);
- PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+ PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
PUSH_DATA (push, size);
PUSH_DATA (push, 1);
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 05/23] nv50: remove unnecessary include
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (2 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 04/23] nv50: switch nv50_transfer.c to g80_defs.xml.h Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 06/23] nvc0: switch nvc0_surface.c to updated g80_defs.xml.h Ben Skeggs
` (17 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
index 4af9699..5536978 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c
@@ -2,7 +2,6 @@
#include "util/u_format.h"
#include "nv50/nv50_context.h"
-#include "nv50/nv50_defs.xml.h"
static inline void
nv50_fb_set_null_rt(struct nouveau_pushbuf *push, unsigned i)
--
2.7.0
_______________________________________________
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Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 06/23] nvc0: switch nvc0_surface.c to updated g80_defs.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (3 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 05/23] nv50: remove unnecessary include Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 07/23] nvc0: switch nvc0_tex.c " Ben Skeggs
` (16 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index e3843ca..3b29e40 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -34,7 +34,7 @@
#include "nvc0/nvc0_context.h"
#include "nvc0/nvc0_resource.h"
-#include "nv50/nv50_defs.xml.h"
+#include "nv50/g80_defs.xml.h"
#include "nv50/nv50_texture.xml.h"
/* these are used in nv50_blit.h */
@@ -54,7 +54,7 @@ nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
/* A8_UNORM is treated as I8_UNORM as far as the 2D engine is concerned. */
if (!dst && unlikely(format == PIPE_FORMAT_I8_UNORM) && !dst_src_equal)
- return NV50_SURFACE_FORMAT_A8_UNORM;
+ return G80_SURFACE_FORMAT_A8_UNORM;
/* Hardware values for color formats range from 0xc0 to 0xff,
* but the 2D engine doesn't support all of them.
@@ -65,15 +65,15 @@ nvc0_2d_format(enum pipe_format format, bool dst, bool dst_src_equal)
switch (util_format_get_blocksize(format)) {
case 1:
- return NV50_SURFACE_FORMAT_R8_UNORM;
+ return G80_SURFACE_FORMAT_R8_UNORM;
case 2:
- return NV50_SURFACE_FORMAT_RG8_UNORM;
+ return G80_SURFACE_FORMAT_RG8_UNORM;
case 4:
- return NV50_SURFACE_FORMAT_BGRA8_UNORM;
+ return G80_SURFACE_FORMAT_BGRA8_UNORM;
case 8:
- return NV50_SURFACE_FORMAT_RGBA16_UNORM;
+ return G80_SURFACE_FORMAT_RGBA16_UNORM;
case 16:
- return NV50_SURFACE_FORMAT_RGBA32_FLOAT;
+ return G80_SURFACE_FORMAT_RGBA32_FLOAT;
default:
assert(0);
return 0;
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 07/23] nvc0: switch nvc0_tex.c to updated g80_defs.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (4 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 06/23] nvc0: switch nvc0_surface.c to updated g80_defs.xml.h Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 08/23] nvc0: remove unnecessary includes Ben Skeggs
` (15 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 80 ++++++++++++++---------------
1 file changed, 40 insertions(+), 40 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index 7223f5a..cbfebb8 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -23,7 +23,7 @@
#include "nvc0/nvc0_context.h"
#include "nvc0/nvc0_resource.h"
#include "nv50/nv50_texture.xml.h"
-#include "nv50/nv50_defs.xml.h"
+#include "nv50/g80_defs.xml.h"
#include "util/u_format.h"
@@ -686,45 +686,45 @@ nvc0_validate_surfaces(struct nvc0_context *nvc0)
static const uint8_t nve4_su_format_map[PIPE_FORMAT_COUNT] =
{
- [PIPE_FORMAT_R32G32B32A32_FLOAT] = NVE4_IMAGE_FORMAT_RGBA32_FLOAT,
- [PIPE_FORMAT_R32G32B32A32_SINT] = NVE4_IMAGE_FORMAT_RGBA32_SINT,
- [PIPE_FORMAT_R32G32B32A32_UINT] = NVE4_IMAGE_FORMAT_RGBA32_UINT,
- [PIPE_FORMAT_R16G16B16A16_FLOAT] = NVE4_IMAGE_FORMAT_RGBA16_FLOAT,
- [PIPE_FORMAT_R16G16B16A16_UNORM] = NVE4_IMAGE_FORMAT_RGBA16_UNORM,
- [PIPE_FORMAT_R16G16B16A16_SNORM] = NVE4_IMAGE_FORMAT_RGBA16_SNORM,
- [PIPE_FORMAT_R16G16B16A16_SINT] = NVE4_IMAGE_FORMAT_RGBA16_SINT,
- [PIPE_FORMAT_R16G16B16A16_UINT] = NVE4_IMAGE_FORMAT_RGBA16_UINT,
- [PIPE_FORMAT_R8G8B8A8_UNORM] = NVE4_IMAGE_FORMAT_RGBA8_UNORM,
- [PIPE_FORMAT_R8G8B8A8_SNORM] = NVE4_IMAGE_FORMAT_RGBA8_SNORM,
- [PIPE_FORMAT_R8G8B8A8_SINT] = NVE4_IMAGE_FORMAT_RGBA8_SINT,
- [PIPE_FORMAT_R8G8B8A8_UINT] = NVE4_IMAGE_FORMAT_RGBA8_UINT,
- [PIPE_FORMAT_R11G11B10_FLOAT] = NVE4_IMAGE_FORMAT_R11G11B10_FLOAT,
- [PIPE_FORMAT_R10G10B10A2_UNORM] = NVE4_IMAGE_FORMAT_RGB10_A2_UNORM,
-/* [PIPE_FORMAT_R10G10B10A2_UINT] = NVE4_IMAGE_FORMAT_RGB10_A2_UINT, */
- [PIPE_FORMAT_R32G32_FLOAT] = NVE4_IMAGE_FORMAT_RG32_FLOAT,
- [PIPE_FORMAT_R32G32_SINT] = NVE4_IMAGE_FORMAT_RG32_SINT,
- [PIPE_FORMAT_R32G32_UINT] = NVE4_IMAGE_FORMAT_RG32_UINT,
- [PIPE_FORMAT_R16G16_FLOAT] = NVE4_IMAGE_FORMAT_RG16_FLOAT,
- [PIPE_FORMAT_R16G16_UNORM] = NVE4_IMAGE_FORMAT_RG16_UNORM,
- [PIPE_FORMAT_R16G16_SNORM] = NVE4_IMAGE_FORMAT_RG16_SNORM,
- [PIPE_FORMAT_R16G16_SINT] = NVE4_IMAGE_FORMAT_RG16_SINT,
- [PIPE_FORMAT_R16G16_UINT] = NVE4_IMAGE_FORMAT_RG16_UINT,
- [PIPE_FORMAT_R8G8_UNORM] = NVE4_IMAGE_FORMAT_RG8_UNORM,
- [PIPE_FORMAT_R8G8_SNORM] = NVE4_IMAGE_FORMAT_RG8_SNORM,
- [PIPE_FORMAT_R8G8_SINT] = NVE4_IMAGE_FORMAT_RG8_SINT,
- [PIPE_FORMAT_R8G8_UINT] = NVE4_IMAGE_FORMAT_RG8_UINT,
- [PIPE_FORMAT_R32_FLOAT] = NVE4_IMAGE_FORMAT_R32_FLOAT,
- [PIPE_FORMAT_R32_SINT] = NVE4_IMAGE_FORMAT_R32_SINT,
- [PIPE_FORMAT_R32_UINT] = NVE4_IMAGE_FORMAT_R32_UINT,
- [PIPE_FORMAT_R16_FLOAT] = NVE4_IMAGE_FORMAT_R16_FLOAT,
- [PIPE_FORMAT_R16_UNORM] = NVE4_IMAGE_FORMAT_R16_UNORM,
- [PIPE_FORMAT_R16_SNORM] = NVE4_IMAGE_FORMAT_R16_SNORM,
- [PIPE_FORMAT_R16_SINT] = NVE4_IMAGE_FORMAT_R16_SINT,
- [PIPE_FORMAT_R16_UINT] = NVE4_IMAGE_FORMAT_R16_UINT,
- [PIPE_FORMAT_R8_UNORM] = NVE4_IMAGE_FORMAT_R8_UNORM,
- [PIPE_FORMAT_R8_SNORM] = NVE4_IMAGE_FORMAT_R8_SNORM,
- [PIPE_FORMAT_R8_SINT] = NVE4_IMAGE_FORMAT_R8_SINT,
- [PIPE_FORMAT_R8_UINT] = NVE4_IMAGE_FORMAT_R8_UINT,
+ [PIPE_FORMAT_R32G32B32A32_FLOAT] = GK104_IMAGE_FORMAT_RGBA32_FLOAT,
+ [PIPE_FORMAT_R32G32B32A32_SINT] = GK104_IMAGE_FORMAT_RGBA32_SINT,
+ [PIPE_FORMAT_R32G32B32A32_UINT] = GK104_IMAGE_FORMAT_RGBA32_UINT,
+ [PIPE_FORMAT_R16G16B16A16_FLOAT] = GK104_IMAGE_FORMAT_RGBA16_FLOAT,
+ [PIPE_FORMAT_R16G16B16A16_UNORM] = GK104_IMAGE_FORMAT_RGBA16_UNORM,
+ [PIPE_FORMAT_R16G16B16A16_SNORM] = GK104_IMAGE_FORMAT_RGBA16_SNORM,
+ [PIPE_FORMAT_R16G16B16A16_SINT] = GK104_IMAGE_FORMAT_RGBA16_SINT,
+ [PIPE_FORMAT_R16G16B16A16_UINT] = GK104_IMAGE_FORMAT_RGBA16_UINT,
+ [PIPE_FORMAT_R8G8B8A8_UNORM] = GK104_IMAGE_FORMAT_RGBA8_UNORM,
+ [PIPE_FORMAT_R8G8B8A8_SNORM] = GK104_IMAGE_FORMAT_RGBA8_SNORM,
+ [PIPE_FORMAT_R8G8B8A8_SINT] = GK104_IMAGE_FORMAT_RGBA8_SINT,
+ [PIPE_FORMAT_R8G8B8A8_UINT] = GK104_IMAGE_FORMAT_RGBA8_UINT,
+ [PIPE_FORMAT_R11G11B10_FLOAT] = GK104_IMAGE_FORMAT_R11G11B10_FLOAT,
+ [PIPE_FORMAT_R10G10B10A2_UNORM] = GK104_IMAGE_FORMAT_RGB10_A2_UNORM,
+/* [PIPE_FORMAT_R10G10B10A2_UINT] = GK104_IMAGE_FORMAT_RGB10_A2_UINT, */
+ [PIPE_FORMAT_R32G32_FLOAT] = GK104_IMAGE_FORMAT_RG32_FLOAT,
+ [PIPE_FORMAT_R32G32_SINT] = GK104_IMAGE_FORMAT_RG32_SINT,
+ [PIPE_FORMAT_R32G32_UINT] = GK104_IMAGE_FORMAT_RG32_UINT,
+ [PIPE_FORMAT_R16G16_FLOAT] = GK104_IMAGE_FORMAT_RG16_FLOAT,
+ [PIPE_FORMAT_R16G16_UNORM] = GK104_IMAGE_FORMAT_RG16_UNORM,
+ [PIPE_FORMAT_R16G16_SNORM] = GK104_IMAGE_FORMAT_RG16_SNORM,
+ [PIPE_FORMAT_R16G16_SINT] = GK104_IMAGE_FORMAT_RG16_SINT,
+ [PIPE_FORMAT_R16G16_UINT] = GK104_IMAGE_FORMAT_RG16_UINT,
+ [PIPE_FORMAT_R8G8_UNORM] = GK104_IMAGE_FORMAT_RG8_UNORM,
+ [PIPE_FORMAT_R8G8_SNORM] = GK104_IMAGE_FORMAT_RG8_SNORM,
+ [PIPE_FORMAT_R8G8_SINT] = GK104_IMAGE_FORMAT_RG8_SINT,
+ [PIPE_FORMAT_R8G8_UINT] = GK104_IMAGE_FORMAT_RG8_UINT,
+ [PIPE_FORMAT_R32_FLOAT] = GK104_IMAGE_FORMAT_R32_FLOAT,
+ [PIPE_FORMAT_R32_SINT] = GK104_IMAGE_FORMAT_R32_SINT,
+ [PIPE_FORMAT_R32_UINT] = GK104_IMAGE_FORMAT_R32_UINT,
+ [PIPE_FORMAT_R16_FLOAT] = GK104_IMAGE_FORMAT_R16_FLOAT,
+ [PIPE_FORMAT_R16_UNORM] = GK104_IMAGE_FORMAT_R16_UNORM,
+ [PIPE_FORMAT_R16_SNORM] = GK104_IMAGE_FORMAT_R16_SNORM,
+ [PIPE_FORMAT_R16_SINT] = GK104_IMAGE_FORMAT_R16_SINT,
+ [PIPE_FORMAT_R16_UINT] = GK104_IMAGE_FORMAT_R16_UINT,
+ [PIPE_FORMAT_R8_UNORM] = GK104_IMAGE_FORMAT_R8_UNORM,
+ [PIPE_FORMAT_R8_SNORM] = GK104_IMAGE_FORMAT_R8_SNORM,
+ [PIPE_FORMAT_R8_SINT] = GK104_IMAGE_FORMAT_R8_SINT,
+ [PIPE_FORMAT_R8_UINT] = GK104_IMAGE_FORMAT_R8_UINT,
};
/* Auxiliary format description values for surface instructions.
--
2.7.0
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^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 08/23] nvc0: remove unnecessary includes
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (5 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 07/23] nvc0: switch nvc0_tex.c " Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 09/23] nv50-: separate vertex formats from surface format descriptions Ben Skeggs
` (14 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nvc0/nvc0_compute.h | 1 -
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 1 -
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c | 1 -
src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c | 2 --
src/gallium/drivers/nouveau/nvc0/nve4_compute.h | 1 -
5 files changed, 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h
index 168a6d1..a23f7f3 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.h
@@ -1,7 +1,6 @@
#ifndef NVC0_COMPUTE_H
#define NVC0_COMPUTE_H
-#include "nv50/nv50_defs.xml.h"
#include "nvc0/nvc0_compute.xml.h"
bool
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index cd3f1ff..758203b 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -33,7 +33,6 @@
#include "nvc0/nvc0_query_hw.h"
#include "nvc0/nvc0_3d.xml.h"
-#include "nv50/nv50_texture.xml.h"
#include "nouveau_gldefs.h"
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
index e0d8ab0..31ef34c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
@@ -3,7 +3,6 @@
#include "util/u_math.h"
#include "nvc0/nvc0_context.h"
-#include "nv50/nv50_defs.xml.h"
#if 0
static void
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
index 279c7e9..24d23d2 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_transfer.c
@@ -3,8 +3,6 @@
#include "nvc0/nvc0_context.h"
-#include "nv50/nv50_defs.xml.h"
-
struct nvc0_transfer {
struct pipe_transfer base;
struct nv50_m2mf_rect rect[2];
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.h b/src/gallium/drivers/nouveau/nvc0/nve4_compute.h
index 7364a68..84f8593 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.h
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.h
@@ -2,7 +2,6 @@
#ifndef NVE4_COMPUTE_H
#define NVE4_COMPUTE_H
-#include "nv50/nv50_defs.xml.h"
#include "nvc0/nve4_compute.xml.h"
/* Input space is implemented as c0[], to which we bind the screen->parm bo.
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 09/23] nv50-: separate vertex formats from surface format descriptions
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (6 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 08/23] nvc0: remove unnecessary includes Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
[not found] ` <1455514736-8909-9-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-15 5:38 ` [PATCH 10/23] nv50-: improved macros to handle format specification Ben Skeggs
` (13 subsequent siblings)
21 siblings, 1 reply; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
We've previously had identical naming between vertex and texture
formats, so it mostly made sense to define these together.
However, upcoming patches are going to transition the driver over to
using updated texture header definitions using NVIDIA's naming, and this
will no longer be the case.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 249 ++++++++++++++++++------
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 3 +-
src/gallium/drivers/nouveau/nv50/nv50_screen.h | 5 +
src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 4 +-
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 +-
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 5 +
src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 4 +-
7 files changed, 206 insertions(+), 67 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index 49a93bf..a9ddae5 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -39,10 +39,9 @@
* C: render target (color), blendable only on nvc0
* D: scanout/display target, blendable
* Z: depth/stencil
- * V: vertex fetch
* I: image / surface, implies T
*/
-#define U_V PIPE_BIND_VERTEX_BUFFER
+#define U_V 0
#define U_T PIPE_BIND_SAMPLER_VIEW
#define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | PIPE_BIND_COMPUTE_RESOURCE
#define U_TR PIPE_BIND_RENDER_TARGET | U_T
@@ -103,10 +102,7 @@
(NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
(NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
(NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
- NV50_TIC_0_FMT_##sz, \
- NVXX_3D_VAF_SIZE(sz) | \
- NVXX_3D_VAF_TYPE(t0) | (br << 31), \
- U_##u \
+ NV50_TIC_0_FMT_##sz, U_##u \
}
#define TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
@@ -120,7 +116,7 @@
(NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
(NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
(NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
- NV50_TIC_0_FMT_##sz, 0, U_##u \
+ NV50_TIC_0_FMT_##sz, U_##u \
}
#define C4A(p, n, r, g, b, a, t, s, u, br) \
@@ -308,6 +304,10 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
I3B(R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT, 32_32_32_32, TR),
I3B(R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT, 32_32_32_32, TR),
+ F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
+ I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
+ I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
+
F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
@@ -381,64 +381,191 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 8_8_8_8, T),
TBLENT_B_(R5SG5SB6U_NORM, 0,
C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 5_5_6, T),
+};
- /* vertex-only formats: */
+#define V_TBLENT_A_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u, br) \
+ [PIPE_FORMAT_##pf] = { \
+ NVXX_3D_VAF_SIZE(sz) | NVXX_3D_VAF_TYPE(t0) | (br << 31), \
+ PIPE_BIND_VERTEX_BUFFER \
+ }
- C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 32_32_32_32, V, 0),
- C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED, 32_32_32_32, V, 0),
- F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
- F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
- F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
- I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
- I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
- F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
- F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
- F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
- F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
- F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
- F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
-
- C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 16_16_16_16, V, 0),
- C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED, 16_16_16_16, V, 0),
- F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
- F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
- F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
- I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
- I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
- F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
- F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
- F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
- F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
- F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
- F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
-
- C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 0),
- C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 0),
- C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 1),
- C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 1),
-
- C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
- C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
- F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
- F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
- I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
- I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
- F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
- F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
- F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
- F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
- F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
- F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
+#define V_TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
+ [PIPE_FORMAT_##pf] = { \
+ 0, \
+ PIPE_BIND_VERTEX_BUFFER \
+ }
+
+#define V_C4A(p, n, r, g, b, a, t, s, u, br) \
+ V_TBLENT_A_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u, br)
+#define V_C4B(p, n, r, g, b, a, t, s, u) \
+ V_TBLENT_B_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
+
+#define V_ZXB(p, n, r, g, b, a, t, s, u) \
+ V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
+ r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
+#define V_ZSB(p, n, r, g, b, a, t, s, u) \
+ V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
+ r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
+#define V_SZB(p, n, r, g, b, a, t, s, u) \
+ V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
+ r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
+#define V_SXB(p, r, s, u) \
+ V_TBLENT_B_(p, NV50_ZETA_FORMAT_NONE, \
+ r, r, r, r, UINT, UINT, UINT, UINT, s, u)
+
+#define V_F3A(p, n, r, g, b, a, t, s, u) \
+ V_C4A(p, n, r, g, b, ONE_FLOAT, t, s, u, 0)
+#define V_I3A(p, n, r, g, b, a, t, s, u) \
+ V_C4A(p, n, r, g, b, ONE_INT, t, s, u, 0)
+#define V_F3B(p, n, r, g, b, a, t, s, u) \
+ V_C4B(p, n, r, g, b, ONE_FLOAT, t, s, u)
+#define V_I3B(p, n, r, g, b, a, t, s, u) \
+ V_C4B(p, n, r, g, b, ONE_INT, t, s, u)
+
+#define V_F2A(p, n, r, g, b, a, t, s, u) \
+ V_C4A(p, n, r, g, ZERO, ONE_FLOAT, t, s, u, 0)
+#define V_I2A(p, n, r, g, b, a, t, s, u) \
+ V_C4A(p, n, r, g, ZERO, ONE_INT, t, s, u, 0)
+#define V_F2B(p, n, r, g, b, a, t, s, u) \
+ V_C4B(p, n, r, g, ZERO, ONE_FLOAT, t, s, u)
+#define V_I2B(p, n, r, g, b, a, t, s, u) \
+ V_C4B(p, n, r, g, ZERO, ONE_INT, t, s, u)
+
+#define V_F1A(p, n, r, g, b, a, t, s, u) \
+ V_C4A(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u, 0)
+#define V_I1A(p, n, r, g, b, a, t, s, u) \
+ V_C4A(p, n, r, ZERO, ZERO, ONE_INT, t, s, u, 0)
+#define V_F1B(p, n, r, g, b, a, t, s, u) \
+ V_C4B(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u)
+#define V_I1B(p, n, r, g, b, a, t, s, u) \
+ V_C4B(p, n, r, ZERO, ZERO, ONE_INT, t, s, u)
+
+#define V_A1B(p, n, r, g, b, a, t, s, u) \
+ V_C4B(p, n, ZERO, ZERO, ZERO, a, t, s, u)
+
+#if NOUVEAU_DRIVER == 0xc0
+const struct nvc0_vertex_format nvc0_vertex_format[PIPE_FORMAT_COUNT] =
+#else
+const struct nv50_vertex_format nv50_vertex_format[PIPE_FORMAT_COUNT] =
+#endif
+{
+ V_C4A(B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM, 8_8_8_8, TDV, 1),
+ V_C4A(R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8, IBV, 0),
+
+ V_C4A(R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM, 10_10_10_2, IBV, 0),
+ V_C4A(B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM, 10_10_10_2, TDV, 1),
+ V_C4A(R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM, 10_10_10_2, TV, 0),
+ V_C4A(B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM, 10_10_10_2, TV, 1),
+ V_C4A(R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT, 10_10_10_2, TRV, 0),
+ V_C4A(B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT, 10_10_10_2, TV, 0),
+
+ V_F3A(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, IBV),
+
+ V_C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32, IBV, 0),
+ V_C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, TV, 0),
+ V_C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, TV, 0),
+ V_C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32, IRV, 0),
+ V_C4A(R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT, 32_32_32_32, IRV, 0),
+
+ V_F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
+ V_F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
+ V_F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
+ V_I2A(R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IRV),
+ V_I2A(R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IRV),
+
+ V_F1A(R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IBV),
+ V_F1A(R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, TV),
+ V_F1A(R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, TV),
+ V_I1A(R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IRV),
+ V_I1A(R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IRV),
+
+ V_C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16, IBV, 0),
+ V_C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16, ICV, 0),
+ V_C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16, ICV, 0),
+ V_C4A(R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT, 16_16_16_16, IRV, 0),
+ V_C4A(R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT, 16_16_16_16, IRV, 0),
+
+ V_F2A(R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IBV),
+ V_F2A(R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, ICV),
+ V_F2A(R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, ICV),
+ V_I2A(R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IRV),
+ V_I2A(R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IRV),
+
+ V_F1A(R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IBV),
+ V_F1A(R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, ICV),
+ V_F1A(R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, ICV),
+ V_I1A(R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IRV),
+ V_I1A(R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IRV),
+
+ V_C4A(R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8, ICV, 0),
+ V_C4A(R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IRV, 0),
+ V_C4A(R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IRV, 0),
+
+ V_F2A(R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IBV),
+ V_F2A(R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, ICV),
+ V_I2A(R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IRV),
+ V_I2A(R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IRV),
+
+ V_F1A(R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IBV),
+ V_F1A(R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, ICV),
+ V_I1A(R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IRV),
+ V_I1A(R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IRV),
+
+ V_C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 32_32_32_32, V, 0),
+ V_C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED, 32_32_32_32, V, 0),
+ V_F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
+ V_F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
+ V_F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
+ V_I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
+ V_I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
+ V_F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
+ V_F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
+ V_F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
+ V_F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
+ V_F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
+ V_F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
+
+ V_C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 16_16_16_16, V, 0),
+ V_C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED, 16_16_16_16, V, 0),
+ V_F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
+ V_F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
+ V_F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
+ V_I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
+ V_I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
+ V_F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
+ V_F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
+ V_F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
+ V_F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
+ V_F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
+ V_F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
+
+ V_C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 0),
+ V_C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 0),
+ V_C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 1),
+ V_C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 1),
+
+ V_C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
+ V_C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
+ V_F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
+ V_F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
+ V_I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
+ V_I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
+ V_F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
+ V_F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
+ V_F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
+ V_F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
+ V_F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
+ V_F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
/* FIXED types: not supported natively, converted on VBO push */
- C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
- F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
- F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
- F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
+ V_C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
+ V_F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
+ V_F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
+ V_F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
- C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
- F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
- F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
- F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
+ V_C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
+ V_F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
+ V_F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
+ V_F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
};
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index fd7b3d9..057e065 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -72,7 +72,8 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
PIPE_BIND_TRANSFER_WRITE |
PIPE_BIND_SHARED);
- return (nv50_format_table[format].usage & bindings) == bindings;
+ return (( nv50_format_table[format].usage |
+ nv50_vertex_format[format].usage) & bindings) == bindings;
}
static int
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index 2a4983d..a117237 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -157,11 +157,16 @@ nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
struct nv50_format {
uint32_t rt;
uint32_t tic;
+ uint32_t usage;
+};
+
+struct nv50_vertex_format {
uint32_t vtx;
uint32_t usage;
};
extern const struct nv50_format nv50_format_table[];
+extern const struct nv50_vertex_format nv50_vertex_format[];
static inline void
nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry *tic)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
index 5369d52..028f4c8 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -76,7 +76,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
enum pipe_format fmt = ve->src_format;
so->element[i].pipe = elements[i];
- so->element[i].state = nv50_format_table[fmt].vtx;
+ so->element[i].state = nv50_vertex_format[fmt].vtx;
if (!so->element[i].state) {
switch (util_format_get_nr_components(fmt)) {
@@ -89,7 +89,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
FREE(so);
return NULL;
}
- so->element[i].state = nv50_format_table[fmt].vtx;
+ so->element[i].state = nv50_vertex_format[fmt].vtx;
so->need_conversion = true;
pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
"Converting vertex element %d, no hw format %s",
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 2b12de4..d435bec 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -61,7 +61,8 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
PIPE_BIND_TRANSFER_WRITE |
PIPE_BIND_SHARED);
- return (nvc0_format_table[format].usage & bindings) == bindings;
+ return (( nvc0_format_table[format].usage |
+ nvc0_vertex_format[format].usage) & bindings) == bindings;
}
static int
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 1a56177..e2b617f 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -165,11 +165,16 @@ nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
struct nvc0_format {
uint32_t rt;
uint32_t tic;
+ uint32_t usage;
+};
+
+struct nvc0_vertex_format {
uint32_t vtx;
uint32_t usage;
};
extern const struct nvc0_format nvc0_format_table[];
+extern const struct nvc0_vertex_format nvc0_vertex_format[];
static inline void
nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index 032b3c1..8239624 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -80,7 +80,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
enum pipe_format fmt = ve->src_format;
so->element[i].pipe = elements[i];
- so->element[i].state = nvc0_format_table[fmt].vtx;
+ so->element[i].state = nvc0_vertex_format[fmt].vtx;
if (!so->element[i].state) {
switch (util_format_get_nr_components(fmt)) {
@@ -93,7 +93,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
FREE(so);
return NULL;
}
- so->element[i].state = nvc0_format_table[fmt].vtx;
+ so->element[i].state = nvc0_vertex_format[fmt].vtx;
so->need_conversion = true;
pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
"Converting vertex element %d, no hw format %s",
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 10/23] nv50-: improved macros to handle format specification
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (7 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 09/23] nv50-: separate vertex formats from surface format descriptions Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 11/23] nv50-: switch nv50_formats.c to updated g80_defs.xml.h Ben Skeggs
` (12 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 829 ++++++++++--------------
1 file changed, 359 insertions(+), 470 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index a9ddae5..01cdd54 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -41,7 +41,6 @@
* Z: depth/stencil
* I: image / surface, implies T
*/
-#define U_V 0
#define U_T PIPE_BIND_SAMPLER_VIEW
#define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE | PIPE_BIND_COMPUTE_RESOURCE
#define U_TR PIPE_BIND_RENDER_TARGET | U_T
@@ -50,62 +49,22 @@
#define U_IB PIPE_BIND_BLENDABLE | U_IR
#define U_TD PIPE_BIND_SCANOUT | PIPE_BIND_DISPLAY_TARGET | U_TB
#define U_TZ PIPE_BIND_DEPTH_STENCIL | U_T
-#define U_TV U_V | U_T
-#define U_TRV U_V | U_TR
-#define U_IRV U_V | U_IR
-#define U_TBV U_V | U_TB
-#define U_IBV U_V | U_IB
-#define U_TDV U_V | U_TD
#if NOUVEAU_DRIVER == 0xc0
# define U_TC U_TB
# define U_IC U_IB
-# define U_TCV U_TBV
-# define U_ICV U_IBV
# define U_t U_T
-# define U_tV U_TV
#else
# define U_TC U_TR
# define U_IC U_IR
-# define U_TCV U_TRV
-# define U_ICV U_IRV
# define U_t 0
-# define U_tV U_V
#endif
#define NV50_ZETA_FORMAT_NONE 0
#define NV50_SURFACE_FORMAT_NONE 0
-/* for vertex buffers: */
-#define NV50_TIC_0_FMT_8_8_8 NV50_TIC_0_FMT_8_8_8_8
-#define NV50_TIC_0_FMT_16_16_16 NV50_TIC_0_FMT_16_16_16_16
-#define NV50_TIC_0_FMT_32_32_32 NVC0_TIC_0_FMT_32_32_32
-#define NV50_TIC_0_FMT_BPTC NVC0_TIC_0_FMT_BPTC
-#define NV50_TIC_0_FMT_BPTC_FLOAT NVC0_TIC_0_FMT_BPTC_FLOAT
-#define NV50_TIC_0_FMT_BPTC_UFLOAT NVC0_TIC_0_FMT_BPTC_UFLOAT
-
-#if NOUVEAU_DRIVER == 0xc0
-# define NVXX_3D_VAF_SIZE(s) NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_##s
-# define NVXX_3D_VAF_TYPE(t) NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_##t
-#else
-# define NVXX_3D_VAF_SIZE(s) NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_##s
-# define NVXX_3D_VAF_TYPE(t) NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_##t
-#endif
-
-#define TBLENT_A_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u, br) \
- [PIPE_FORMAT_##pf] = { \
- sf, \
- (NV50_TIC_MAP_##r << NV50_TIC_0_MAPR__SHIFT) | \
- (NV50_TIC_MAP_##g << NV50_TIC_0_MAPG__SHIFT) | \
- (NV50_TIC_MAP_##b << NV50_TIC_0_MAPB__SHIFT) | \
- (NV50_TIC_MAP_##a << NV50_TIC_0_MAPA__SHIFT) | \
- (NV50_TIC_TYPE_##t0 << NV50_TIC_0_TYPE0__SHIFT) | \
- (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
- (NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
- (NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
- NV50_TIC_0_FMT_##sz, U_##u \
- }
-
-#define TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
+#define SF_A(sz) NV50_TIC_0_FMT_##sz
+#define SF_C(sz) NVC0_TIC_0_FMT_##sz
+#define SF(c, pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
[PIPE_FORMAT_##pf] = { \
sf, \
(NV50_TIC_MAP_##r << NV50_TIC_0_MAPR__SHIFT) | \
@@ -116,56 +75,42 @@
(NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
(NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
(NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
- NV50_TIC_0_FMT_##sz, U_##u \
+ SF_##c(sz), U_##u \
}
-#define C4A(p, n, r, g, b, a, t, s, u, br) \
- TBLENT_A_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u, br)
-#define C4B(p, n, r, g, b, a, t, s, u) \
- TBLENT_B_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
-
-#define ZXB(p, n, r, g, b, a, t, s, u) \
- TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
- r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
-#define ZSB(p, n, r, g, b, a, t, s, u) \
- TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
- r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
-#define SZB(p, n, r, g, b, a, t, s, u) \
- TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
- r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
-#define SXB(p, r, s, u) \
- TBLENT_B_(p, NV50_ZETA_FORMAT_NONE, \
- r, r, r, r, UINT, UINT, UINT, UINT, s, u)
-
-#define F3A(p, n, r, g, b, a, t, s, u) \
- C4A(p, n, r, g, b, ONE_FLOAT, t, s, u, 0)
-#define I3A(p, n, r, g, b, a, t, s, u) \
- C4A(p, n, r, g, b, ONE_INT, t, s, u, 0)
-#define F3B(p, n, r, g, b, a, t, s, u) \
- C4B(p, n, r, g, b, ONE_FLOAT, t, s, u)
-#define I3B(p, n, r, g, b, a, t, s, u) \
- C4B(p, n, r, g, b, ONE_INT, t, s, u)
-
-#define F2A(p, n, r, g, b, a, t, s, u) \
- C4A(p, n, r, g, ZERO, ONE_FLOAT, t, s, u, 0)
-#define I2A(p, n, r, g, b, a, t, s, u) \
- C4A(p, n, r, g, ZERO, ONE_INT, t, s, u, 0)
-#define F2B(p, n, r, g, b, a, t, s, u) \
- C4B(p, n, r, g, ZERO, ONE_FLOAT, t, s, u)
-#define I2B(p, n, r, g, b, a, t, s, u) \
- C4B(p, n, r, g, ZERO, ONE_INT, t, s, u)
-
-#define F1A(p, n, r, g, b, a, t, s, u) \
- C4A(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u, 0)
-#define I1A(p, n, r, g, b, a, t, s, u) \
- C4A(p, n, r, ZERO, ZERO, ONE_INT, t, s, u, 0)
-#define F1B(p, n, r, g, b, a, t, s, u) \
- C4B(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u)
-#define I1B(p, n, r, g, b, a, t, s, u) \
- C4B(p, n, r, ZERO, ZERO, ONE_INT, t, s, u)
-
-#define A1B(p, n, r, g, b, a, t, s, u) \
- C4B(p, n, ZERO, ZERO, ZERO, a, t, s, u)
+#define C4(c, p, n, r, g, b, a, t, s, u) \
+ SF(c, p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
+
+#define ZX(c, p, n, r, g, b, a, t, s, u) \
+ SF(c, p, NV50_ZETA_FORMAT_##n, \
+ r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
+#define ZS(c, p, n, r, g, b, a, t, s, u) \
+ SF(c, p, NV50_ZETA_FORMAT_##n, \
+ r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
+#define SZ(c, p, n, r, g, b, a, t, s, u) \
+ SF(c, p, NV50_ZETA_FORMAT_##n, \
+ r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
+#define SX(c, p, r, s, u) \
+ SF(c, p, NV50_ZETA_FORMAT_NONE, \
+ r, r, r, r, UINT, UINT, UINT, UINT, s, u)
+
+#define F3(c, p, n, r, g, b, a, t, s, u) \
+ C4(c, p, n, r, g, b, ONE_FLOAT, t, s, u)
+#define I3(c, p, n, r, g, b, a, t, s, u) \
+ C4(c, p, n, r, g, b, ONE_INT, t, s, u)
+
+#define F2(c, p, n, r, g, b, a, t, s, u) \
+ C4(c, p, n, r, g, ZERO, ONE_FLOAT, t, s, u)
+#define I2(c, p, n, r, g, b, a, t, s, u) \
+ C4(c, p, n, r, g, ZERO, ONE_INT, t, s, u)
+
+#define F1(c, p, n, r, g, b, a, t, s, u) \
+ C4(c, p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u)
+#define I1(c, p, n, r, g, b, a, t, s, u) \
+ C4(c, p, n, r, ZERO, ZERO, ONE_INT, t, s, u)
+
+#define A1(c, p, n, r, g, b, a, t, s, u) \
+ C4(c, p, n, ZERO, ZERO, ZERO, a, t, s, u)
#if NOUVEAU_DRIVER == 0xc0
const struct nvc0_format nvc0_format_table[PIPE_FORMAT_COUNT] =
@@ -173,399 +118,343 @@ const struct nvc0_format nvc0_format_table[PIPE_FORMAT_COUNT] =
const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
#endif
{
- C4A(B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM, 8_8_8_8, TDV, 1),
- F3A(B8G8R8X8_UNORM, BGRX8_UNORM, C2, C1, C0, xx, UNORM, 8_8_8_8, TD),
- C4A(B8G8R8A8_SRGB, BGRA8_SRGB, C2, C1, C0, C3, UNORM, 8_8_8_8, TD, 1),
- F3A(B8G8R8X8_SRGB, BGRX8_SRGB, C2, C1, C0, xx, UNORM, 8_8_8_8, TD),
- C4A(R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8, IBV, 0),
- F3A(R8G8B8X8_UNORM, RGBX8_UNORM, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
- C4A(R8G8B8A8_SRGB, RGBA8_SRGB, C0, C1, C2, C3, UNORM, 8_8_8_8, TB, 0),
- F3B(R8G8B8X8_SRGB, RGBX8_SRGB, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
-
- ZXB(Z16_UNORM, Z16_UNORM, C0, C0, C0, xx, UNORM, Z16, TZ),
- ZXB(Z32_FLOAT, Z32_FLOAT, C0, C0, C0, xx, FLOAT, Z32, TZ),
- ZXB(Z24X8_UNORM, Z24_X8_UNORM, C0, C0, C0, xx, UNORM, Z24_X8, TZ),
- SZB(X8Z24_UNORM, S8_Z24_UNORM, C1, C1, C1, xx, UNORM, S8_Z24, TZ),
- ZSB(Z24_UNORM_S8_UINT, Z24_S8_UNORM, C0, C0, C0, xx, UNORM, Z24_S8, TZ),
- SZB(S8_UINT_Z24_UNORM, S8_Z24_UNORM, C1, C1, C1, xx, UNORM, S8_Z24, TZ),
- ZSB(Z32_FLOAT_S8X24_UINT, Z32_S8_X24_FLOAT, C0, C0, C0, xx, FLOAT,
- Z32_S8_X24, TZ),
-
- SXB(S8_UINT, C0, 8, T),
- SXB(X24S8_UINT, C1, Z24_S8, T),
- SXB(S8X24_UINT, C0, S8_Z24, T),
- SXB(X32_S8X24_UINT, C1, Z32_S8_X24, T),
-
- F3B(B5G6R5_UNORM, B5G6R5_UNORM, C2, C1, C0, xx, UNORM, 5_6_5, TD),
- C4B(B5G5R5A1_UNORM, BGR5_A1_UNORM, C2, C1, C0, C3, UNORM, 5_5_5_1, TD),
- F3B(B5G5R5X1_UNORM, BGR5_X1_UNORM, C2, C1, C0, xx, UNORM, 5_5_5_1, TD),
- C4B(B4G4R4A4_UNORM, NONE, C2, C1, C0, C3, UNORM, 4_4_4_4, T),
- F3B(B4G4R4X4_UNORM, NONE, C2, C1, C0, xx, UNORM, 4_4_4_4, T),
- F3B(R9G9B9E5_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 9_9_9_E5, T),
-
- C4A(R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM, 10_10_10_2,
- IBV, 0),
- C4A(B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM, 10_10_10_2,
- TDV, 1),
- C4A(R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM, 10_10_10_2, TV, 0),
- C4A(B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM, 10_10_10_2, TV, 1),
- C4A(R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT, 10_10_10_2, TRV, 0),
- C4A(B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT, 10_10_10_2, TV, 0),
-
- F3A(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, IBV),
-
- F3B(L8_UNORM, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
- F3B(L8_SRGB, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
- F3B(L8_SNORM, R8_SNORM, C0, C0, C0, xx, SNORM, 8, TC),
- I3B(L8_SINT, R8_SINT, C0, C0, C0, xx, SINT, 8, TR),
- I3B(L8_UINT, R8_UINT, C0, C0, C0, xx, UINT, 8, TR),
- F3B(L16_UNORM, R16_UNORM, C0, C0, C0, xx, UNORM, 16, TC),
- F3B(L16_SNORM, R16_SNORM, C0, C0, C0, xx, SNORM, 16, TC),
- F3B(L16_FLOAT, R16_FLOAT, C0, C0, C0, xx, FLOAT, 16, TB),
- I3B(L16_SINT, R16_SINT, C0, C0, C0, xx, SINT, 16, TR),
- I3B(L16_UINT, R16_UINT, C0, C0, C0, xx, UINT, 16, TR),
- F3B(L32_FLOAT, R32_FLOAT, C0, C0, C0, xx, FLOAT, 32, TB),
- I3B(L32_SINT, R32_SINT, C0, C0, C0, xx, SINT, 32, TR),
- I3B(L32_UINT, R32_UINT, C0, C0, C0, xx, UINT, 32, TR),
-
- C4B(I8_UNORM, R8_UNORM, C0, C0, C0, C0, UNORM, 8, TR),
- C4B(I8_SNORM, R8_SNORM, C0, C0, C0, C0, SNORM, 8, TR),
- C4B(I8_SINT, R8_SINT, C0, C0, C0, C0, SINT, 8, TR),
- C4B(I8_UINT, R8_UINT, C0, C0, C0, C0, UINT, 8, TR),
- C4B(I16_UNORM, R16_UNORM, C0, C0, C0, C0, UNORM, 16, TR),
- C4B(I16_SNORM, R16_SNORM, C0, C0, C0, C0, SNORM, 16, TR),
- C4B(I16_FLOAT, R16_FLOAT, C0, C0, C0, C0, FLOAT, 16, TR),
- C4B(I16_SINT, R16_SINT, C0, C0, C0, C0, SINT, 16, TR),
- C4B(I16_UINT, R16_UINT, C0, C0, C0, C0, UINT, 16, TR),
- C4B(I32_FLOAT, R32_FLOAT, C0, C0, C0, C0, FLOAT, 32, TR),
- C4B(I32_SINT, R32_SINT, C0, C0, C0, C0, SINT, 32, TR),
- C4B(I32_UINT, R32_UINT, C0, C0, C0, C0, UINT, 32, TR),
-
- A1B(A8_UNORM, A8_UNORM, xx, xx, xx, C0, UNORM, 8, TB),
- A1B(A8_SNORM, R8_SNORM, xx, xx, xx, C0, SNORM, 8, T),
- A1B(A8_SINT, R8_SINT, xx, xx, xx, C0, SINT, 8, T),
- A1B(A8_UINT, R8_UINT, xx, xx, xx, C0, UINT, 8, T),
- A1B(A16_UNORM, R16_UNORM, xx, xx, xx, C0, UNORM, 16, T),
- A1B(A16_SNORM, R16_SNORM, xx, xx, xx, C0, SNORM, 16, T),
- A1B(A16_FLOAT, R16_FLOAT, xx, xx, xx, C0, FLOAT, 16, T),
- A1B(A16_SINT, R16_SINT, xx, xx, xx, C0, SINT, 16, T),
- A1B(A16_UINT, R16_UINT, xx, xx, xx, C0, UINT, 16, T),
- A1B(A32_FLOAT, R32_FLOAT, xx, xx, xx, C0, FLOAT, 32, T),
- A1B(A32_SINT, R32_SINT, xx, xx, xx, C0, SINT, 32, T),
- A1B(A32_UINT, R32_UINT, xx, xx, xx, C0, UINT, 32, T),
-
- C4B(L4A4_UNORM, NONE, C0, C0, C0, C1, UNORM, 4_4, T),
- C4B(L8A8_UNORM, RG8_UNORM, C0, C0, C0, C1, UNORM, 8_8, T),
- C4B(L8A8_SNORM, RG8_SNORM, C0, C0, C0, C1, SNORM, 8_8, T),
- C4B(L8A8_SRGB, RG8_UNORM, C0, C0, C0, C1, UNORM, 8_8, T),
- C4B(L8A8_SINT, RG8_SINT, C0, C0, C0, C1, SINT, 8_8, T),
- C4B(L8A8_UINT, RG8_UINT, C0, C0, C0, C1, UINT, 8_8, T),
- C4B(L16A16_UNORM, RG16_UNORM, C0, C0, C0, C1, UNORM, 16_16, T),
- C4B(L16A16_SNORM, RG16_SNORM, C0, C0, C0, C1, SNORM, 16_16, T),
- C4B(L16A16_FLOAT, RG16_FLOAT, C0, C0, C0, C1, FLOAT, 16_16, T),
- C4B(L16A16_SINT, RG16_SINT, C0, C0, C0, C1, SINT, 16_16, T),
- C4B(L16A16_UINT, RG16_UINT, C0, C0, C0, C1, UINT, 16_16, T),
- C4B(L32A32_FLOAT, RG32_FLOAT, C0, C0, C0, C1, FLOAT, 32_32, T),
- C4B(L32A32_SINT, RG32_SINT, C0, C0, C0, C1, SINT, 32_32, T),
- C4B(L32A32_UINT, RG32_UINT, C0, C0, C0, C1, UINT, 32_32, T),
-
- F3B(DXT1_RGB, NONE, C0, C1, C2, xx, UNORM, DXT1, T),
- F3B(DXT1_SRGB, NONE, C0, C1, C2, xx, UNORM, DXT1, T),
- C4B(DXT1_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT1, T),
- C4B(DXT1_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT1, T),
- C4B(DXT3_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT3, T),
- C4B(DXT3_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT3, T),
- C4B(DXT5_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT5, T),
- C4B(DXT5_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT5, T),
-
- F1B(RGTC1_UNORM, NONE, C0, xx, xx, xx, UNORM, RGTC1, T),
- F1B(RGTC1_SNORM, NONE, C0, xx, xx, xx, SNORM, RGTC1, T),
- F2B(RGTC2_UNORM, NONE, C0, C1, xx, xx, UNORM, RGTC2, T),
- F2B(RGTC2_SNORM, NONE, C0, C1, xx, xx, SNORM, RGTC2, T),
- F3B(LATC1_UNORM, NONE, C0, C0, C0, xx, UNORM, RGTC1, T),
- F3B(LATC1_SNORM, NONE, C0, C0, C0, xx, SNORM, RGTC1, T),
- C4B(LATC2_UNORM, NONE, C0, C0, C0, C1, UNORM, RGTC2, T),
- C4B(LATC2_SNORM, NONE, C0, C0, C0, C1, SNORM, RGTC2, T),
-
- C4B(BPTC_RGBA_UNORM, NONE, C0, C1, C2, C3, UNORM, BPTC, t),
- C4B(BPTC_SRGBA, NONE, C0, C1, C2, C3, UNORM, BPTC, t),
- F3B(BPTC_RGB_FLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_FLOAT, t),
- F3B(BPTC_RGB_UFLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_UFLOAT, t),
-
- C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32,
- IBV, 0),
- C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, TV, 0),
- C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, TV, 0),
- C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32,
- IRV, 0),
- C4A(R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT, 32_32_32_32,
- IRV, 0),
- F3B(R32G32B32X32_FLOAT, RGBX32_FLOAT, C0, C1, C2, xx, FLOAT, 32_32_32_32, TB),
- I3B(R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT, 32_32_32_32, TR),
- I3B(R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT, 32_32_32_32, TR),
-
- F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
- I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
- I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
-
- F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
- F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
- F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
- I2A(R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IRV),
- I2A(R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IRV),
-
- F1A(R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IBV),
- F1A(R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, TV),
- F1A(R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, TV),
- I1A(R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IRV),
- I1A(R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IRV),
-
- C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16,
- IBV, 0),
- C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16,
- ICV, 0),
- C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16,
- ICV, 0),
- C4A(R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT, 16_16_16_16,
- IRV, 0),
- C4A(R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT, 16_16_16_16,
- IRV, 0),
- F3B(R16G16B16X16_FLOAT, RGBX16_FLOAT, C0, C1, C2, xx, FLOAT, 16_16_16_16, TB),
- F3B(R16G16B16X16_UNORM, RGBA16_UNORM, C0, C1, C2, xx, UNORM, 16_16_16_16, T),
- F3B(R16G16B16X16_SNORM, RGBA16_SNORM, C0, C1, C2, xx, SNORM, 16_16_16_16, T),
- I3B(R16G16B16X16_SINT, RGBA16_SINT, C0, C1, C2, xx, SINT, 16_16_16_16, T),
- I3B(R16G16B16X16_UINT, RGBA16_UINT, C0, C1, C2, xx, UINT, 16_16_16_16, T),
-
- F2A(R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IBV),
- F2A(R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, ICV),
- F2A(R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, ICV),
- I2A(R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IRV),
- I2A(R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IRV),
-
- F1A(R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IBV),
- F1A(R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, ICV),
- F1A(R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, ICV),
- I1A(R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IRV),
- I1A(R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IRV),
-
- C4A(R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8, ICV, 0),
- C4A(R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IRV, 0),
- C4A(R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IRV, 0),
- F3B(R8G8B8X8_SNORM, RGBA8_SNORM, C0, C1, C2, xx, SNORM, 8_8_8_8, T),
- I3B(R8G8B8X8_SINT, RGBA8_SINT, C0, C1, C2, xx, SINT, 8_8_8_8, T),
- I3B(R8G8B8X8_UINT, RGBA8_UINT, C0, C1, C2, xx, UINT, 8_8_8_8, T),
-
- F2A(R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IBV),
- F2A(R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, ICV),
- I2A(R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IRV),
- I2A(R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IRV),
-
- F1A(R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IBV),
- F1A(R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, ICV),
- I1A(R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IRV),
- I1A(R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IRV),
-
- F3B(R8G8_B8G8_UNORM, NONE, C0, C1, C2, xx, UNORM, U8_YA8_V8_YB8, T),
- F3B(G8R8_B8R8_UNORM, NONE, C1, C0, C2, xx, UNORM, U8_YA8_V8_YB8, T),
- F3B(G8R8_G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, YA8_U8_YB8_V8, T),
- F3B(R8G8_R8B8_UNORM, NONE, C1, C0, C2, xx, UNORM, YA8_U8_YB8_V8, T),
-
- F1B(R1_UNORM, BITMAP, C0, xx, xx, xx, UNORM, BITMAP, T),
-
- C4B(R4A4_UNORM, NONE, C0, ZERO, ZERO, C1, UNORM, 4_4, T),
- C4B(R8A8_UNORM, NONE, C0, ZERO, ZERO, C1, UNORM, 8_8, T),
- C4B(A4R4_UNORM, NONE, C1, ZERO, ZERO, C0, UNORM, 4_4, T),
- C4B(A8R8_UNORM, NONE, C1, ZERO, ZERO, C0, UNORM, 8_8, T),
-
- TBLENT_B_(R8SG8SB8UX8U_NORM, 0,
- C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 8_8_8_8, T),
- TBLENT_B_(R5SG5SB6U_NORM, 0,
- C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 5_5_6, T),
+ C4(A, B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM, 8_8_8_8, TD),
+ F3(A, B8G8R8X8_UNORM, BGRX8_UNORM, C2, C1, C0, xx, UNORM, 8_8_8_8, TD),
+ C4(A, B8G8R8A8_SRGB, BGRA8_SRGB, C2, C1, C0, C3, UNORM, 8_8_8_8, TD),
+ F3(A, B8G8R8X8_SRGB, BGRX8_SRGB, C2, C1, C0, xx, UNORM, 8_8_8_8, TD),
+ C4(A, R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8, IB),
+ F3(A, R8G8B8X8_UNORM, RGBX8_UNORM, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
+ C4(A, R8G8B8A8_SRGB, RGBA8_SRGB, C0, C1, C2, C3, UNORM, 8_8_8_8, TB),
+ F3(A, R8G8B8X8_SRGB, RGBX8_SRGB, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
+
+ ZX(A, Z16_UNORM, Z16_UNORM, C0, C0, C0, xx, UNORM, Z16, TZ),
+ ZX(A, Z32_FLOAT, Z32_FLOAT, C0, C0, C0, xx, FLOAT, Z32, TZ),
+ ZX(A, Z24X8_UNORM, Z24_X8_UNORM, C0, C0, C0, xx, UNORM, Z24_X8, TZ),
+ SZ(A, X8Z24_UNORM, S8_Z24_UNORM, C1, C1, C1, xx, UNORM, S8_Z24, TZ),
+ ZS(A, Z24_UNORM_S8_UINT, Z24_S8_UNORM, C0, C0, C0, xx, UNORM, Z24_S8, TZ),
+ SZ(A, S8_UINT_Z24_UNORM, S8_Z24_UNORM, C1, C1, C1, xx, UNORM, S8_Z24, TZ),
+ ZS(A, Z32_FLOAT_S8X24_UINT, Z32_S8_X24_FLOAT, C0, C0, C0, xx, FLOAT, Z32_S8_X24, TZ),
+
+ SX(A, S8_UINT, C0, 8, T),
+ SX(A, X24S8_UINT, C1, Z24_S8, T),
+ SX(A, S8X24_UINT, C0, S8_Z24, T),
+ SX(A, X32_S8X24_UINT, C1, Z32_S8_X24, T),
+
+ F3(A, B5G6R5_UNORM, B5G6R5_UNORM, C2, C1, C0, xx, UNORM, 5_6_5, TD),
+ C4(A, B5G5R5A1_UNORM, BGR5_A1_UNORM, C2, C1, C0, C3, UNORM, 5_5_5_1, TD),
+ F3(A, B5G5R5X1_UNORM, BGR5_X1_UNORM, C2, C1, C0, xx, UNORM, 5_5_5_1, TD),
+ C4(A, B4G4R4A4_UNORM, NONE, C2, C1, C0, C3, UNORM, 4_4_4_4, T),
+ F3(A, B4G4R4X4_UNORM, NONE, C2, C1, C0, xx, UNORM, 4_4_4_4, T),
+ F3(A, R9G9B9E5_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 9_9_9_E5, T),
+
+ C4(A, R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM, 10_10_10_2, IB),
+ C4(A, B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM, 10_10_10_2, TD),
+ C4(A, R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM, 10_10_10_2, T),
+ C4(A, B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM, 10_10_10_2, T),
+ C4(A, R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT, 10_10_10_2, TR),
+ C4(A, B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT, 10_10_10_2, T),
+
+ F3(A, R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, IB),
+
+ F3(A, L8_UNORM, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
+ F3(A, L8_SRGB, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
+ F3(A, L8_SNORM, R8_SNORM, C0, C0, C0, xx, SNORM, 8, TC),
+ I3(A, L8_SINT, R8_SINT, C0, C0, C0, xx, SINT, 8, TR),
+ I3(A, L8_UINT, R8_UINT, C0, C0, C0, xx, UINT, 8, TR),
+ F3(A, L16_UNORM, R16_UNORM, C0, C0, C0, xx, UNORM, 16, TC),
+ F3(A, L16_SNORM, R16_SNORM, C0, C0, C0, xx, SNORM, 16, TC),
+ F3(A, L16_FLOAT, R16_FLOAT, C0, C0, C0, xx, FLOAT, 16, TB),
+ I3(A, L16_SINT, R16_SINT, C0, C0, C0, xx, SINT, 16, TR),
+ I3(A, L16_UINT, R16_UINT, C0, C0, C0, xx, UINT, 16, TR),
+ F3(A, L32_FLOAT, R32_FLOAT, C0, C0, C0, xx, FLOAT, 32, TB),
+ I3(A, L32_SINT, R32_SINT, C0, C0, C0, xx, SINT, 32, TR),
+ I3(A, L32_UINT, R32_UINT, C0, C0, C0, xx, UINT, 32, TR),
+
+ C4(A, I8_UNORM, R8_UNORM, C0, C0, C0, C0, UNORM, 8, TR),
+ C4(A, I8_SNORM, R8_SNORM, C0, C0, C0, C0, SNORM, 8, TR),
+ C4(A, I8_SINT, R8_SINT, C0, C0, C0, C0, SINT, 8, TR),
+ C4(A, I8_UINT, R8_UINT, C0, C0, C0, C0, UINT, 8, TR),
+ C4(A, I16_UNORM, R16_UNORM, C0, C0, C0, C0, UNORM, 16, TR),
+ C4(A, I16_SNORM, R16_SNORM, C0, C0, C0, C0, SNORM, 16, TR),
+ C4(A, I16_FLOAT, R16_FLOAT, C0, C0, C0, C0, FLOAT, 16, TR),
+ C4(A, I16_SINT, R16_SINT, C0, C0, C0, C0, SINT, 16, TR),
+ C4(A, I16_UINT, R16_UINT, C0, C0, C0, C0, UINT, 16, TR),
+ C4(A, I32_FLOAT, R32_FLOAT, C0, C0, C0, C0, FLOAT, 32, TR),
+ C4(A, I32_SINT, R32_SINT, C0, C0, C0, C0, SINT, 32, TR),
+ C4(A, I32_UINT, R32_UINT, C0, C0, C0, C0, UINT, 32, TR),
+
+ A1(A, A8_UNORM, A8_UNORM, xx, xx, xx, C0, UNORM, 8, TB),
+ A1(A, A8_SNORM, R8_SNORM, xx, xx, xx, C0, SNORM, 8, T),
+ A1(A, A8_SINT, R8_SINT, xx, xx, xx, C0, SINT, 8, T),
+ A1(A, A8_UINT, R8_UINT, xx, xx, xx, C0, UINT, 8, T),
+ A1(A, A16_UNORM, R16_UNORM, xx, xx, xx, C0, UNORM, 16, T),
+ A1(A, A16_SNORM, R16_SNORM, xx, xx, xx, C0, SNORM, 16, T),
+ A1(A, A16_FLOAT, R16_FLOAT, xx, xx, xx, C0, FLOAT, 16, T),
+ A1(A, A16_SINT, R16_SINT, xx, xx, xx, C0, SINT, 16, T),
+ A1(A, A16_UINT, R16_UINT, xx, xx, xx, C0, UINT, 16, T),
+ A1(A, A32_FLOAT, R32_FLOAT, xx, xx, xx, C0, FLOAT, 32, T),
+ A1(A, A32_SINT, R32_SINT, xx, xx, xx, C0, SINT, 32, T),
+ A1(A, A32_UINT, R32_UINT, xx, xx, xx, C0, UINT, 32, T),
+
+ C4(A, L4A4_UNORM, NONE, C0, C0, C0, C1, UNORM, 4_4, T),
+ C4(A, L8A8_UNORM, RG8_UNORM, C0, C0, C0, C1, UNORM, 8_8, T),
+ C4(A, L8A8_SNORM, RG8_SNORM, C0, C0, C0, C1, SNORM, 8_8, T),
+ C4(A, L8A8_SRGB, RG8_UNORM, C0, C0, C0, C1, UNORM, 8_8, T),
+ C4(A, L8A8_SINT, RG8_SINT, C0, C0, C0, C1, SINT, 8_8, T),
+ C4(A, L8A8_UINT, RG8_UINT, C0, C0, C0, C1, UINT, 8_8, T),
+ C4(A, L16A16_UNORM, RG16_UNORM, C0, C0, C0, C1, UNORM, 16_16, T),
+ C4(A, L16A16_SNORM, RG16_SNORM, C0, C0, C0, C1, SNORM, 16_16, T),
+ C4(A, L16A16_FLOAT, RG16_FLOAT, C0, C0, C0, C1, FLOAT, 16_16, T),
+ C4(A, L16A16_SINT, RG16_SINT, C0, C0, C0, C1, SINT, 16_16, T),
+ C4(A, L16A16_UINT, RG16_UINT, C0, C0, C0, C1, UINT, 16_16, T),
+ C4(A, L32A32_FLOAT, RG32_FLOAT, C0, C0, C0, C1, FLOAT, 32_32, T),
+ C4(A, L32A32_SINT, RG32_SINT, C0, C0, C0, C1, SINT, 32_32, T),
+ C4(A, L32A32_UINT, RG32_UINT, C0, C0, C0, C1, UINT, 32_32, T),
+
+ F3(A, DXT1_RGB, NONE, C0, C1, C2, xx, UNORM, DXT1, T),
+ F3(A, DXT1_SRGB, NONE, C0, C1, C2, xx, UNORM, DXT1, T),
+ C4(A, DXT1_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT1, T),
+ C4(A, DXT1_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT1, T),
+ C4(A, DXT3_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT3, T),
+ C4(A, DXT3_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT3, T),
+ C4(A, DXT5_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT5, T),
+ C4(A, DXT5_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT5, T),
+
+ F1(A, RGTC1_UNORM, NONE, C0, xx, xx, xx, UNORM, RGTC1, T),
+ F1(A, RGTC1_SNORM, NONE, C0, xx, xx, xx, SNORM, RGTC1, T),
+ F2(A, RGTC2_UNORM, NONE, C0, C1, xx, xx, UNORM, RGTC2, T),
+ F2(A, RGTC2_SNORM, NONE, C0, C1, xx, xx, SNORM, RGTC2, T),
+ F3(A, LATC1_UNORM, NONE, C0, C0, C0, xx, UNORM, RGTC1, T),
+ F3(A, LATC1_SNORM, NONE, C0, C0, C0, xx, SNORM, RGTC1, T),
+ C4(A, LATC2_UNORM, NONE, C0, C0, C0, C1, UNORM, RGTC2, T),
+ C4(A, LATC2_SNORM, NONE, C0, C0, C0, C1, SNORM, RGTC2, T),
+
+ C4(C, BPTC_RGBA_UNORM, NONE, C0, C1, C2, C3, UNORM, BPTC, t),
+ C4(C, BPTC_SRGBA, NONE, C0, C1, C2, C3, UNORM, BPTC, t),
+ F3(C, BPTC_RGB_FLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_FLOAT, t),
+ F3(C, BPTC_RGB_UFLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_UFLOAT, t),
+
+ C4(A, R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32, IB),
+ C4(A, R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, T),
+ C4(A, R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, T),
+ C4(A, R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32, IR),
+ C4(A, R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT, 32_32_32_32, IR),
+ F3(A, R32G32B32X32_FLOAT, RGBX32_FLOAT, C0, C1, C2, xx, FLOAT, 32_32_32_32, TB),
+ I3(A, R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT, 32_32_32_32, TR),
+ I3(A, R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT, 32_32_32_32, TR),
+
+ F3(C, R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, t),
+ I3(C, R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, t),
+ I3(C, R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, t),
+
+ F2(A, R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IB),
+ F2(A, R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, T),
+ F2(A, R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, T),
+ I2(A, R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IR),
+ I2(A, R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IR),
+
+ F1(A, R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IB),
+ F1(A, R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, T),
+ F1(A, R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, T),
+ I1(A, R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IR),
+ I1(A, R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IR),
+
+ C4(A, R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16, IB),
+ C4(A, R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16, IC),
+ C4(A, R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16, IC),
+ C4(A, R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT, 16_16_16_16, IR),
+ C4(A, R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT, 16_16_16_16, IR),
+ F3(A, R16G16B16X16_FLOAT, RGBX16_FLOAT, C0, C1, C2, xx, FLOAT, 16_16_16_16, TB),
+ F3(A, R16G16B16X16_UNORM, RGBA16_UNORM, C0, C1, C2, xx, UNORM, 16_16_16_16, T),
+ F3(A, R16G16B16X16_SNORM, RGBA16_SNORM, C0, C1, C2, xx, SNORM, 16_16_16_16, T),
+ I3(A, R16G16B16X16_SINT, RGBA16_SINT, C0, C1, C2, xx, SINT, 16_16_16_16, T),
+ I3(A, R16G16B16X16_UINT, RGBA16_UINT, C0, C1, C2, xx, UINT, 16_16_16_16, T),
+
+ F2(A, R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IB),
+ F2(A, R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, IC),
+ F2(A, R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, IC),
+ I2(A, R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IR),
+ I2(A, R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IR),
+
+ F1(A, R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IB),
+ F1(A, R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, IC),
+ F1(A, R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, IC),
+ I1(A, R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IR),
+ I1(A, R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IR),
+
+ C4(A, R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8, IC),
+ C4(A, R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IR),
+ C4(A, R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IR),
+ F3(A, R8G8B8X8_SNORM, RGBA8_SNORM, C0, C1, C2, xx, SNORM, 8_8_8_8, T),
+ I3(A, R8G8B8X8_SINT, RGBA8_SINT, C0, C1, C2, xx, SINT, 8_8_8_8, T),
+ I3(A, R8G8B8X8_UINT, RGBA8_UINT, C0, C1, C2, xx, UINT, 8_8_8_8, T),
+
+ F2(A, R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IB),
+ F2(A, R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, IC),
+ I2(A, R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IR),
+ I2(A, R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IR),
+
+ F1(A, R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IB),
+ F1(A, R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, IC),
+ I1(A, R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IR),
+ I1(A, R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IR),
+
+ F3(A, R8G8_B8G8_UNORM, NONE, C0, C1, C2, xx, UNORM, U8_YA8_V8_YB8, T),
+ F3(A, G8R8_B8R8_UNORM, NONE, C1, C0, C2, xx, UNORM, U8_YA8_V8_YB8, T),
+ F3(A, G8R8_G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, YA8_U8_YB8_V8, T),
+ F3(A, R8G8_R8B8_UNORM, NONE, C1, C0, C2, xx, UNORM, YA8_U8_YB8_V8, T),
+
+ F1(A, R1_UNORM, BITMAP, C0, xx, xx, xx, UNORM, BITMAP, T),
+
+ C4(A, R4A4_UNORM, NONE, C0, ZERO, ZERO, C1, UNORM, 4_4, T),
+ C4(A, R8A8_UNORM, NONE, C0, ZERO, ZERO, C1, UNORM, 8_8, T),
+ C4(A, A4R4_UNORM, NONE, C1, ZERO, ZERO, C0, UNORM, 4_4, T),
+ C4(A, A8R8_UNORM, NONE, C1, ZERO, ZERO, C0, UNORM, 8_8, T),
+
+ SF(A, R8SG8SB8UX8U_NORM, 0, C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 8_8_8_8, T),
+ SF(A, R5SG5SB6U_NORM, 0, C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 5_5_6, T),
};
-#define V_TBLENT_A_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u, br) \
- [PIPE_FORMAT_##pf] = { \
- NVXX_3D_VAF_SIZE(sz) | NVXX_3D_VAF_TYPE(t0) | (br << 31), \
- PIPE_BIND_VERTEX_BUFFER \
- }
+#if NOUVEAU_DRIVER == 0xc0
+# define NVXX_3D_VAF_SIZE(s) NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_##s
+# define NVXX_3D_VAF_TYPE(t) NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_##t
+#else
+# define NVXX_3D_VAF_SIZE(s) NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_##s
+# define NVXX_3D_VAF_TYPE(t) NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_##t
+#endif
-#define V_TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
+#define VF_x(pf, type, size, bgra) 0
+#define VF_A(pf, type, size, bgra) \
+ NVXX_3D_VAF_SIZE(size) | NVXX_3D_VAF_TYPE(type) | (bgra << 31)
+#define VF(c, pf, type, size, bgra) \
[PIPE_FORMAT_##pf] = { \
- 0, \
+ VF_##c(pf, type, size, bgra), \
PIPE_BIND_VERTEX_BUFFER \
}
-#define V_C4A(p, n, r, g, b, a, t, s, u, br) \
- V_TBLENT_A_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u, br)
-#define V_C4B(p, n, r, g, b, a, t, s, u) \
- V_TBLENT_B_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
-
-#define V_ZXB(p, n, r, g, b, a, t, s, u) \
- V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
- r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
-#define V_ZSB(p, n, r, g, b, a, t, s, u) \
- V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
- r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
-#define V_SZB(p, n, r, g, b, a, t, s, u) \
- V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n, \
- r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
-#define V_SXB(p, r, s, u) \
- V_TBLENT_B_(p, NV50_ZETA_FORMAT_NONE, \
- r, r, r, r, UINT, UINT, UINT, UINT, s, u)
-
-#define V_F3A(p, n, r, g, b, a, t, s, u) \
- V_C4A(p, n, r, g, b, ONE_FLOAT, t, s, u, 0)
-#define V_I3A(p, n, r, g, b, a, t, s, u) \
- V_C4A(p, n, r, g, b, ONE_INT, t, s, u, 0)
-#define V_F3B(p, n, r, g, b, a, t, s, u) \
- V_C4B(p, n, r, g, b, ONE_FLOAT, t, s, u)
-#define V_I3B(p, n, r, g, b, a, t, s, u) \
- V_C4B(p, n, r, g, b, ONE_INT, t, s, u)
-
-#define V_F2A(p, n, r, g, b, a, t, s, u) \
- V_C4A(p, n, r, g, ZERO, ONE_FLOAT, t, s, u, 0)
-#define V_I2A(p, n, r, g, b, a, t, s, u) \
- V_C4A(p, n, r, g, ZERO, ONE_INT, t, s, u, 0)
-#define V_F2B(p, n, r, g, b, a, t, s, u) \
- V_C4B(p, n, r, g, ZERO, ONE_FLOAT, t, s, u)
-#define V_I2B(p, n, r, g, b, a, t, s, u) \
- V_C4B(p, n, r, g, ZERO, ONE_INT, t, s, u)
-
-#define V_F1A(p, n, r, g, b, a, t, s, u) \
- V_C4A(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u, 0)
-#define V_I1A(p, n, r, g, b, a, t, s, u) \
- V_C4A(p, n, r, ZERO, ZERO, ONE_INT, t, s, u, 0)
-#define V_F1B(p, n, r, g, b, a, t, s, u) \
- V_C4B(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u)
-#define V_I1B(p, n, r, g, b, a, t, s, u) \
- V_C4B(p, n, r, ZERO, ZERO, ONE_INT, t, s, u)
-
-#define V_A1B(p, n, r, g, b, a, t, s, u) \
- V_C4B(p, n, ZERO, ZERO, ZERO, a, t, s, u)
-
#if NOUVEAU_DRIVER == 0xc0
const struct nvc0_vertex_format nvc0_vertex_format[PIPE_FORMAT_COUNT] =
#else
const struct nv50_vertex_format nv50_vertex_format[PIPE_FORMAT_COUNT] =
#endif
{
- V_C4A(B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM, 8_8_8_8, TDV, 1),
- V_C4A(R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8, IBV, 0),
-
- V_C4A(R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM, 10_10_10_2, IBV, 0),
- V_C4A(B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM, 10_10_10_2, TDV, 1),
- V_C4A(R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM, 10_10_10_2, TV, 0),
- V_C4A(B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM, 10_10_10_2, TV, 1),
- V_C4A(R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT, 10_10_10_2, TRV, 0),
- V_C4A(B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT, 10_10_10_2, TV, 0),
-
- V_F3A(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, IBV),
-
- V_C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32, IBV, 0),
- V_C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, TV, 0),
- V_C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, TV, 0),
- V_C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32, IRV, 0),
- V_C4A(R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT, 32_32_32_32, IRV, 0),
-
- V_F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
- V_F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
- V_F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
- V_I2A(R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IRV),
- V_I2A(R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IRV),
-
- V_F1A(R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IBV),
- V_F1A(R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, TV),
- V_F1A(R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, TV),
- V_I1A(R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IRV),
- V_I1A(R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IRV),
-
- V_C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16, IBV, 0),
- V_C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16, ICV, 0),
- V_C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16, ICV, 0),
- V_C4A(R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT, 16_16_16_16, IRV, 0),
- V_C4A(R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT, 16_16_16_16, IRV, 0),
-
- V_F2A(R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IBV),
- V_F2A(R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, ICV),
- V_F2A(R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, ICV),
- V_I2A(R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IRV),
- V_I2A(R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IRV),
-
- V_F1A(R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IBV),
- V_F1A(R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, ICV),
- V_F1A(R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, ICV),
- V_I1A(R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IRV),
- V_I1A(R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IRV),
-
- V_C4A(R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8, ICV, 0),
- V_C4A(R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IRV, 0),
- V_C4A(R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IRV, 0),
-
- V_F2A(R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IBV),
- V_F2A(R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, ICV),
- V_I2A(R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IRV),
- V_I2A(R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IRV),
-
- V_F1A(R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IBV),
- V_F1A(R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, ICV),
- V_I1A(R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IRV),
- V_I1A(R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IRV),
-
- V_C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 32_32_32_32, V, 0),
- V_C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED, 32_32_32_32, V, 0),
- V_F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
- V_F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
- V_F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
- V_I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
- V_I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
- V_F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
- V_F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
- V_F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
- V_F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
- V_F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
- V_F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
-
- V_C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 16_16_16_16, V, 0),
- V_C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED, 16_16_16_16, V, 0),
- V_F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
- V_F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
- V_F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
- V_I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
- V_I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
- V_F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
- V_F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
- V_F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
- V_F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
- V_F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
- V_F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
-
- V_C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 0),
- V_C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 0),
- V_C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V, 1),
- V_C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V, 1),
-
- V_C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
- V_C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
- V_F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
- V_F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
- V_I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
- V_I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
- V_F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
- V_F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
- V_F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
- V_F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
- V_F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
- V_F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
+ VF(A, B8G8R8A8_UNORM, UNORM, 8_8_8_8, 1),
+ VF(A, R8G8B8A8_UNORM, UNORM, 8_8_8_8, 0),
+
+ VF(A, R10G10B10A2_UNORM, UNORM, 10_10_10_2, 0),
+ VF(A, B10G10R10A2_UNORM, UNORM, 10_10_10_2, 1),
+ VF(A, R10G10B10A2_SNORM, SNORM, 10_10_10_2, 0),
+ VF(A, B10G10R10A2_SNORM, SNORM, 10_10_10_2, 1),
+ VF(A, R10G10B10A2_UINT, UINT, 10_10_10_2, 0),
+ VF(A, B10G10R10A2_UINT, UINT, 10_10_10_2, 0),
+
+ VF(A, R11G11B10_FLOAT, FLOAT, 11_11_10, 0),
+
+ VF(A, R32G32B32A32_FLOAT, FLOAT, 32_32_32_32, 0),
+ VF(A, R32G32B32A32_UNORM, UNORM, 32_32_32_32, 0),
+ VF(A, R32G32B32A32_SNORM, SNORM, 32_32_32_32, 0),
+ VF(A, R32G32B32A32_SINT, SINT, 32_32_32_32, 0),
+ VF(A, R32G32B32A32_UINT, UINT, 32_32_32_32, 0),
+
+ VF(A, R32G32_FLOAT, FLOAT, 32_32, 0),
+ VF(A, R32G32_UNORM, UNORM, 32_32, 0),
+ VF(A, R32G32_SNORM, SNORM, 32_32, 0),
+ VF(A, R32G32_SINT, SINT, 32_32, 0),
+ VF(A, R32G32_UINT, UINT, 32_32, 0),
+
+ VF(A, R32_FLOAT, FLOAT, 32, 0),
+ VF(A, R32_UNORM, UNORM, 32, 0),
+ VF(A, R32_SNORM, SNORM, 32, 0),
+ VF(A, R32_SINT, SINT, 32, 0),
+ VF(A, R32_UINT, UINT, 32, 0),
+
+ VF(A, R16G16B16A16_FLOAT, FLOAT, 16_16_16_16, 0),
+ VF(A, R16G16B16A16_UNORM, UNORM, 16_16_16_16, 0),
+ VF(A, R16G16B16A16_SNORM, SNORM, 16_16_16_16, 0),
+ VF(A, R16G16B16A16_SINT, SINT, 16_16_16_16, 0),
+ VF(A, R16G16B16A16_UINT, UINT, 16_16_16_16, 0),
+
+ VF(A, R16G16_FLOAT, FLOAT, 16_16, 0),
+ VF(A, R16G16_UNORM, UNORM, 16_16, 0),
+ VF(A, R16G16_SNORM, SNORM, 16_16, 0),
+ VF(A, R16G16_SINT, SINT, 16_16, 0),
+ VF(A, R16G16_UINT, UINT, 16_16, 0),
+
+ VF(A, R16_FLOAT, FLOAT, 16, 0),
+ VF(A, R16_UNORM, UNORM, 16, 0),
+ VF(A, R16_SNORM, SNORM, 16, 0),
+ VF(A, R16_SINT, SINT, 16, 0),
+ VF(A, R16_UINT, UINT, 16, 0),
+
+ VF(A, R8G8B8A8_SNORM, SNORM, 8_8_8_8, 0),
+ VF(A, R8G8B8A8_SINT, SINT, 8_8_8_8, 0),
+ VF(A, R8G8B8A8_UINT, UINT, 8_8_8_8, 0),
+
+ VF(A, R8G8_UNORM, UNORM, 8_8, 0),
+ VF(A, R8G8_SNORM, SNORM, 8_8, 0),
+ VF(A, R8G8_SINT, SINT, 8_8, 0),
+ VF(A, R8G8_UINT, UINT, 8_8, 0),
+
+ VF(A, R8_UNORM, UNORM, 8, 0),
+ VF(A, R8_SNORM, SNORM, 8, 0),
+ VF(A, R8_SINT, SINT, 8, 0),
+ VF(A, R8_UINT, UINT, 8, 0),
+
+ VF(A, R32G32B32A32_SSCALED, SSCALED, 32_32_32_32, 0),
+ VF(A, R32G32B32A32_USCALED, USCALED, 32_32_32_32, 0),
+ VF(A, R32G32B32_FLOAT, FLOAT, 32_32_32, 0),
+ VF(A, R32G32B32_UNORM, UNORM, 32_32_32, 0),
+ VF(A, R32G32B32_SNORM, SNORM, 32_32_32, 0),
+ VF(A, R32G32B32_SINT, SINT, 32_32_32, 0),
+ VF(A, R32G32B32_UINT, UINT, 32_32_32, 0),
+ VF(A, R32G32B32_SSCALED, SSCALED, 32_32_32, 0),
+ VF(A, R32G32B32_USCALED, USCALED, 32_32_32, 0),
+ VF(A, R32G32_SSCALED, SSCALED, 32_32, 0),
+ VF(A, R32G32_USCALED, USCALED, 32_32, 0),
+ VF(A, R32_SSCALED, SSCALED, 32, 0),
+ VF(A, R32_USCALED, USCALED, 32, 0),
+
+ VF(A, R16G16B16A16_SSCALED, SSCALED, 16_16_16_16, 0),
+ VF(A, R16G16B16A16_USCALED, USCALED, 16_16_16_16, 0),
+ VF(A, R16G16B16_FLOAT, FLOAT, 16_16_16, 0),
+ VF(A, R16G16B16_UNORM, UNORM, 16_16_16, 0),
+ VF(A, R16G16B16_SNORM, SNORM, 16_16_16, 0),
+ VF(A, R16G16B16_SINT, SINT, 16_16_16, 0),
+ VF(A, R16G16B16_UINT, UINT, 16_16_16, 0),
+ VF(A, R16G16B16_SSCALED, SSCALED, 16_16_16, 0),
+ VF(A, R16G16B16_USCALED, USCALED, 16_16_16, 0),
+ VF(A, R16G16_SSCALED, SSCALED, 16_16, 0),
+ VF(A, R16G16_USCALED, USCALED, 16_16, 0),
+ VF(A, R16_SSCALED, SSCALED, 16, 0),
+ VF(A, R16_USCALED, USCALED, 16, 0),
+
+ VF(A, R10G10B10A2_USCALED, USCALED, 10_10_10_2, 0),
+ VF(A, R10G10B10A2_SSCALED, SSCALED, 10_10_10_2, 0),
+ VF(A, B10G10R10A2_USCALED, USCALED, 10_10_10_2, 1),
+ VF(A, B10G10R10A2_SSCALED, SSCALED, 10_10_10_2, 1),
+
+ VF(A, R8G8B8A8_SSCALED, SSCALED, 8_8_8_8, 0),
+ VF(A, R8G8B8A8_USCALED, USCALED, 8_8_8_8, 0),
+ VF(A, R8G8B8_UNORM, UNORM, 8_8_8, 0),
+ VF(A, R8G8B8_SNORM, SNORM, 8_8_8, 0),
+ VF(A, R8G8B8_SINT, SINT, 8_8_8, 0),
+ VF(A, R8G8B8_UINT, UINT, 8_8_8, 0),
+ VF(A, R8G8B8_SSCALED, SSCALED, 8_8_8, 0),
+ VF(A, R8G8B8_USCALED, USCALED, 8_8_8, 0),
+ VF(A, R8G8_SSCALED, SSCALED, 8_8, 0),
+ VF(A, R8G8_USCALED, USCALED, 8_8, 0),
+ VF(A, R8_SSCALED, SSCALED, 8, 0),
+ VF(A, R8_USCALED, USCALED, 8, 0),
/* FIXED types: not supported natively, converted on VBO push */
- V_C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
- V_F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
- V_F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
- V_F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
+ VF(x, R32G32B32A32_FIXED, xx, xx, xx),
+ VF(x, R32G32B32_FIXED, xx, xx, xx),
+ VF(x, R32G32_FIXED, xx, xx, xx),
+ VF(x, R32_FIXED, xx, xx, xx),
- V_C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
- V_F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
- V_F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
- V_F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
+ VF(x, R64G64B64A64_FLOAT, xx, xx, xx),
+ VF(x, R64G64B64_FLOAT, xx, xx, xx),
+ VF(x, R64G64_FLOAT, xx, xx, xx),
+ VF(x, R64_FLOAT, xx, xx, xx),
};
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 11/23] nv50-: switch nv50_formats.c to updated g80_defs.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (8 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 10/23] nv50-: improved macros to handle format specification Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 12/23] nv50-: remove nv50_defs.xml.h Ben Skeggs
` (11 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index 01cdd54..9f17ab6 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -28,7 +28,7 @@
# include "nv50/nv50_3d.xml.h"
#endif
#include "nv50/nv50_texture.xml.h"
-#include "nv50/nv50_defs.xml.h"
+#include "nv50/g80_defs.xml.h"
#include "pipe/p_defines.h"
@@ -59,8 +59,8 @@
# define U_t 0
#endif
-#define NV50_ZETA_FORMAT_NONE 0
-#define NV50_SURFACE_FORMAT_NONE 0
+#define G80_ZETA_FORMAT_NONE 0
+#define G80_SURFACE_FORMAT_NONE 0
#define SF_A(sz) NV50_TIC_0_FMT_##sz
#define SF_C(sz) NVC0_TIC_0_FMT_##sz
@@ -79,19 +79,19 @@
}
#define C4(c, p, n, r, g, b, a, t, s, u) \
- SF(c, p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
+ SF(c, p, G80_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
#define ZX(c, p, n, r, g, b, a, t, s, u) \
- SF(c, p, NV50_ZETA_FORMAT_##n, \
+ SF(c, p, G80_ZETA_FORMAT_##n, \
r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
#define ZS(c, p, n, r, g, b, a, t, s, u) \
- SF(c, p, NV50_ZETA_FORMAT_##n, \
+ SF(c, p, G80_ZETA_FORMAT_##n, \
r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
#define SZ(c, p, n, r, g, b, a, t, s, u) \
- SF(c, p, NV50_ZETA_FORMAT_##n, \
+ SF(c, p, G80_ZETA_FORMAT_##n, \
r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
#define SX(c, p, r, s, u) \
- SF(c, p, NV50_ZETA_FORMAT_NONE, \
+ SF(c, p, G80_ZETA_FORMAT_NONE, \
r, r, r, r, UINT, UINT, UINT, UINT, s, u)
#define F3(c, p, n, r, g, b, a, t, s, u) \
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 12/23] nv50-: remove nv50_defs.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (9 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 11/23] nv50-: switch nv50_formats.c to updated g80_defs.xml.h Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 13/23] nv50: import updated g80_texture.xml.h from rnndb Ben Skeggs
` (10 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_defs.xml.h | 263 -----------------------
1 file changed, 263 deletions(-)
delete mode 100644 src/gallium/drivers/nouveau/nv50/nv50_defs.xml.h
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_defs.xml.h b/src/gallium/drivers/nouveau/nv50/nv50_defs.xml.h
deleted file mode 100644
index aad2a85..0000000
--- a/src/gallium/drivers/nouveau/nv50/nv50_defs.xml.h
+++ /dev/null
@@ -1,263 +0,0 @@
-#ifndef NV50_DEFS_XML
-#define NV50_DEFS_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/envytools/envytools/
-git clone https://github.com/envytools/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- rnndb/g80_defs.xml ( 18175 bytes, from 2014-09-25 06:32:11)
-- rnndb/copyright.xml ( 6452 bytes, from 2013-05-14 03:57:49)
-- rnndb/nvchipsets.xml ( 2759 bytes, from 2014-10-05 01:51:02)
-
-Copyright (C) 2006-2014 by the following authors:
-- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
-- Ben Skeggs (darktama, darktama_)
-- B. R. <koala_br@users.sourceforge.net> (koala_br)
-- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
-- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
-- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
-- Dmitry Baryshkov
-- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
-- EdB <edb_@users.sf.net> (edb_)
-- Erik Waling <erikwailing@users.sf.net> (erikwaling)
-- Francisco Jerez <currojerez@riseup.net> (curro)
-- imirkin <imirkin@users.sf.net> (imirkin)
-- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
-- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
-- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
-- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
-- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
-- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
-- Mark Carey <mark.carey@gmail.com> (careym)
-- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
-- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
-- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
-- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
-- Peter Popov <ironpeter@users.sf.net> (ironpeter)
-- Richard Hughes <hughsient@users.sf.net> (hughsient)
-- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
-- Serge Martin
-- Simon Raffeiner
-- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
-- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
-- sturmflut <sturmflut@users.sf.net> (sturmflut)
-- Sylvain Munaut <tnt@246tNt.com>
-- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
-- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
-- Younes Manton <younes.m@gmail.com> (ymanton)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define NV50_VSTATUS_IDLE 0x00000000
-#define NV50_VSTATUS_BUSY 0x00000001
-#define NV50_VSTATUS_UNK2 0x00000002
-#define NV50_VSTATUS_WAITING 0x00000003
-#define NV50_VSTATUS_BLOCKED 0x00000005
-#define NV50_VSTATUS_FAULTED 0x00000006
-#define NV50_VSTATUS_PAUSED 0x00000007
-#define NV50_SURFACE_FORMAT_BITMAP 0x0000001c
-#define NV50_SURFACE_FORMAT_UNK1D 0x0000001d
-#define NV50_SURFACE_FORMAT_RGBA32_FLOAT 0x000000c0
-#define NV50_SURFACE_FORMAT_RGBA32_SINT 0x000000c1
-#define NV50_SURFACE_FORMAT_RGBA32_UINT 0x000000c2
-#define NV50_SURFACE_FORMAT_RGBX32_FLOAT 0x000000c3
-#define NV50_SURFACE_FORMAT_RGBX32_SINT 0x000000c4
-#define NV50_SURFACE_FORMAT_RGBX32_UINT 0x000000c5
-#define NV50_SURFACE_FORMAT_RGBA16_UNORM 0x000000c6
-#define NV50_SURFACE_FORMAT_RGBA16_SNORM 0x000000c7
-#define NV50_SURFACE_FORMAT_RGBA16_SINT 0x000000c8
-#define NV50_SURFACE_FORMAT_RGBA16_UINT 0x000000c9
-#define NV50_SURFACE_FORMAT_RGBA16_FLOAT 0x000000ca
-#define NV50_SURFACE_FORMAT_RG32_FLOAT 0x000000cb
-#define NV50_SURFACE_FORMAT_RG32_SINT 0x000000cc
-#define NV50_SURFACE_FORMAT_RG32_UINT 0x000000cd
-#define NV50_SURFACE_FORMAT_RGBX16_FLOAT 0x000000ce
-#define NV50_SURFACE_FORMAT_BGRA8_UNORM 0x000000cf
-#define NV50_SURFACE_FORMAT_BGRA8_SRGB 0x000000d0
-#define NV50_SURFACE_FORMAT_RGB10_A2_UNORM 0x000000d1
-#define NV50_SURFACE_FORMAT_RGB10_A2_UINT 0x000000d2
-#define NV50_SURFACE_FORMAT_RGBA8_UNORM 0x000000d5
-#define NV50_SURFACE_FORMAT_RGBA8_SRGB 0x000000d6
-#define NV50_SURFACE_FORMAT_RGBA8_SNORM 0x000000d7
-#define NV50_SURFACE_FORMAT_RGBA8_SINT 0x000000d8
-#define NV50_SURFACE_FORMAT_RGBA8_UINT 0x000000d9
-#define NV50_SURFACE_FORMAT_RG16_UNORM 0x000000da
-#define NV50_SURFACE_FORMAT_RG16_SNORM 0x000000db
-#define NV50_SURFACE_FORMAT_RG16_SINT 0x000000dc
-#define NV50_SURFACE_FORMAT_RG16_UINT 0x000000dd
-#define NV50_SURFACE_FORMAT_RG16_FLOAT 0x000000de
-#define NV50_SURFACE_FORMAT_BGR10_A2_UNORM 0x000000df
-#define NV50_SURFACE_FORMAT_R11G11B10_FLOAT 0x000000e0
-#define NV50_SURFACE_FORMAT_R32_SINT 0x000000e3
-#define NV50_SURFACE_FORMAT_R32_UINT 0x000000e4
-#define NV50_SURFACE_FORMAT_R32_FLOAT 0x000000e5
-#define NV50_SURFACE_FORMAT_BGRX8_UNORM 0x000000e6
-#define NV50_SURFACE_FORMAT_BGRX8_SRGB 0x000000e7
-#define NV50_SURFACE_FORMAT_B5G6R5_UNORM 0x000000e8
-#define NV50_SURFACE_FORMAT_BGR5_A1_UNORM 0x000000e9
-#define NV50_SURFACE_FORMAT_RG8_UNORM 0x000000ea
-#define NV50_SURFACE_FORMAT_RG8_SNORM 0x000000eb
-#define NV50_SURFACE_FORMAT_RG8_SINT 0x000000ec
-#define NV50_SURFACE_FORMAT_RG8_UINT 0x000000ed
-#define NV50_SURFACE_FORMAT_R16_UNORM 0x000000ee
-#define NV50_SURFACE_FORMAT_R16_SNORM 0x000000ef
-#define NV50_SURFACE_FORMAT_R16_SINT 0x000000f0
-#define NV50_SURFACE_FORMAT_R16_UINT 0x000000f1
-#define NV50_SURFACE_FORMAT_R16_FLOAT 0x000000f2
-#define NV50_SURFACE_FORMAT_R8_UNORM 0x000000f3
-#define NV50_SURFACE_FORMAT_R8_SNORM 0x000000f4
-#define NV50_SURFACE_FORMAT_R8_SINT 0x000000f5
-#define NV50_SURFACE_FORMAT_R8_UINT 0x000000f6
-#define NV50_SURFACE_FORMAT_A8_UNORM 0x000000f7
-#define NV50_SURFACE_FORMAT_BGR5_X1_UNORM 0x000000f8
-#define NV50_SURFACE_FORMAT_RGBX8_UNORM 0x000000f9
-#define NV50_SURFACE_FORMAT_RGBX8_SRGB 0x000000fa
-#define NV50_SURFACE_FORMAT_BGR5_X1_UNORM_UNKFB 0x000000fb
-#define NV50_SURFACE_FORMAT_BGR5_X1_UNORM_UNKFC 0x000000fc
-#define NV50_SURFACE_FORMAT_BGRX8_UNORM_UNKFD 0x000000fd
-#define NV50_SURFACE_FORMAT_BGRX8_UNORM_UNKFE 0x000000fe
-#define NV50_SURFACE_FORMAT_Y32_UINT_UNKFF 0x000000ff
-#define NV50_ZETA_FORMAT_Z32_FLOAT 0x0000000a
-#define NV50_ZETA_FORMAT_Z16_UNORM 0x00000013
-#define NV50_ZETA_FORMAT_S8_Z24_UNORM 0x00000014
-#define NV50_ZETA_FORMAT_Z24_X8_UNORM 0x00000015
-#define NV50_ZETA_FORMAT_Z24_S8_UNORM 0x00000016
-#define NV50_ZETA_FORMAT_Z24_C8_UNORM 0x00000018
-#define NV50_ZETA_FORMAT_Z32_S8_X24_FLOAT 0x00000019
-#define NV50_ZETA_FORMAT_Z24_X8_S8_C8_X16_UNORM 0x0000001d
-#define NV50_ZETA_FORMAT_Z32_X8_C8_X16_FLOAT 0x0000001e
-#define NV50_ZETA_FORMAT_Z32_S8_C8_X16_FLOAT 0x0000001f
-#define NVE4_IMAGE_FORMAT_RGBA32_FLOAT 0x00000002
-#define NVE4_IMAGE_FORMAT_RGBA32_SINT 0x00000003
-#define NVE4_IMAGE_FORMAT_RGBA32_UINT 0x00000004
-#define NVE4_IMAGE_FORMAT_RGBA16_UNORM 0x00000008
-#define NVE4_IMAGE_FORMAT_RGBA16_SNORM 0x00000009
-#define NVE4_IMAGE_FORMAT_RGBA16_SINT 0x0000000a
-#define NVE4_IMAGE_FORMAT_RGBA16_UINT 0x0000000b
-#define NVE4_IMAGE_FORMAT_RGBA16_FLOAT 0x0000000c
-#define NVE4_IMAGE_FORMAT_RG32_FLOAT 0x0000000d
-#define NVE4_IMAGE_FORMAT_RG32_SINT 0x0000000e
-#define NVE4_IMAGE_FORMAT_RG32_UINT 0x0000000f
-#define NVE4_IMAGE_FORMAT_RGB10_A2_UNORM 0x00000013
-#define NVE4_IMAGE_FORMAT_RGB10_A2_UINT 0x00000015
-#define NVE4_IMAGE_FORMAT_RGBA8_UNORM 0x00000018
-#define NVE4_IMAGE_FORMAT_RGBA8_SNORM 0x0000001a
-#define NVE4_IMAGE_FORMAT_RGBA8_SINT 0x0000001b
-#define NVE4_IMAGE_FORMAT_RGBA8_UINT 0x0000001c
-#define NVE4_IMAGE_FORMAT_RG16_UNORM 0x0000001d
-#define NVE4_IMAGE_FORMAT_RG16_SNORM 0x0000001e
-#define NVE4_IMAGE_FORMAT_RG16_SINT 0x0000001f
-#define NVE4_IMAGE_FORMAT_RG16_UINT 0x00000020
-#define NVE4_IMAGE_FORMAT_RG16_FLOAT 0x00000021
-#define NVE4_IMAGE_FORMAT_R11G11B10_FLOAT 0x00000024
-#define NVE4_IMAGE_FORMAT_R32_SINT 0x00000027
-#define NVE4_IMAGE_FORMAT_R32_UINT 0x00000028
-#define NVE4_IMAGE_FORMAT_R32_FLOAT 0x00000029
-#define NVE4_IMAGE_FORMAT_RG8_UNORM 0x0000002e
-#define NVE4_IMAGE_FORMAT_RG8_SNORM 0x0000002f
-#define NVE4_IMAGE_FORMAT_RG8_SINT 0x00000030
-#define NVE4_IMAGE_FORMAT_RG8_UINT 0x00000031
-#define NVE4_IMAGE_FORMAT_R16_UNORM 0x00000032
-#define NVE4_IMAGE_FORMAT_R16_SNORM 0x00000033
-#define NVE4_IMAGE_FORMAT_R16_SINT 0x00000034
-#define NVE4_IMAGE_FORMAT_R16_UINT 0x00000035
-#define NVE4_IMAGE_FORMAT_R16_FLOAT 0x00000036
-#define NVE4_IMAGE_FORMAT_R8_UNORM 0x00000037
-#define NVE4_IMAGE_FORMAT_R8_SNORM 0x00000038
-#define NVE4_IMAGE_FORMAT_R8_SINT 0x00000039
-#define NVE4_IMAGE_FORMAT_R8_UINT 0x0000003a
-#define NV50_PGRAPH_DATA_ERROR_INVALID_OPERATION 0x00000003
-#define NV50_PGRAPH_DATA_ERROR_INVALID_VALUE 0x00000004
-#define NV50_PGRAPH_DATA_ERROR_INVALID_ENUM 0x00000005
-#define NV50_PGRAPH_DATA_ERROR_INVALID_OBJECT 0x00000008
-#define NV50_PGRAPH_DATA_ERROR_READ_ONLY_OBJECT 0x00000009
-#define NV50_PGRAPH_DATA_ERROR_SUPERVISOR_OBJECT 0x0000000a
-#define NV50_PGRAPH_DATA_ERROR_INVALID_ADDRESS_ALIGNMENT 0x0000000b
-#define NV50_PGRAPH_DATA_ERROR_INVALID_BITFIELD 0x0000000c
-#define NV50_PGRAPH_DATA_ERROR_BEGIN_END_ACTIVE 0x0000000d
-#define NV50_PGRAPH_DATA_ERROR_SEMANTIC_COLOR_BACK_OVER_LIMIT 0x0000000e
-#define NV50_PGRAPH_DATA_ERROR_VIEWPORT_ID_NEEDS_GP 0x0000000f
-#define NV50_PGRAPH_DATA_ERROR_RT_DOUBLE_BIND 0x00000010
-#define NV50_PGRAPH_DATA_ERROR_RT_TYPES_MISMATCH 0x00000011
-#define NV50_PGRAPH_DATA_ERROR_RT_LINEAR_WITH_ZETA 0x00000012
-#define NV50_PGRAPH_DATA_ERROR_FP_TOO_FEW_REGS 0x00000015
-#define NV50_PGRAPH_DATA_ERROR_ZETA_FORMAT_CSAA_MISMATCH 0x00000016
-#define NV50_PGRAPH_DATA_ERROR_RT_LINEAR_WITH_MSAA 0x00000017
-#define NV50_PGRAPH_DATA_ERROR_FP_INTERPOLANT_START_OVER_LIMIT 0x00000018
-#define NV50_PGRAPH_DATA_ERROR_SEMANTIC_LAYER_OVER_LIMIT 0x00000019
-#define NV50_PGRAPH_DATA_ERROR_RT_INVALID_ALIGNMENT 0x0000001a
-#define NV50_PGRAPH_DATA_ERROR_SAMPLER_OVER_LIMIT 0x0000001b
-#define NV50_PGRAPH_DATA_ERROR_TEXTURE_OVER_LIMIT 0x0000001c
-#define NV50_PGRAPH_DATA_ERROR_GP_TOO_MANY_OUTPUTS 0x0000001e
-#define NV50_PGRAPH_DATA_ERROR_RT_BPP128_WITH_MS8 0x0000001f
-#define NV50_PGRAPH_DATA_ERROR_Z_OUT_OF_BOUNDS 0x00000021
-#define NV50_PGRAPH_DATA_ERROR_XY_OUT_OF_BOUNDS 0x00000023
-#define NV50_PGRAPH_DATA_ERROR_VP_ZERO_INPUTS 0x00000024
-#define NV50_PGRAPH_DATA_ERROR_CP_MORE_PARAMS_THAN_SHARED 0x00000027
-#define NV50_PGRAPH_DATA_ERROR_CP_NO_REG_SPACE_STRIPED 0x00000028
-#define NV50_PGRAPH_DATA_ERROR_CP_NO_REG_SPACE_PACKED 0x00000029
-#define NV50_PGRAPH_DATA_ERROR_CP_NOT_ENOUGH_WARPS 0x0000002a
-#define NV50_PGRAPH_DATA_ERROR_CP_BLOCK_SIZE_MISMATCH 0x0000002b
-#define NV50_PGRAPH_DATA_ERROR_CP_NOT_ENOUGH_LOCAL_WARPS 0x0000002c
-#define NV50_PGRAPH_DATA_ERROR_CP_NOT_ENOUGH_STACK_WARPS 0x0000002d
-#define NV50_PGRAPH_DATA_ERROR_CP_NO_BLOCKDIM_LATCH 0x0000002e
-#define NV50_PGRAPH_DATA_ERROR_ENG2D_FORMAT_MISMATCH 0x00000031
-#define NV50_PGRAPH_DATA_ERROR_ENG2D_OPERATION_ILLEGAL_FOR_DST_FORMAT 0x00000033
-#define NV50_PGRAPH_DATA_ERROR_ENG2D_FORMAT_MISMATCH_B 0x00000034
-#define NV50_PGRAPH_DATA_ERROR_PRIMITIVE_ID_NEEDS_GP 0x0000003f
-#define NV50_PGRAPH_DATA_ERROR_SEMANTIC_VIEWPORT_OVER_LIMIT 0x00000044
-#define NV50_PGRAPH_DATA_ERROR_SEMANTIC_COLOR_FRONT_OVER_LIMIT 0x00000045
-#define NV50_PGRAPH_DATA_ERROR_LAYER_ID_NEEDS_GP 0x00000046
-#define NV50_PGRAPH_DATA_ERROR_SEMANTIC_CLIP_OVER_LIMIT 0x00000047
-#define NV50_PGRAPH_DATA_ERROR_SEMANTIC_PTSZ_OVER_LIMIT 0x00000048
-#define NV50_PGRAPH_DATA_ERROR_M2MF_LINE_LENGTH_EXCEEDS_PITCH_IN 0x00000051
-#define NV50_PGRAPH_DATA_ERROR_M2MF_LINE_LENGTH_EXCEEDS_PITCH_OUT 0x00000053
-#define NV50_PGRAPH_DATA_ERROR_RT_LINEAR_WITH_ZETA_GF100 0x00000098
-#define NV50_PGRAPH_DATA_ERROR_ENG2D_UNALIGNED_PITCH_GF100 0x000000a5
-#define NV50_CG_IDLE_TIMEOUT__MASK 0x0000003f
-#define NV50_CG_IDLE_TIMEOUT__SHIFT 0
-#define NV50_CG_IDLE_TIMEOUT_ENABLE 0x00000040
-#define NV50_CG_INTERFACE_REENABLE_TIME__MASK 0x000f0000
-#define NV50_CG_INTERFACE_REENABLE_TIME__SHIFT 16
-#define NV50_CG_THROTTLE_DUTY_M1__MASK 0x00f00000
-#define NV50_CG_THROTTLE_DUTY_M1__SHIFT 20
-#define NV50_CG_DELAY__MASK 0x0f000000
-#define NV50_CG_DELAY__SHIFT 24
-#define NV50_CG_CLOCK_THROTTLE_ENABLE 0x10000000
-#define NV50_CG_THROTTLE_MODE__MASK 0x20000000
-#define NV50_CG_THROTTLE_MODE__SHIFT 29
-#define NV50_CG_THROTTLE_MODE_AUTO 0x00000000
-#define NV50_CG_THROTTLE_MODE_MANUAL 0x20000000
-#define NV50_CG_INTERFACE_THROTTLE_ENABLE 0x40000000
-#define NV50_QUERY__SIZE 0x00000010
-#define NV50_QUERY_COUNTER 0x00000000
-
-#define NV50_QUERY_RES 0x00000004
-
-#define NV50_QUERY_TIME 0x00000008
-
-
-#endif /* NV50_DEFS_XML */
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 13/23] nv50: import updated g80_texture.xml.h from rnndb
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (10 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 12/23] nv50-: remove nv50_defs.xml.h Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 14/23] nv50-: switch nv50_formats.c to updated g80_texture.xml.h Ben Skeggs
` (9 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/g80_texture.xml.h | 451 +++++++++++++++++++++
1 file changed, 451 insertions(+)
create mode 100644 src/gallium/drivers/nouveau/nv50/g80_texture.xml.h
diff --git a/src/gallium/drivers/nouveau/nv50/g80_texture.xml.h b/src/gallium/drivers/nouveau/nv50/g80_texture.xml.h
new file mode 100644
index 0000000..542963c
--- /dev/null
+++ b/src/gallium/drivers/nouveau/nv50/g80_texture.xml.h
@@ -0,0 +1,451 @@
+#ifndef G80_TEXTURE_XML
+#define G80_TEXTURE_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/envytools/envytools/
+git clone https://github.com/envytools/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/skeggsb/git/envytools/rnndb/../rnndb/graph/g80_texture.xml ( 18837 bytes, from 2016-01-14 23:54:22)
+- /home/skeggsb/git/envytools/rnndb/copyright.xml ( 6456 bytes, from 2015-09-10 02:57:40)
+- /home/skeggsb/git/envytools/rnndb/nvchipsets.xml ( 2908 bytes, from 2016-02-02 23:45:00)
+- /home/skeggsb/git/envytools/rnndb/g80_defs.xml ( 21739 bytes, from 2016-02-04 00:29:42)
+- /home/skeggsb/git/envytools/rnndb/nv_defs.xml ( 5388 bytes, from 2016-01-14 23:54:22)
+
+Copyright (C) 2006-2016 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define G80_TSC_WRAP_WRAP 0x00000000
+#define G80_TSC_WRAP_MIRROR 0x00000001
+#define G80_TSC_WRAP_CLAMP_TO_EDGE 0x00000002
+#define G80_TSC_WRAP_BORDER 0x00000003
+#define G80_TSC_WRAP_CLAMP_OGL 0x00000004
+#define G80_TSC_WRAP_MIRROR_ONCE_CLAMP_TO_EDGE 0x00000005
+#define G80_TSC_WRAP_MIRROR_ONCE_BORDER 0x00000006
+#define G80_TSC_WRAP_MIRROR_ONCE_CLAMP_OGL 0x00000007
+#define G80_TIC__SIZE 0x00000020
+#define G80_TIC_0 0x00000000
+#define GK20A_TIC_0_USE_COMPONENT_SIZES_EXTENDED__MASK 0x80000000
+#define GK20A_TIC_0_USE_COMPONENT_SIZES_EXTENDED__SHIFT 31
+#define GK20A_TIC_0_USE_COMPONENT_SIZES_EXTENDED_NO 0x00000000
+#define GK20A_TIC_0_USE_COMPONENT_SIZES_EXTENDED_YES 0x80000000
+#define G84_TIC_0_PACK_COMPONENTS 0x40000000
+#define G80_TIC_0_W_SOURCE__MASK 0x38000000
+#define G80_TIC_0_W_SOURCE__SHIFT 27
+#define G80_TIC_0_Z_SOURCE__MASK 0x07000000
+#define G80_TIC_0_Z_SOURCE__SHIFT 24
+#define G80_TIC_0_Y_SOURCE__MASK 0x00e00000
+#define G80_TIC_0_Y_SOURCE__SHIFT 21
+#define G80_TIC_0_X_SOURCE__MASK 0x001c0000
+#define G80_TIC_0_X_SOURCE__SHIFT 18
+#define G80_TIC_0_A_DATA_TYPE__MASK 0x00038000
+#define G80_TIC_0_A_DATA_TYPE__SHIFT 15
+#define G80_TIC_0_B_DATA_TYPE__MASK 0x00007000
+#define G80_TIC_0_B_DATA_TYPE__SHIFT 12
+#define G80_TIC_0_G_DATA_TYPE__MASK 0x00000e00
+#define G80_TIC_0_G_DATA_TYPE__SHIFT 9
+#define G80_TIC_0_R_DATA_TYPE__MASK 0x000001c0
+#define G80_TIC_0_R_DATA_TYPE__SHIFT 6
+#define G80_TIC_0_COMPONENTS_SIZES__MASK 0x0000003f
+#define G80_TIC_0_COMPONENTS_SIZES__SHIFT 0
+#define G80_TIC_0_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001
+#define GF100_TIC_0_COMPONENTS_SIZES_R32_G32_B32 0x00000002
+#define G80_TIC_0_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003
+#define G80_TIC_0_COMPONENTS_SIZES_R32_G32 0x00000004
+#define G80_TIC_0_COMPONENTS_SIZES_R32_B24G8 0x00000005
+#define G80_TIC_0_COMPONENTS_SIZES_X8B8G8R8 0x00000007
+#define G80_TIC_0_COMPONENTS_SIZES_A8B8G8R8 0x00000008
+#define G80_TIC_0_COMPONENTS_SIZES_A2B10G10R10 0x00000009
+#define G80_TIC_0_COMPONENTS_SIZES_R16_G16 0x0000000c
+#define G80_TIC_0_COMPONENTS_SIZES_G8R24 0x0000000d
+#define G80_TIC_0_COMPONENTS_SIZES_G24R8 0x0000000e
+#define G80_TIC_0_COMPONENTS_SIZES_R32 0x0000000f
+#define G80_TIC_0_COMPONENTS_SIZES_A4B4G4R4 0x00000012
+#define G80_TIC_0_COMPONENTS_SIZES_A5B5G5R1 0x00000013
+#define G80_TIC_0_COMPONENTS_SIZES_A1B5G5R5 0x00000014
+#define G80_TIC_0_COMPONENTS_SIZES_B5G6R5 0x00000015
+#define G80_TIC_0_COMPONENTS_SIZES_B6G5R5 0x00000016
+#define G80_TIC_0_COMPONENTS_SIZES_G8R8 0x00000018
+#define G80_TIC_0_COMPONENTS_SIZES_R16 0x0000001b
+#define G80_TIC_0_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c
+#define G80_TIC_0_COMPONENTS_SIZES_R8 0x0000001d
+#define G80_TIC_0_COMPONENTS_SIZES_G4R4 0x0000001e
+#define G80_TIC_0_COMPONENTS_SIZES_R1 0x0000001f
+#define G80_TIC_0_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020
+#define G80_TIC_0_COMPONENTS_SIZES_BF10GF11RF11 0x00000021
+#define G80_TIC_0_COMPONENTS_SIZES_G8B8G8R8 0x00000022
+#define G80_TIC_0_COMPONENTS_SIZES_B8G8R8G8 0x00000023
+#define G80_TIC_0_COMPONENTS_SIZES_DXT1 0x00000024
+#define G80_TIC_0_COMPONENTS_SIZES_DXT23 0x00000025
+#define G80_TIC_0_COMPONENTS_SIZES_DXT45 0x00000026
+#define G80_TIC_0_COMPONENTS_SIZES_DXN1 0x00000027
+#define G80_TIC_0_COMPONENTS_SIZES_DXN2 0x00000028
+#define GF100_TIC_0_COMPONENTS_SIZES_BC6H_SF16 0x00000010
+#define GF100_TIC_0_COMPONENTS_SIZES_BC6H_UF16 0x00000011
+#define GF100_TIC_0_COMPONENTS_SIZES_BC7U 0x00000017
+#define GK20A_TIC_0_COMPONENTS_SIZES_ETC2_RGB 0x00000006
+#define GK20A_TIC_0_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a
+#define GK20A_TIC_0_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b
+#define GK20A_TIC_0_COMPONENTS_SIZES_EAC 0x00000019
+#define GK20A_TIC_0_COMPONENTS_SIZES_EACX2 0x0000001a
+#define G80_TIC_0_COMPONENTS_SIZES_Z24S8 0x00000029
+#define G80_TIC_0_COMPONENTS_SIZES_X8Z24 0x0000002a
+#define G80_TIC_0_COMPONENTS_SIZES_S8Z24 0x0000002b
+#define G80_TIC_0_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c
+#define G80_TIC_0_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d
+#define G80_TIC_0_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32 0x0000002f
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32_X24S8 0x00000030
+#define G80_TIC_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031
+#define G80_TIC_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036
+#define G80_TIC_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038
+#define G80_TIC_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039
+#define G200_TIC_0_COMPONENTS_SIZES_Z16 0x0000003a
+#define G200_TIC_0_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b
+#define G200_TIC_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c
+#define G200_TIC_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d
+#define G200_TIC_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e
+#define G80_TIC_0_COMPONENTS_SIZES__MASK 0x0000003f
+#define G80_TIC_0_COMPONENTS_SIZES__SHIFT 0
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000000
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000010
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000001
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000011
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000002
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000015
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000012
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000004
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000016
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000017
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000013
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000005
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000014
+#define GK20A_TIC_0_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000006
+
+#define G80_TIC_1 0x00000004
+#define G80_TIC_1_OFFSET_LOWER__MASK 0xffffffff
+#define G80_TIC_1_OFFSET_LOWER__SHIFT 0
+
+#define G80_TIC_2 0x00000008
+#define G80_TIC_2_OFFSET_UPPER__MASK 0x000000ff
+#define G80_TIC_2_OFFSET_UPPER__SHIFT 0
+#define G84_TIC_2_ANISO_SPREAD_MAX_LOG2_LSB__MASK 0x00000300
+#define G84_TIC_2_ANISO_SPREAD_MAX_LOG2_LSB__SHIFT 8
+#define G80_TIC_2_SRGB_CONVERSION 0x00000400
+#define G84_TIC_2_ANISO_SPREAD_MAX_LOG2_MSB 0x00000800
+#define G80_TIC_2_LOD_ANISO_QUALITY_2 0x00001000
+#define G80_TIC_2_COLOR_KEY_OP 0x00002000
+#define G80_TIC_2_TEXTURE_TYPE__MASK 0x0003c000
+#define G80_TIC_2_TEXTURE_TYPE__SHIFT 14
+#define G80_TIC_2_TEXTURE_TYPE_ONE_D 0x00000000
+#define G80_TIC_2_TEXTURE_TYPE_TWO_D 0x00004000
+#define G80_TIC_2_TEXTURE_TYPE_THREE_D 0x00008000
+#define G80_TIC_2_TEXTURE_TYPE_CUBEMAP 0x0000c000
+#define G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY 0x00010000
+#define G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY 0x00014000
+#define G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER 0x00018000
+#define G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x0001c000
+#define G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY 0x00020000
+#define G80_TIC_2_LAYOUT__MASK 0x00040000
+#define G80_TIC_2_LAYOUT__SHIFT 18
+#define G80_TIC_2_LAYOUT_BLOCKLINEAR 0x00000000
+#define G80_TIC_2_LAYOUT_PITCH 0x00040000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH__MASK 0x00380000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH__SHIFT 19
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH__MIN 0x00000000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH__MAX 0x00000000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH_ONE 0x00000000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH_TWO 0x00080000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH_FOUR 0x00100000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH_EIGHT 0x00180000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH_SIXTEEN 0x00200000
+#define G80_TIC_2_GOBS_PER_BLOCK_WIDTH_THIRTYTWO 0x00280000
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT__MASK 0x01c00000
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT__SHIFT 22
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT_ONE 0x00000000
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT_TWO 0x00400000
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT_FOUR 0x00800000
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT_EIGHT 0x00c00000
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT_SIXTEEN 0x01000000
+#define G80_TIC_2_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO 0x01400000
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH__MASK 0x0e000000
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH__SHIFT 25
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH_ONE 0x00000000
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH_TWO 0x02000000
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH_FOUR 0x04000000
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH_EIGHT 0x06000000
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH_SIXTEEN 0x08000000
+#define G80_TIC_2_GOBS_PER_BLOCK_DEPTH_THIRTYTWO 0x0a000000
+#define G80_TIC_2_SECTOR_PROMOTION__MASK 0x30000000
+#define G80_TIC_2_SECTOR_PROMOTION__SHIFT 28
+#define G80_TIC_2_SECTOR_PROMOTION_NO_PROMOTION 0x00000000
+#define G80_TIC_2_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x10000000
+#define G80_TIC_2_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x20000000
+#define G80_TIC_2_SECTOR_PROMOTION_PROMOTE_TO_4 0x30000000
+#define G80_TIC_2_BORDER_SOURCE__MASK 0x40000000
+#define G80_TIC_2_BORDER_SOURCE__SHIFT 30
+#define G80_TIC_2_BORDER_SOURCE_TEXTURE 0x00000000
+#define G80_TIC_2_BORDER_SOURCE_COLOR 0x40000000
+#define G80_TIC_2_NORMALIZED_COORDS 0x80000000
+
+#define G80_TIC_3 0x0000000c
+#define G80_TIC_3_PITCH__MASK 0x000fffff
+#define G80_TIC_3_PITCH__SHIFT 0
+#define G80_TIC_3_LOD_ANISO_QUALITY__MASK 0x00100000
+#define G80_TIC_3_LOD_ANISO_QUALITY__SHIFT 20
+#define G80_TIC_3_LOD_ANISO_QUALITY_LOW 0x00000000
+#define G80_TIC_3_LOD_ANISO_QUALITY_HIGH 0x00100000
+#define G80_TIC_3_LOD_ISO_QUALITY__MASK 0x00200000
+#define G80_TIC_3_LOD_ISO_QUALITY__SHIFT 21
+#define G80_TIC_3_LOD_ISO_QUALITY_LOW 0x00000000
+#define G80_TIC_3_LOD_ISO_QUALITY_HIGH 0x00200000
+#define G80_TIC_3_ANISO_COARSE_SPREAD_MODIFIER__MASK 0x00c00000
+#define G80_TIC_3_ANISO_COARSE_SPREAD_MODIFIER__SHIFT 22
+#define G80_TIC_3_ANISO_COARSE_SPREAD_MODIFIER_NONE 0x00000000
+#define G80_TIC_3_ANISO_COARSE_SPREAD_MODIFIER_CONST_ONE 0x00400000
+#define G80_TIC_3_ANISO_COARSE_SPREAD_MODIFIER_CONST_TWO 0x00800000
+#define G80_TIC_3_ANISO_COARSE_SPREAD_MODIFIER_SQRT 0x00c00000
+#define G80_TIC_3_ANISO_SPREAD_SCALE__MASK 0x1f000000
+#define G80_TIC_3_ANISO_SPREAD_SCALE__SHIFT 24
+#define G80_TIC_3_USE_HEADER_OPT_CONTROL 0x20000000
+#define G84_TIC_3_ANISO_CLAMP_AT_MAX_LOD 0x40000000
+#define G84_TIC_3_ANISO_POW2 0x80000000
+
+#define G80_TIC_4 0x00000010
+#define G80_TIC_4_WIDTH__MASK 0x3fffffff
+#define G80_TIC_4_WIDTH__SHIFT 0
+#define G80_TIC_4_DEPTH_TEXTURE 0x40000000
+#define G84_TIC_4_USE_TEXTURE_HEADER_V2 0x80000000
+
+#define G80_TIC_5 0x00000014
+#define G80_TIC_5_MAP_MIP_LEVEL__MASK 0xf0000000
+#define G80_TIC_5_MAP_MIP_LEVEL__SHIFT 28
+#define G80_TIC_5_DEPTH__MASK 0x0fff0000
+#define G80_TIC_5_DEPTH__SHIFT 16
+#define G80_TIC_5_HEIGHT__MASK 0x0000ffff
+#define G80_TIC_5_HEIGHT__SHIFT 0
+
+#define G80_TIC_6 0x00000018
+#define G80_TIC_6_TRILIN_OPT__MASK 0x0000001f
+#define G80_TIC_6_TRILIN_OPT__SHIFT 0
+#define G80_TIC_6_MIP_LOD_BIAS__MASK 0x0003ffe0
+#define G80_TIC_6_MIP_LOD_BIAS__SHIFT 5
+#define G80_TIC_6_MIP_LOD_BIAS__RADIX 0x00000008
+#define G80_TIC_6_ANISO_BIAS__MASK 0x00780000
+#define G80_TIC_6_ANISO_BIAS__SHIFT 19
+#define G80_TIC_6_ANISO_BIAS__RADIX 0x00000004
+#define G80_TIC_6_ANISO_FINE_SPREAD_FUNC__MASK 0x01800000
+#define G80_TIC_6_ANISO_FINE_SPREAD_FUNC__SHIFT 23
+#define G80_TIC_6_ANISO_FINE_SPREAD_FUNC_HALF 0x00000000
+#define G80_TIC_6_ANISO_FINE_SPREAD_FUNC_ONE 0x00800000
+#define G80_TIC_6_ANISO_FINE_SPREAD_FUNC_TWO 0x01000000
+#define G80_TIC_6_ANISO_FINE_SPREAD_FUNC_MAX 0x01800000
+#define G80_TIC_6_ANISO_COARSE_SPREAD_FUNC__MASK 0x06000000
+#define G80_TIC_6_ANISO_COARSE_SPREAD_FUNC__SHIFT 25
+#define G80_TIC_6_ANISO_COARSE_SPREAD_FUNC_HALF 0x00000000
+#define G80_TIC_6_ANISO_COARSE_SPREAD_FUNC_ONE 0x02000000
+#define G80_TIC_6_ANISO_COARSE_SPREAD_FUNC_TWO 0x04000000
+#define G80_TIC_6_ANISO_COARSE_SPREAD_FUNC_MAX 0x06000000
+#define G80_TIC_6_MAX_ANISOTROPY__MASK 0x38000000
+#define G80_TIC_6_MAX_ANISOTROPY__SHIFT 27
+#define G80_TIC_6_MAX_ANISOTROPY_1_TO_1 0x00000000
+#define G80_TIC_6_MAX_ANISOTROPY_2_TO_1 0x08000000
+#define G80_TIC_6_MAX_ANISOTROPY_4_TO_1 0x10000000
+#define G80_TIC_6_MAX_ANISOTROPY_6_TO_1 0x18000000
+#define G80_TIC_6_MAX_ANISOTROPY_8_TO_1 0x20000000
+#define G80_TIC_6_MAX_ANISOTROPY_10_TO_1 0x28000000
+#define G80_TIC_6_MAX_ANISOTROPY_12_TO_1 0x30000000
+#define G80_TIC_6_MAX_ANISOTROPY_16_TO_1 0x38000000
+#define G80_TIC_6_ANISO_FINE_SPREAD_MODIFIER__MASK 0xc0000000
+#define G80_TIC_6_ANISO_FINE_SPREAD_MODIFIER__SHIFT 30
+#define G80_TIC_6_ANISO_FINE_SPREAD_MODIFIER_NONE 0x00000000
+#define G80_TIC_6_ANISO_FINE_SPREAD_MODIFIER_CONST_ONE 0x40000000
+#define G80_TIC_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO 0x80000000
+#define G80_TIC_6_ANISO_FINE_SPREAD_MODIFIER_SQRT 0xc0000000
+
+#define G80_TIC_7 0x0000001c
+#define G80_TIC_7_COLOR_KEY_VALUE__MASK 0xffffffff
+#define G80_TIC_7_COLOR_KEY_VALUE__SHIFT 0
+
+#define G84_TIC_7 0x0000001c
+#define G84_TIC_7_RES_VIEW_MIN_MIP_LEVEL__MASK 0x0000000f
+#define G84_TIC_7_RES_VIEW_MIN_MIP_LEVEL__SHIFT 0
+#define G84_TIC_7_RES_VIEW_MAX_MIP_LEVEL__MASK 0x000000f0
+#define G84_TIC_7_RES_VIEW_MAX_MIP_LEVEL__SHIFT 4
+#define G84_TIC_7_HEIGHT_MSB 0x00000100
+#define G84_TIC_7_MULTI_SAMPLE_COUNT__MASK 0x0000f000
+#define G84_TIC_7_MULTI_SAMPLE_COUNT__SHIFT 12
+#define G84_TIC_7_MULTI_SAMPLE_COUNT_1X1 0x00000000
+#define G84_TIC_7_MULTI_SAMPLE_COUNT_2X1 0x00001000
+#define G84_TIC_7_MULTI_SAMPLE_COUNT_2X2 0x00002000
+#define G84_TIC_7_MULTI_SAMPLE_COUNT_4X2 0x00003000
+#define GT215_TIC_7_MULTI_SAMPLE_COUNT_4X2_D3D 0x00004000
+#define GT215_TIC_7_MULTI_SAMPLE_COUNT_2X1_D3D 0x00005000
+#define GF100_TIC_7_MULTI_SAMPLE_COUNT_4X4 0x00006000
+#define G84_TIC_7_MULTI_SAMPLE_COUNT_2X2_VC_4 0x00008000
+#define G84_TIC_7_MULTI_SAMPLE_COUNT_2X2_VC_12 0x00009000
+#define G84_TIC_7_MULTI_SAMPLE_COUNT_4X2_VC_8 0x0000a000
+#define GF100_TIC_7_MULTI_SAMPLE_COUNT_4X2_VC_24 0x0000b000
+#define G84_TIC_7_MIN_LOD_CLAMP__MASK 0x0fff0000
+#define G84_TIC_7_MIN_LOD_CLAMP__SHIFT 16
+#define G84_TIC_7_MIN_LOD_CLAMP__RADIX 0x00000008
+#define G84_TIC_7_DEPTH_MSB__MASK 0x70000000
+#define G84_TIC_7_DEPTH_MSB__SHIFT 28
+
+#define G80_TSC__SIZE 0x00000020
+#define G80_TSC_0 0x00000000
+#define G80_TSC_0_ADDRESS_U__MASK 0x00000007
+#define G80_TSC_0_ADDRESS_U__SHIFT 0
+#define G80_TSC_0_ADDRESS_V__MASK 0x00000038
+#define G80_TSC_0_ADDRESS_V__SHIFT 3
+#define G80_TSC_0_ADDRESS_P__MASK 0x000001c0
+#define G80_TSC_0_ADDRESS_P__SHIFT 6
+#define G80_TSC_0_DEPTH_COMPARE 0x00000200
+#define G80_TSC_0_DEPTH_COMPARE_FUNC__MASK 0x00001c00
+#define G80_TSC_0_DEPTH_COMPARE_FUNC__SHIFT 10
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_NEVER 0x00000000
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_LESS 0x00000400
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_EQUAL 0x00000800
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_LEQUAL 0x00000c00
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_GREATER 0x00001000
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_NOTEQUAL 0x00001400
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_GEQUAL 0x00001800
+#define G80_TSC_0_DEPTH_COMPARE_FUNC_ALWAYS 0x00001c00
+#define G80_TSC_0_SRGB_CONVERSION 0x00002000
+#define G80_TSC_0_FONT_FILTER_WIDTH__MASK 0x0001c000
+#define G80_TSC_0_FONT_FILTER_WIDTH__SHIFT 14
+#define G80_TSC_0_FONT_FILTER_HEIGHT__MASK 0x000e0000
+#define G80_TSC_0_FONT_FILTER_HEIGHT__SHIFT 17
+#define G80_TSC_0_MAX_ANISOTROPY__MASK 0x00700000
+#define G80_TSC_0_MAX_ANISOTROPY__SHIFT 20
+#define G80_TSC_0_MAX_ANISOTROPY_1_TO_1 0x00000000
+#define G80_TSC_0_MAX_ANISOTROPY_2_TO_1 0x00100000
+#define G80_TSC_0_MAX_ANISOTROPY_4_TO_1 0x00200000
+#define G80_TSC_0_MAX_ANISOTROPY_6_TO_1 0x00300000
+#define G80_TSC_0_MAX_ANISOTROPY_8_TO_1 0x00400000
+#define G80_TSC_0_MAX_ANISOTROPY_10_TO_1 0x00500000
+#define G80_TSC_0_MAX_ANISOTROPY_12_TO_1 0x00600000
+#define G80_TSC_0_MAX_ANISOTROPY_16_TO_1 0x00700000
+
+#define G80_TSC_1 0x00000004
+#define G80_TSC_1_MAG_FILTER__MASK 0x00000003
+#define G80_TSC_1_MAG_FILTER__SHIFT 0
+#define G80_TSC_1_MAG_FILTER_NEAREST 0x00000001
+#define G80_TSC_1_MAG_FILTER_LINEAR 0x00000002
+#define G80_TSC_1_MIN_FILTER__MASK 0x00000030
+#define G80_TSC_1_MIN_FILTER__SHIFT 4
+#define G80_TSC_1_MIN_FILTER_NEAREST 0x00000010
+#define G80_TSC_1_MIN_FILTER_LINEAR 0x00000020
+#define G80_TSC_1_MIP_FILTER__MASK 0x000000c0
+#define G80_TSC_1_MIP_FILTER__SHIFT 6
+#define G80_TSC_1_MIP_FILTER_NONE 0x00000040
+#define G80_TSC_1_MIP_FILTER_NEAREST 0x00000080
+#define G80_TSC_1_MIP_FILTER_LINEAR 0x000000c0
+#define GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING 0x00000200
+#define G80_TSC_1_MIP_LOD_BIAS__MASK 0x01fff000
+#define G80_TSC_1_MIP_LOD_BIAS__SHIFT 12
+#define G80_TSC_1_MIP_LOD_BIAS__RADIX 0x00000008
+#define GK104_TSC_1_FLOAT_COORD_NORMALIZATION__MASK 0x02000000
+#define GK104_TSC_1_FLOAT_COORD_NORMALIZATION__SHIFT 25
+#define GK104_TSC_1_FLOAT_COORD_NORMALIZATION_USE_HEADER_SETTING 0x00000000
+#define GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS 0x02000000
+#define G80_TSC_1_TRILIN_OPT__MASK 0x7c000000
+#define G80_TSC_1_TRILIN_OPT__SHIFT 26
+
+#define G80_TSC_2 0x00000008
+#define G80_TSC_2_MIN_LOD_CLAMP__MASK 0x00000fff
+#define G80_TSC_2_MIN_LOD_CLAMP__SHIFT 0
+#define G80_TSC_2_MIN_LOD_CLAMP__RADIX 0x00000008
+#define G80_TSC_2_MAX_LOD_CLAMP__MASK 0x00fff000
+#define G80_TSC_2_MAX_LOD_CLAMP__SHIFT 12
+#define G80_TSC_2_MAX_LOD_CLAMP__RADIX 0x00000008
+#define G80_TSC_2_SRGB_BORDER_COLOR_R__MASK 0xff000000
+#define G80_TSC_2_SRGB_BORDER_COLOR_R__SHIFT 24
+
+#define G80_TSC_3 0x0000000c
+#define G80_TSC_3_SRGB_BORDER_COLOR_G__MASK 0x000ff000
+#define G80_TSC_3_SRGB_BORDER_COLOR_G__SHIFT 12
+#define G80_TSC_3_SRGB_BORDER_COLOR_B__MASK 0x0ff00000
+#define G80_TSC_3_SRGB_BORDER_COLOR_B__SHIFT 20
+
+#define G80_TSC_4 0x00000010
+#define G80_TSC_4_BORDER_COLOR_R__MASK 0xffffffff
+#define G80_TSC_4_BORDER_COLOR_R__SHIFT 0
+
+#define G80_TSC_5 0x00000014
+#define G80_TSC_5_BORDER_COLOR_G__MASK 0xffffffff
+#define G80_TSC_5_BORDER_COLOR_G__SHIFT 0
+
+#define G80_TSC_6 0x00000018
+#define G80_TSC_6_BORDER_COLOR_B__MASK 0xffffffff
+#define G80_TSC_6_BORDER_COLOR_B__SHIFT 0
+
+#define G80_TSC_7 0x0000001c
+#define G80_TSC_7_BORDER_COLOR_A__MASK 0xffffffff
+#define G80_TSC_7_BORDER_COLOR_A__SHIFT 0
+
+
+#endif /* G80_TEXTURE_XML */
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 14/23] nv50-: switch nv50_formats.c to updated g80_texture.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (11 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 13/23] nv50: import updated g80_texture.xml.h from rnndb Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 15/23] nv50: switch nv50_state.c " Ben Skeggs
` (8 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 413 ++++++++++++------------
1 file changed, 207 insertions(+), 206 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index 9f17ab6..c91d29b 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -27,7 +27,7 @@
# include "nv50/nv50_screen.h"
# include "nv50/nv50_3d.xml.h"
#endif
-#include "nv50/nv50_texture.xml.h"
+#include "nv50/g80_texture.xml.h"
#include "nv50/g80_defs.xml.h"
#include "pipe/p_defines.h"
@@ -62,19 +62,20 @@
#define G80_ZETA_FORMAT_NONE 0
#define G80_SURFACE_FORMAT_NONE 0
-#define SF_A(sz) NV50_TIC_0_FMT_##sz
-#define SF_C(sz) NVC0_TIC_0_FMT_##sz
+#define SF_A(sz) G80_TIC_0_COMPONENTS_SIZES_##sz
+#define SF_B(sz) G200_TIC_0_COMPONENTS_SIZES_##sz
+#define SF_C(sz) GF100_TIC_0_COMPONENTS_SIZES_##sz
#define SF(c, pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
[PIPE_FORMAT_##pf] = { \
sf, \
- (NV50_TIC_MAP_##r << NV50_TIC_0_MAPR__SHIFT) | \
- (NV50_TIC_MAP_##g << NV50_TIC_0_MAPG__SHIFT) | \
- (NV50_TIC_MAP_##b << NV50_TIC_0_MAPB__SHIFT) | \
- (NV50_TIC_MAP_##a << NV50_TIC_0_MAPA__SHIFT) | \
- (NV50_TIC_TYPE_##t0 << NV50_TIC_0_TYPE0__SHIFT) | \
- (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
- (NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
- (NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
+ (G80_TIC_SOURCE_##r << G80_TIC_0_X_SOURCE__SHIFT) | \
+ (G80_TIC_SOURCE_##g << G80_TIC_0_Y_SOURCE__SHIFT) | \
+ (G80_TIC_SOURCE_##b << G80_TIC_0_Z_SOURCE__SHIFT) | \
+ (G80_TIC_SOURCE_##a << G80_TIC_0_W_SOURCE__SHIFT) | \
+ (G80_TIC_TYPE_##t0 << G80_TIC_0_R_DATA_TYPE__SHIFT) | \
+ (G80_TIC_TYPE_##t1 << G80_TIC_0_G_DATA_TYPE__SHIFT) | \
+ (G80_TIC_TYPE_##t2 << G80_TIC_0_B_DATA_TYPE__SHIFT) | \
+ (G80_TIC_TYPE_##t3 << G80_TIC_0_A_DATA_TYPE__SHIFT) | \
SF_##c(sz), U_##u \
}
@@ -118,201 +119,201 @@ const struct nvc0_format nvc0_format_table[PIPE_FORMAT_COUNT] =
const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
#endif
{
- C4(A, B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM, 8_8_8_8, TD),
- F3(A, B8G8R8X8_UNORM, BGRX8_UNORM, C2, C1, C0, xx, UNORM, 8_8_8_8, TD),
- C4(A, B8G8R8A8_SRGB, BGRA8_SRGB, C2, C1, C0, C3, UNORM, 8_8_8_8, TD),
- F3(A, B8G8R8X8_SRGB, BGRX8_SRGB, C2, C1, C0, xx, UNORM, 8_8_8_8, TD),
- C4(A, R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8, IB),
- F3(A, R8G8B8X8_UNORM, RGBX8_UNORM, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
- C4(A, R8G8B8A8_SRGB, RGBA8_SRGB, C0, C1, C2, C3, UNORM, 8_8_8_8, TB),
- F3(A, R8G8B8X8_SRGB, RGBX8_SRGB, C0, C1, C2, xx, UNORM, 8_8_8_8, TB),
-
- ZX(A, Z16_UNORM, Z16_UNORM, C0, C0, C0, xx, UNORM, Z16, TZ),
- ZX(A, Z32_FLOAT, Z32_FLOAT, C0, C0, C0, xx, FLOAT, Z32, TZ),
- ZX(A, Z24X8_UNORM, Z24_X8_UNORM, C0, C0, C0, xx, UNORM, Z24_X8, TZ),
- SZ(A, X8Z24_UNORM, S8_Z24_UNORM, C1, C1, C1, xx, UNORM, S8_Z24, TZ),
- ZS(A, Z24_UNORM_S8_UINT, Z24_S8_UNORM, C0, C0, C0, xx, UNORM, Z24_S8, TZ),
- SZ(A, S8_UINT_Z24_UNORM, S8_Z24_UNORM, C1, C1, C1, xx, UNORM, S8_Z24, TZ),
- ZS(A, Z32_FLOAT_S8X24_UINT, Z32_S8_X24_FLOAT, C0, C0, C0, xx, FLOAT, Z32_S8_X24, TZ),
-
- SX(A, S8_UINT, C0, 8, T),
- SX(A, X24S8_UINT, C1, Z24_S8, T),
- SX(A, S8X24_UINT, C0, S8_Z24, T),
- SX(A, X32_S8X24_UINT, C1, Z32_S8_X24, T),
-
- F3(A, B5G6R5_UNORM, B5G6R5_UNORM, C2, C1, C0, xx, UNORM, 5_6_5, TD),
- C4(A, B5G5R5A1_UNORM, BGR5_A1_UNORM, C2, C1, C0, C3, UNORM, 5_5_5_1, TD),
- F3(A, B5G5R5X1_UNORM, BGR5_X1_UNORM, C2, C1, C0, xx, UNORM, 5_5_5_1, TD),
- C4(A, B4G4R4A4_UNORM, NONE, C2, C1, C0, C3, UNORM, 4_4_4_4, T),
- F3(A, B4G4R4X4_UNORM, NONE, C2, C1, C0, xx, UNORM, 4_4_4_4, T),
- F3(A, R9G9B9E5_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 9_9_9_E5, T),
-
- C4(A, R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM, 10_10_10_2, IB),
- C4(A, B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM, 10_10_10_2, TD),
- C4(A, R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM, 10_10_10_2, T),
- C4(A, B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM, 10_10_10_2, T),
- C4(A, R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT, 10_10_10_2, TR),
- C4(A, B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT, 10_10_10_2, T),
-
- F3(A, R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT, 11_11_10, IB),
-
- F3(A, L8_UNORM, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
- F3(A, L8_SRGB, R8_UNORM, C0, C0, C0, xx, UNORM, 8, TB),
- F3(A, L8_SNORM, R8_SNORM, C0, C0, C0, xx, SNORM, 8, TC),
- I3(A, L8_SINT, R8_SINT, C0, C0, C0, xx, SINT, 8, TR),
- I3(A, L8_UINT, R8_UINT, C0, C0, C0, xx, UINT, 8, TR),
- F3(A, L16_UNORM, R16_UNORM, C0, C0, C0, xx, UNORM, 16, TC),
- F3(A, L16_SNORM, R16_SNORM, C0, C0, C0, xx, SNORM, 16, TC),
- F3(A, L16_FLOAT, R16_FLOAT, C0, C0, C0, xx, FLOAT, 16, TB),
- I3(A, L16_SINT, R16_SINT, C0, C0, C0, xx, SINT, 16, TR),
- I3(A, L16_UINT, R16_UINT, C0, C0, C0, xx, UINT, 16, TR),
- F3(A, L32_FLOAT, R32_FLOAT, C0, C0, C0, xx, FLOAT, 32, TB),
- I3(A, L32_SINT, R32_SINT, C0, C0, C0, xx, SINT, 32, TR),
- I3(A, L32_UINT, R32_UINT, C0, C0, C0, xx, UINT, 32, TR),
-
- C4(A, I8_UNORM, R8_UNORM, C0, C0, C0, C0, UNORM, 8, TR),
- C4(A, I8_SNORM, R8_SNORM, C0, C0, C0, C0, SNORM, 8, TR),
- C4(A, I8_SINT, R8_SINT, C0, C0, C0, C0, SINT, 8, TR),
- C4(A, I8_UINT, R8_UINT, C0, C0, C0, C0, UINT, 8, TR),
- C4(A, I16_UNORM, R16_UNORM, C0, C0, C0, C0, UNORM, 16, TR),
- C4(A, I16_SNORM, R16_SNORM, C0, C0, C0, C0, SNORM, 16, TR),
- C4(A, I16_FLOAT, R16_FLOAT, C0, C0, C0, C0, FLOAT, 16, TR),
- C4(A, I16_SINT, R16_SINT, C0, C0, C0, C0, SINT, 16, TR),
- C4(A, I16_UINT, R16_UINT, C0, C0, C0, C0, UINT, 16, TR),
- C4(A, I32_FLOAT, R32_FLOAT, C0, C0, C0, C0, FLOAT, 32, TR),
- C4(A, I32_SINT, R32_SINT, C0, C0, C0, C0, SINT, 32, TR),
- C4(A, I32_UINT, R32_UINT, C0, C0, C0, C0, UINT, 32, TR),
-
- A1(A, A8_UNORM, A8_UNORM, xx, xx, xx, C0, UNORM, 8, TB),
- A1(A, A8_SNORM, R8_SNORM, xx, xx, xx, C0, SNORM, 8, T),
- A1(A, A8_SINT, R8_SINT, xx, xx, xx, C0, SINT, 8, T),
- A1(A, A8_UINT, R8_UINT, xx, xx, xx, C0, UINT, 8, T),
- A1(A, A16_UNORM, R16_UNORM, xx, xx, xx, C0, UNORM, 16, T),
- A1(A, A16_SNORM, R16_SNORM, xx, xx, xx, C0, SNORM, 16, T),
- A1(A, A16_FLOAT, R16_FLOAT, xx, xx, xx, C0, FLOAT, 16, T),
- A1(A, A16_SINT, R16_SINT, xx, xx, xx, C0, SINT, 16, T),
- A1(A, A16_UINT, R16_UINT, xx, xx, xx, C0, UINT, 16, T),
- A1(A, A32_FLOAT, R32_FLOAT, xx, xx, xx, C0, FLOAT, 32, T),
- A1(A, A32_SINT, R32_SINT, xx, xx, xx, C0, SINT, 32, T),
- A1(A, A32_UINT, R32_UINT, xx, xx, xx, C0, UINT, 32, T),
-
- C4(A, L4A4_UNORM, NONE, C0, C0, C0, C1, UNORM, 4_4, T),
- C4(A, L8A8_UNORM, RG8_UNORM, C0, C0, C0, C1, UNORM, 8_8, T),
- C4(A, L8A8_SNORM, RG8_SNORM, C0, C0, C0, C1, SNORM, 8_8, T),
- C4(A, L8A8_SRGB, RG8_UNORM, C0, C0, C0, C1, UNORM, 8_8, T),
- C4(A, L8A8_SINT, RG8_SINT, C0, C0, C0, C1, SINT, 8_8, T),
- C4(A, L8A8_UINT, RG8_UINT, C0, C0, C0, C1, UINT, 8_8, T),
- C4(A, L16A16_UNORM, RG16_UNORM, C0, C0, C0, C1, UNORM, 16_16, T),
- C4(A, L16A16_SNORM, RG16_SNORM, C0, C0, C0, C1, SNORM, 16_16, T),
- C4(A, L16A16_FLOAT, RG16_FLOAT, C0, C0, C0, C1, FLOAT, 16_16, T),
- C4(A, L16A16_SINT, RG16_SINT, C0, C0, C0, C1, SINT, 16_16, T),
- C4(A, L16A16_UINT, RG16_UINT, C0, C0, C0, C1, UINT, 16_16, T),
- C4(A, L32A32_FLOAT, RG32_FLOAT, C0, C0, C0, C1, FLOAT, 32_32, T),
- C4(A, L32A32_SINT, RG32_SINT, C0, C0, C0, C1, SINT, 32_32, T),
- C4(A, L32A32_UINT, RG32_UINT, C0, C0, C0, C1, UINT, 32_32, T),
-
- F3(A, DXT1_RGB, NONE, C0, C1, C2, xx, UNORM, DXT1, T),
- F3(A, DXT1_SRGB, NONE, C0, C1, C2, xx, UNORM, DXT1, T),
- C4(A, DXT1_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT1, T),
- C4(A, DXT1_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT1, T),
- C4(A, DXT3_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT3, T),
- C4(A, DXT3_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT3, T),
- C4(A, DXT5_RGBA, NONE, C0, C1, C2, C3, UNORM, DXT5, T),
- C4(A, DXT5_SRGBA, NONE, C0, C1, C2, C3, UNORM, DXT5, T),
-
- F1(A, RGTC1_UNORM, NONE, C0, xx, xx, xx, UNORM, RGTC1, T),
- F1(A, RGTC1_SNORM, NONE, C0, xx, xx, xx, SNORM, RGTC1, T),
- F2(A, RGTC2_UNORM, NONE, C0, C1, xx, xx, UNORM, RGTC2, T),
- F2(A, RGTC2_SNORM, NONE, C0, C1, xx, xx, SNORM, RGTC2, T),
- F3(A, LATC1_UNORM, NONE, C0, C0, C0, xx, UNORM, RGTC1, T),
- F3(A, LATC1_SNORM, NONE, C0, C0, C0, xx, SNORM, RGTC1, T),
- C4(A, LATC2_UNORM, NONE, C0, C0, C0, C1, UNORM, RGTC2, T),
- C4(A, LATC2_SNORM, NONE, C0, C0, C0, C1, SNORM, RGTC2, T),
-
- C4(C, BPTC_RGBA_UNORM, NONE, C0, C1, C2, C3, UNORM, BPTC, t),
- C4(C, BPTC_SRGBA, NONE, C0, C1, C2, C3, UNORM, BPTC, t),
- F3(C, BPTC_RGB_FLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_FLOAT, t),
- F3(C, BPTC_RGB_UFLOAT, NONE, C0, C1, C2, xx, FLOAT, BPTC_UFLOAT, t),
-
- C4(A, R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT, 32_32_32_32, IB),
- C4(A, R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32, T),
- C4(A, R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32, T),
- C4(A, R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT, 32_32_32_32, IR),
- C4(A, R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT, 32_32_32_32, IR),
- F3(A, R32G32B32X32_FLOAT, RGBX32_FLOAT, C0, C1, C2, xx, FLOAT, 32_32_32_32, TB),
- I3(A, R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT, 32_32_32_32, TR),
- I3(A, R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT, 32_32_32_32, TR),
-
- F3(C, R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, t),
- I3(C, R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, t),
- I3(C, R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, t),
-
- F2(A, R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IB),
- F2(A, R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, T),
- F2(A, R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, T),
- I2(A, R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IR),
- I2(A, R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IR),
-
- F1(A, R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IB),
- F1(A, R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, T),
- F1(A, R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, T),
- I1(A, R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IR),
- I1(A, R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IR),
-
- C4(A, R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT, 16_16_16_16, IB),
- C4(A, R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM, 16_16_16_16, IC),
- C4(A, R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM, 16_16_16_16, IC),
- C4(A, R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT, 16_16_16_16, IR),
- C4(A, R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT, 16_16_16_16, IR),
- F3(A, R16G16B16X16_FLOAT, RGBX16_FLOAT, C0, C1, C2, xx, FLOAT, 16_16_16_16, TB),
- F3(A, R16G16B16X16_UNORM, RGBA16_UNORM, C0, C1, C2, xx, UNORM, 16_16_16_16, T),
- F3(A, R16G16B16X16_SNORM, RGBA16_SNORM, C0, C1, C2, xx, SNORM, 16_16_16_16, T),
- I3(A, R16G16B16X16_SINT, RGBA16_SINT, C0, C1, C2, xx, SINT, 16_16_16_16, T),
- I3(A, R16G16B16X16_UINT, RGBA16_UINT, C0, C1, C2, xx, UINT, 16_16_16_16, T),
-
- F2(A, R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IB),
- F2(A, R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, IC),
- F2(A, R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, IC),
- I2(A, R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IR),
- I2(A, R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IR),
-
- F1(A, R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IB),
- F1(A, R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, IC),
- F1(A, R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, IC),
- I1(A, R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IR),
- I1(A, R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IR),
-
- C4(A, R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8, IC),
- C4(A, R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IR),
- C4(A, R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IR),
- F3(A, R8G8B8X8_SNORM, RGBA8_SNORM, C0, C1, C2, xx, SNORM, 8_8_8_8, T),
- I3(A, R8G8B8X8_SINT, RGBA8_SINT, C0, C1, C2, xx, SINT, 8_8_8_8, T),
- I3(A, R8G8B8X8_UINT, RGBA8_UINT, C0, C1, C2, xx, UINT, 8_8_8_8, T),
-
- F2(A, R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IB),
- F2(A, R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, IC),
- I2(A, R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IR),
- I2(A, R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IR),
-
- F1(A, R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IB),
- F1(A, R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, IC),
- I1(A, R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IR),
- I1(A, R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IR),
-
- F3(A, R8G8_B8G8_UNORM, NONE, C0, C1, C2, xx, UNORM, U8_YA8_V8_YB8, T),
- F3(A, G8R8_B8R8_UNORM, NONE, C1, C0, C2, xx, UNORM, U8_YA8_V8_YB8, T),
- F3(A, G8R8_G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, YA8_U8_YB8_V8, T),
- F3(A, R8G8_R8B8_UNORM, NONE, C1, C0, C2, xx, UNORM, YA8_U8_YB8_V8, T),
-
- F1(A, R1_UNORM, BITMAP, C0, xx, xx, xx, UNORM, BITMAP, T),
-
- C4(A, R4A4_UNORM, NONE, C0, ZERO, ZERO, C1, UNORM, 4_4, T),
- C4(A, R8A8_UNORM, NONE, C0, ZERO, ZERO, C1, UNORM, 8_8, T),
- C4(A, A4R4_UNORM, NONE, C1, ZERO, ZERO, C0, UNORM, 4_4, T),
- C4(A, A8R8_UNORM, NONE, C1, ZERO, ZERO, C0, UNORM, 8_8, T),
-
- SF(A, R8SG8SB8UX8U_NORM, 0, C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 8_8_8_8, T),
- SF(A, R5SG5SB6U_NORM, 0, C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 5_5_6, T),
+ C4(A, B8G8R8A8_UNORM, BGRA8_UNORM, B, G, R, A, UNORM, A8B8G8R8, TD),
+ F3(A, B8G8R8X8_UNORM, BGRX8_UNORM, B, G, R, xx, UNORM, A8B8G8R8, TD),
+ C4(A, B8G8R8A8_SRGB, BGRA8_SRGB, B, G, R, A, UNORM, A8B8G8R8, TD),
+ F3(A, B8G8R8X8_SRGB, BGRX8_SRGB, B, G, R, xx, UNORM, A8B8G8R8, TD),
+ C4(A, R8G8B8A8_UNORM, RGBA8_UNORM, R, G, B, A, UNORM, A8B8G8R8, IB),
+ F3(A, R8G8B8X8_UNORM, RGBX8_UNORM, R, G, B, xx, UNORM, A8B8G8R8, TB),
+ C4(A, R8G8B8A8_SRGB, RGBA8_SRGB, R, G, B, A, UNORM, A8B8G8R8, TB),
+ F3(A, R8G8B8X8_SRGB, RGBX8_SRGB, R, G, B, xx, UNORM, A8B8G8R8, TB),
+
+ ZX(B, Z16_UNORM, Z16_UNORM, R, R, R, xx, UNORM, Z16, TZ),
+ ZX(A, Z32_FLOAT, Z32_FLOAT, R, R, R, xx, FLOAT, ZF32, TZ),
+ ZX(A, Z24X8_UNORM, Z24_X8_UNORM, R, R, R, xx, UNORM, X8Z24, TZ),
+ SZ(A, X8Z24_UNORM, S8_Z24_UNORM, G, G, G, xx, UNORM, Z24S8, TZ),
+ ZS(A, Z24_UNORM_S8_UINT, Z24_S8_UNORM, R, R, R, xx, UNORM, S8Z24, TZ),
+ SZ(A, S8_UINT_Z24_UNORM, S8_Z24_UNORM, G, G, G, xx, UNORM, Z24S8, TZ),
+ ZS(A, Z32_FLOAT_S8X24_UINT, Z32_S8_X24_FLOAT, R, R, R, xx, FLOAT, ZF32_X24S8, TZ),
+
+ SX(A, S8_UINT, R, R8, T),
+ SX(A, X24S8_UINT, G, S8Z24, T),
+ SX(A, S8X24_UINT, R, Z24S8, T),
+ SX(A, X32_S8X24_UINT, G, ZF32_X24S8, T),
+
+ F3(A, B5G6R5_UNORM, B5G6R5_UNORM, B, G, R, xx, UNORM, B5G6R5, TD),
+ C4(A, B5G5R5A1_UNORM, BGR5_A1_UNORM, B, G, R, A, UNORM, A1B5G5R5, TD),
+ F3(A, B5G5R5X1_UNORM, BGR5_X1_UNORM, B, G, R, xx, UNORM, A1B5G5R5, TD),
+ C4(A, B4G4R4A4_UNORM, NONE, B, G, R, A, UNORM, A4B4G4R4, T),
+ F3(A, B4G4R4X4_UNORM, NONE, B, G, R, xx, UNORM, A4B4G4R4, T),
+ F3(A, R9G9B9E5_FLOAT, NONE, R, G, B, xx, FLOAT, E5B9G9R9_SHAREDEXP, T),
+
+ C4(A, R10G10B10A2_UNORM, RGB10_A2_UNORM, R, G, B, A, UNORM, A2B10G10R10, IB),
+ C4(A, B10G10R10A2_UNORM, BGR10_A2_UNORM, B, G, R, A, UNORM, A2B10G10R10, TD),
+ C4(A, R10G10B10A2_SNORM, NONE, R, G, B, A, SNORM, A2B10G10R10, T),
+ C4(A, B10G10R10A2_SNORM, NONE, B, G, R, A, SNORM, A2B10G10R10, T),
+ C4(A, R10G10B10A2_UINT, RGB10_A2_UINT, R, G, B, A, UINT, A2B10G10R10, TR),
+ C4(A, B10G10R10A2_UINT, RGB10_A2_UINT, B, G, R, A, UINT, A2B10G10R10, T),
+
+ F3(A, R11G11B10_FLOAT, R11G11B10_FLOAT, R, G, B, xx, FLOAT, BF10GF11RF11, IB),
+
+ F3(A, L8_UNORM, R8_UNORM, R, R, R, xx, UNORM, R8, TB),
+ F3(A, L8_SRGB, R8_UNORM, R, R, R, xx, UNORM, R8, TB),
+ F3(A, L8_SNORM, R8_SNORM, R, R, R, xx, SNORM, R8, TC),
+ I3(A, L8_SINT, R8_SINT, R, R, R, xx, SINT, R8, TR),
+ I3(A, L8_UINT, R8_UINT, R, R, R, xx, UINT, R8, TR),
+ F3(A, L16_UNORM, R16_UNORM, R, R, R, xx, UNORM, R16, TC),
+ F3(A, L16_SNORM, R16_SNORM, R, R, R, xx, SNORM, R16, TC),
+ F3(A, L16_FLOAT, R16_FLOAT, R, R, R, xx, FLOAT, R16, TB),
+ I3(A, L16_SINT, R16_SINT, R, R, R, xx, SINT, R16, TR),
+ I3(A, L16_UINT, R16_UINT, R, R, R, xx, UINT, R16, TR),
+ F3(A, L32_FLOAT, R32_FLOAT, R, R, R, xx, FLOAT, R32, TB),
+ I3(A, L32_SINT, R32_SINT, R, R, R, xx, SINT, R32, TR),
+ I3(A, L32_UINT, R32_UINT, R, R, R, xx, UINT, R32, TR),
+
+ C4(A, I8_UNORM, R8_UNORM, R, R, R, R, UNORM, R8, TR),
+ C4(A, I8_SNORM, R8_SNORM, R, R, R, R, SNORM, R8, TR),
+ C4(A, I8_SINT, R8_SINT, R, R, R, R, SINT, R8, TR),
+ C4(A, I8_UINT, R8_UINT, R, R, R, R, UINT, R8, TR),
+ C4(A, I16_UNORM, R16_UNORM, R, R, R, R, UNORM, R16, TR),
+ C4(A, I16_SNORM, R16_SNORM, R, R, R, R, SNORM, R16, TR),
+ C4(A, I16_FLOAT, R16_FLOAT, R, R, R, R, FLOAT, R16, TR),
+ C4(A, I16_SINT, R16_SINT, R, R, R, R, SINT, R16, TR),
+ C4(A, I16_UINT, R16_UINT, R, R, R, R, UINT, R16, TR),
+ C4(A, I32_FLOAT, R32_FLOAT, R, R, R, R, FLOAT, R32, TR),
+ C4(A, I32_SINT, R32_SINT, R, R, R, R, SINT, R32, TR),
+ C4(A, I32_UINT, R32_UINT, R, R, R, R, UINT, R32, TR),
+
+ A1(A, A8_UNORM, A8_UNORM, xx, xx, xx, R, UNORM, R8, TB),
+ A1(A, A8_SNORM, R8_SNORM, xx, xx, xx, R, SNORM, R8, T),
+ A1(A, A8_SINT, R8_SINT, xx, xx, xx, R, SINT, R8, T),
+ A1(A, A8_UINT, R8_UINT, xx, xx, xx, R, UINT, R8, T),
+ A1(A, A16_UNORM, R16_UNORM, xx, xx, xx, R, UNORM, R16, T),
+ A1(A, A16_SNORM, R16_SNORM, xx, xx, xx, R, SNORM, R16, T),
+ A1(A, A16_FLOAT, R16_FLOAT, xx, xx, xx, R, FLOAT, R16, T),
+ A1(A, A16_SINT, R16_SINT, xx, xx, xx, R, SINT, R16, T),
+ A1(A, A16_UINT, R16_UINT, xx, xx, xx, R, UINT, R16, T),
+ A1(A, A32_FLOAT, R32_FLOAT, xx, xx, xx, R, FLOAT, R32, T),
+ A1(A, A32_SINT, R32_SINT, xx, xx, xx, R, SINT, R32, T),
+ A1(A, A32_UINT, R32_UINT, xx, xx, xx, R, UINT, R32, T),
+
+ C4(A, L4A4_UNORM, NONE, R, R, R, G, UNORM, G4R4, T),
+ C4(A, L8A8_UNORM, RG8_UNORM, R, R, R, G, UNORM, G8R8, T),
+ C4(A, L8A8_SNORM, RG8_SNORM, R, R, R, G, SNORM, G8R8, T),
+ C4(A, L8A8_SRGB, RG8_UNORM, R, R, R, G, UNORM, G8R8, T),
+ C4(A, L8A8_SINT, RG8_SINT, R, R, R, G, SINT, G8R8, T),
+ C4(A, L8A8_UINT, RG8_UINT, R, R, R, G, UINT, G8R8, T),
+ C4(A, L16A16_UNORM, RG16_UNORM, R, R, R, G, UNORM, R16_G16, T),
+ C4(A, L16A16_SNORM, RG16_SNORM, R, R, R, G, SNORM, R16_G16, T),
+ C4(A, L16A16_FLOAT, RG16_FLOAT, R, R, R, G, FLOAT, R16_G16, T),
+ C4(A, L16A16_SINT, RG16_SINT, R, R, R, G, SINT, R16_G16, T),
+ C4(A, L16A16_UINT, RG16_UINT, R, R, R, G, UINT, R16_G16, T),
+ C4(A, L32A32_FLOAT, RG32_FLOAT, R, R, R, G, FLOAT, R32_G32, T),
+ C4(A, L32A32_SINT, RG32_SINT, R, R, R, G, SINT, R32_G32, T),
+ C4(A, L32A32_UINT, RG32_UINT, R, R, R, G, UINT, R32_G32, T),
+
+ F3(A, DXT1_RGB, NONE, R, G, B, xx, UNORM, DXT1, T),
+ F3(A, DXT1_SRGB, NONE, R, G, B, xx, UNORM, DXT1, T),
+ C4(A, DXT1_RGBA, NONE, R, G, B, A, UNORM, DXT1, T),
+ C4(A, DXT1_SRGBA, NONE, R, G, B, A, UNORM, DXT1, T),
+ C4(A, DXT3_RGBA, NONE, R, G, B, A, UNORM, DXT23, T),
+ C4(A, DXT3_SRGBA, NONE, R, G, B, A, UNORM, DXT23, T),
+ C4(A, DXT5_RGBA, NONE, R, G, B, A, UNORM, DXT45, T),
+ C4(A, DXT5_SRGBA, NONE, R, G, B, A, UNORM, DXT45, T),
+
+ F1(A, RGTC1_UNORM, NONE, R, xx, xx, xx, UNORM, DXN1, T),
+ F1(A, RGTC1_SNORM, NONE, R, xx, xx, xx, SNORM, DXN1, T),
+ F2(A, RGTC2_UNORM, NONE, R, G, xx, xx, UNORM, DXN2, T),
+ F2(A, RGTC2_SNORM, NONE, R, G, xx, xx, SNORM, DXN2, T),
+ F3(A, LATC1_UNORM, NONE, R, R, R, xx, UNORM, DXN1, T),
+ F3(A, LATC1_SNORM, NONE, R, R, R, xx, SNORM, DXN1, T),
+ C4(A, LATC2_UNORM, NONE, R, R, R, G, UNORM, DXN2, T),
+ C4(A, LATC2_SNORM, NONE, R, R, R, G, SNORM, DXN2, T),
+
+ C4(C, BPTC_RGBA_UNORM, NONE, R, G, B, A, UNORM, BC7U, t),
+ C4(C, BPTC_SRGBA, NONE, R, G, B, A, UNORM, BC7U, t),
+ F3(C, BPTC_RGB_FLOAT, NONE, R, G, B, xx, FLOAT, BC6H_SF16, t),
+ F3(C, BPTC_RGB_UFLOAT, NONE, R, G, B, xx, FLOAT, BC6H_UF16, t),
+
+ C4(A, R32G32B32A32_FLOAT, RGBA32_FLOAT, R, G, B, A, FLOAT, R32_G32_B32_A32, IB),
+ C4(A, R32G32B32A32_UNORM, NONE, R, G, B, A, UNORM, R32_G32_B32_A32, T),
+ C4(A, R32G32B32A32_SNORM, NONE, R, G, B, A, SNORM, R32_G32_B32_A32, T),
+ C4(A, R32G32B32A32_SINT, RGBA32_SINT, R, G, B, A, SINT, R32_G32_B32_A32, IR),
+ C4(A, R32G32B32A32_UINT, RGBA32_UINT, R, G, B, A, UINT, R32_G32_B32_A32, IR),
+ F3(A, R32G32B32X32_FLOAT, RGBX32_FLOAT, R, G, B, xx, FLOAT, R32_G32_B32_A32, TB),
+ I3(A, R32G32B32X32_SINT, RGBX32_SINT, R, G, B, xx, SINT, R32_G32_B32_A32, TR),
+ I3(A, R32G32B32X32_UINT, RGBX32_UINT, R, G, B, xx, UINT, R32_G32_B32_A32, TR),
+
+ F3(C, R32G32B32_FLOAT, NONE, R, G, B, xx, FLOAT, R32_G32_B32, t),
+ I3(C, R32G32B32_SINT, NONE, R, G, B, xx, SINT, R32_G32_B32, t),
+ I3(C, R32G32B32_UINT, NONE, R, G, B, xx, UINT, R32_G32_B32, t),
+
+ F2(A, R32G32_FLOAT, RG32_FLOAT, R, G, xx, xx, FLOAT, R32_G32, IB),
+ F2(A, R32G32_UNORM, NONE, R, G, xx, xx, UNORM, R32_G32, T),
+ F2(A, R32G32_SNORM, NONE, R, G, xx, xx, SNORM, R32_G32, T),
+ I2(A, R32G32_SINT, RG32_SINT, R, G, xx, xx, SINT, R32_G32, IR),
+ I2(A, R32G32_UINT, RG32_UINT, R, G, xx, xx, UINT, R32_G32, IR),
+
+ F1(A, R32_FLOAT, R32_FLOAT, R, xx, xx, xx, FLOAT, R32, IB),
+ F1(A, R32_UNORM, NONE, R, xx, xx, xx, UNORM, R32, T),
+ F1(A, R32_SNORM, NONE, R, xx, xx, xx, SNORM, R32, T),
+ I1(A, R32_SINT, R32_SINT, R, xx, xx, xx, SINT, R32, IR),
+ I1(A, R32_UINT, R32_UINT, R, xx, xx, xx, UINT, R32, IR),
+
+ C4(A, R16G16B16A16_FLOAT, RGBA16_FLOAT, R, G, B, A, FLOAT, R16_G16_B16_A16, IB),
+ C4(A, R16G16B16A16_UNORM, RGBA16_UNORM, R, G, B, A, UNORM, R16_G16_B16_A16, IC),
+ C4(A, R16G16B16A16_SNORM, RGBA16_SNORM, R, G, B, A, SNORM, R16_G16_B16_A16, IC),
+ C4(A, R16G16B16A16_SINT, RGBA16_SINT, R, G, B, A, SINT, R16_G16_B16_A16, IR),
+ C4(A, R16G16B16A16_UINT, RGBA16_UINT, R, G, B, A, UINT, R16_G16_B16_A16, IR),
+ F3(A, R16G16B16X16_FLOAT, RGBX16_FLOAT, R, G, B, xx, FLOAT, R16_G16_B16_A16, TB),
+ F3(A, R16G16B16X16_UNORM, RGBA16_UNORM, R, G, B, xx, UNORM, R16_G16_B16_A16, T),
+ F3(A, R16G16B16X16_SNORM, RGBA16_SNORM, R, G, B, xx, SNORM, R16_G16_B16_A16, T),
+ I3(A, R16G16B16X16_SINT, RGBA16_SINT, R, G, B, xx, SINT, R16_G16_B16_A16, T),
+ I3(A, R16G16B16X16_UINT, RGBA16_UINT, R, G, B, xx, UINT, R16_G16_B16_A16, T),
+
+ F2(A, R16G16_FLOAT, RG16_FLOAT, R, G, xx, xx, FLOAT, R16_G16, IB),
+ F2(A, R16G16_UNORM, RG16_UNORM, R, G, xx, xx, UNORM, R16_G16, IC),
+ F2(A, R16G16_SNORM, RG16_SNORM, R, G, xx, xx, SNORM, R16_G16, IC),
+ I2(A, R16G16_SINT, RG16_SINT, R, G, xx, xx, SINT, R16_G16, IR),
+ I2(A, R16G16_UINT, RG16_UINT, R, G, xx, xx, UINT, R16_G16, IR),
+
+ F1(A, R16_FLOAT, R16_FLOAT, R, xx, xx, xx, FLOAT, R16, IB),
+ F1(A, R16_UNORM, R16_UNORM, R, xx, xx, xx, UNORM, R16, IC),
+ F1(A, R16_SNORM, R16_SNORM, R, xx, xx, xx, SNORM, R16, IC),
+ I1(A, R16_SINT, R16_SINT, R, xx, xx, xx, SINT, R16, IR),
+ I1(A, R16_UINT, R16_UINT, R, xx, xx, xx, UINT, R16, IR),
+
+ C4(A, R8G8B8A8_SNORM, RGBA8_SNORM, R, G, B, A, SNORM, A8B8G8R8, IC),
+ C4(A, R8G8B8A8_SINT, RGBA8_SINT, R, G, B, A, SINT, A8B8G8R8, IR),
+ C4(A, R8G8B8A8_UINT, RGBA8_UINT, R, G, B, A, UINT, A8B8G8R8, IR),
+ F3(A, R8G8B8X8_SNORM, RGBA8_SNORM, R, G, B, xx, SNORM, A8B8G8R8, T),
+ I3(A, R8G8B8X8_SINT, RGBA8_SINT, R, G, B, xx, SINT, A8B8G8R8, T),
+ I3(A, R8G8B8X8_UINT, RGBA8_UINT, R, G, B, xx, UINT, A8B8G8R8, T),
+
+ F2(A, R8G8_UNORM, RG8_UNORM, R, G, xx, xx, UNORM, G8R8, IB),
+ F2(A, R8G8_SNORM, RG8_SNORM, R, G, xx, xx, SNORM, G8R8, IC),
+ I2(A, R8G8_SINT, RG8_SINT, R, G, xx, xx, SINT, G8R8, IR),
+ I2(A, R8G8_UINT, RG8_UINT, R, G, xx, xx, UINT, G8R8, IR),
+
+ F1(A, R8_UNORM, R8_UNORM, R, xx, xx, xx, UNORM, R8, IB),
+ F1(A, R8_SNORM, R8_SNORM, R, xx, xx, xx, SNORM, R8, IC),
+ I1(A, R8_SINT, R8_SINT, R, xx, xx, xx, SINT, R8, IR),
+ I1(A, R8_UINT, R8_UINT, R, xx, xx, xx, UINT, R8, IR),
+
+ F3(A, R8G8_B8G8_UNORM, NONE, R, G, B, xx, UNORM, G8B8G8R8, T),
+ F3(A, G8R8_B8R8_UNORM, NONE, G, R, B, xx, UNORM, G8B8G8R8, T),
+ F3(A, G8R8_G8B8_UNORM, NONE, R, G, B, xx, UNORM, B8G8R8G8, T),
+ F3(A, R8G8_R8B8_UNORM, NONE, G, R, B, xx, UNORM, B8G8R8G8, T),
+
+ F1(A, R1_UNORM, BITMAP, R, xx, xx, xx, UNORM, R1, T),
+
+ C4(A, R4A4_UNORM, NONE, R, ZERO, ZERO, G, UNORM, G4R4, T),
+ C4(A, R8A8_UNORM, NONE, R, ZERO, ZERO, G, UNORM, G8R8, T),
+ C4(A, A4R4_UNORM, NONE, G, ZERO, ZERO, R, UNORM, G4R4, T),
+ C4(A, A8R8_UNORM, NONE, G, ZERO, ZERO, R, UNORM, G8R8, T),
+
+ SF(A, R8SG8SB8UX8U_NORM, 0, R, G, B, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, A8B8G8R8, T),
+ SF(A, R5SG5SB6U_NORM, 0, R, G, B, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, B6G5R5, T),
};
#if NOUVEAU_DRIVER == 0xc0
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 15/23] nv50: switch nv50_state.c to updated g80_texture.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (12 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 14/23] nv50-: switch nv50_formats.c to updated g80_texture.xml.h Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 16/23] nv50: switch nv50_surface.c " Ben Skeggs
` (7 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_state.c | 53 +++++++++++++++------------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state.c b/src/gallium/drivers/nouveau/nv50/nv50_state.c
index 438f413..c8eea99 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state.c
@@ -34,7 +34,7 @@
#include "nv50/nv50_query_hw.h"
#include "nv50/nv50_3d.xml.h"
-#include "nv50/nv50_texture.xml.h"
+#include "nv50/g80_texture.xml.h"
#include "nouveau_gldefs.h"
@@ -438,24 +438,29 @@ nv50_zsa_state_delete(struct pipe_context *pipe, void *hwcso)
/* ====================== SAMPLERS AND TEXTURES ================================
*/
-#define NV50_TSC_WRAP_CASE(n) \
- case PIPE_TEX_WRAP_##n: return NV50_TSC_WRAP_##n
-
static inline unsigned
nv50_tsc_wrap_mode(unsigned wrap)
{
switch (wrap) {
- NV50_TSC_WRAP_CASE(REPEAT);
- NV50_TSC_WRAP_CASE(MIRROR_REPEAT);
- NV50_TSC_WRAP_CASE(CLAMP_TO_EDGE);
- NV50_TSC_WRAP_CASE(CLAMP_TO_BORDER);
- NV50_TSC_WRAP_CASE(CLAMP);
- NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_EDGE);
- NV50_TSC_WRAP_CASE(MIRROR_CLAMP_TO_BORDER);
- NV50_TSC_WRAP_CASE(MIRROR_CLAMP);
+ case PIPE_TEX_WRAP_REPEAT:
+ return G80_TSC_WRAP_WRAP;
+ case PIPE_TEX_WRAP_MIRROR_REPEAT:
+ return G80_TSC_WRAP_MIRROR;
+ case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+ return G80_TSC_WRAP_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+ return G80_TSC_WRAP_BORDER;
+ case PIPE_TEX_WRAP_CLAMP:
+ return G80_TSC_WRAP_CLAMP_OGL;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+ return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_TO_EDGE;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+ return G80_TSC_WRAP_MIRROR_ONCE_BORDER;
+ case PIPE_TEX_WRAP_MIRROR_CLAMP:
+ return G80_TSC_WRAP_MIRROR_ONCE_CLAMP_OGL;
default:
NOUVEAU_ERR("unknown wrap mode: %d\n", wrap);
- return NV50_TSC_WRAP_REPEAT;
+ return G80_TSC_WRAP_WRAP;
}
}
@@ -475,42 +480,42 @@ nv50_sampler_state_create(struct pipe_context *pipe,
switch (cso->mag_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
- so->tsc[1] = NV50_TSC_1_MAGF_LINEAR;
+ so->tsc[1] = G80_TSC_1_MAG_FILTER_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
- so->tsc[1] = NV50_TSC_1_MAGF_NEAREST;
+ so->tsc[1] = G80_TSC_1_MAG_FILTER_NEAREST;
break;
}
switch (cso->min_img_filter) {
case PIPE_TEX_FILTER_LINEAR:
- so->tsc[1] |= NV50_TSC_1_MINF_LINEAR;
+ so->tsc[1] |= G80_TSC_1_MIN_FILTER_LINEAR;
break;
case PIPE_TEX_FILTER_NEAREST:
default:
- so->tsc[1] |= NV50_TSC_1_MINF_NEAREST;
+ so->tsc[1] |= G80_TSC_1_MIN_FILTER_NEAREST;
break;
}
switch (cso->min_mip_filter) {
case PIPE_TEX_MIPFILTER_LINEAR:
- so->tsc[1] |= NV50_TSC_1_MIPF_LINEAR;
+ so->tsc[1] |= G80_TSC_1_MIP_FILTER_LINEAR;
break;
case PIPE_TEX_MIPFILTER_NEAREST:
- so->tsc[1] |= NV50_TSC_1_MIPF_NEAREST;
+ so->tsc[1] |= G80_TSC_1_MIP_FILTER_NEAREST;
break;
case PIPE_TEX_MIPFILTER_NONE:
default:
- so->tsc[1] |= NV50_TSC_1_MIPF_NONE;
+ so->tsc[1] |= G80_TSC_1_MIP_FILTER_NONE;
break;
}
if (nouveau_screen(pipe->screen)->class_3d >= NVE4_3D_CLASS) {
if (cso->seamless_cube_map)
- so->tsc[1] |= NVE4_TSC_1_CUBE_SEAMLESS;
+ so->tsc[1] |= GK104_TSC_1_CUBEMAP_INTERFACE_FILTERING;
if (!cso->normalized_coords)
- so->tsc[1] |= NVE4_TSC_1_FORCE_NONNORMALIZED_COORDS;
+ so->tsc[1] |= GK104_TSC_1_FLOAT_COORD_NORMALIZATION_FORCE_UNNORMALIZED_COORDS;
}
if (cso->max_anisotropy >= 16)
@@ -522,10 +527,10 @@ nv50_sampler_state_create(struct pipe_context *pipe,
so->tsc[0] |= (cso->max_anisotropy >> 1) << 20;
if (cso->max_anisotropy >= 4)
- so->tsc[1] |= NV50_TSC_1_UNKN_ANISO_35;
+ so->tsc[1] |= 6 << G80_TSC_1_TRILIN_OPT__SHIFT;
else
if (cso->max_anisotropy >= 2)
- so->tsc[1] |= NV50_TSC_1_UNKN_ANISO_15;
+ so->tsc[1] |= 4 << G80_TSC_1_TRILIN_OPT__SHIFT;
}
if (cso->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) {
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 16/23] nv50: switch nv50_surface.c to updated g80_texture.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (13 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 15/23] nv50: switch nv50_state.c " Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 17/23] nv50: switch nv50_tex.c " Ben Skeggs
` (6 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_surface.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
index 8080b81..4db73cb 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c
@@ -38,7 +38,7 @@
#include "nv50/nv50_resource.h"
#include "nv50/g80_defs.xml.h"
-#include "nv50/nv50_texture.xml.h"
+#include "nv50/g80_texture.xml.h"
/* these are used in nv50_blit.h */
#define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
@@ -997,12 +997,14 @@ nv50_blitter_make_sampler(struct nv50_blitter *blit)
blit->sampler[0].id = -1;
- blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
- (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
- (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
- (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
+ blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
+ (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
+ (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
+ (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
blit->sampler[0].tsc[1] =
- NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
+ G80_TSC_1_MAG_FILTER_NEAREST |
+ G80_TSC_1_MIN_FILTER_NEAREST |
+ G80_TSC_1_MIP_FILTER_NONE;
/* clamp to edge, min/max lod = 0, bilinear filtering */
@@ -1010,7 +1012,9 @@ nv50_blitter_make_sampler(struct nv50_blitter *blit)
blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
blit->sampler[1].tsc[1] =
- NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
+ G80_TSC_1_MAG_FILTER_LINEAR |
+ G80_TSC_1_MIN_FILTER_LINEAR |
+ G80_TSC_1_MIP_FILTER_NONE;
}
unsigned
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 17/23] nv50: switch nv50_tex.c to updated g80_texture.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (14 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 16/23] nv50: switch nv50_surface.c " Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 18/23] nvc0: switch nvc0_surface.c " Ben Skeggs
` (5 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_tex.c | 66 ++++++++++++++---------------
1 file changed, 33 insertions(+), 33 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_tex.c b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
index b53a435..7c96677 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
@@ -22,32 +22,32 @@
#include "nv50/nv50_context.h"
#include "nv50/nv50_resource.h"
-#include "nv50/nv50_texture.xml.h"
+#include "nv50/g80_texture.xml.h"
#include "nv50/g80_defs.xml.h"
#include "util/u_format.h"
-#define NV50_TIC_0_SWIZZLE__MASK \
- (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK | \
- NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
+#define G80_TIC_0_SWIZZLE__MASK \
+ (G80_TIC_0_W_SOURCE__MASK | G80_TIC_0_Z_SOURCE__MASK | \
+ G80_TIC_0_Y_SOURCE__MASK | G80_TIC_0_X_SOURCE__MASK)
static inline uint32_t
nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
{
switch (swz) {
case PIPE_SWIZZLE_RED:
- return (tc & NV50_TIC_0_MAPR__MASK) >> NV50_TIC_0_MAPR__SHIFT;
+ return (tc & G80_TIC_0_X_SOURCE__MASK) >> G80_TIC_0_X_SOURCE__SHIFT;
case PIPE_SWIZZLE_GREEN:
- return (tc & NV50_TIC_0_MAPG__MASK) >> NV50_TIC_0_MAPG__SHIFT;
+ return (tc & G80_TIC_0_Y_SOURCE__MASK) >> G80_TIC_0_Y_SOURCE__SHIFT;
case PIPE_SWIZZLE_BLUE:
- return (tc & NV50_TIC_0_MAPB__MASK) >> NV50_TIC_0_MAPB__SHIFT;
+ return (tc & G80_TIC_0_Z_SOURCE__MASK) >> G80_TIC_0_Z_SOURCE__SHIFT;
case PIPE_SWIZZLE_ALPHA:
- return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT;
+ return (tc & G80_TIC_0_W_SOURCE__MASK) >> G80_TIC_0_W_SOURCE__SHIFT;
case PIPE_SWIZZLE_ONE:
- return tex_int ? NV50_TIC_MAP_ONE_INT : NV50_TIC_MAP_ONE_FLOAT;
+ return tex_int ? G80_TIC_SOURCE_ONE_INT : G80_TIC_SOURCE_ONE_FLOAT;
case PIPE_SWIZZLE_ZERO:
default:
- return NV50_TIC_MAP_ZERO;
+ return G80_TIC_SOURCE_ZERO;
}
}
@@ -108,11 +108,11 @@ nv50_create_texture_view(struct pipe_context *pipe,
swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
- tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
- (swz[0] << NV50_TIC_0_MAPR__SHIFT) |
- (swz[1] << NV50_TIC_0_MAPG__SHIFT) |
- (swz[2] << NV50_TIC_0_MAPB__SHIFT) |
- (swz[3] << NV50_TIC_0_MAPA__SHIFT);
+ tic[0] = (tic[0] & ~G80_TIC_0_SWIZZLE__MASK) |
+ (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
+ (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
+ (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
+ (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
addr = mt->base.address;
@@ -124,24 +124,24 @@ nv50_create_texture_view(struct pipe_context *pipe,
depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
}
- tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER;
+ tic[2] = 0x10001000 | G80_TIC_2_BORDER_SOURCE_COLOR;
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
- tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
+ tic[2] |= G80_TIC_2_SRGB_CONVERSION;
if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
- tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
+ tic[2] |= G80_TIC_2_NORMALIZED_COORDS;
if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
if (target == PIPE_BUFFER) {
addr += view->pipe.u.buf.first_element * desc->block.bits / 8;
- tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER;
+ tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER;
tic[3] = 0;
tic[4] = /* width */
view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1;
tic[5] = 0;
} else {
- tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
+ tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
tic[3] = mt->level[0].pitch;
tic[4] = mt->base.base.width0;
tic[5] = (1 << 16) | (mt->base.base.height0);
@@ -162,34 +162,34 @@ nv50_create_texture_view(struct pipe_context *pipe,
switch (target) {
case PIPE_TEXTURE_1D:
- tic[2] |= NV50_TIC_2_TARGET_1D;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D;
break;
case PIPE_TEXTURE_2D:
- tic[2] |= NV50_TIC_2_TARGET_2D;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
break;
case PIPE_TEXTURE_RECT:
- tic[2] |= NV50_TIC_2_TARGET_RECT;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
break;
case PIPE_TEXTURE_3D:
- tic[2] |= NV50_TIC_2_TARGET_3D;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_THREE_D;
break;
case PIPE_TEXTURE_CUBE:
depth /= 6;
- tic[2] |= NV50_TIC_2_TARGET_CUBE;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBEMAP;
break;
case PIPE_TEXTURE_1D_ARRAY:
- tic[2] |= NV50_TIC_2_TARGET_1D_ARRAY;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY;
break;
case PIPE_TEXTURE_2D_ARRAY:
- tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY;
break;
case PIPE_TEXTURE_CUBE_ARRAY:
depth /= 6;
- tic[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY;
break;
case PIPE_BUFFER:
assert(0); /* should be linear and handled above ! */
- tic[2] |= NV50_TIC_2_TARGET_BUFFER | NV50_TIC_2_LINEAR;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER | G80_TIC_2_LAYOUT_PITCH;
break;
default:
unreachable("unexpected/invalid texture target");
@@ -202,9 +202,9 @@ nv50_create_texture_view(struct pipe_context *pipe,
tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff;
tic[5] |= depth << 16;
if (class_3d > NV50_3D_CLASS)
- tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+ tic[5] |= mt->base.base.last_level << G80_TIC_5_MAP_MIP_LEVEL__SHIFT;
else
- tic[5] |= view->pipe.u.tex.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+ tic[5] |= view->pipe.u.tex.last_level << G80_TIC_5_MAP_MIP_LEVEL__SHIFT;
tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */
@@ -213,9 +213,9 @@ nv50_create_texture_view(struct pipe_context *pipe,
else
tic[7] = 0;
- if (unlikely(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS)))
+ if (unlikely(!(tic[2] & G80_TIC_2_NORMALIZED_COORDS)))
if (mt->base.base.last_level)
- tic[5] &= ~NV50_TIC_5_LAST_LEVEL__MASK;
+ tic[5] &= ~G80_TIC_5_MAP_MIP_LEVEL__MASK;
return &view->pipe;
}
--
2.7.0
_______________________________________________
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Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 18/23] nvc0: switch nvc0_surface.c to updated g80_texture.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (15 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 17/23] nv50: switch nv50_tex.c " Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 19/23] nvc0: switch nvc0_tex.c " Ben Skeggs
` (4 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index 3b29e40..6f6d46c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -35,7 +35,7 @@
#include "nvc0/nvc0_resource.h"
#include "nv50/g80_defs.xml.h"
-#include "nv50/nv50_texture.xml.h"
+#include "nv50/g80_texture.xml.h"
/* these are used in nv50_blit.h */
#define NV50_ENG2D_SUPPORTED_FORMATS 0xff9ccfe1cce3ccc9ULL
@@ -871,12 +871,14 @@ nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
blit->sampler[0].id = -1;
- blit->sampler[0].tsc[0] = NV50_TSC_0_SRGB_CONVERSION_ALLOWED |
- (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPS__SHIFT) |
- (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPT__SHIFT) |
- (NV50_TSC_WRAP_CLAMP_TO_EDGE << NV50_TSC_0_WRAPR__SHIFT);
+ blit->sampler[0].tsc[0] = G80_TSC_0_SRGB_CONVERSION |
+ (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_U__SHIFT) |
+ (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_V__SHIFT) |
+ (G80_TSC_WRAP_CLAMP_TO_EDGE << G80_TSC_0_ADDRESS_P__SHIFT);
blit->sampler[0].tsc[1] =
- NV50_TSC_1_MAGF_NEAREST | NV50_TSC_1_MINF_NEAREST | NV50_TSC_1_MIPF_NONE;
+ G80_TSC_1_MAG_FILTER_NEAREST |
+ G80_TSC_1_MIN_FILTER_NEAREST |
+ G80_TSC_1_MIP_FILTER_NONE;
/* clamp to edge, min/max lod = 0, bilinear filtering */
@@ -884,7 +886,9 @@ nvc0_blitter_make_sampler(struct nvc0_blitter *blit)
blit->sampler[1].tsc[0] = blit->sampler[0].tsc[0];
blit->sampler[1].tsc[1] =
- NV50_TSC_1_MAGF_LINEAR | NV50_TSC_1_MINF_LINEAR | NV50_TSC_1_MIPF_NONE;
+ G80_TSC_1_MAG_FILTER_LINEAR |
+ G80_TSC_1_MIN_FILTER_LINEAR |
+ G80_TSC_1_MIP_FILTER_NONE;
}
static void
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 19/23] nvc0: switch nvc0_tex.c to updated g80_texture.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (16 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 18/23] nvc0: switch nvc0_surface.c " Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 20/23] nv50-: remove nv50_texture.xml.h Ben Skeggs
` (3 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Verified (binary diff) to produce identical code.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 58 ++++++++++++++---------------
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index cbfebb8..ac74dc3 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -22,7 +22,7 @@
#include "nvc0/nvc0_context.h"
#include "nvc0/nvc0_resource.h"
-#include "nv50/nv50_texture.xml.h"
+#include "nv50/g80_texture.xml.h"
#include "nv50/g80_defs.xml.h"
#include "util/u_format.h"
@@ -30,27 +30,27 @@
#define NVE4_TIC_ENTRY_INVALID 0x000fffff
#define NVE4_TSC_ENTRY_INVALID 0xfff00000
-#define NV50_TIC_0_SWIZZLE__MASK \
- (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK | \
- NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
+#define G80_TIC_0_SWIZZLE__MASK \
+ (G80_TIC_0_W_SOURCE__MASK | G80_TIC_0_Z_SOURCE__MASK | \
+ G80_TIC_0_Y_SOURCE__MASK | G80_TIC_0_X_SOURCE__MASK)
static inline uint32_t
nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
{
switch (swz) {
case PIPE_SWIZZLE_RED:
- return (tc & NV50_TIC_0_MAPR__MASK) >> NV50_TIC_0_MAPR__SHIFT;
+ return (tc & G80_TIC_0_X_SOURCE__MASK) >> G80_TIC_0_X_SOURCE__SHIFT;
case PIPE_SWIZZLE_GREEN:
- return (tc & NV50_TIC_0_MAPG__MASK) >> NV50_TIC_0_MAPG__SHIFT;
+ return (tc & G80_TIC_0_Y_SOURCE__MASK) >> G80_TIC_0_Y_SOURCE__SHIFT;
case PIPE_SWIZZLE_BLUE:
- return (tc & NV50_TIC_0_MAPB__MASK) >> NV50_TIC_0_MAPB__SHIFT;
+ return (tc & G80_TIC_0_Z_SOURCE__MASK) >> G80_TIC_0_Z_SOURCE__SHIFT;
case PIPE_SWIZZLE_ALPHA:
- return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT;
+ return (tc & G80_TIC_0_W_SOURCE__MASK) >> G80_TIC_0_W_SOURCE__SHIFT;
case PIPE_SWIZZLE_ONE:
- return tex_int ? NV50_TIC_MAP_ONE_INT : NV50_TIC_MAP_ONE_FLOAT;
+ return tex_int ? G80_TIC_SOURCE_ONE_INT : G80_TIC_SOURCE_ONE_FLOAT;
case PIPE_SWIZZLE_ZERO:
default:
- return NV50_TIC_MAP_ZERO;
+ return G80_TIC_SOURCE_ZERO;
}
}
@@ -110,36 +110,36 @@ nvc0_create_texture_view(struct pipe_context *pipe,
swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
- tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
- (swz[0] << NV50_TIC_0_MAPR__SHIFT) |
- (swz[1] << NV50_TIC_0_MAPG__SHIFT) |
- (swz[2] << NV50_TIC_0_MAPB__SHIFT) |
- (swz[3] << NV50_TIC_0_MAPA__SHIFT);
+ tic[0] = (tic[0] & ~G80_TIC_0_SWIZZLE__MASK) |
+ (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
+ (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
+ (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
+ (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
address = mt->base.address;
- tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER;
+ tic[2] = 0x10001000 | G80_TIC_2_BORDER_SOURCE_COLOR;
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
- tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
+ tic[2] |= G80_TIC_2_SRGB_CONVERSION;
if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
- tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
+ tic[2] |= G80_TIC_2_NORMALIZED_COORDS;
/* check for linear storage type */
if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
if (texture->target == PIPE_BUFFER) {
- assert(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS));
+ assert(!(tic[2] & G80_TIC_2_NORMALIZED_COORDS));
address +=
view->pipe.u.buf.first_element * desc->block.bits / 8;
- tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER;
+ tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER;
tic[3] = 0;
tic[4] = /* width */
view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1;
tic[5] = 0;
} else {
/* must be 2D texture without mip maps */
- tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
+ tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
tic[3] = mt->level[0].pitch;
tic[4] = mt->base.base.width0;
tic[5] = (1 << 16) | mt->base.base.height0;
@@ -167,30 +167,30 @@ nvc0_create_texture_view(struct pipe_context *pipe,
switch (target) {
case PIPE_TEXTURE_1D:
- tic[2] |= NV50_TIC_2_TARGET_1D;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D;
break;
case PIPE_TEXTURE_2D:
- tic[2] |= NV50_TIC_2_TARGET_2D;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
break;
case PIPE_TEXTURE_RECT:
- tic[2] |= NV50_TIC_2_TARGET_2D;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
break;
case PIPE_TEXTURE_3D:
- tic[2] |= NV50_TIC_2_TARGET_3D;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_THREE_D;
break;
case PIPE_TEXTURE_CUBE:
depth /= 6;
- tic[2] |= NV50_TIC_2_TARGET_CUBE;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBEMAP;
break;
case PIPE_TEXTURE_1D_ARRAY:
- tic[2] |= NV50_TIC_2_TARGET_1D_ARRAY;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY;
break;
case PIPE_TEXTURE_2D_ARRAY:
- tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY;
break;
case PIPE_TEXTURE_CUBE_ARRAY:
depth /= 6;
- tic[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY;
+ tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY;
break;
default:
unreachable("unexpected/invalid texture target");
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 20/23] nv50-: remove nv50_texture.xml.h
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (17 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 19/23] nvc0: switch nvc0_tex.c " Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 21/23] nv50-: split tic format specification Ben Skeggs
` (2 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drivers/nouveau/nv50/nv50_texture.xml.h | 306 ---------------------
1 file changed, 306 deletions(-)
delete mode 100644 src/gallium/drivers/nouveau/nv50/nv50_texture.xml.h
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_texture.xml.h b/src/gallium/drivers/nouveau/nv50/nv50_texture.xml.h
deleted file mode 100644
index a2b9921..0000000
--- a/src/gallium/drivers/nouveau/nv50/nv50_texture.xml.h
+++ /dev/null
@@ -1,306 +0,0 @@
-#ifndef NV50_TEXTURE_XML
-#define NV50_TEXTURE_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/envytools/envytools/
-git clone https://github.com/envytools/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- rnndb/graph/g80_texture.xml ( 8881 bytes, from 2014-09-25 06:32:11)
-- rnndb/copyright.xml ( 6452 bytes, from 2013-05-14 03:57:49)
-- rnndb/nvchipsets.xml ( 2759 bytes, from 2014-10-05 01:51:02)
-- rnndb/g80_defs.xml ( 18175 bytes, from 2014-09-25 06:32:11)
-
-Copyright (C) 2006-2014 by the following authors:
-- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
-- Ben Skeggs (darktama, darktama_)
-- B. R. <koala_br@users.sourceforge.net> (koala_br)
-- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
-- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
-- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
-- Dmitry Baryshkov
-- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
-- EdB <edb_@users.sf.net> (edb_)
-- Erik Waling <erikwailing@users.sf.net> (erikwaling)
-- Francisco Jerez <currojerez@riseup.net> (curro)
-- imirkin <imirkin@users.sf.net> (imirkin)
-- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
-- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
-- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
-- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
-- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
-- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
-- Mark Carey <mark.carey@gmail.com> (careym)
-- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
-- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
-- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
-- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
-- Peter Popov <ironpeter@users.sf.net> (ironpeter)
-- Richard Hughes <hughsient@users.sf.net> (hughsient)
-- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
-- Serge Martin
-- Simon Raffeiner
-- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
-- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
-- sturmflut <sturmflut@users.sf.net> (sturmflut)
-- Sylvain Munaut <tnt@246tNt.com>
-- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
-- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
-- Younes Manton <younes.m@gmail.com> (ymanton)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define NV50_TIC_MAP_ZERO 0x00000000
-#define NV50_TIC_MAP_C0 0x00000002
-#define NV50_TIC_MAP_C1 0x00000003
-#define NV50_TIC_MAP_C2 0x00000004
-#define NV50_TIC_MAP_C3 0x00000005
-#define NV50_TIC_MAP_ONE_INT 0x00000006
-#define NV50_TIC_MAP_ONE_FLOAT 0x00000007
-#define NV50_TIC_TYPE_SNORM 0x00000001
-#define NV50_TIC_TYPE_UNORM 0x00000002
-#define NV50_TIC_TYPE_SINT 0x00000003
-#define NV50_TIC_TYPE_UINT 0x00000004
-#define NV50_TIC_TYPE_SSCALED 0x00000005
-#define NV50_TIC_TYPE_USCALED 0x00000006
-#define NV50_TIC_TYPE_FLOAT 0x00000007
-#define NV50_TSC_WRAP_REPEAT 0x00000000
-#define NV50_TSC_WRAP_MIRROR_REPEAT 0x00000001
-#define NV50_TSC_WRAP_CLAMP_TO_EDGE 0x00000002
-#define NV50_TSC_WRAP_CLAMP_TO_BORDER 0x00000003
-#define NV50_TSC_WRAP_CLAMP 0x00000004
-#define NV50_TSC_WRAP_MIRROR_CLAMP_TO_EDGE 0x00000005
-#define NV50_TSC_WRAP_MIRROR_CLAMP_TO_BORDER 0x00000006
-#define NV50_TSC_WRAP_MIRROR_CLAMP 0x00000007
-#define NV50_TIC__SIZE 0x00000020
-#define NV50_TIC_0 0x00000000
-#define NV50_TIC_0_MAPA__MASK 0x38000000
-#define NV50_TIC_0_MAPA__SHIFT 27
-#define NV50_TIC_0_MAPB__MASK 0x07000000
-#define NV50_TIC_0_MAPB__SHIFT 24
-#define NV50_TIC_0_MAPG__MASK 0x00e00000
-#define NV50_TIC_0_MAPG__SHIFT 21
-#define NV50_TIC_0_MAPR__MASK 0x001c0000
-#define NV50_TIC_0_MAPR__SHIFT 18
-#define NV50_TIC_0_TYPE3__MASK 0x00038000
-#define NV50_TIC_0_TYPE3__SHIFT 15
-#define NV50_TIC_0_TYPE2__MASK 0x00007000
-#define NV50_TIC_0_TYPE2__SHIFT 12
-#define NV50_TIC_0_TYPE1__MASK 0x00000e00
-#define NV50_TIC_0_TYPE1__SHIFT 9
-#define NV50_TIC_0_TYPE0__MASK 0x000001c0
-#define NV50_TIC_0_TYPE0__SHIFT 6
-#define NV50_TIC_0_FMT__MASK 0x0000003f
-#define NV50_TIC_0_FMT__SHIFT 0
-#define NV50_TIC_0_FMT_32_32_32_32 0x00000001
-#define NVC0_TIC_0_FMT_32_32_32 0x00000002
-#define NV50_TIC_0_FMT_16_16_16_16 0x00000003
-#define NV50_TIC_0_FMT_32_32 0x00000004
-#define NV50_TIC_0_FMT_32_8_X24 0x00000005
-#define NV50_TIC_0_FMT_8_8_8_8 0x00000008
-#define NV50_TIC_0_FMT_10_10_10_2 0x00000009
-#define NV50_TIC_0_FMT_16_16 0x0000000c
-#define NV50_TIC_0_FMT_24_8 0x0000000d
-#define NV50_TIC_0_FMT_8_24 0x0000000e
-#define NV50_TIC_0_FMT_32 0x0000000f
-#define NVC0_TIC_0_FMT_BPTC_FLOAT 0x00000010
-#define NVC0_TIC_0_FMT_BPTC_UFLOAT 0x00000011
-#define NV50_TIC_0_FMT_4_4_4_4 0x00000012
-#define NV50_TIC_0_FMT_1_5_5_5 0x00000013
-#define NV50_TIC_0_FMT_5_5_5_1 0x00000014
-#define NV50_TIC_0_FMT_5_6_5 0x00000015
-#define NV50_TIC_0_FMT_5_5_6 0x00000016
-#define NVC0_TIC_0_FMT_BPTC 0x00000017
-#define NV50_TIC_0_FMT_8_8 0x00000018
-#define NV50_TIC_0_FMT_16 0x0000001b
-#define NV50_TIC_0_FMT_8 0x0000001d
-#define NV50_TIC_0_FMT_4_4 0x0000001e
-#define NV50_TIC_0_FMT_BITMAP 0x0000001f
-#define NV50_TIC_0_FMT_9_9_9_E5 0x00000020
-#define NV50_TIC_0_FMT_11_11_10 0x00000021
-#define NV50_TIC_0_FMT_U8_YA8_V8_YB8 0x00000022
-#define NV50_TIC_0_FMT_YA8_U8_YB8_V8 0x00000023
-#define NV50_TIC_0_FMT_DXT1 0x00000024
-#define NV50_TIC_0_FMT_DXT3 0x00000025
-#define NV50_TIC_0_FMT_DXT5 0x00000026
-#define NV50_TIC_0_FMT_RGTC1 0x00000027
-#define NV50_TIC_0_FMT_RGTC2 0x00000028
-#define NV50_TIC_0_FMT_S8_Z24 0x00000029
-#define NV50_TIC_0_FMT_Z24_X8 0x0000002a
-#define NV50_TIC_0_FMT_Z24_S8 0x0000002b
-#define NV50_TIC_0_FMT_Z24_C8_MS4_CS4 0x0000002c
-#define NV50_TIC_0_FMT_Z24_C8_MS8_CS8 0x0000002d
-#define NV50_TIC_0_FMT_Z24_C8_MS4_CS12 0x0000002e
-#define NV50_TIC_0_FMT_Z32 0x0000002f
-#define NV50_TIC_0_FMT_Z32_S8_X24 0x00000030
-#define NV50_TIC_0_FMT_Z24_X8_S8_C8_X16_MS4_CS4 0x00000031
-#define NV50_TIC_0_FMT_Z24_X8_S8_C8_X16_MS8_CS8 0x00000032
-#define NV50_TIC_0_FMT_Z32_X8_C8_X16_MS4_CS4 0x00000033
-#define NV50_TIC_0_FMT_Z32_X8_C8_X16_MS8_CS8 0x00000034
-#define NV50_TIC_0_FMT_Z32_S8_C8_X16_MS4_CS4 0x00000035
-#define NV50_TIC_0_FMT_Z32_S8_C8_X16_MS8_CS8 0x00000036
-#define NV50_TIC_0_FMT_Z24_X8_S8_C8_X16_MS4_CS12 0x00000037
-#define NV50_TIC_0_FMT_Z32_X8_C8_X16_MS4_CS12 0x00000038
-#define NV50_TIC_0_FMT_Z32_S8_C8_X16_MS4_CS12 0x00000039
-#define NV50_TIC_0_FMT_Z16 0x0000003a
-
-#define NV50_TIC_1 0x00000004
-#define NV50_TIC_1_OFFSET_LOW__MASK 0xffffffff
-#define NV50_TIC_1_OFFSET_LOW__SHIFT 0
-
-#define NV50_TIC_2 0x00000008
-#define NV50_TIC_2_OFFSET_HIGH__MASK 0x000000ff
-#define NV50_TIC_2_OFFSET_HIGH__SHIFT 0
-#define NV50_TIC_2_COLORSPACE_SRGB 0x00000400
-#define NV50_TIC_2_TARGET__MASK 0x0003c000
-#define NV50_TIC_2_TARGET__SHIFT 14
-#define NV50_TIC_2_TARGET_1D 0x00000000
-#define NV50_TIC_2_TARGET_2D 0x00004000
-#define NV50_TIC_2_TARGET_3D 0x00008000
-#define NV50_TIC_2_TARGET_CUBE 0x0000c000
-#define NV50_TIC_2_TARGET_1D_ARRAY 0x00010000
-#define NV50_TIC_2_TARGET_2D_ARRAY 0x00014000
-#define NV50_TIC_2_TARGET_BUFFER 0x00018000
-#define NV50_TIC_2_TARGET_RECT 0x0001c000
-#define NV50_TIC_2_TARGET_CUBE_ARRAY 0x00020000
-#define NV50_TIC_2_LINEAR 0x00040000
-#define NV50_TIC_2_TILE_MODE_X__MASK 0x00380000
-#define NV50_TIC_2_TILE_MODE_X__SHIFT 19
-#define NV50_TIC_2_TILE_MODE_Y__MASK 0x01c00000
-#define NV50_TIC_2_TILE_MODE_Y__SHIFT 22
-#define NV50_TIC_2_TILE_MODE_Z__MASK 0x0e000000
-#define NV50_TIC_2_TILE_MODE_Z__SHIFT 25
-#define NV50_TIC_2_2D_UNK0258__MASK 0x30000000
-#define NV50_TIC_2_2D_UNK0258__SHIFT 28
-#define NV50_TIC_2_NO_BORDER 0x40000000
-#define NV50_TIC_2_NORMALIZED_COORDS 0x80000000
-
-#define NV50_TIC_3 0x0000000c
-#define NV50_TIC_3_PITCH__MASK 0xffffffff
-#define NV50_TIC_3_PITCH__SHIFT 0
-
-#define NV50_TIC_4 0x00000010
-#define NV50_TIC_4_WIDTH__MASK 0xffffffff
-#define NV50_TIC_4_WIDTH__SHIFT 0
-
-#define NV50_TIC_5 0x00000014
-#define NV50_TIC_5_LAST_LEVEL__MASK 0xf0000000
-#define NV50_TIC_5_LAST_LEVEL__SHIFT 28
-#define NV50_TIC_5_DEPTH__MASK 0x0fff0000
-#define NV50_TIC_5_DEPTH__SHIFT 16
-#define NV50_TIC_5_HEIGHT__MASK 0x0000ffff
-#define NV50_TIC_5_HEIGHT__SHIFT 0
-
-#define NV50_TIC_7 0x0000001c
-#define NV50_TIC_7_BASE_LEVEL__MASK 0x0000000f
-#define NV50_TIC_7_BASE_LEVEL__SHIFT 0
-#define NV50_TIC_7_MAX_LEVEL__MASK 0x000000f0
-#define NV50_TIC_7_MAX_LEVEL__SHIFT 4
-#define NV50_TIC_7_MS_MODE__MASK 0x0000f000
-#define NV50_TIC_7_MS_MODE__SHIFT 12
-#define NV50_TIC_7_MS_MODE_MS1 0x00000000
-#define NV50_TIC_7_MS_MODE_MS2 0x00001000
-#define NV50_TIC_7_MS_MODE_MS4 0x00002000
-#define NV50_TIC_7_MS_MODE_MS8 0x00003000
-#define NVA3_TIC_7_MS_MODE_MS8_ALT 0x00004000
-#define NVA3_TIC_7_MS_MODE_MS2_ALT 0x00005000
-#define NVC0_TIC_7_MS_MODE_UNK6 0x00006000
-#define NV50_TIC_7_MS_MODE_MS4_CS4 0x00008000
-#define NV50_TIC_7_MS_MODE_MS4_CS12 0x00009000
-#define NV50_TIC_7_MS_MODE_MS8_CS8 0x0000a000
-#define NVC0_TIC_7_MS_MODE_MS8_CS24 0x0000b000
-
-#define NV50_TSC__SIZE 0x00000020
-#define NV50_TSC_0 0x00000000
-#define NV50_TSC_0_WRAPS__MASK 0x00000007
-#define NV50_TSC_0_WRAPS__SHIFT 0
-#define NV50_TSC_0_WRAPT__MASK 0x00000038
-#define NV50_TSC_0_WRAPT__SHIFT 3
-#define NV50_TSC_0_WRAPR__MASK 0x000001c0
-#define NV50_TSC_0_WRAPR__SHIFT 6
-#define NV50_TSC_0_SHADOW_COMPARE_ENABLE 0x00000200
-#define NV50_TSC_0_SHADOW_COMPARE_FUNC__MASK 0x00001c00
-#define NV50_TSC_0_SHADOW_COMPARE_FUNC__SHIFT 10
-#define NV50_TSC_0_SRGB_CONVERSION_ALLOWED 0x00002000
-#define NV50_TSC_0_BOX_S__MASK 0x0001c000
-#define NV50_TSC_0_BOX_S__SHIFT 14
-#define NV50_TSC_0_BOX_T__MASK 0x000e0000
-#define NV50_TSC_0_BOX_T__SHIFT 17
-#define NV50_TSC_0_ANISOTROPY_MASK__MASK 0x00700000
-#define NV50_TSC_0_ANISOTROPY_MASK__SHIFT 20
-
-#define NV50_TSC_1 0x00000004
-#define NV50_TSC_1_UNKN_ANISO_15 0x10000000
-#define NV50_TSC_1_UNKN_ANISO_35 0x18000000
-#define NV50_TSC_1_MAGF__MASK 0x00000003
-#define NV50_TSC_1_MAGF__SHIFT 0
-#define NV50_TSC_1_MAGF_NEAREST 0x00000001
-#define NV50_TSC_1_MAGF_LINEAR 0x00000002
-#define NV50_TSC_1_MINF__MASK 0x00000030
-#define NV50_TSC_1_MINF__SHIFT 4
-#define NV50_TSC_1_MINF_NEAREST 0x00000010
-#define NV50_TSC_1_MINF_LINEAR 0x00000020
-#define NV50_TSC_1_MIPF__MASK 0x000000c0
-#define NV50_TSC_1_MIPF__SHIFT 6
-#define NV50_TSC_1_MIPF_NONE 0x00000040
-#define NV50_TSC_1_MIPF_NEAREST 0x00000080
-#define NV50_TSC_1_MIPF_LINEAR 0x000000c0
-#define NVE4_TSC_1_CUBE_SEAMLESS 0x00000200
-#define NV50_TSC_1_LOD_BIAS__MASK 0x01fff000
-#define NV50_TSC_1_LOD_BIAS__SHIFT 12
-#define NVE4_TSC_1_FORCE_NONNORMALIZED_COORDS 0x02000000
-
-#define NV50_TSC_2 0x00000008
-#define NV50_TSC_2_MIN_LOD__MASK 0x00000fff
-#define NV50_TSC_2_MIN_LOD__SHIFT 0
-#define NV50_TSC_2_MAX_LOD__MASK 0x00fff000
-#define NV50_TSC_2_MAX_LOD__SHIFT 12
-#define NV50_TSC_2_BORDER_COLOR_SRGB_RED__MASK 0xff000000
-#define NV50_TSC_2_BORDER_COLOR_SRGB_RED__SHIFT 24
-
-#define NV50_TSC_3 0x0000000c
-#define NV50_TSC_3_BORDER_COLOR_SRGB_GREEN__MASK 0x000ff000
-#define NV50_TSC_3_BORDER_COLOR_SRGB_GREEN__SHIFT 12
-#define NV50_TSC_3_BORDER_COLOR_SRGB_BLUE__MASK 0x0ff00000
-#define NV50_TSC_3_BORDER_COLOR_SRGB_BLUE__SHIFT 20
-
-#define NV50_TSC_4 0x00000010
-#define NV50_TSC_4_BORDER_COLOR_RED__MASK 0xffffffff
-#define NV50_TSC_4_BORDER_COLOR_RED__SHIFT 0
-
-#define NV50_TSC_5 0x00000014
-#define NV50_TSC_5_BORDER_COLOR_GREEN__MASK 0xffffffff
-#define NV50_TSC_5_BORDER_COLOR_GREEN__SHIFT 0
-
-#define NV50_TSC_6 0x00000018
-#define NV50_TSC_6_BORDER_COLOR_BLUE__MASK 0xffffffff
-#define NV50_TSC_6_BORDER_COLOR_BLUE__SHIFT 0
-
-#define NV50_TSC_7 0x0000001c
-#define NV50_TSC_7_BORDER_COLOR_ALPHA__MASK 0xffffffff
-#define NV50_TSC_7_BORDER_COLOR_ALPHA__SHIFT 0
-
-
-#endif /* NV50_TEXTURE_XML */
--
2.7.0
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Nouveau@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 21/23] nv50-: split tic format specification
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (18 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 20/23] nv50-: remove nv50_texture.xml.h Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 22/23] nvc0: import maxwell texture header definitions from rnndb Ben Skeggs
2016-02-15 5:38 ` [PATCH 23/23] nvc0: implement support for maxwell texture headers Ben Skeggs
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
We previously stored texture format information as it would appear in
the TIC.
We're about to support the new TIC layout that appeared with Maxwell,
so it makes more sense to store the data in a split-out format.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 21 ++++++------
src/gallium/drivers/nouveau/nv50/nv50_screen.h | 12 ++++++-
src/gallium/drivers/nouveau/nv50/nv50_tex.c | 43 ++++++++++++-------------
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 12 ++++++-
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 43 ++++++++++++-------------
5 files changed, 73 insertions(+), 58 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index c91d29b..717067c 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -67,16 +67,17 @@
#define SF_C(sz) GF100_TIC_0_COMPONENTS_SIZES_##sz
#define SF(c, pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
[PIPE_FORMAT_##pf] = { \
- sf, \
- (G80_TIC_SOURCE_##r << G80_TIC_0_X_SOURCE__SHIFT) | \
- (G80_TIC_SOURCE_##g << G80_TIC_0_Y_SOURCE__SHIFT) | \
- (G80_TIC_SOURCE_##b << G80_TIC_0_Z_SOURCE__SHIFT) | \
- (G80_TIC_SOURCE_##a << G80_TIC_0_W_SOURCE__SHIFT) | \
- (G80_TIC_TYPE_##t0 << G80_TIC_0_R_DATA_TYPE__SHIFT) | \
- (G80_TIC_TYPE_##t1 << G80_TIC_0_G_DATA_TYPE__SHIFT) | \
- (G80_TIC_TYPE_##t2 << G80_TIC_0_B_DATA_TYPE__SHIFT) | \
- (G80_TIC_TYPE_##t3 << G80_TIC_0_A_DATA_TYPE__SHIFT) | \
- SF_##c(sz), U_##u \
+ sf, { \
+ SF_##c(sz), \
+ G80_TIC_TYPE_##t0, \
+ G80_TIC_TYPE_##t1, \
+ G80_TIC_TYPE_##t2, \
+ G80_TIC_TYPE_##t3, \
+ G80_TIC_SOURCE_##r, \
+ G80_TIC_SOURCE_##g, \
+ G80_TIC_SOURCE_##b, \
+ G80_TIC_SOURCE_##a, \
+ }, U_##u \
}
#define C4(c, p, n, r, g, b, a, t, s, u) \
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index a117237..f8f5d16 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -156,7 +156,17 @@ nv50_resource_validate(struct nv04_resource *res, uint32_t flags)
struct nv50_format {
uint32_t rt;
- uint32_t tic;
+ struct {
+ unsigned format:6;
+ unsigned type_r:3;
+ unsigned type_g:3;
+ unsigned type_b:3;
+ unsigned type_a:3;
+ unsigned src_x:3;
+ unsigned src_y:3;
+ unsigned src_z:3;
+ unsigned src_w:3;
+ } tic;
uint32_t usage;
};
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_tex.c b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
index 7c96677..475e277 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_tex.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_tex.c
@@ -27,22 +27,14 @@
#include "util/u_format.h"
-#define G80_TIC_0_SWIZZLE__MASK \
- (G80_TIC_0_W_SOURCE__MASK | G80_TIC_0_Z_SOURCE__MASK | \
- G80_TIC_0_Y_SOURCE__MASK | G80_TIC_0_X_SOURCE__MASK)
-
static inline uint32_t
-nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
+nv50_tic_swizzle(const struct nv50_format *fmt, unsigned swz, bool tex_int)
{
switch (swz) {
- case PIPE_SWIZZLE_RED:
- return (tc & G80_TIC_0_X_SOURCE__MASK) >> G80_TIC_0_X_SOURCE__SHIFT;
- case PIPE_SWIZZLE_GREEN:
- return (tc & G80_TIC_0_Y_SOURCE__MASK) >> G80_TIC_0_Y_SOURCE__SHIFT;
- case PIPE_SWIZZLE_BLUE:
- return (tc & G80_TIC_0_Z_SOURCE__MASK) >> G80_TIC_0_Z_SOURCE__SHIFT;
- case PIPE_SWIZZLE_ALPHA:
- return (tc & G80_TIC_0_W_SOURCE__MASK) >> G80_TIC_0_W_SOURCE__SHIFT;
+ case PIPE_SWIZZLE_RED : return fmt->tic.src_x;
+ case PIPE_SWIZZLE_GREEN: return fmt->tic.src_y;
+ case PIPE_SWIZZLE_BLUE : return fmt->tic.src_z;
+ case PIPE_SWIZZLE_ALPHA: return fmt->tic.src_w;
case PIPE_SWIZZLE_ONE:
return tex_int ? G80_TIC_SOURCE_ONE_INT : G80_TIC_SOURCE_ONE_FLOAT;
case PIPE_SWIZZLE_ZERO:
@@ -73,6 +65,7 @@ nv50_create_texture_view(struct pipe_context *pipe,
{
const uint32_t class_3d = nouveau_context(pipe)->screen->class_3d;
const struct util_format_description *desc;
+ const struct nv50_format *fmt;
uint64_t addr;
uint32_t *tic;
uint32_t swz[4];
@@ -100,19 +93,23 @@ nv50_create_texture_view(struct pipe_context *pipe,
/* TIC[0] */
- tic[0] = nv50_format_table[view->pipe.format].tic;
+ fmt = &nv50_format_table[view->pipe.format];
tex_int = util_format_is_pure_integer(view->pipe.format);
- swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
- swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
- swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
- swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
- tic[0] = (tic[0] & ~G80_TIC_0_SWIZZLE__MASK) |
- (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
- (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
- (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
- (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
+ swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
+ swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
+ swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
+ swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
+ tic[0] = (fmt->tic.format << G80_TIC_0_COMPONENTS_SIZES__SHIFT) |
+ (fmt->tic.type_r << G80_TIC_0_R_DATA_TYPE__SHIFT) |
+ (fmt->tic.type_g << G80_TIC_0_G_DATA_TYPE__SHIFT) |
+ (fmt->tic.type_b << G80_TIC_0_B_DATA_TYPE__SHIFT) |
+ (fmt->tic.type_a << G80_TIC_0_A_DATA_TYPE__SHIFT) |
+ (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
+ (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
+ (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
+ (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
addr = mt->base.address;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index e2b617f..40c9c7a 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -164,7 +164,17 @@ nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
struct nvc0_format {
uint32_t rt;
- uint32_t tic;
+ struct {
+ unsigned format:7;
+ unsigned type_r:3;
+ unsigned type_g:3;
+ unsigned type_b:3;
+ unsigned type_a:3;
+ unsigned src_x:3;
+ unsigned src_y:3;
+ unsigned src_z:3;
+ unsigned src_w:3;
+ } tic;
uint32_t usage;
};
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index ac74dc3..ae4d53c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -30,22 +30,14 @@
#define NVE4_TIC_ENTRY_INVALID 0x000fffff
#define NVE4_TSC_ENTRY_INVALID 0xfff00000
-#define G80_TIC_0_SWIZZLE__MASK \
- (G80_TIC_0_W_SOURCE__MASK | G80_TIC_0_Z_SOURCE__MASK | \
- G80_TIC_0_Y_SOURCE__MASK | G80_TIC_0_X_SOURCE__MASK)
-
static inline uint32_t
-nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
+nv50_tic_swizzle(const struct nvc0_format *fmt, unsigned swz, bool tex_int)
{
switch (swz) {
- case PIPE_SWIZZLE_RED:
- return (tc & G80_TIC_0_X_SOURCE__MASK) >> G80_TIC_0_X_SOURCE__SHIFT;
- case PIPE_SWIZZLE_GREEN:
- return (tc & G80_TIC_0_Y_SOURCE__MASK) >> G80_TIC_0_Y_SOURCE__SHIFT;
- case PIPE_SWIZZLE_BLUE:
- return (tc & G80_TIC_0_Z_SOURCE__MASK) >> G80_TIC_0_Z_SOURCE__SHIFT;
- case PIPE_SWIZZLE_ALPHA:
- return (tc & G80_TIC_0_W_SOURCE__MASK) >> G80_TIC_0_W_SOURCE__SHIFT;
+ case PIPE_SWIZZLE_RED : return fmt->tic.src_x;
+ case PIPE_SWIZZLE_GREEN: return fmt->tic.src_y;
+ case PIPE_SWIZZLE_BLUE : return fmt->tic.src_z;
+ case PIPE_SWIZZLE_ALPHA: return fmt->tic.src_w;
case PIPE_SWIZZLE_ONE:
return tex_int ? G80_TIC_SOURCE_ONE_INT : G80_TIC_SOURCE_ONE_FLOAT;
case PIPE_SWIZZLE_ZERO:
@@ -75,6 +67,7 @@ nvc0_create_texture_view(struct pipe_context *pipe,
enum pipe_texture_target target)
{
const struct util_format_description *desc;
+ const struct nvc0_format *fmt;
uint64_t address;
uint32_t *tic;
uint32_t swz[4];
@@ -102,19 +95,23 @@ nvc0_create_texture_view(struct pipe_context *pipe,
desc = util_format_description(view->pipe.format);
- tic[0] = nvc0_format_table[view->pipe.format].tic;
+ fmt = &nvc0_format_table[view->pipe.format];
tex_int = util_format_is_pure_integer(view->pipe.format);
- swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
- swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
- swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
- swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
- tic[0] = (tic[0] & ~G80_TIC_0_SWIZZLE__MASK) |
- (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
- (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
- (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
- (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
+ swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
+ swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
+ swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
+ swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
+ tic[0] = (fmt->tic.format << G80_TIC_0_COMPONENTS_SIZES__SHIFT) |
+ (fmt->tic.type_r << G80_TIC_0_R_DATA_TYPE__SHIFT) |
+ (fmt->tic.type_g << G80_TIC_0_G_DATA_TYPE__SHIFT) |
+ (fmt->tic.type_b << G80_TIC_0_B_DATA_TYPE__SHIFT) |
+ (fmt->tic.type_a << G80_TIC_0_A_DATA_TYPE__SHIFT) |
+ (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
+ (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
+ (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
+ (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
address = mt->base.address;
--
2.7.0
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 22/23] nvc0: import maxwell texture header definitions from rnndb
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (19 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 21/23] nv50-: split tic format specification Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 23/23] nvc0: implement support for maxwell texture headers Ben Skeggs
21 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
.../drivers/nouveau/nvc0/gm107_texture.xml.h | 365 +++++++++++++++++++++
1 file changed, 365 insertions(+)
create mode 100644 src/gallium/drivers/nouveau/nvc0/gm107_texture.xml.h
diff --git a/src/gallium/drivers/nouveau/nvc0/gm107_texture.xml.h b/src/gallium/drivers/nouveau/nvc0/gm107_texture.xml.h
new file mode 100644
index 0000000..a4bc380
--- /dev/null
+++ b/src/gallium/drivers/nouveau/nvc0/gm107_texture.xml.h
@@ -0,0 +1,365 @@
+#ifndef GM107_TEXTURE_XML
+#define GM107_TEXTURE_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://github.com/envytools/envytools/
+git clone https://github.com/envytools/envytools.git
+
+The rules-ng-ng source files this header was generated from are:
+- /home/skeggsb/git/envytools/rnndb/../rnndb/graph/gm107_texture.xml ( 22057 bytes, from 2016-02-12 03:01:43)
+- /home/skeggsb/git/envytools/rnndb/copyright.xml ( 6456 bytes, from 2015-09-10 02:57:40)
+- /home/skeggsb/git/envytools/rnndb/nvchipsets.xml ( 2908 bytes, from 2016-02-04 22:19:11)
+- /home/skeggsb/git/envytools/rnndb/g80_defs.xml ( 21739 bytes, from 2016-02-04 00:29:42)
+
+Copyright (C) 2006-2016 by the following authors:
+- Artur Huillet <arthur.huillet@free.fr> (ahuillet)
+- Ben Skeggs (darktama, darktama_)
+- B. R. <koala_br@users.sourceforge.net> (koala_br)
+- Carlos Martin <carlosmn@users.sf.net> (carlosmn)
+- Christoph Bumiller <e0425955@student.tuwien.ac.at> (calim, chrisbmr)
+- Dawid Gajownik <gajownik@users.sf.net> (gajownik)
+- Dmitry Baryshkov
+- Dmitry Eremin-Solenikov <lumag@users.sf.net> (lumag)
+- EdB <edb_@users.sf.net> (edb_)
+- Erik Waling <erikwailing@users.sf.net> (erikwaling)
+- Francisco Jerez <currojerez@riseup.net> (curro)
+- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
+- jb17bsome <jb17bsome@bellsouth.net> (jb17bsome)
+- Jeremy Kolb <kjeremy@users.sf.net> (kjeremy)
+- Laurent Carlier <lordheavym@gmail.com> (lordheavy)
+- Luca Barbieri <luca@luca-barbieri.com> (lb, lb1)
+- Maarten Maathuis <madman2003@gmail.com> (stillunknown)
+- Marcin Kościelnicki <koriakin@0x04.net> (mwk, koriakin)
+- Mark Carey <mark.carey@gmail.com> (careym)
+- Matthieu Castet <matthieu.castet@parrot.com> (mat-c)
+- nvidiaman <nvidiaman@users.sf.net> (nvidiaman)
+- Patrice Mandin <patmandin@gmail.com> (pmandin, pmdata)
+- Pekka Paalanen <pq@iki.fi> (pq, ppaalanen)
+- Peter Popov <ironpeter@users.sf.net> (ironpeter)
+- Richard Hughes <hughsient@users.sf.net> (hughsient)
+- Rudi Cilibrasi <cilibrar@users.sf.net> (cilibrar)
+- Serge Martin
+- Simon Raffeiner
+- Stephane Loeuillet <leroutier@users.sf.net> (leroutier)
+- Stephane Marchesin <stephane.marchesin@gmail.com> (marcheu)
+- sturmflut <sturmflut@users.sf.net> (sturmflut)
+- Sylvain Munaut <tnt@246tNt.com>
+- Victor Stinner <victor.stinner@haypocalc.com> (haypo)
+- Wladmir van der Laan <laanwj@gmail.com> (miathan6)
+- Younes Manton <younes.m@gmail.com> (ymanton)
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#define GM107_TIC2__SIZE 0x00000020
+#define GM107_TIC2_0 0x00000000
+#define GM107_TIC2_0_COMPONENTS_SIZES__MASK 0x0000007f
+#define GM107_TIC2_0_COMPONENTS_SIZES__SHIFT 0
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32_A32 0x00000001
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32_B32 0x00000002
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16_B16_A16 0x00000003
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_G32 0x00000004
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32_B24G8 0x00000005
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8B8G8R8 0x00000007
+#define GM107_TIC2_0_COMPONENTS_SIZES_A8B8G8R8 0x00000008
+#define GM107_TIC2_0_COMPONENTS_SIZES_A2B10G10R10 0x00000009
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16_G16 0x0000000c
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8R24 0x0000000d
+#define GM107_TIC2_0_COMPONENTS_SIZES_G24R8 0x0000000e
+#define GM107_TIC2_0_COMPONENTS_SIZES_R32 0x0000000f
+#define GM107_TIC2_0_COMPONENTS_SIZES_A4B4G4R4 0x00000012
+#define GM107_TIC2_0_COMPONENTS_SIZES_A5B5G5R1 0x00000013
+#define GM107_TIC2_0_COMPONENTS_SIZES_A1B5G5R5 0x00000014
+#define GM107_TIC2_0_COMPONENTS_SIZES_B5G6R5 0x00000015
+#define GM107_TIC2_0_COMPONENTS_SIZES_B6G5R5 0x00000016
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8R8 0x00000018
+#define GM107_TIC2_0_COMPONENTS_SIZES_R16 0x0000001b
+#define GM107_TIC2_0_COMPONENTS_SIZES_Y8_VIDEO 0x0000001c
+#define GM107_TIC2_0_COMPONENTS_SIZES_R8 0x0000001d
+#define GM107_TIC2_0_COMPONENTS_SIZES_G4R4 0x0000001e
+#define GM107_TIC2_0_COMPONENTS_SIZES_R1 0x0000001f
+#define GM107_TIC2_0_COMPONENTS_SIZES_E5B9G9R9_SHAREDEXP 0x00000020
+#define GM107_TIC2_0_COMPONENTS_SIZES_BF10GF11RF11 0x00000021
+#define GM107_TIC2_0_COMPONENTS_SIZES_G8B8G8R8 0x00000022
+#define GM107_TIC2_0_COMPONENTS_SIZES_B8G8R8G8 0x00000023
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXT1 0x00000024
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXT23 0x00000025
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXT45 0x00000026
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXN1 0x00000027
+#define GM107_TIC2_0_COMPONENTS_SIZES_DXN2 0x00000028
+#define GM107_TIC2_0_COMPONENTS_SIZES_BC6H_SF16 0x00000010
+#define GM107_TIC2_0_COMPONENTS_SIZES_BC6H_UF16 0x00000011
+#define GM107_TIC2_0_COMPONENTS_SIZES_BC7U 0x00000017
+#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGB 0x00000006
+#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGB_PTA 0x0000000a
+#define GM107_TIC2_0_COMPONENTS_SIZES_ETC2_RGBA 0x0000000b
+#define GM107_TIC2_0_COMPONENTS_SIZES_EAC 0x00000019
+#define GM107_TIC2_0_COMPONENTS_SIZES_EACX2 0x0000001a
+#define GM107_TIC2_0_COMPONENTS_SIZES_Z24S8 0x00000029
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24 0x0000002a
+#define GM107_TIC2_0_COMPONENTS_SIZES_S8Z24 0x0000002b
+#define GM107_TIC2_0_COMPONENTS_SIZES_X4V4Z24__COV4R4V 0x0000002c
+#define GM107_TIC2_0_COMPONENTS_SIZES_X4V4Z24__COV8R8V 0x0000002d
+#define GM107_TIC2_0_COMPONENTS_SIZES_V8Z24__COV4R12V 0x0000002e
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32 0x0000002f
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X24S8 0x00000030
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV4R4V 0x00000031
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X20V4S8__COV8R8V 0x00000032
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV4R4V 0x00000033
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4X8__COV8R8V 0x00000034
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV4R4V 0x00000035
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X20V4S8__COV8R8V 0x00000036
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV4R12V 0x00000037
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV4R12V 0x00000038
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV4R12V 0x00000039
+#define GM107_TIC2_0_COMPONENTS_SIZES_Z16 0x0000003a
+#define GM107_TIC2_0_COMPONENTS_SIZES_V8Z24__COV8R24V 0x0000003b
+#define GM107_TIC2_0_COMPONENTS_SIZES_X8Z24_X16V8S8__COV8R24V 0x0000003c
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8X8__COV8R24V 0x0000003d
+#define GM107_TIC2_0_COMPONENTS_SIZES_ZF32_X16V8S8__COV8R24V 0x0000003e
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_4X4 0x00000040
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_5X4 0x00000050
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_5X5 0x00000041
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_6X5 0x00000051
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_6X6 0x00000042
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X5 0x00000055
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X6 0x00000052
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_8X8 0x00000044
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X5 0x00000056
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X6 0x00000057
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X8 0x00000053
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_10X10 0x00000045
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_12X10 0x00000054
+#define GM107_TIC2_0_COMPONENTS_SIZES_ASTC_2D_12X12 0x00000046
+#define GM107_TIC2_0_R_DATA_TYPE__MASK 0x00000380
+#define GM107_TIC2_0_R_DATA_TYPE__SHIFT 7
+#define GM107_TIC2_0_G_DATA_TYPE__MASK 0x00001c00
+#define GM107_TIC2_0_G_DATA_TYPE__SHIFT 10
+#define GM107_TIC2_0_B_DATA_TYPE__MASK 0x0000e000
+#define GM107_TIC2_0_B_DATA_TYPE__SHIFT 13
+#define GM107_TIC2_0_A_DATA_TYPE__MASK 0x00070000
+#define GM107_TIC2_0_A_DATA_TYPE__SHIFT 16
+#define GM107_TIC2_0_X_SOURCE__MASK 0x00380000
+#define GM107_TIC2_0_X_SOURCE__SHIFT 19
+#define GM107_TIC2_0_Y_SOURCE__MASK 0x01c00000
+#define GM107_TIC2_0_Y_SOURCE__SHIFT 22
+#define GM107_TIC2_0_Z_SOURCE__MASK 0x0e000000
+#define GM107_TIC2_0_Z_SOURCE__SHIFT 25
+#define GM107_TIC2_0_W_SOURCE__MASK 0x70000000
+#define GM107_TIC2_0_W_SOURCE__SHIFT 28
+#define GM107_TIC2_0_PACK_COMPONENTS 0x80000000
+
+#define GM107_TIC2_1 0x00000004
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_0__MASK 0xffffffff
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_0__SHIFT 0
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__MASK 0xffffffe0
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__SHIFT 5
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_5__SHR 5
+#define GM107_TIC2_1_GOB_DEPTH_OFFSET__MASK 0x00000060
+#define GM107_TIC2_1_GOB_DEPTH_OFFSET__SHIFT 5
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__MASK 0xfffffe00
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__SHIFT 9
+#define GM107_TIC2_1_ADDRESS_BITS_31_TO_9__SHR 9
+
+#define GM107_TIC2_2 0x00000008
+#define GM107_TIC2_2_ADDRESS_BITS_47_TO_32__MASK 0x0000ffff
+#define GM107_TIC2_2_ADDRESS_BITS_47_TO_32__SHIFT 0
+#define GM107_TIC2_2_HEADER_VERSION__MASK 0x00e00000
+#define GM107_TIC2_2_HEADER_VERSION__SHIFT 21
+#define GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER 0x00000000
+#define GM107_TIC2_2_HEADER_VERSION_PITCH_COLORKEY 0x00200000
+#define GM107_TIC2_2_HEADER_VERSION_PITCH 0x00400000
+#define GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR 0x00600000
+#define GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR_COLORKEY 0x00800000
+#define GM107_TIC2_2_RESOURCE_VIEW_COHERENCY_HASH__MASK 0x1e000000
+#define GM107_TIC2_2_RESOURCE_VIEW_COHERENCY_HASH__SHIFT 25
+
+#define GM107_TIC2_3 0x0000000c
+#define GM107_TIC2_3_WIDTH_MINUS_ONE_BITS_31_TO_16__MASK 0x0000ffff
+#define GM107_TIC2_3_WIDTH_MINUS_ONE_BITS_31_TO_16__SHIFT 0
+#define GM107_TIC2_3_PITCH_BITS_20_TO_5__MASK 0x0000ffff
+#define GM107_TIC2_3_PITCH_BITS_20_TO_5__SHIFT 0
+#define GM107_TIC2_3_PITCH_BITS_20_TO_5__SHR 5
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MASK 0x00000007
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__SHIFT 0
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MIN 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH__MAX 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_ONE 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_TWO 0x00000001
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_FOUR 0x00000002
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_EIGHT 0x00000003
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_SIXTEEN 0x00000004
+#define GM107_TIC2_3_GOBS_PER_BLOCK_WIDTH_THIRTYTWO 0x00000005
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT__MASK 0x00000038
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT__SHIFT 3
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_ONE 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_TWO 0x00000008
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_FOUR 0x00000010
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_EIGHT 0x00000018
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_SIXTEEN 0x00000020
+#define GM107_TIC2_3_GOBS_PER_BLOCK_HEIGHT_THIRTYTWO 0x00000028
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH__MASK 0x000001c0
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH__SHIFT 6
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_ONE 0x00000000
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_TWO 0x00000040
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_FOUR 0x00000080
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_EIGHT 0x000000c0
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_SIXTEEN 0x00000100
+#define GM107_TIC2_3_GOBS_PER_BLOCK_DEPTH_THIRTYTWO 0x00000140
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS__MASK 0x00001c00
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS__SHIFT 10
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_ONE 0x00000000
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_TWO 0x00000400
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_FOUR 0x00000800
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_EIGHT 0x00000c00
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_SIXTEEN 0x00001000
+#define GM107_TIC2_3_TILE_WIDTH_IN_GOBS_THIRTYTWO 0x00001400
+#define GM107_TIC2_3_GOB_3D 0x00002000
+#define GM107_TIC2_3_LOD_ANISO_QUALITY_2 0x00010000
+#define GM107_TIC2_3_LOD_ANISO_QUALITY__MASK 0x00020000
+#define GM107_TIC2_3_LOD_ANISO_QUALITY__SHIFT 17
+#define GM107_TIC2_3_LOD_ANISO_QUALITY_LOW 0x00000000
+#define GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH 0x00020000
+#define GM107_TIC2_3_LOD_ISO_QUALITY__MASK 0x00040000
+#define GM107_TIC2_3_LOD_ISO_QUALITY__SHIFT 18
+#define GM107_TIC2_3_LOD_ISO_QUALITY_LOW 0x00000000
+#define GM107_TIC2_3_LOD_ISO_QUALITY_HIGH 0x00040000
+#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER__MASK 0x00180000
+#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER__SHIFT 19
+#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_NONE 0x00000000
+#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_CONST_ONE 0x00080000
+#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_CONST_TWO 0x00100000
+#define GM107_TIC2_3_ANISO_COARSE_SPREAD_MODIFIER_SQRT 0x00180000
+#define GM107_TIC2_3_ANISO_SPREAD_SCALE__MASK 0x03e00000
+#define GM107_TIC2_3_ANISO_SPREAD_SCALE__SHIFT 21
+#define GM107_TIC2_3_USE_HEADER_OPT_CONTROL 0x04000000
+#define GM107_TIC2_3_DEPTH_TEXTURE 0x08000000
+#define GM107_TIC2_3_MAX_MIP_LEVEL__MASK 0xf0000000
+#define GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT 28
+
+#define GM107_TIC2_4 0x00000010
+#define GM107_TIC2_4_WIDTH_MINUS_ONE_BITS_15_TO_0__MASK 0x0000ffff
+#define GM107_TIC2_4_WIDTH_MINUS_ONE_BITS_15_TO_0__SHIFT 0
+#define GM107_TIC2_4_WIDTH_MINUS_ONE__MASK 0x0000ffff
+#define GM107_TIC2_4_WIDTH_MINUS_ONE__SHIFT 0
+#define GM107_TIC2_4_ANISO_SPREAD_MAX_LOG2__MASK 0x00380000
+#define GM107_TIC2_4_ANISO_SPREAD_MAX_LOG2__SHIFT 19
+#define GM107_TIC2_4_SRGB_CONVERSION 0x00400000
+#define GM107_TIC2_4_TEXTURE_TYPE__MASK 0x07800000
+#define GM107_TIC2_4_TEXTURE_TYPE__SHIFT 23
+#define GM107_TIC2_4_TEXTURE_TYPE_ONE_D 0x00000000
+#define GM107_TIC2_4_TEXTURE_TYPE_TWO_D 0x00800000
+#define GM107_TIC2_4_TEXTURE_TYPE_THREE_D 0x01000000
+#define GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP 0x01800000
+#define GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY 0x02000000
+#define GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY 0x02800000
+#define GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER 0x03000000
+#define GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP 0x03800000
+#define GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY 0x04000000
+#define GM107_TIC2_4_SECTOR_PROMOTION__MASK 0x18000000
+#define GM107_TIC2_4_SECTOR_PROMOTION__SHIFT 27
+#define GM107_TIC2_4_SECTOR_PROMOTION_NO_PROMOTION 0x00000000
+#define GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V 0x08000000
+#define GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_H 0x10000000
+#define GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_4 0x18000000
+#define GM107_TIC2_4_BORDER_SIZE__MASK 0xe0000000
+#define GM107_TIC2_4_BORDER_SIZE__SHIFT 29
+#define GM107_TIC2_4_BORDER_SIZE_ONE 0x00000000
+#define GM107_TIC2_4_BORDER_SIZE_TWO 0x20000000
+#define GM107_TIC2_4_BORDER_SIZE_FOUR 0x40000000
+#define GM107_TIC2_4_BORDER_SIZE_EIGHT 0x60000000
+#define GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR 0xe0000000
+
+#define GM107_TIC2_5 0x00000014
+#define GM107_TIC2_5_HEIGHT_MINUS_ONE__MASK 0x0000ffff
+#define GM107_TIC2_5_HEIGHT_MINUS_ONE__SHIFT 0
+#define GM107_TIC2_5_DEPTH_MINUS_ONE__MASK 0x3fff0000
+#define GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT 16
+#define GM107_TIC2_5_NORMALIZED_COORDS 0x80000000
+
+#define GM107_TIC2_6 0x00000018
+#define GM107_TIC2_6_COLOR_KEY_OP 0x00000001
+#define GM107_TIC2_6_TRILIN_OPT__MASK 0x0000003e
+#define GM107_TIC2_6_TRILIN_OPT__SHIFT 1
+#define GM107_TIC2_6_MIP_LOD_BIAS__MASK 0x0007ffc0
+#define GM107_TIC2_6_MIP_LOD_BIAS__SHIFT 6
+#define GM107_TIC2_6_MIP_LOD_BIAS__RADIX 0x00000008
+#define GM107_TIC2_6_ANISO_BIAS__MASK 0x00780000
+#define GM107_TIC2_6_ANISO_BIAS__SHIFT 19
+#define GM107_TIC2_6_ANISO_BIAS__RADIX 0x00000004
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC__MASK 0x01800000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC__SHIFT 23
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_HALF 0x00000000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_ONE 0x00800000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO 0x01000000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_MAX 0x01800000
+#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC__MASK 0x06000000
+#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC__SHIFT 25
+#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_HALF 0x00000000
+#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE 0x02000000
+#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_TWO 0x04000000
+#define GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_MAX 0x06000000
+#define GM107_TIC2_6_MAX_ANISOTROPY__MASK 0x38000000
+#define GM107_TIC2_6_MAX_ANISOTROPY__SHIFT 27
+#define GM107_TIC2_6_MAX_ANISOTROPY_1_TO_1 0x00000000
+#define GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1 0x08000000
+#define GM107_TIC2_6_MAX_ANISOTROPY_4_TO_1 0x10000000
+#define GM107_TIC2_6_MAX_ANISOTROPY_6_TO_1 0x18000000
+#define GM107_TIC2_6_MAX_ANISOTROPY_8_TO_1 0x20000000
+#define GM107_TIC2_6_MAX_ANISOTROPY_10_TO_1 0x28000000
+#define GM107_TIC2_6_MAX_ANISOTROPY_12_TO_1 0x30000000
+#define GM107_TIC2_6_MAX_ANISOTROPY_16_TO_1 0x38000000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER__MASK 0xc0000000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER__SHIFT 30
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_NONE 0x00000000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_ONE 0x40000000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO 0x80000000
+#define GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_SQRT 0xc0000000
+
+#define GM107_TIC2_7 0x0000001c
+#define GM107_TIC2_7_COLOR_KEY_VALUE__MASK 0xffffffff
+#define GM107_TIC2_7_COLOR_KEY_VALUE__SHIFT 0
+#define GM107_TIC2_7_RES_VIEW_MIN_MIP_LEVEL__MASK 0x0000000f
+#define GM107_TIC2_7_RES_VIEW_MIN_MIP_LEVEL__SHIFT 0
+#define GM107_TIC2_7_RES_VIEW_MAX_MIP_LEVEL__MASK 0x000000f0
+#define GM107_TIC2_7_RES_VIEW_MAX_MIP_LEVEL__SHIFT 4
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT__MASK 0x00000f00
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT 8
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_1X1 0x00000000
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X1 0x00000100
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X2 0x00000200
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2 0x00000300
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2_D3D 0x00000400
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X1_D3D 0x00000500
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X4 0x00000600
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X2_VC_4 0x00000800
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_2X2_VC_12 0x00000900
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2_VC_8 0x00000a00
+#define GM107_TIC2_7_MULTI_SAMPLE_COUNT_4X2_VC_24 0x00000b00
+#define GM107_TIC2_7_MIN_LOD_CLAMP__MASK 0x00fff000
+#define GM107_TIC2_7_MIN_LOD_CLAMP__SHIFT 12
+#define GM107_TIC2_7_MIN_LOD_CLAMP__RADIX 0x00000008
+
+
+#endif /* GM107_TEXTURE_XML */
--
2.7.0
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Nouveau@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH 23/23] nvc0: implement support for maxwell texture headers
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
` (20 preceding siblings ...)
2016-02-15 5:38 ` [PATCH 22/23] nvc0: import maxwell texture header definitions from rnndb Ben Skeggs
@ 2016-02-15 5:38 ` Ben Skeggs
[not found] ` <1455514736-8909-23-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
21 siblings, 1 reply; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:38 UTC (permalink / raw)
To: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Ben Skeggs
From: Ben Skeggs <bskeggs@redhat.com>
Adds support for the new TIC layout that's present on Maxwell GPUs,
heavily based on the code for the existing layout.
This code is required for GM20x support. While GM10x supports the older
layout still, this commit switches it to use the updated version instead.
Piglit testing shows zero regressions on GM107.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 8 +
src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 +
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 201 ++++++++++++++++++++++++-
3 files changed, 204 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index d435bec..820e38d 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
PUSH_DATAh(push, screen->txc->offset);
PUSH_DATA (push, screen->txc->offset);
PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
+ if (screen->eng3d->oclass >= GM107_3D_CLASS) {
+ screen->tic.maxwell = true;
+ if (screen->eng3d->oclass == GM107_3D_CLASS) {
+ screen->tic.maxwell =
+ debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
+ IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
+ }
+ }
BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset + 65536);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 40c9c7a..f34fabd 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -83,6 +83,7 @@ struct nvc0_screen {
void **entries;
int next;
uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
+ bool maxwell;
} tic;
struct {
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index ae4d53c..c0da959 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -22,6 +22,7 @@
#include "nvc0/nvc0_context.h"
#include "nvc0/nvc0_resource.h"
+#include "nvc0/gm107_texture.xml.h"
#include "nv50/g80_texture.xml.h"
#include "nv50/g80_defs.xml.h"
@@ -59,12 +60,188 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
return nvc0_create_texture_view(pipe, res, templ, flags, templ->target);
}
-struct pipe_sampler_view *
-nvc0_create_texture_view(struct pipe_context *pipe,
- struct pipe_resource *texture,
- const struct pipe_sampler_view *templ,
- uint32_t flags,
- enum pipe_texture_target target)
+static struct pipe_sampler_view *
+gm107_create_texture_view(struct pipe_context *pipe,
+ struct pipe_resource *texture,
+ const struct pipe_sampler_view *templ,
+ uint32_t flags,
+ enum pipe_texture_target target)
+{
+ const struct util_format_description *desc;
+ const struct nvc0_format *fmt;
+ uint64_t address;
+ uint32_t *tic;
+ uint32_t swz[4];
+ uint32_t width, height;
+ uint32_t depth;
+ struct nv50_tic_entry *view;
+ struct nv50_miptree *mt;
+ bool tex_int;
+
+ view = MALLOC_STRUCT(nv50_tic_entry);
+ if (!view)
+ return NULL;
+ mt = nv50_miptree(texture);
+
+ view->pipe = *templ;
+ view->pipe.reference.count = 1;
+ view->pipe.texture = NULL;
+ view->pipe.context = pipe;
+
+ view->id = -1;
+
+ pipe_resource_reference(&view->pipe.texture, texture);
+
+ tic = &view->tic[0];
+
+ desc = util_format_description(view->pipe.format);
+ tex_int = util_format_is_pure_integer(view->pipe.format);
+
+ fmt = &nvc0_format_table[view->pipe.format];
+ swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
+ swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
+ swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
+ swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
+
+ tic[0] = fmt->tic.format << GM107_TIC2_0_COMPONENTS_SIZES__SHIFT;
+ tic[0] |= fmt->tic.type_r << GM107_TIC2_0_R_DATA_TYPE__SHIFT;
+ tic[0] |= fmt->tic.type_g << GM107_TIC2_0_G_DATA_TYPE__SHIFT;
+ tic[0] |= fmt->tic.type_b << GM107_TIC2_0_B_DATA_TYPE__SHIFT;
+ tic[0] |= fmt->tic.type_a << GM107_TIC2_0_A_DATA_TYPE__SHIFT;
+ tic[0] |= swz[0] << GM107_TIC2_0_X_SOURCE__SHIFT;
+ tic[0] |= swz[1] << GM107_TIC2_0_Y_SOURCE__SHIFT;
+ tic[0] |= swz[2] << GM107_TIC2_0_Z_SOURCE__SHIFT;
+ tic[0] |= swz[3] << GM107_TIC2_0_W_SOURCE__SHIFT;
+ // PACK_COMPONENTS?
+
+ address = mt->base.address;
+
+ tic[3] = GM107_TIC2_3_LOD_ANISO_QUALITY_2;
+ tic[4] = GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V;
+ tic[4] |= GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR;
+
+ if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
+ tic[4] |= GM107_TIC2_4_SRGB_CONVERSION;
+
+ if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
+ tic[5] = GM107_TIC2_5_NORMALIZED_COORDS;
+ else
+ tic[5] = 0;
+
+ /* check for linear storage type */
+ if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
+ if (texture->target == PIPE_BUFFER) {
+ assert(!(tic[5] & GM107_TIC2_5_NORMALIZED_COORDS));
+ width = view->pipe.u.buf.last_element - view->pipe.u.buf.first_element;
+ address +=
+ view->pipe.u.buf.first_element * desc->block.bits / 8;
+ tic[2] = GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER;
+ tic[3] |= width >> 16;
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER;
+ tic[4] |= width & 0xffff;
+ } else {
+ assert(!(mt->level[0].pitch & 0x1f));
+ /* must be 2D texture without mip maps */
+ tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH;
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
+ tic[3] |= mt->level[0].pitch >> 5;
+ tic[4] |= mt->base.base.width0 - 1;
+ tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
+ tic[5] |= mt->base.base.height0 - 1;
+ }
+ tic[1] = address;
+ tic[2] |= address >> 32;
+ tic[6] = 0;
+ tic[7] = 0;
+ return &view->pipe;
+ }
+
+ tic[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR;
+ tic[3] |=
+ ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) |
+ ((mt->level[0].tile_mode & 0xf00) >> 8 << 6);
+
+ depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
+
+ if (mt->base.base.array_size > 1) {
+ /* there doesn't seem to be a base layer field in TIC */
+ address += view->pipe.u.tex.first_layer * mt->layer_stride;
+ depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
+ }
+ tic[1] = address;
+ tic[2] |= address >> 32;
+
+ switch (target) {
+ case PIPE_TEXTURE_1D:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D;
+ break;
+ case PIPE_TEXTURE_2D:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
+ break;
+ case PIPE_TEXTURE_RECT:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
+ break;
+ case PIPE_TEXTURE_3D:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
+ break;
+ case PIPE_TEXTURE_CUBE:
+ depth /= 6;
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
+ break;
+ case PIPE_TEXTURE_1D_ARRAY:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
+ break;
+ case PIPE_TEXTURE_2D_ARRAY:
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
+ break;
+ case PIPE_TEXTURE_CUBE_ARRAY:
+ depth /= 6;
+ tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY;
+ break;
+ default:
+ unreachable("unexpected/invalid texture target");
+ }
+
+ tic[3] |= (flags & NV50_TEXVIEW_FILTER_MSAA8) ?
+ GM107_TIC2_3_USE_HEADER_OPT_CONTROL :
+ GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH |
+ GM107_TIC2_3_LOD_ISO_QUALITY_HIGH;
+
+ if (flags & NV50_TEXVIEW_ACCESS_RESOLVE) {
+ width = mt->base.base.width0 << mt->ms_x;
+ height = mt->base.base.height0 << mt->ms_y;
+ } else {
+ width = mt->base.base.width0;
+ height = mt->base.base.height0;
+ }
+
+ tic[4] |= width - 1;
+
+ tic[5] |= (height - 1) & 0xffff;
+ tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
+ tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
+
+ /* sampling points: (?) */
+ if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
+ tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
+ tic[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1;
+ } else {
+ tic[6] | GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO;
+ tic[6] |= GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE;
+ }
+
+ tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
+ tic[7] |= mt->ms_mode << GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT;
+
+ return &view->pipe;
+}
+
+static struct pipe_sampler_view *
+gf100_create_texture_view(struct pipe_context *pipe,
+ struct pipe_resource *texture,
+ const struct pipe_sampler_view *templ,
+ uint32_t flags,
+ enum pipe_texture_target target)
{
const struct util_format_description *desc;
const struct nvc0_format *fmt;
@@ -221,6 +398,18 @@ nvc0_create_texture_view(struct pipe_context *pipe,
return &view->pipe;
}
+struct pipe_sampler_view *
+nvc0_create_texture_view(struct pipe_context *pipe,
+ struct pipe_resource *texture,
+ const struct pipe_sampler_view *templ,
+ uint32_t flags,
+ enum pipe_texture_target target)
+{
+ if (nvc0_context(pipe)->screen->tic.maxwell)
+ return gm107_create_texture_view(pipe, texture, templ, flags, target);
+ return gf100_create_texture_view(pipe, texture, templ, flags, target);
+}
+
static void
nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
struct nv04_resource *res)
--
2.7.0
_______________________________________________
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Nouveau@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH 09/23] nv50-: separate vertex formats from surface format descriptions
[not found] ` <1455514736-8909-9-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-02-15 5:43 ` Ilia Mirkin
[not found] ` <CAKb7Uvg=rL_GLTRU+u_rvWZOmE8C1HiuonmgdvEKxV9ZzSyQ6A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 29+ messages in thread
From: Ilia Mirkin @ 2016-02-15 5:43 UTC (permalink / raw)
To: Ben Skeggs; +Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ben Skeggs
[-- Attachment #1.1: Type: text/plain, Size: 23528 bytes --]
Why not fix the new names instead to be like the old names? Seems like that
would be way simpler...
On Feb 15, 2016 12:38 AM, "Ben Skeggs" <skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> From: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>
> We've previously had identical naming between vertex and texture
> formats, so it mostly made sense to define these together.
>
> However, upcoming patches are going to transition the driver over to
> using updated texture header definitions using NVIDIA's naming, and this
> will no longer be the case.
>
> Signed-off-by: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> src/gallium/drivers/nouveau/nv50/nv50_formats.c | 249
> ++++++++++++++++++------
> src/gallium/drivers/nouveau/nv50/nv50_screen.c | 3 +-
> src/gallium/drivers/nouveau/nv50/nv50_screen.h | 5 +
> src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 4 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 5 +
> src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 4 +-
> 7 files changed, 206 insertions(+), 67 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> index 49a93bf..a9ddae5 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> @@ -39,10 +39,9 @@
> * C: render target (color), blendable only on nvc0
> * D: scanout/display target, blendable
> * Z: depth/stencil
> - * V: vertex fetch
> * I: image / surface, implies T
> */
> -#define U_V PIPE_BIND_VERTEX_BUFFER
> +#define U_V 0
> #define U_T PIPE_BIND_SAMPLER_VIEW
> #define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE |
> PIPE_BIND_COMPUTE_RESOURCE
> #define U_TR PIPE_BIND_RENDER_TARGET | U_T
> @@ -103,10 +102,7 @@
> (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
> (NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
> (NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
> - NV50_TIC_0_FMT_##sz, \
> - NVXX_3D_VAF_SIZE(sz) | \
> - NVXX_3D_VAF_TYPE(t0) | (br << 31), \
> - U_##u \
> + NV50_TIC_0_FMT_##sz, U_##u \
> }
>
> #define TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
> @@ -120,7 +116,7 @@
> (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) | \
> (NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) | \
> (NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) | \
> - NV50_TIC_0_FMT_##sz, 0, U_##u \
> + NV50_TIC_0_FMT_##sz, U_##u \
> }
>
> #define C4A(p, n, r, g, b, a, t, s, u, br) \
> @@ -308,6 +304,10 @@ const struct nv50_format
> nv50_format_table[PIPE_FORMAT_COUNT] =
> I3B(R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT, 32_32_32_32,
> TR),
> I3B(R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT, 32_32_32_32,
> TR),
>
> + F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
> + I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
> + I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
> +
> F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
> F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
> F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
> @@ -381,64 +381,191 @@ const struct nv50_format
> nv50_format_table[PIPE_FORMAT_COUNT] =
> C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 8_8_8_8,
> T),
> TBLENT_B_(R5SG5SB6U_NORM, 0,
> C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM, 5_5_6, T),
> +};
>
> - /* vertex-only formats: */
> +#define V_TBLENT_A_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u, br) \
> + [PIPE_FORMAT_##pf] = { \
> + NVXX_3D_VAF_SIZE(sz) | NVXX_3D_VAF_TYPE(t0) | (br << 31), \
> + PIPE_BIND_VERTEX_BUFFER \
> + }
>
> - C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 32_32_32_32,
> V, 0),
> - C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED, 32_32_32_32,
> V, 0),
> - F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
> - F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
> - F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
> - I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
> - I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
> - F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
> - F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
> - F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
> - F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
> - F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
> - F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
> -
> - C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 16_16_16_16,
> V, 0),
> - C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED, 16_16_16_16,
> V, 0),
> - F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
> - F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
> - F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
> - I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
> - I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
> - F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
> - F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
> - F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
> - F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
> - F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
> - F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
> -
> - C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V,
> 0),
> - C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V,
> 0),
> - C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2, V,
> 1),
> - C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2, V,
> 1),
> -
> - C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
> - C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
> - F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
> - F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
> - I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
> - I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
> - F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
> - F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
> - F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
> - F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
> - F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
> - F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
> +#define V_TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
> + [PIPE_FORMAT_##pf] = { \
> + 0, \
> + PIPE_BIND_VERTEX_BUFFER \
> + }
> +
> +#define V_C4A(p, n, r, g, b, a, t, s, u, br)
> \
> + V_TBLENT_A_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u,
> br)
> +#define V_C4B(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t, s, u)
> +
> +#define V_ZXB(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n,
> \
> + r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
> +#define V_ZSB(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n,
> \
> + r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
> +#define V_SZB(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n,
> \
> + r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
> +#define V_SXB(p, r, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_NONE,
> \
> + r, r, r, r, UINT, UINT, UINT, UINT, s, u)
> +
> +#define V_F3A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, b, ONE_FLOAT, t, s, u, 0)
> +#define V_I3A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, b, ONE_INT, t, s, u, 0)
> +#define V_F3B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, b, ONE_FLOAT, t, s, u)
> +#define V_I3B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, b, ONE_INT, t, s, u)
> +
> +#define V_F2A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, ZERO, ONE_FLOAT, t, s, u, 0)
> +#define V_I2A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, ZERO, ONE_INT, t, s, u, 0)
> +#define V_F2B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, ZERO, ONE_FLOAT, t, s, u)
> +#define V_I2B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, ZERO, ONE_INT, t, s, u)
> +
> +#define V_F1A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u, 0)
> +#define V_I1A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, ZERO, ZERO, ONE_INT, t, s, u, 0)
> +#define V_F1B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u)
> +#define V_I1B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, ZERO, ZERO, ONE_INT, t, s, u)
> +
> +#define V_A1B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, ZERO, ZERO, ZERO, a, t, s, u)
> +
> +#if NOUVEAU_DRIVER == 0xc0
> +const struct nvc0_vertex_format nvc0_vertex_format[PIPE_FORMAT_COUNT] =
> +#else
> +const struct nv50_vertex_format nv50_vertex_format[PIPE_FORMAT_COUNT] =
> +#endif
> +{
> + V_C4A(B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM, 8_8_8_8,
> TDV, 1),
> + V_C4A(R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM, 8_8_8_8,
> IBV, 0),
> +
> + V_C4A(R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM,
> 10_10_10_2, IBV, 0),
> + V_C4A(B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM,
> 10_10_10_2, TDV, 1),
> + V_C4A(R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM, 10_10_10_2, TV,
> 0),
> + V_C4A(B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM, 10_10_10_2, TV,
> 1),
> + V_C4A(R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT,
> 10_10_10_2, TRV, 0),
> + V_C4A(B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT,
> 10_10_10_2, TV, 0),
> +
> + V_F3A(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT,
> 11_11_10, IBV),
> +
> + V_C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT,
> 32_32_32_32, IBV, 0),
> + V_C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM, 32_32_32_32,
> TV, 0),
> + V_C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM, 32_32_32_32,
> TV, 0),
> + V_C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT,
> 32_32_32_32, IRV, 0),
> + V_C4A(R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT,
> 32_32_32_32, IRV, 0),
> +
> + V_F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
> + V_F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
> + V_F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
> + V_I2A(R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IRV),
> + V_I2A(R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IRV),
> +
> + V_F1A(R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IBV),
> + V_F1A(R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, TV),
> + V_F1A(R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, TV),
> + V_I1A(R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IRV),
> + V_I1A(R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IRV),
> +
> + V_C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT,
> 16_16_16_16, IBV, 0),
> + V_C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM,
> 16_16_16_16, ICV, 0),
> + V_C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM,
> 16_16_16_16, ICV, 0),
> + V_C4A(R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT,
> 16_16_16_16, IRV, 0),
> + V_C4A(R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT,
> 16_16_16_16, IRV, 0),
> +
> + V_F2A(R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IBV),
> + V_F2A(R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, ICV),
> + V_F2A(R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, ICV),
> + V_I2A(R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IRV),
> + V_I2A(R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IRV),
> +
> + V_F1A(R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IBV),
> + V_F1A(R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, ICV),
> + V_F1A(R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, ICV),
> + V_I1A(R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IRV),
> + V_I1A(R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IRV),
> +
> + V_C4A(R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM, 8_8_8_8,
> ICV, 0),
> + V_C4A(R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8, IRV,
> 0),
> + V_C4A(R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8, IRV,
> 0),
> +
> + V_F2A(R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IBV),
> + V_F2A(R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, ICV),
> + V_I2A(R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IRV),
> + V_I2A(R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IRV),
> +
> + V_F1A(R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IBV),
> + V_F1A(R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, ICV),
> + V_I1A(R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IRV),
> + V_I1A(R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IRV),
> +
> + V_C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 32_32_32_32, V, 0),
> + V_C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 32_32_32_32, V, 0),
> + V_F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
> + V_F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
> + V_F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
> + V_I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
> + V_I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
> + V_F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
> + V_F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
> + V_F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
> + V_F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
> + V_F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
> + V_F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
> +
> + V_C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 16_16_16_16, V, 0),
> + V_C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 16_16_16_16, V, 0),
> + V_F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
> + V_F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
> + V_F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
> + V_I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
> + V_I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
> + V_F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
> + V_F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
> + V_F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
> + V_F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
> + V_F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
> + V_F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
> +
> + V_C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2,
> V, 0),
> + V_C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2,
> V, 0),
> + V_C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED, 10_10_10_2,
> V, 1),
> + V_C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 10_10_10_2,
> V, 1),
> +
> + V_C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
> + V_C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
> + V_F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
> + V_F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
> + V_I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
> + V_I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
> + V_F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
> + V_F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
> + V_F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
> + V_F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
> + V_F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
> + V_F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
>
> /* FIXED types: not supported natively, converted on VBO push */
>
> - C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
> - F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> - F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> - F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
> + V_C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
> + V_F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> + V_F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> + V_F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
>
> - C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
> - F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> - F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> - F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
> + V_C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT, 32_32_32_32, V),
> + V_F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> + V_F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> + V_F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
> };
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> index fd7b3d9..057e065 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> @@ -72,7 +72,8 @@ nv50_screen_is_format_supported(struct pipe_screen
> *pscreen,
> PIPE_BIND_TRANSFER_WRITE |
> PIPE_BIND_SHARED);
>
> - return (nv50_format_table[format].usage & bindings) == bindings;
> + return (( nv50_format_table[format].usage |
> + nv50_vertex_format[format].usage) & bindings) == bindings;
> }
>
> static int
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> index 2a4983d..a117237 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> @@ -157,11 +157,16 @@ nv50_resource_validate(struct nv04_resource *res,
> uint32_t flags)
> struct nv50_format {
> uint32_t rt;
> uint32_t tic;
> + uint32_t usage;
> +};
> +
> +struct nv50_vertex_format {
> uint32_t vtx;
> uint32_t usage;
> };
>
> extern const struct nv50_format nv50_format_table[];
> +extern const struct nv50_vertex_format nv50_vertex_format[];
>
> static inline void
> nv50_screen_tic_unlock(struct nv50_screen *screen, struct nv50_tic_entry
> *tic)
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> index 5369d52..028f4c8 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> @@ -76,7 +76,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
> enum pipe_format fmt = ve->src_format;
>
> so->element[i].pipe = elements[i];
> - so->element[i].state = nv50_format_table[fmt].vtx;
> + so->element[i].state = nv50_vertex_format[fmt].vtx;
>
> if (!so->element[i].state) {
> switch (util_format_get_nr_components(fmt)) {
> @@ -89,7 +89,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
> FREE(so);
> return NULL;
> }
> - so->element[i].state = nv50_format_table[fmt].vtx;
> + so->element[i].state = nv50_vertex_format[fmt].vtx;
> so->need_conversion = true;
> pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
> "Converting vertex element %d, no hw
> format %s",
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index 2b12de4..d435bec 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -61,7 +61,8 @@ nvc0_screen_is_format_supported(struct pipe_screen
> *pscreen,
> PIPE_BIND_TRANSFER_WRITE |
> PIPE_BIND_SHARED);
>
> - return (nvc0_format_table[format].usage & bindings) == bindings;
> + return (( nvc0_format_table[format].usage |
> + nvc0_vertex_format[format].usage) & bindings) == bindings;
> }
>
> static int
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> index 1a56177..e2b617f 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> @@ -165,11 +165,16 @@ nvc0_resource_validate(struct nv04_resource *res,
> uint32_t flags)
> struct nvc0_format {
> uint32_t rt;
> uint32_t tic;
> + uint32_t usage;
> +};
> +
> +struct nvc0_vertex_format {
> uint32_t vtx;
> uint32_t usage;
> };
>
> extern const struct nvc0_format nvc0_format_table[];
> +extern const struct nvc0_vertex_format nvc0_vertex_format[];
>
> static inline void
> nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry
> *tic)
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> index 032b3c1..8239624 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> @@ -80,7 +80,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
> enum pipe_format fmt = ve->src_format;
>
> so->element[i].pipe = elements[i];
> - so->element[i].state = nvc0_format_table[fmt].vtx;
> + so->element[i].state = nvc0_vertex_format[fmt].vtx;
>
> if (!so->element[i].state) {
> switch (util_format_get_nr_components(fmt)) {
> @@ -93,7 +93,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
> FREE(so);
> return NULL;
> }
> - so->element[i].state = nvc0_format_table[fmt].vtx;
> + so->element[i].state = nvc0_vertex_format[fmt].vtx;
> so->need_conversion = true;
> pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
> "Converting vertex element %d, no hw
> format %s",
> --
> 2.7.0
>
> _______________________________________________
> Nouveau mailing list
> Nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/nouveau
>
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_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 09/23] nv50-: separate vertex formats from surface format descriptions
[not found] ` <CAKb7Uvg=rL_GLTRU+u_rvWZOmE8C1HiuonmgdvEKxV9ZzSyQ6A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-02-15 5:49 ` Ben Skeggs
0 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 5:49 UTC (permalink / raw)
To: Ilia Mirkin; +Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ben Skeggs
[-- Attachment #1.1: Type: text/plain, Size: 27158 bytes --]
On 02/15/2016 03:43 PM, Ilia Mirkin wrote:
> Why not fix the new names instead to be like the old names? Seems like
> that would be way simpler...
I initially did just that, then realised that:
- If we ever get official headers for the class, there's zero guarantee
they'll share names even then.
- We actually share very little information when defining the two
formats, so it causes no harm to split them.
Ben.
>
> On Feb 15, 2016 12:38 AM, "Ben Skeggs" <skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> <mailto:skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
>
> From: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org <mailto:bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>>
>
> We've previously had identical naming between vertex and texture
> formats, so it mostly made sense to define these together.
>
> However, upcoming patches are going to transition the driver over to
> using updated texture header definitions using NVIDIA's naming, and this
> will no longer be the case.
>
> Signed-off-by: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org
> <mailto:bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>>
> ---
> src/gallium/drivers/nouveau/nv50/nv50_formats.c | 249
> ++++++++++++++++++------
> src/gallium/drivers/nouveau/nv50/nv50_screen.c | 3 +-
> src/gallium/drivers/nouveau/nv50/nv50_screen.h | 5 +
> src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 4 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 3 +-
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 5 +
> src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c | 4 +-
> 7 files changed, 206 insertions(+), 67 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> index 49a93bf..a9ddae5 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
> @@ -39,10 +39,9 @@
> * C: render target (color), blendable only on nvc0
> * D: scanout/display target, blendable
> * Z: depth/stencil
> - * V: vertex fetch
> * I: image / surface, implies T
> */
> -#define U_V PIPE_BIND_VERTEX_BUFFER
> +#define U_V 0
> #define U_T PIPE_BIND_SAMPLER_VIEW
> #define U_I PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE |
> PIPE_BIND_COMPUTE_RESOURCE
> #define U_TR PIPE_BIND_RENDER_TARGET | U_T
> @@ -103,10 +102,7 @@
> (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) |
> \
> (NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) |
> \
> (NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) |
> \
> - NV50_TIC_0_FMT_##sz,
> \
> - NVXX_3D_VAF_SIZE(sz) |
> \
> - NVXX_3D_VAF_TYPE(t0) | (br << 31),
> \
> - U_##u
> \
> + NV50_TIC_0_FMT_##sz, U_##u
> \
> }
>
> #define TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u)
> \
> @@ -120,7 +116,7 @@
> (NV50_TIC_TYPE_##t1 << NV50_TIC_0_TYPE1__SHIFT) |
> \
> (NV50_TIC_TYPE_##t2 << NV50_TIC_0_TYPE2__SHIFT) |
> \
> (NV50_TIC_TYPE_##t3 << NV50_TIC_0_TYPE3__SHIFT) |
> \
> - NV50_TIC_0_FMT_##sz, 0, U_##u
> \
> + NV50_TIC_0_FMT_##sz, U_##u
> \
> }
>
> #define C4A(p, n, r, g, b, a, t, s, u, br)
> \
> @@ -308,6 +304,10 @@ const struct nv50_format
> nv50_format_table[PIPE_FORMAT_COUNT] =
> I3B(R32G32B32X32_SINT, RGBX32_SINT, C0, C1, C2, xx, SINT,
> 32_32_32_32, TR),
> I3B(R32G32B32X32_UINT, RGBX32_UINT, C0, C1, C2, xx, UINT,
> 32_32_32_32, TR),
>
> + F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
> + I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
> + I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
> +
> F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
> F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
> F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
> @@ -381,64 +381,191 @@ const struct nv50_format
> nv50_format_table[PIPE_FORMAT_COUNT] =
> C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM,
> 8_8_8_8, T),
> TBLENT_B_(R5SG5SB6U_NORM, 0,
> C0, C1, C2, ONE_FLOAT, SNORM, SNORM, UNORM, UNORM,
> 5_5_6, T),
> +};
>
> - /* vertex-only formats: */
> +#define V_TBLENT_A_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u, br)
> \
> + [PIPE_FORMAT_##pf] = {
> \
> + NVXX_3D_VAF_SIZE(sz) | NVXX_3D_VAF_TYPE(t0) | (br << 31),
> \
> + PIPE_BIND_VERTEX_BUFFER
> \
> + }
>
> - C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 32_32_32_32, V, 0),
> - C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 32_32_32_32, V, 0),
> - F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
> - F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
> - F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
> - I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
> - I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
> - F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 32_32_32, V),
> - F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED, 32_32_32, V),
> - F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
> - F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
> - F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
> - F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
> -
> - C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 16_16_16_16, V, 0),
> - C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 16_16_16_16, V, 0),
> - F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
> - F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
> - F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
> - I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
> - I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
> - F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 16_16_16, V),
> - F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED, 16_16_16, V),
> - F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
> - F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
> - F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
> - F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
> -
> - C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 10_10_10_2, V, 0),
> - C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 10_10_10_2, V, 0),
> - C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 10_10_10_2, V, 1),
> - C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 10_10_10_2, V, 1),
> -
> - C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8, V, 0),
> - C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8, V, 0),
> - F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
> - F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
> - I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
> - I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
> - F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
> - F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
> - F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
> - F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
> - F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
> - F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
> +#define V_TBLENT_B_(pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u)
> \
> + [PIPE_FORMAT_##pf] = {
> \
> + 0,
> \
> + PIPE_BIND_VERTEX_BUFFER
> \
> + }
> +
> +#define V_C4A(p, n, r, g, b, a, t, s, u, br)
> \
> + V_TBLENT_A_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t,
> s, u, br)
> +#define V_C4B(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_SURFACE_FORMAT_##n, r, g, b, a, t, t, t, t,
> s, u)
> +
> +#define V_ZXB(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n,
> \
> + r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
> +#define V_ZSB(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n,
> \
> + r, g, b, ONE_FLOAT, t, UINT, UINT, UINT, s, u)
> +#define V_SZB(p, n, r, g, b, a, t, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_##n,
> \
> + r, g, b, ONE_FLOAT, UINT, t, UINT, UINT, s, u)
> +#define V_SXB(p, r, s, u)
> \
> + V_TBLENT_B_(p, NV50_ZETA_FORMAT_NONE,
> \
> + r, r, r, r, UINT, UINT, UINT, UINT, s, u)
> +
> +#define V_F3A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, b, ONE_FLOAT, t, s, u, 0)
> +#define V_I3A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, b, ONE_INT, t, s, u, 0)
> +#define V_F3B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, b, ONE_FLOAT, t, s, u)
> +#define V_I3B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, b, ONE_INT, t, s, u)
> +
> +#define V_F2A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, ZERO, ONE_FLOAT, t, s, u, 0)
> +#define V_I2A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, g, ZERO, ONE_INT, t, s, u, 0)
> +#define V_F2B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, ZERO, ONE_FLOAT, t, s, u)
> +#define V_I2B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, g, ZERO, ONE_INT, t, s, u)
> +
> +#define V_F1A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u, 0)
> +#define V_I1A(p, n, r, g, b, a, t, s, u) \
> + V_C4A(p, n, r, ZERO, ZERO, ONE_INT, t, s, u, 0)
> +#define V_F1B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, ZERO, ZERO, ONE_FLOAT, t, s, u)
> +#define V_I1B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, r, ZERO, ZERO, ONE_INT, t, s, u)
> +
> +#define V_A1B(p, n, r, g, b, a, t, s, u) \
> + V_C4B(p, n, ZERO, ZERO, ZERO, a, t, s, u)
> +
> +#if NOUVEAU_DRIVER == 0xc0
> +const struct nvc0_vertex_format nvc0_vertex_format[PIPE_FORMAT_COUNT] =
> +#else
> +const struct nv50_vertex_format nv50_vertex_format[PIPE_FORMAT_COUNT] =
> +#endif
> +{
> + V_C4A(B8G8R8A8_UNORM, BGRA8_UNORM, C2, C1, C0, C3, UNORM,
> 8_8_8_8, TDV, 1),
> + V_C4A(R8G8B8A8_UNORM, RGBA8_UNORM, C0, C1, C2, C3, UNORM,
> 8_8_8_8, IBV, 0),
> +
> + V_C4A(R10G10B10A2_UNORM, RGB10_A2_UNORM, C0, C1, C2, C3, UNORM,
> 10_10_10_2, IBV, 0),
> + V_C4A(B10G10R10A2_UNORM, BGR10_A2_UNORM, C2, C1, C0, C3, UNORM,
> 10_10_10_2, TDV, 1),
> + V_C4A(R10G10B10A2_SNORM, NONE, C0, C1, C2, C3, SNORM,
> 10_10_10_2, TV, 0),
> + V_C4A(B10G10R10A2_SNORM, NONE, C2, C1, C0, C3, SNORM,
> 10_10_10_2, TV, 1),
> + V_C4A(R10G10B10A2_UINT, RGB10_A2_UINT, C0, C1, C2, C3, UINT,
> 10_10_10_2, TRV, 0),
> + V_C4A(B10G10R10A2_UINT, RGB10_A2_UINT, C2, C1, C0, C3, UINT,
> 10_10_10_2, TV, 0),
> +
> + V_F3A(R11G11B10_FLOAT, R11G11B10_FLOAT, C0, C1, C2, xx, FLOAT,
> 11_11_10, IBV),
> +
> + V_C4A(R32G32B32A32_FLOAT, RGBA32_FLOAT, C0, C1, C2, C3, FLOAT,
> 32_32_32_32, IBV, 0),
> + V_C4A(R32G32B32A32_UNORM, NONE, C0, C1, C2, C3, UNORM,
> 32_32_32_32, TV, 0),
> + V_C4A(R32G32B32A32_SNORM, NONE, C0, C1, C2, C3, SNORM,
> 32_32_32_32, TV, 0),
> + V_C4A(R32G32B32A32_SINT, RGBA32_SINT, C0, C1, C2, C3, SINT,
> 32_32_32_32, IRV, 0),
> + V_C4A(R32G32B32A32_UINT, RGBA32_UINT, C0, C1, C2, C3, UINT,
> 32_32_32_32, IRV, 0),
> +
> + V_F2A(R32G32_FLOAT, RG32_FLOAT, C0, C1, xx, xx, FLOAT, 32_32, IBV),
> + V_F2A(R32G32_UNORM, NONE, C0, C1, xx, xx, UNORM, 32_32, TV),
> + V_F2A(R32G32_SNORM, NONE, C0, C1, xx, xx, SNORM, 32_32, TV),
> + V_I2A(R32G32_SINT, RG32_SINT, C0, C1, xx, xx, SINT, 32_32, IRV),
> + V_I2A(R32G32_UINT, RG32_UINT, C0, C1, xx, xx, UINT, 32_32, IRV),
> +
> + V_F1A(R32_FLOAT, R32_FLOAT, C0, xx, xx, xx, FLOAT, 32, IBV),
> + V_F1A(R32_UNORM, NONE, C0, xx, xx, xx, UNORM, 32, TV),
> + V_F1A(R32_SNORM, NONE, C0, xx, xx, xx, SNORM, 32, TV),
> + V_I1A(R32_SINT, R32_SINT, C0, xx, xx, xx, SINT, 32, IRV),
> + V_I1A(R32_UINT, R32_UINT, C0, xx, xx, xx, UINT, 32, IRV),
> +
> + V_C4A(R16G16B16A16_FLOAT, RGBA16_FLOAT, C0, C1, C2, C3, FLOAT,
> 16_16_16_16, IBV, 0),
> + V_C4A(R16G16B16A16_UNORM, RGBA16_UNORM, C0, C1, C2, C3, UNORM,
> 16_16_16_16, ICV, 0),
> + V_C4A(R16G16B16A16_SNORM, RGBA16_SNORM, C0, C1, C2, C3, SNORM,
> 16_16_16_16, ICV, 0),
> + V_C4A(R16G16B16A16_SINT, RGBA16_SINT, C0, C1, C2, C3, SINT,
> 16_16_16_16, IRV, 0),
> + V_C4A(R16G16B16A16_UINT, RGBA16_UINT, C0, C1, C2, C3, UINT,
> 16_16_16_16, IRV, 0),
> +
> + V_F2A(R16G16_FLOAT, RG16_FLOAT, C0, C1, xx, xx, FLOAT, 16_16, IBV),
> + V_F2A(R16G16_UNORM, RG16_UNORM, C0, C1, xx, xx, UNORM, 16_16, ICV),
> + V_F2A(R16G16_SNORM, RG16_SNORM, C0, C1, xx, xx, SNORM, 16_16, ICV),
> + V_I2A(R16G16_SINT, RG16_SINT, C0, C1, xx, xx, SINT, 16_16, IRV),
> + V_I2A(R16G16_UINT, RG16_UINT, C0, C1, xx, xx, UINT, 16_16, IRV),
> +
> + V_F1A(R16_FLOAT, R16_FLOAT, C0, xx, xx, xx, FLOAT, 16, IBV),
> + V_F1A(R16_UNORM, R16_UNORM, C0, xx, xx, xx, UNORM, 16, ICV),
> + V_F1A(R16_SNORM, R16_SNORM, C0, xx, xx, xx, SNORM, 16, ICV),
> + V_I1A(R16_SINT, R16_SINT, C0, xx, xx, xx, SINT, 16, IRV),
> + V_I1A(R16_UINT, R16_UINT, C0, xx, xx, xx, UINT, 16, IRV),
> +
> + V_C4A(R8G8B8A8_SNORM, RGBA8_SNORM, C0, C1, C2, C3, SNORM,
> 8_8_8_8, ICV, 0),
> + V_C4A(R8G8B8A8_SINT, RGBA8_SINT, C0, C1, C2, C3, SINT, 8_8_8_8,
> IRV, 0),
> + V_C4A(R8G8B8A8_UINT, RGBA8_UINT, C0, C1, C2, C3, UINT, 8_8_8_8,
> IRV, 0),
> +
> + V_F2A(R8G8_UNORM, RG8_UNORM, C0, C1, xx, xx, UNORM, 8_8, IBV),
> + V_F2A(R8G8_SNORM, RG8_SNORM, C0, C1, xx, xx, SNORM, 8_8, ICV),
> + V_I2A(R8G8_SINT, RG8_SINT, C0, C1, xx, xx, SINT, 8_8, IRV),
> + V_I2A(R8G8_UINT, RG8_UINT, C0, C1, xx, xx, UINT, 8_8, IRV),
> +
> + V_F1A(R8_UNORM, R8_UNORM, C0, xx, xx, xx, UNORM, 8, IBV),
> + V_F1A(R8_SNORM, R8_SNORM, C0, xx, xx, xx, SNORM, 8, ICV),
> + V_I1A(R8_SINT, R8_SINT, C0, xx, xx, xx, SINT, 8, IRV),
> + V_I1A(R8_UINT, R8_UINT, C0, xx, xx, xx, UINT, 8, IRV),
> +
> + V_C4A(R32G32B32A32_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 32_32_32_32, V, 0),
> + V_C4A(R32G32B32A32_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 32_32_32_32, V, 0),
> + V_F3A(R32G32B32_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, tV),
> + V_F3A(R32G32B32_UNORM, NONE, C0, C1, C2, xx, UNORM, 32_32_32, V),
> + V_F3A(R32G32B32_SNORM, NONE, C0, C1, C2, xx, SNORM, 32_32_32, V),
> + V_I3A(R32G32B32_SINT, NONE, C0, C1, C2, xx, SINT, 32_32_32, tV),
> + V_I3A(R32G32B32_UINT, NONE, C0, C1, C2, xx, UINT, 32_32_32, tV),
> + V_F3A(R32G32B32_SSCALED, NONE, C0, C1, C2, xx, SSCALED,
> 32_32_32, V),
> + V_F3A(R32G32B32_USCALED, NONE, C0, C1, C2, xx, USCALED,
> 32_32_32, V),
> + V_F2A(R32G32_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 32_32, V),
> + V_F2A(R32G32_USCALED, NONE, C0, C1, xx, xx, USCALED, 32_32, V),
> + V_F1A(R32_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 32, V),
> + V_F1A(R32_USCALED, NONE, C0, xx, xx, xx, USCALED, 32, V),
> +
> + V_C4A(R16G16B16A16_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 16_16_16_16, V, 0),
> + V_C4A(R16G16B16A16_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 16_16_16_16, V, 0),
> + V_F3A(R16G16B16_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 16_16_16, V),
> + V_F3A(R16G16B16_UNORM, NONE, C0, C1, C2, xx, UNORM, 16_16_16, V),
> + V_F3A(R16G16B16_SNORM, NONE, C0, C1, C2, xx, SNORM, 16_16_16, V),
> + V_I3A(R16G16B16_SINT, NONE, C0, C1, C2, xx, SINT, 16_16_16, V),
> + V_I3A(R16G16B16_UINT, NONE, C0, C1, C2, xx, UINT, 16_16_16, V),
> + V_F3A(R16G16B16_SSCALED, NONE, C0, C1, C2, xx, SSCALED,
> 16_16_16, V),
> + V_F3A(R16G16B16_USCALED, NONE, C0, C1, C2, xx, USCALED,
> 16_16_16, V),
> + V_F2A(R16G16_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 16_16, V),
> + V_F2A(R16G16_USCALED, NONE, C0, C1, xx, xx, USCALED, 16_16, V),
> + V_F1A(R16_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 16, V),
> + V_F1A(R16_USCALED, NONE, C0, xx, xx, xx, USCALED, 16, V),
> +
> + V_C4A(R10G10B10A2_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 10_10_10_2, V, 0),
> + V_C4A(R10G10B10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 10_10_10_2, V, 0),
> + V_C4A(B10G10R10A2_USCALED, NONE, C0, C1, C2, C3, USCALED,
> 10_10_10_2, V, 1),
> + V_C4A(B10G10R10A2_SSCALED, NONE, C0, C1, C2, C3, SSCALED,
> 10_10_10_2, V, 1),
> +
> + V_C4A(R8G8B8A8_SSCALED, NONE, C0, C1, C2, C3, SSCALED, 8_8_8_8,
> V, 0),
> + V_C4A(R8G8B8A8_USCALED, NONE, C0, C1, C2, C3, USCALED, 8_8_8_8,
> V, 0),
> + V_F3A(R8G8B8_UNORM, NONE, C0, C1, C2, xx, UNORM, 8_8_8, V),
> + V_F3A(R8G8B8_SNORM, NONE, C0, C1, C2, xx, SNORM, 8_8_8, V),
> + V_I2A(R8G8B8_SINT, NONE, C0, C1, C2, xx, SINT, 8_8_8, V),
> + V_I2A(R8G8B8_UINT, NONE, C0, C1, C2, xx, UINT, 8_8_8, V),
> + V_F3A(R8G8B8_SSCALED, NONE, C0, C1, C2, xx, SSCALED, 8_8_8, V),
> + V_F3A(R8G8B8_USCALED, NONE, C0, C1, C2, xx, USCALED, 8_8_8, V),
> + V_F2A(R8G8_SSCALED, NONE, C0, C1, xx, xx, SSCALED, 8_8, V),
> + V_F2A(R8G8_USCALED, NONE, C0, C1, xx, xx, USCALED, 8_8, V),
> + V_F1A(R8_SSCALED, NONE, C0, xx, xx, xx, SSCALED, 8, V),
> + V_F1A(R8_USCALED, NONE, C0, xx, xx, xx, USCALED, 8, V),
>
> /* FIXED types: not supported natively, converted on VBO push */
>
> - C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT,
> 32_32_32_32, V),
> - F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> - F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> - F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
> + V_C4B(R32G32B32A32_FIXED, NONE, C0, C1, C2, C3, FLOAT,
> 32_32_32_32, V),
> + V_F3B(R32G32B32_FIXED, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> + V_F2B(R32G32_FIXED, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> + V_F1B(R32_FIXED, NONE, C0, xx, xx, xx, FLOAT, 32, V),
>
> - C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT,
> 32_32_32_32, V),
> - F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> - F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> - F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
> + V_C4B(R64G64B64A64_FLOAT, NONE, C0, C1, C2, C3, FLOAT,
> 32_32_32_32, V),
> + V_F3B(R64G64B64_FLOAT, NONE, C0, C1, C2, xx, FLOAT, 32_32_32, V),
> + V_F2B(R64G64_FLOAT, NONE, C0, C1, xx, xx, FLOAT, 32_32, V),
> + V_F1B(R64_FLOAT, NONE, C0, xx, xx, xx, FLOAT, 32, V),
> };
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> index fd7b3d9..057e065 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
> @@ -72,7 +72,8 @@ nv50_screen_is_format_supported(struct pipe_screen
> *pscreen,
> PIPE_BIND_TRANSFER_WRITE |
> PIPE_BIND_SHARED);
>
> - return (nv50_format_table[format].usage & bindings) == bindings;
> + return (( nv50_format_table[format].usage |
> + nv50_vertex_format[format].usage) & bindings) == bindings;
> }
>
> static int
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> index 2a4983d..a117237 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
> @@ -157,11 +157,16 @@ nv50_resource_validate(struct nv04_resource
> *res, uint32_t flags)
> struct nv50_format {
> uint32_t rt;
> uint32_t tic;
> + uint32_t usage;
> +};
> +
> +struct nv50_vertex_format {
> uint32_t vtx;
> uint32_t usage;
> };
>
> extern const struct nv50_format nv50_format_table[];
> +extern const struct nv50_vertex_format nv50_vertex_format[];
>
> static inline void
> nv50_screen_tic_unlock(struct nv50_screen *screen, struct
> nv50_tic_entry *tic)
> diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> index 5369d52..028f4c8 100644
> --- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> +++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
> @@ -76,7 +76,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
> enum pipe_format fmt = ve->src_format;
>
> so->element[i].pipe = elements[i];
> - so->element[i].state = nv50_format_table[fmt].vtx;
> + so->element[i].state = nv50_vertex_format[fmt].vtx;
>
> if (!so->element[i].state) {
> switch (util_format_get_nr_components(fmt)) {
> @@ -89,7 +89,7 @@ nv50_vertex_state_create(struct pipe_context *pipe,
> FREE(so);
> return NULL;
> }
> - so->element[i].state = nv50_format_table[fmt].vtx;
> + so->element[i].state = nv50_vertex_format[fmt].vtx;
> so->need_conversion = true;
> pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
> "Converting vertex element %d, no hw
> format %s",
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index 2b12de4..d435bec 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -61,7 +61,8 @@ nvc0_screen_is_format_supported(struct pipe_screen
> *pscreen,
> PIPE_BIND_TRANSFER_WRITE |
> PIPE_BIND_SHARED);
>
> - return (nvc0_format_table[format].usage & bindings) == bindings;
> + return (( nvc0_format_table[format].usage |
> + nvc0_vertex_format[format].usage) & bindings) == bindings;
> }
>
> static int
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> index 1a56177..e2b617f 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> @@ -165,11 +165,16 @@ nvc0_resource_validate(struct nv04_resource
> *res, uint32_t flags)
> struct nvc0_format {
> uint32_t rt;
> uint32_t tic;
> + uint32_t usage;
> +};
> +
> +struct nvc0_vertex_format {
> uint32_t vtx;
> uint32_t usage;
> };
>
> extern const struct nvc0_format nvc0_format_table[];
> +extern const struct nvc0_vertex_format nvc0_vertex_format[];
>
> static inline void
> nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct
> nv50_tic_entry *tic)
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> index 032b3c1..8239624 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> @@ -80,7 +80,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
> enum pipe_format fmt = ve->src_format;
>
> so->element[i].pipe = elements[i];
> - so->element[i].state = nvc0_format_table[fmt].vtx;
> + so->element[i].state = nvc0_vertex_format[fmt].vtx;
>
> if (!so->element[i].state) {
> switch (util_format_get_nr_components(fmt)) {
> @@ -93,7 +93,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe,
> FREE(so);
> return NULL;
> }
> - so->element[i].state = nvc0_format_table[fmt].vtx;
> + so->element[i].state = nvc0_vertex_format[fmt].vtx;
> so->need_conversion = true;
> pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK,
> "Converting vertex element %d, no hw
> format %s",
> --
> 2.7.0
>
> _______________________________________________
> Nouveau mailing list
> Nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <mailto:Nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
> https://lists.freedesktop.org/mailman/listinfo/nouveau
>
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 23/23] nvc0: implement support for maxwell texture headers
[not found] ` <1455514736-8909-23-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-02-15 17:47 ` Ilia Mirkin
[not found] ` <CAKb7UvgjAjgyvMUS31fS8Jq+vqsO_XyeVreuFsaioU1etoQ_pw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 29+ messages in thread
From: Ilia Mirkin @ 2016-02-15 17:47 UTC (permalink / raw)
To: Ben Skeggs; +Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ben Skeggs
Can you push this to a repo somewhere? I want to see what the final
version looks like after all your changes, but it's hard to see that
with these patches.
On Mon, Feb 15, 2016 at 12:38 AM, Ben Skeggs <skeggsb@gmail.com> wrote:
> From: Ben Skeggs <bskeggs@redhat.com>
>
> Adds support for the new TIC layout that's present on Maxwell GPUs,
> heavily based on the code for the existing layout.
>
> This code is required for GM20x support. While GM10x supports the older
> layout still, this commit switches it to use the updated version instead.
>
> Piglit testing shows zero regressions on GM107.
>
> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
> ---
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 8 +
> src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 +
> src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 201 ++++++++++++++++++++++++-
> 3 files changed, 204 insertions(+), 6 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index d435bec..820e38d 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
> PUSH_DATAh(push, screen->txc->offset);
> PUSH_DATA (push, screen->txc->offset);
> PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
> + if (screen->eng3d->oclass >= GM107_3D_CLASS) {
> + screen->tic.maxwell = true;
> + if (screen->eng3d->oclass == GM107_3D_CLASS) {
> + screen->tic.maxwell =
> + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
> + IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
> + }
> + }
>
> BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
> PUSH_DATAh(push, screen->txc->offset + 65536);
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> index 40c9c7a..f34fabd 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> @@ -83,6 +83,7 @@ struct nvc0_screen {
> void **entries;
> int next;
> uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
> + bool maxwell;
> } tic;
>
> struct {
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
> index ae4d53c..c0da959 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
> @@ -22,6 +22,7 @@
>
> #include "nvc0/nvc0_context.h"
> #include "nvc0/nvc0_resource.h"
> +#include "nvc0/gm107_texture.xml.h"
> #include "nv50/g80_texture.xml.h"
> #include "nv50/g80_defs.xml.h"
>
> @@ -59,12 +60,188 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
> return nvc0_create_texture_view(pipe, res, templ, flags, templ->target);
> }
>
> -struct pipe_sampler_view *
> -nvc0_create_texture_view(struct pipe_context *pipe,
> - struct pipe_resource *texture,
> - const struct pipe_sampler_view *templ,
> - uint32_t flags,
> - enum pipe_texture_target target)
> +static struct pipe_sampler_view *
> +gm107_create_texture_view(struct pipe_context *pipe,
> + struct pipe_resource *texture,
> + const struct pipe_sampler_view *templ,
> + uint32_t flags,
> + enum pipe_texture_target target)
> +{
> + const struct util_format_description *desc;
> + const struct nvc0_format *fmt;
> + uint64_t address;
> + uint32_t *tic;
> + uint32_t swz[4];
> + uint32_t width, height;
> + uint32_t depth;
> + struct nv50_tic_entry *view;
> + struct nv50_miptree *mt;
> + bool tex_int;
> +
> + view = MALLOC_STRUCT(nv50_tic_entry);
> + if (!view)
> + return NULL;
> + mt = nv50_miptree(texture);
> +
> + view->pipe = *templ;
> + view->pipe.reference.count = 1;
> + view->pipe.texture = NULL;
> + view->pipe.context = pipe;
> +
> + view->id = -1;
> +
> + pipe_resource_reference(&view->pipe.texture, texture);
> +
> + tic = &view->tic[0];
> +
> + desc = util_format_description(view->pipe.format);
> + tex_int = util_format_is_pure_integer(view->pipe.format);
> +
> + fmt = &nvc0_format_table[view->pipe.format];
> + swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
> + swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
> + swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
> + swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
> +
> + tic[0] = fmt->tic.format << GM107_TIC2_0_COMPONENTS_SIZES__SHIFT;
> + tic[0] |= fmt->tic.type_r << GM107_TIC2_0_R_DATA_TYPE__SHIFT;
> + tic[0] |= fmt->tic.type_g << GM107_TIC2_0_G_DATA_TYPE__SHIFT;
> + tic[0] |= fmt->tic.type_b << GM107_TIC2_0_B_DATA_TYPE__SHIFT;
> + tic[0] |= fmt->tic.type_a << GM107_TIC2_0_A_DATA_TYPE__SHIFT;
> + tic[0] |= swz[0] << GM107_TIC2_0_X_SOURCE__SHIFT;
> + tic[0] |= swz[1] << GM107_TIC2_0_Y_SOURCE__SHIFT;
> + tic[0] |= swz[2] << GM107_TIC2_0_Z_SOURCE__SHIFT;
> + tic[0] |= swz[3] << GM107_TIC2_0_W_SOURCE__SHIFT;
> + // PACK_COMPONENTS?
> +
> + address = mt->base.address;
> +
> + tic[3] = GM107_TIC2_3_LOD_ANISO_QUALITY_2;
> + tic[4] = GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V;
> + tic[4] |= GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR;
> +
> + if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
> + tic[4] |= GM107_TIC2_4_SRGB_CONVERSION;
> +
> + if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
> + tic[5] = GM107_TIC2_5_NORMALIZED_COORDS;
> + else
> + tic[5] = 0;
> +
> + /* check for linear storage type */
> + if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
> + if (texture->target == PIPE_BUFFER) {
> + assert(!(tic[5] & GM107_TIC2_5_NORMALIZED_COORDS));
> + width = view->pipe.u.buf.last_element - view->pipe.u.buf.first_element;
> + address +=
> + view->pipe.u.buf.first_element * desc->block.bits / 8;
> + tic[2] = GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER;
> + tic[3] |= width >> 16;
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER;
> + tic[4] |= width & 0xffff;
> + } else {
> + assert(!(mt->level[0].pitch & 0x1f));
> + /* must be 2D texture without mip maps */
> + tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH;
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
> + tic[3] |= mt->level[0].pitch >> 5;
> + tic[4] |= mt->base.base.width0 - 1;
> + tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
> + tic[5] |= mt->base.base.height0 - 1;
> + }
> + tic[1] = address;
> + tic[2] |= address >> 32;
> + tic[6] = 0;
> + tic[7] = 0;
> + return &view->pipe;
> + }
> +
> + tic[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR;
> + tic[3] |=
> + ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) |
> + ((mt->level[0].tile_mode & 0xf00) >> 8 << 6);
> +
> + depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
> +
> + if (mt->base.base.array_size > 1) {
> + /* there doesn't seem to be a base layer field in TIC */
> + address += view->pipe.u.tex.first_layer * mt->layer_stride;
> + depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
> + }
> + tic[1] = address;
> + tic[2] |= address >> 32;
> +
> + switch (target) {
> + case PIPE_TEXTURE_1D:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D;
> + break;
> + case PIPE_TEXTURE_2D:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
> + break;
> + case PIPE_TEXTURE_RECT:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
> + break;
> + case PIPE_TEXTURE_3D:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
> + break;
> + case PIPE_TEXTURE_CUBE:
> + depth /= 6;
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
> + break;
> + case PIPE_TEXTURE_1D_ARRAY:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
> + break;
> + case PIPE_TEXTURE_2D_ARRAY:
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
> + break;
> + case PIPE_TEXTURE_CUBE_ARRAY:
> + depth /= 6;
> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY;
> + break;
> + default:
> + unreachable("unexpected/invalid texture target");
> + }
> +
> + tic[3] |= (flags & NV50_TEXVIEW_FILTER_MSAA8) ?
> + GM107_TIC2_3_USE_HEADER_OPT_CONTROL :
> + GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH |
> + GM107_TIC2_3_LOD_ISO_QUALITY_HIGH;
> +
> + if (flags & NV50_TEXVIEW_ACCESS_RESOLVE) {
> + width = mt->base.base.width0 << mt->ms_x;
> + height = mt->base.base.height0 << mt->ms_y;
> + } else {
> + width = mt->base.base.width0;
> + height = mt->base.base.height0;
> + }
> +
> + tic[4] |= width - 1;
> +
> + tic[5] |= (height - 1) & 0xffff;
> + tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
> + tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
> +
> + /* sampling points: (?) */
> + if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
> + tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
> + tic[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1;
> + } else {
> + tic[6] | GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO;
> + tic[6] |= GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE;
> + }
> +
> + tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
> + tic[7] |= mt->ms_mode << GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT;
> +
> + return &view->pipe;
> +}
> +
> +static struct pipe_sampler_view *
> +gf100_create_texture_view(struct pipe_context *pipe,
> + struct pipe_resource *texture,
> + const struct pipe_sampler_view *templ,
> + uint32_t flags,
> + enum pipe_texture_target target)
> {
> const struct util_format_description *desc;
> const struct nvc0_format *fmt;
> @@ -221,6 +398,18 @@ nvc0_create_texture_view(struct pipe_context *pipe,
> return &view->pipe;
> }
>
> +struct pipe_sampler_view *
> +nvc0_create_texture_view(struct pipe_context *pipe,
> + struct pipe_resource *texture,
> + const struct pipe_sampler_view *templ,
> + uint32_t flags,
> + enum pipe_texture_target target)
> +{
> + if (nvc0_context(pipe)->screen->tic.maxwell)
> + return gm107_create_texture_view(pipe, texture, templ, flags, target);
> + return gf100_create_texture_view(pipe, texture, templ, flags, target);
> +}
> +
> static void
> nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
> struct nv04_resource *res)
> --
> 2.7.0
>
> _______________________________________________
> Nouveau mailing list
> Nouveau@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/nouveau
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 23/23] nvc0: implement support for maxwell texture headers
[not found] ` <CAKb7UvgjAjgyvMUS31fS8Jq+vqsO_XyeVreuFsaioU1etoQ_pw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-02-15 21:40 ` Ben Skeggs
[not found] ` <56C245BF.50908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 29+ messages in thread
From: Ben Skeggs @ 2016-02-15 21:40 UTC (permalink / raw)
To: Ilia Mirkin; +Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ben Skeggs
[-- Attachment #1.1: Type: text/plain, Size: 11892 bytes --]
On 02/16/2016 03:47 AM, Ilia Mirkin wrote:
> Can you push this to a repo somewhere? I want to see what the final
> version looks like after all your changes, but it's hard to see that
> with these patches.
https://github.com/skeggsb/Mesa/commits/master
>
> On Mon, Feb 15, 2016 at 12:38 AM, Ben Skeggs <skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> From: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>
>> Adds support for the new TIC layout that's present on Maxwell GPUs,
>> heavily based on the code for the existing layout.
>>
>> This code is required for GM20x support. While GM10x supports the older
>> layout still, this commit switches it to use the updated version instead.
>>
>> Piglit testing shows zero regressions on GM107.
>>
>> Signed-off-by: Ben Skeggs <bskeggs-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 8 +
>> src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 +
>> src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 201 ++++++++++++++++++++++++-
>> 3 files changed, 204 insertions(+), 6 deletions(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> index d435bec..820e38d 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> @@ -991,6 +991,14 @@ nvc0_screen_create(struct nouveau_device *dev)
>> PUSH_DATAh(push, screen->txc->offset);
>> PUSH_DATA (push, screen->txc->offset);
>> PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
>> + if (screen->eng3d->oclass >= GM107_3D_CLASS) {
>> + screen->tic.maxwell = true;
>> + if (screen->eng3d->oclass == GM107_3D_CLASS) {
>> + screen->tic.maxwell =
>> + debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
>> + IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
>> + }
>> + }
>>
>> BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
>> PUSH_DATAh(push, screen->txc->offset + 65536);
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
>> index 40c9c7a..f34fabd 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
>> @@ -83,6 +83,7 @@ struct nvc0_screen {
>> void **entries;
>> int next;
>> uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
>> + bool maxwell;
>> } tic;
>>
>> struct {
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
>> index ae4d53c..c0da959 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
>> @@ -22,6 +22,7 @@
>>
>> #include "nvc0/nvc0_context.h"
>> #include "nvc0/nvc0_resource.h"
>> +#include "nvc0/gm107_texture.xml.h"
>> #include "nv50/g80_texture.xml.h"
>> #include "nv50/g80_defs.xml.h"
>>
>> @@ -59,12 +60,188 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
>> return nvc0_create_texture_view(pipe, res, templ, flags, templ->target);
>> }
>>
>> -struct pipe_sampler_view *
>> -nvc0_create_texture_view(struct pipe_context *pipe,
>> - struct pipe_resource *texture,
>> - const struct pipe_sampler_view *templ,
>> - uint32_t flags,
>> - enum pipe_texture_target target)
>> +static struct pipe_sampler_view *
>> +gm107_create_texture_view(struct pipe_context *pipe,
>> + struct pipe_resource *texture,
>> + const struct pipe_sampler_view *templ,
>> + uint32_t flags,
>> + enum pipe_texture_target target)
>> +{
>> + const struct util_format_description *desc;
>> + const struct nvc0_format *fmt;
>> + uint64_t address;
>> + uint32_t *tic;
>> + uint32_t swz[4];
>> + uint32_t width, height;
>> + uint32_t depth;
>> + struct nv50_tic_entry *view;
>> + struct nv50_miptree *mt;
>> + bool tex_int;
>> +
>> + view = MALLOC_STRUCT(nv50_tic_entry);
>> + if (!view)
>> + return NULL;
>> + mt = nv50_miptree(texture);
>> +
>> + view->pipe = *templ;
>> + view->pipe.reference.count = 1;
>> + view->pipe.texture = NULL;
>> + view->pipe.context = pipe;
>> +
>> + view->id = -1;
>> +
>> + pipe_resource_reference(&view->pipe.texture, texture);
>> +
>> + tic = &view->tic[0];
>> +
>> + desc = util_format_description(view->pipe.format);
>> + tex_int = util_format_is_pure_integer(view->pipe.format);
>> +
>> + fmt = &nvc0_format_table[view->pipe.format];
>> + swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
>> + swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
>> + swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
>> + swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
>> +
>> + tic[0] = fmt->tic.format << GM107_TIC2_0_COMPONENTS_SIZES__SHIFT;
>> + tic[0] |= fmt->tic.type_r << GM107_TIC2_0_R_DATA_TYPE__SHIFT;
>> + tic[0] |= fmt->tic.type_g << GM107_TIC2_0_G_DATA_TYPE__SHIFT;
>> + tic[0] |= fmt->tic.type_b << GM107_TIC2_0_B_DATA_TYPE__SHIFT;
>> + tic[0] |= fmt->tic.type_a << GM107_TIC2_0_A_DATA_TYPE__SHIFT;
>> + tic[0] |= swz[0] << GM107_TIC2_0_X_SOURCE__SHIFT;
>> + tic[0] |= swz[1] << GM107_TIC2_0_Y_SOURCE__SHIFT;
>> + tic[0] |= swz[2] << GM107_TIC2_0_Z_SOURCE__SHIFT;
>> + tic[0] |= swz[3] << GM107_TIC2_0_W_SOURCE__SHIFT;
>> + // PACK_COMPONENTS?
>> +
>> + address = mt->base.address;
>> +
>> + tic[3] = GM107_TIC2_3_LOD_ANISO_QUALITY_2;
>> + tic[4] = GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V;
>> + tic[4] |= GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR;
>> +
>> + if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
>> + tic[4] |= GM107_TIC2_4_SRGB_CONVERSION;
>> +
>> + if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
>> + tic[5] = GM107_TIC2_5_NORMALIZED_COORDS;
>> + else
>> + tic[5] = 0;
>> +
>> + /* check for linear storage type */
>> + if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
>> + if (texture->target == PIPE_BUFFER) {
>> + assert(!(tic[5] & GM107_TIC2_5_NORMALIZED_COORDS));
>> + width = view->pipe.u.buf.last_element - view->pipe.u.buf.first_element;
>> + address +=
>> + view->pipe.u.buf.first_element * desc->block.bits / 8;
>> + tic[2] = GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER;
>> + tic[3] |= width >> 16;
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER;
>> + tic[4] |= width & 0xffff;
>> + } else {
>> + assert(!(mt->level[0].pitch & 0x1f));
>> + /* must be 2D texture without mip maps */
>> + tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH;
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
>> + tic[3] |= mt->level[0].pitch >> 5;
>> + tic[4] |= mt->base.base.width0 - 1;
>> + tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
>> + tic[5] |= mt->base.base.height0 - 1;
>> + }
>> + tic[1] = address;
>> + tic[2] |= address >> 32;
>> + tic[6] = 0;
>> + tic[7] = 0;
>> + return &view->pipe;
>> + }
>> +
>> + tic[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR;
>> + tic[3] |=
>> + ((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) |
>> + ((mt->level[0].tile_mode & 0xf00) >> 8 << 6);
>> +
>> + depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
>> +
>> + if (mt->base.base.array_size > 1) {
>> + /* there doesn't seem to be a base layer field in TIC */
>> + address += view->pipe.u.tex.first_layer * mt->layer_stride;
>> + depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
>> + }
>> + tic[1] = address;
>> + tic[2] |= address >> 32;
>> +
>> + switch (target) {
>> + case PIPE_TEXTURE_1D:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D;
>> + break;
>> + case PIPE_TEXTURE_2D:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
>> + break;
>> + case PIPE_TEXTURE_RECT:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
>> + break;
>> + case PIPE_TEXTURE_3D:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
>> + break;
>> + case PIPE_TEXTURE_CUBE:
>> + depth /= 6;
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
>> + break;
>> + case PIPE_TEXTURE_1D_ARRAY:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
>> + break;
>> + case PIPE_TEXTURE_2D_ARRAY:
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
>> + break;
>> + case PIPE_TEXTURE_CUBE_ARRAY:
>> + depth /= 6;
>> + tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY;
>> + break;
>> + default:
>> + unreachable("unexpected/invalid texture target");
>> + }
>> +
>> + tic[3] |= (flags & NV50_TEXVIEW_FILTER_MSAA8) ?
>> + GM107_TIC2_3_USE_HEADER_OPT_CONTROL :
>> + GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH |
>> + GM107_TIC2_3_LOD_ISO_QUALITY_HIGH;
>> +
>> + if (flags & NV50_TEXVIEW_ACCESS_RESOLVE) {
>> + width = mt->base.base.width0 << mt->ms_x;
>> + height = mt->base.base.height0 << mt->ms_y;
>> + } else {
>> + width = mt->base.base.width0;
>> + height = mt->base.base.height0;
>> + }
>> +
>> + tic[4] |= width - 1;
>> +
>> + tic[5] |= (height - 1) & 0xffff;
>> + tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
>> + tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
>> +
>> + /* sampling points: (?) */
>> + if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
>> + tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
>> + tic[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1;
>> + } else {
>> + tic[6] | GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO;
>> + tic[6] |= GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE;
>> + }
>> +
>> + tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
>> + tic[7] |= mt->ms_mode << GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT;
>> +
>> + return &view->pipe;
>> +}
>> +
>> +static struct pipe_sampler_view *
>> +gf100_create_texture_view(struct pipe_context *pipe,
>> + struct pipe_resource *texture,
>> + const struct pipe_sampler_view *templ,
>> + uint32_t flags,
>> + enum pipe_texture_target target)
>> {
>> const struct util_format_description *desc;
>> const struct nvc0_format *fmt;
>> @@ -221,6 +398,18 @@ nvc0_create_texture_view(struct pipe_context *pipe,
>> return &view->pipe;
>> }
>>
>> +struct pipe_sampler_view *
>> +nvc0_create_texture_view(struct pipe_context *pipe,
>> + struct pipe_resource *texture,
>> + const struct pipe_sampler_view *templ,
>> + uint32_t flags,
>> + enum pipe_texture_target target)
>> +{
>> + if (nvc0_context(pipe)->screen->tic.maxwell)
>> + return gm107_create_texture_view(pipe, texture, templ, flags, target);
>> + return gf100_create_texture_view(pipe, texture, templ, flags, target);
>> +}
>> +
>> static void
>> nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
>> struct nv04_resource *res)
>> --
>> 2.7.0
>>
>> _______________________________________________
>> Nouveau mailing list
>> Nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/nouveau
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https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 23/23] nvc0: implement support for maxwell texture headers
[not found] ` <56C245BF.50908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-02-15 22:08 ` Ilia Mirkin
[not found] ` <CAKb7UvgRddt2RbF9AJOauTtC22hkhmjR2zKApYBa8Q00Z8Z9MA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 29+ messages in thread
From: Ilia Mirkin @ 2016-02-15 22:08 UTC (permalink / raw)
To: Ben Skeggs; +Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ben Skeggs
On Mon, Feb 15, 2016 at 4:40 PM, Ben Skeggs <skeggsb@gmail.com> wrote:
> On 02/16/2016 03:47 AM, Ilia Mirkin wrote:
>> Can you push this to a repo somewhere? I want to see what the final
>> version looks like after all your changes, but it's hard to see that
>> with these patches.
> https://github.com/skeggsb/Mesa/commits/master
Thanks. I looked over this series and it seems fine. I don't hate the
outcome in nv50_formats.c although it would have been kinda nice to
keep it together. However outside of new compressed formats, I doubt
it'll be getting too many updates.
Perhaps tic.maxwell should really be tic.version? Presumably later
GPUs will also use this new TIC format? [There's also a v0 that we
don't really use but the only tic version supported by G80, which does
the colorkey thing and doesn't support first/last level.]
I would really appreciate it if you could do a piglit run comparison
against both a nv50 and nvc0 GPU (and not maxwell - those can have
extra-special issues). If there are no format-related regressions
(there are a handful of flaky tests), I'm fine with this getting
pushed.
-ilia
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 23/23] nvc0: implement support for maxwell texture headers
[not found] ` <CAKb7UvgRddt2RbF9AJOauTtC22hkhmjR2zKApYBa8Q00Z8Z9MA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-02-16 5:42 ` Ben Skeggs
0 siblings, 0 replies; 29+ messages in thread
From: Ben Skeggs @ 2016-02-16 5:42 UTC (permalink / raw)
To: Ilia Mirkin; +Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ben Skeggs
[-- Attachment #1.1: Type: text/plain, Size: 1678 bytes --]
On 02/16/2016 08:08 AM, Ilia Mirkin wrote:
> On Mon, Feb 15, 2016 at 4:40 PM, Ben Skeggs <skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> On 02/16/2016 03:47 AM, Ilia Mirkin wrote:
>>> Can you push this to a repo somewhere? I want to see what the final
>>> version looks like after all your changes, but it's hard to see that
>>> with these patches.
>> https://github.com/skeggsb/Mesa/commits/master
>
> Thanks. I looked over this series and it seems fine. I don't hate the
> outcome in nv50_formats.c although it would have been kinda nice to
> keep it together. However outside of new compressed formats, I doubt
> it'll be getting too many updates.
>
> Perhaps tic.maxwell should really be tic.version? Presumably later
> GPUs will also use this new TIC format? [There's also a v0 that we
> don't really use but the only tic version supported by G80, which does
> the colorkey thing and doesn't support first/last level.]
>
> I would really appreciate it if you could do a piglit run comparison
> against both a nv50 and nvc0 GPU (and not maxwell - those can have
> extra-special issues). If there are no format-related regressions
> (there are a handful of flaky tests), I'm fine with this getting
> pushed.
Hey Ilia,
I've pushed an updated branch containing a small typo fix to the GM107
texture header commit, as well as an extra commit recognising GM20x
chipsets.
The piglit comparisons you requested are at:
G96:
https://drive.google.com/file/d/0B66cGbmsDhPvTUV6TTNuZHJaVGc/view?usp=sharing
GF100:
https://drive.google.com/file/d/0B66cGbmsDhPvT0hhMGU2UTRDVG8/view?usp=sharing
Thanks,
Ben.
>
> -ilia
>
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^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2016-02-16 5:42 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-15 5:38 [PATCH 01/23] nv50: import updated g80_defs.xml.h from rnndb Ben Skeggs
[not found] ` <1455514736-8909-1-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-15 5:38 ` [PATCH 02/23] nv50: switch nv50_surface.c to updated g80_defs.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 03/23] nv50: switch nv50_tex.c " Ben Skeggs
2016-02-15 5:38 ` [PATCH 04/23] nv50: switch nv50_transfer.c to g80_defs.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 05/23] nv50: remove unnecessary include Ben Skeggs
2016-02-15 5:38 ` [PATCH 06/23] nvc0: switch nvc0_surface.c to updated g80_defs.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 07/23] nvc0: switch nvc0_tex.c " Ben Skeggs
2016-02-15 5:38 ` [PATCH 08/23] nvc0: remove unnecessary includes Ben Skeggs
2016-02-15 5:38 ` [PATCH 09/23] nv50-: separate vertex formats from surface format descriptions Ben Skeggs
[not found] ` <1455514736-8909-9-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-15 5:43 ` Ilia Mirkin
[not found] ` <CAKb7Uvg=rL_GLTRU+u_rvWZOmE8C1HiuonmgdvEKxV9ZzSyQ6A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-02-15 5:49 ` Ben Skeggs
2016-02-15 5:38 ` [PATCH 10/23] nv50-: improved macros to handle format specification Ben Skeggs
2016-02-15 5:38 ` [PATCH 11/23] nv50-: switch nv50_formats.c to updated g80_defs.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 12/23] nv50-: remove nv50_defs.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 13/23] nv50: import updated g80_texture.xml.h from rnndb Ben Skeggs
2016-02-15 5:38 ` [PATCH 14/23] nv50-: switch nv50_formats.c to updated g80_texture.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 15/23] nv50: switch nv50_state.c " Ben Skeggs
2016-02-15 5:38 ` [PATCH 16/23] nv50: switch nv50_surface.c " Ben Skeggs
2016-02-15 5:38 ` [PATCH 17/23] nv50: switch nv50_tex.c " Ben Skeggs
2016-02-15 5:38 ` [PATCH 18/23] nvc0: switch nvc0_surface.c " Ben Skeggs
2016-02-15 5:38 ` [PATCH 19/23] nvc0: switch nvc0_tex.c " Ben Skeggs
2016-02-15 5:38 ` [PATCH 20/23] nv50-: remove nv50_texture.xml.h Ben Skeggs
2016-02-15 5:38 ` [PATCH 21/23] nv50-: split tic format specification Ben Skeggs
2016-02-15 5:38 ` [PATCH 22/23] nvc0: import maxwell texture header definitions from rnndb Ben Skeggs
2016-02-15 5:38 ` [PATCH 23/23] nvc0: implement support for maxwell texture headers Ben Skeggs
[not found] ` <1455514736-8909-23-git-send-email-skeggsb-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-15 17:47 ` Ilia Mirkin
[not found] ` <CAKb7UvgjAjgyvMUS31fS8Jq+vqsO_XyeVreuFsaioU1etoQ_pw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-02-15 21:40 ` Ben Skeggs
[not found] ` <56C245BF.50908-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-02-15 22:08 ` Ilia Mirkin
[not found] ` <CAKb7UvgRddt2RbF9AJOauTtC22hkhmjR2zKApYBa8Q00Z8Z9MA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-02-16 5:42 ` Ben Skeggs
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