[PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel

[PATCH 00/10] enable psr2 for idle_screen on y-cordinate panel

[vathsala nagaraju]

This series enables psr2 on idle on screen for y cordinate panel.
Code is tested on sharp 32X18 edp 1.4 y cordinate enabled panel.
if system enters psr2, the system must go to deep sleep state.
Can be verifed by checking  psr2_status register bit 31:28.
DEEP_SLEEP[value 8]  must be entered while in idle on screen with psr2
panel.

PSR1 and PSR2 are mutually exclusive.
In the current code, when PSR2 is enabled , psr1 is also enabled,
and for psr2 the status is read from psr1 registers, leading to
blank screen.
1-3: Fixes vsc header programming for psr2 as per edp1.4 a
     table 6-11 and  blank screen issue for psr2 panel.
4-5: Enables alpm and disables aux frame sync , need for psr2.
6-7: Progarms CHICKEN_TRANS and PSR_MASK for deep sleep state, as per bspec
8:   Psr2 is enabled only for y cordinate enabled psr2 panel.
     this restriction will be removed after adding gtc support.
9-10: Adds debug support for psr2.It also enables reading of
     EDP_PSR_PERF_CNT on skl+ platforms, when dc6 is disabled through
     kernel parameter i915.enable_dc=0

Vathsala Nagaraju (10):
  drm : adds Y-coordinate and Colorimetry Format
  drm/i915/psr: program vsc header for psr2
  drm/i915/psr: fix blank screen issue for psr2
  drm/i915/psr: disable aux_frame_sync on psr2 exit
  drm/i915/psr: enable ALPM for psr2
  drm/i915/psr: set CHICKEN_TRANS for psr2
  drm/i915/psr: set PSR_MASK bits for deep sleep
  drm/i915/psr: enable psr2 for y cordinate panels
  drm/i915/psr: report live PSR2 State
  drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2

 drivers/gpu/drm/i915/i915_debugfs.c |  38 ++++++-
 drivers/gpu/drm/i915/i915_drv.h     |   3 +
 drivers/gpu/drm/i915/i915_reg.h     |  19 ++++
 drivers/gpu/drm/i915/intel_dp.c     |  35 +++++++
 drivers/gpu/drm/i915/intel_psr.c    | 199 ++++++++++++++++++++++++++++--------
 include/drm/drm_dp_helper.h         |  13 ++-
 6 files changed, 263 insertions(+), 44 deletions(-)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>

-- 
1.9.1

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[PATCH 01/10] drm : adds Y-coordinate and Colorimetry Format

[vathsala nagaraju]

PSR2 vsc revision number hb2( as per table 6-11)is updated to
4 or 5 based on Y cordinate and Colorimetry Format as below
04h = 3D stereo + PSR/PSR2 + Y-coordinate.
05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
Format indication. A DP Source device is allowed to indicate the pixel
encoding/colorimetry format to the DP Sink device with VSC SDP only when
the DP Sink device supports it (
i.e.,VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
DPRX_FEATURE_ENUMERATION_LIST register (DPCD Address 02210h, bit 3;
is set to 1).

v2: (Jani)
- Change DP_PSR_Y_COORDINATE to DP_PSR2_SU_Y_COORDINATE_REQUIRED.
- Add DP_PSR2_SU_GRANULARITY_REQUIRED.
- Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX.
- Add GTC_CAP and AV_SYNC_CAP, other bits in DPRX_FEATURE_ENUMERATION_LIST.

v3: (Jani)
- Add support for bits 7:4 and 1 as per DP v1.4 for
  DPRX_FEATURE_ENUMERATION_LIST.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 include/drm/drm_dp_helper.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 55bbeb0..0468135 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -194,7 +194,8 @@
 # define DP_PSR_SETUP_TIME_0                (6 << 1)
 # define DP_PSR_SETUP_TIME_MASK             (7 << 1)
 # define DP_PSR_SETUP_TIME_SHIFT            1
-
+# define DP_PSR2_SU_Y_COORDINATE_REQUIRED   (1 << 4)  /* eDP 1.4a */
+# define DP_PSR2_SU_GRANULARITY_REQUIRED    (1 << 5)  /* eDP 1.4b */
 /*
  * 0x80-0x8f describe downstream port capabilities, but there are two layouts
  * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
@@ -568,6 +569,16 @@
 #define DP_RECEIVER_ALPM_STATUS		    0x200b  /* eDP 1.4 */
 # define DP_ALPM_LOCK_TIMEOUT_ERROR	    (1 << 0)
 
+#define DP_DPRX_FEATURE_ENUMERATION_LIST    0x2210  /* DP 1.3 */
+# define DP_GTC_CAP					(1 << 0)  /* DP 1.3 */
+# define DP_SST_SPLIT_SDP_CAP				(1 << 1)  /* DP 1.4 */
+# define DP_AV_SYNC_CAP					(1 << 2)  /* DP 1.3 */
+# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED	(1 << 3)  /* DP 1.3 */
+# define DP_VSC_EXT_VESA_SDP_SUPPORTED			(1 << 4)  /* DP 1.4 */
+# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED		(1 << 5)  /* DP 1.4 */
+# define DP_VSC_EXT_CEA_SDP_SUPPORTED			(1 << 6)  /* DP 1.4 */
+# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED		(1 << 7)  /* DP 1.4 */
+
 /* DP 1.2 Sideband message defines */
 /* peer device type - DP 1.2a Table 2-92 */
 #define DP_PEER_DEVICE_NONE		0x0
-- 
1.9.1

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[PATCH 02/10] drm/i915/psr: program vsc header for psr2

[vathsala nagaraju]

Function hsw_psr_setup handles vsc header setup for psr1 and
skl_psr_setup_vsc handles vsc header setup for psr2.

Setup VSC header in function skl_psr_setup_vsc for psr2 support,
as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
operation.

v2: (Jani)
- Initialize variables to 0
- intel_dp_get_y_cord_status and intel_dp_get_y_cord_status made static
- Correct indentation for continuation lines
- Change DP_PSR_Y_COORDINATE to  DP_PSR2_SU_Y_COORDINATE_REQUIRED
- Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX_*
- Change VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED to DP_VSC_*

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  2 ++
 drivers/gpu/drm/i915/intel_dp.c  | 26 ++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++--
 3 files changed, 43 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22d3f61..36dc835 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1164,6 +1164,8 @@ struct i915_psr {
 	bool psr2_support;
 	bool aux_frame_sync;
 	bool link_standby;
+	bool y_cord_support;
+	bool colorimetry_support;
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fb12896..da577c9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3042,6 +3042,24 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
 				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
 }
 
+static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
+{
+	uint8_t psr_caps = 0;
+
+	drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
+	return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
+}
+
+static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
+{
+	uint8_t dprx = 0;
+
+	drm_dp_dpcd_readb(&intel_dp->aux,
+			DP_DPRX_FEATURE_ENUMERATION_LIST,
+			&dprx);
+	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
+}
+
 /* These are source-specific values. */
 uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
@@ -3620,6 +3638,14 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 		dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
 		DRM_DEBUG_KMS("PSR2 %s on sink",
 			      dev_priv->psr.psr2_support ? "supported" : "not supported");
+
+		if (dev_priv->psr.psr2_support) {
+			dev_priv->psr.y_cord_support =
+				intel_dp_get_y_cord_status(intel_dp);
+			dev_priv->psr.colorimetry_support =
+				intel_dp_get_colorimetry_status(intel_dp);
+		}
+
 	}
 
 	/* Read the eDP Display control capabilities registers */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 6aca8ff..c3aa649 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
 {
 	struct edp_vsc_psr psr_vsc;
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = intel_dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
 	memset(&psr_vsc, 0, sizeof(psr_vsc));
 	psr_vsc.sdp_header.HB0 = 0;
 	psr_vsc.sdp_header.HB1 = 0x7;
-	psr_vsc.sdp_header.HB2 = 0x3;
-	psr_vsc.sdp_header.HB3 = 0xb;
+	if (dev_priv->psr.colorimetry_support &&
+		dev_priv->psr.y_cord_support) {
+		psr_vsc.sdp_header.HB2 = 0x5;
+		psr_vsc.sdp_header.HB3 = 0x13;
+	} else if (dev_priv->psr.y_cord_support) {
+		psr_vsc.sdp_header.HB2 = 0x4;
+		psr_vsc.sdp_header.HB3 = 0xe;
+	} else {
+		psr_vsc.sdp_header.HB2 = 0x3;
+		psr_vsc.sdp_header.HB3 = 0xc;
+	}
+
 	intel_psr_write_vsc(intel_dp, &psr_vsc);
 }
 
-- 
1.9.1

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[PATCH 03/10] drm/i915/psr: fix blank screen issue for psr2

[vathsala nagaraju]

Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
psr1 should be disabled.When psr2 is exited , bit 31 of reg
PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
(psr1 control register)is set to 0.
Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
instead of PSR2_STATUS register, which has wrong data, resulting
in blankscreen.
hsw_enable_source is split into hsw_enable_source_psr1 and
hsw_enable_source_psr2 for easier code review and maintenance,
as suggested by rodrigo and jim.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   3 +
 drivers/gpu/drm/i915/intel_psr.c | 124 +++++++++++++++++++++++++++++----------
 2 files changed, 97 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00970aa..7830e6e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3615,6 +3615,9 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
 
+#define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
+#define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
+
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index c3aa649..ff2ecfd 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -261,12 +261,11 @@ static void vlv_psr_activate(struct intel_dp *intel_dp)
 		   VLV_EDP_PSR_ACTIVE_ENTRY);
 }
 
-static void hsw_psr_enable_source(struct intel_dp *intel_dp)
+static void hsw_enable_source_psr1(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-
 	uint32_t max_sleep_time = 0x1f;
 	/*
 	 * Let's respect VBT in case VBT asks a higher idle_frame value.
@@ -312,14 +311,30 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 		val |= EDP_PSR_TP1_TP2_SEL;
 
 	I915_WRITE(EDP_PSR_CTL, val);
+}
 
-	if (!dev_priv->psr.psr2_support)
-		return;
+static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	/*
+	 * Let's respect VBT in case VBT asks a higher idle_frame value.
+	 * Let's use 6 as the minimum to cover all known cases including
+	 * the off-by-one issue that HW has in some cases. Also there are
+	 * cases where sink should be able to train
+	 * with the 5 or 6 idle patterns.
+	 */
+	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+	uint32_t val = EDP_PSR_ENABLE;
+
+	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
@@ -333,6 +348,20 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
+
+static void hsw_psr_enable_source(struct intel_dp *intel_dp)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_device *dev = dig_port->base.base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	/* psr1 and psr2 are mutually exclusive.*/
+	if (dev_priv->psr.psr2_support)
+		hsw_enable_source_psr2(intel_dp);
+	else
+		hsw_enable_source_psr1(intel_dp);
+}
+
 static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
@@ -410,7 +439,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
-	WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+	if (dev_priv->psr.psr2_support)
+		WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
+	else
+		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	WARN_ON(dev_priv->psr.active);
 	lockdep_assert_held(&dev_priv->psr.lock);
 
@@ -462,8 +494,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	if (HAS_DDI(dev_priv)) {
-		hsw_psr_setup_vsc(intel_dp);
-
 		if (dev_priv->psr.psr2_support) {
 			/* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
 			if (crtc->config->pipe_src_w > 3200 ||
@@ -471,8 +501,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 				dev_priv->psr.psr2_support = false;
 			else
 				skl_psr_setup_su_vsc(intel_dp);
+		} else {
+			/* set up vsc header for psr1 */
+			hsw_psr_setup_vsc(intel_dp);
 		}
-
 		/*
 		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
 		 * Also mask LPSP to avoid dependency on other drivers that
@@ -557,20 +589,37 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	if (dev_priv->psr.active) {
-		I915_WRITE(EDP_PSR_CTL,
-			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
+		if (dev_priv->psr.psr2_support)
+			I915_WRITE(EDP_PSR2_CTL,
+				I915_READ(EDP_PSR2_CTL) &
+					~(EDP_PSR2_ENABLE |
+					EDP_SU_TRACK_ENABLE));
+		else
+			I915_WRITE(EDP_PSR_CTL,
+				   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
 
 		/* Wait till PSR is idle */
-		if (intel_wait_for_register(dev_priv,
-					    EDP_PSR_STATUS_CTL,
-					    EDP_PSR_STATUS_STATE_MASK,
-					    0,
-					    2000))
+		if (dev_priv->psr.psr2_support) {
+			if (intel_wait_for_register(dev_priv,
+						    EDP_PSR2_STATUS_CTL,
+						    EDP_PSR2_STATUS_STATE_MASK,
+						    0,
+						    2000))
+			DRM_ERROR("Timed out waiting for PSR2 Idle State\n");
+		} else {
+			if (intel_wait_for_register(dev_priv,
+						    EDP_PSR_STATUS_CTL,
+						    EDP_PSR_STATUS_STATE_MASK,
+						    0,
+						    2000))
 			DRM_ERROR("Timed out waiting for PSR Idle State\n");
-
+		}
 		dev_priv->psr.active = false;
 	} else {
-		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
+		if (dev_priv->psr.psr2_support)
+			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
+		else
+			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
 	}
 }
 
@@ -621,13 +670,24 @@ static void intel_psr_work(struct work_struct *work)
 	 * and be ready for re-enable.
 	 */
 	if (HAS_DDI(dev_priv)) {
-		if (intel_wait_for_register(dev_priv,
-					    EDP_PSR_STATUS_CTL,
-					    EDP_PSR_STATUS_STATE_MASK,
-					    0,
-					    50)) {
-			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
-			return;
+		if (dev_priv->psr.psr2_support) {
+			if (intel_wait_for_register(dev_priv,
+						EDP_PSR2_STATUS_CTL,
+						EDP_PSR2_STATUS_STATE_MASK,
+						0,
+						50)) {
+				DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
+				return;
+			}
+		} else {
+			if (intel_wait_for_register(dev_priv,
+						EDP_PSR_STATUS_CTL,
+						EDP_PSR_STATUS_STATE_MASK,
+						0,
+						50)) {
+				DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
+				return;
+			}
 		}
 	} else {
 		if (intel_wait_for_register(dev_priv,
@@ -669,11 +729,15 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 		return;
 
 	if (HAS_DDI(dev_priv)) {
-		val = I915_READ(EDP_PSR_CTL);
-
-		WARN_ON(!(val & EDP_PSR_ENABLE));
-
-		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
+		if (dev_priv->psr.psr2_support) {
+			val = I915_READ(EDP_PSR2_CTL);
+			WARN_ON(!(val & EDP_PSR2_ENABLE));
+			I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
+		} else {
+			val = I915_READ(EDP_PSR_CTL);
+			WARN_ON(!(val & EDP_PSR_ENABLE));
+			I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
+		}
 	} else {
 		val = I915_READ(VLV_PSRCTL(pipe));
 
-- 
1.9.1

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[PATCH 04/10] drm/i915/psr: disable aux_frame_sync on psr2 exit

[vathsala nagaraju]

Screen freeze observed if AUX_FRAME_SYNC is not disabled
on psr2 exit.AUX_FRAME_SYNC needed for psr2 is enabled during
psr2 entry. It must be disabled on psr2 exit.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index ff2ecfd..93eb0f0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -589,6 +589,11 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	if (dev_priv->psr.active) {
+		if (dev_priv->psr.aux_frame_sync)
+			drm_dp_dpcd_writeb(&intel_dp->aux,
+					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
+					0);
+
 		if (dev_priv->psr.psr2_support)
 			I915_WRITE(EDP_PSR2_CTL,
 				I915_READ(EDP_PSR2_CTL) &
@@ -729,6 +734,10 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 		return;
 
 	if (HAS_DDI(dev_priv)) {
+		if (dev_priv->psr.aux_frame_sync)
+			drm_dp_dpcd_writeb(&intel_dp->aux,
+					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
+					0);
 		if (dev_priv->psr.psr2_support) {
 			val = I915_READ(EDP_PSR2_CTL);
 			WARN_ON(!(val & EDP_PSR2_ENABLE));
-- 
1.9.1

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[PATCH 05/10] drm/i915/psr: enable ALPM for psr2

[vathsala nagaraju]

As per edp1.4 spec , alpm is required for psr2 operation as it's
used for all psr2  main link power down management and alpm enable
bit must be set for psr2 operation.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_dp.c  | 10 ++++++++++
 drivers/gpu/drm/i915/intel_psr.c |  6 +++++-
 3 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 36dc835..0742b81 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1166,6 +1166,7 @@ struct i915_psr {
 	bool link_standby;
 	bool y_cord_support;
 	bool colorimetry_support;
+	bool alpm;
 };
 
 enum intel_pch {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index da577c9..9b313a3 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3060,6 +3060,14 @@ static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
 	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
 }
 
+bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
+{
+	uint8_t alpm_caps = 0;
+
+	drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
+	return alpm_caps & DP_ALPM_CAP;
+}
+
 /* These are source-specific values. */
 uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
@@ -3644,6 +3652,8 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 				intel_dp_get_y_cord_status(intel_dp);
 			dev_priv->psr.colorimetry_support =
 				intel_dp_get_colorimetry_status(intel_dp);
+			dev_priv->psr.alpm =
+				intel_dp_get_alpm_status(intel_dp);
 		}
 
 	}
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 93eb0f0..494e4b2 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -209,7 +209,11 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
 		drm_dp_dpcd_writeb(&intel_dp->aux,
 				DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
 				DP_AUX_FRAME_SYNC_ENABLE);
-
+	/* Enable ALPM at sink for psr2 */
+	if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
+		drm_dp_dpcd_writeb(&intel_dp->aux,
+				DP_RECEIVER_ALPM_CONFIG,
+				DP_ALPM_ENABLE);
 	if (dev_priv->psr.link_standby)
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
 				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
-- 
1.9.1

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[PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

[vathsala nagaraju]

As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 7 +++++++
 drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
 #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
 
+#define CHICKEN_TRANS_A         0x420c0
+#define CHICKEN_TRANS_B         0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
+#define TRANS_EDP              3
+#define CHICKEN_TRANS_BIT12    (1<<12)
+#define CHICKEN_TRANS_BIT15    (1<<15)
+
 #define DISP_ARB_CTL	_MMIO(0x45000)
 #define  DISP_FBC_MEMORY_WAKE		(1<<31)
 #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 494e4b2..2e75ef6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -332,6 +332,7 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
 	 */
 	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
 	uint32_t val = EDP_PSR_ENABLE;
+	uint32_t chicken_trans = 0;
 
 	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
 
@@ -349,6 +350,12 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
 	else
 		val |= EDP_PSR2_TP2_TIME_50;
 
+	/* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
+	if (dev_priv->psr.y_cord_support)
+		chicken_trans = CHICKEN_TRANS_BIT15;
+	/* Set CHICKEN_TRANS_BIT12 for programable header */
+	chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
+	I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
-- 
1.9.1

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[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[vathsala nagaraju]

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  7 +++++++
 drivers/gpu/drm/i915/intel_dp.c  |  1 -
 drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
 3 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca506a..0cbe564 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3600,6 +3600,12 @@ enum {
 #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -3614,6 +3620,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9b313a3..0a10858 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3655,7 +3655,6 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 			dev_priv->psr.alpm =
 				intel_dp_get_alpm_status(intel_dp);
 		}
-
 	}
 
 	/* Read the eDP Display control capabilities registers */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2e75ef6..19cd4d7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -339,7 +339,9 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE |
+		EDP_SU_TRACK_ENABLE |
+		EDP_FRAMES_BEFORE_SU_ENTRY;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
@@ -512,18 +514,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 				dev_priv->psr.psr2_support = false;
 			else
 				skl_psr_setup_su_vsc(intel_dp);
+				I915_WRITE(EDP_PSR_DEBUG_CTL,
+					   EDP_PSR_DEBUG_MASK_MEMUP |
+					   EDP_PSR_DEBUG_MASK_HPD |
+					   EDP_PSR_DEBUG_MASK_LPSP |
+					   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+					   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 		} else {
 			/* set up vsc header for psr1 */
 			hsw_psr_setup_vsc(intel_dp);
+			/*
+			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+			 * and HPD. also mask LPSP to avoid dependency on other
+			 * drivers that might block runtime_pm besides
+			 * preventing  other hw tracking issues now we can rely
+			 * on frontbuffer tracking.
+			 */
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP);
 		}
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-		 * Also mask LPSP to avoid dependency on other drivers that
-		 * might block runtime_pm besides preventing other hw tracking
-		 * issues now we can rely on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 
 		/* Enable PSR on the panel */
 		hsw_psr_enable_sink(intel_dp);
-- 
1.9.1

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[PATCH 08/10] drm/i915/psr: enable psr2 for y cordinate panels

[vathsala nagaraju]

Psr2 is enabled only for y cordinate panels.Once GTC (global time code)
is implemented,this restriction is removed so that psr2
can work on panels without y cordinate support.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 19cd4d7..ca3ef3e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -495,6 +495,15 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 		return;
 	}
 
+	/*
+	 * FIXME:enable psr2 only for y-cordinate psr2 panels
+	 * After gtc implementation , remove this restriction.
+	 */
+	if (!dev_priv->psr.y_cord_support &&  dev_priv->psr.psr2_support) {
+		DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
+		return;
+	}
+
 	mutex_lock(&dev_priv->psr.lock);
 	if (dev_priv->psr.enabled) {
 		DRM_DEBUG_KMS("PSR already in use\n");
-- 
1.9.1

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[PATCH 09/10] drm/i915/psr: report live PSR2 State

[vathsala nagaraju]

Reports  live state of PSR2 form PSR2_STATUS register.
bit field 31:28 gives the live state of PSR2.
It can be used to check if system is in deep sleep,
selective update or selective update standby.
During video play back, we can use this to check
if system is entering SU mode or not.
when system is in idle state, DEEP_SLEEP(8) must be entered.
When video playback is happening, system must be in
SLEEP(3 / selective update) or SU_STANDBY( 6 / selective update standby)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h     |  2 ++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9d7b5a8..8b0e3f9 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2606,6 +2606,30 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
 	}
+	if (dev_priv->psr.psr2_support) {
+		static const char * const live_status[] = {
+							"IDLE",
+							"CAPTURE",
+							"CAPTURE_Fs",
+							"SLEEP",
+							"BUFON_FW",
+							"ML_UP",
+							"SU_STANDBY",
+							"FAST_SLEEP",
+							"DEEP_SLEEP",
+							"BUF_ON",
+							"TG_ON" };
+		u8 pos = (I915_READ(EDP_PSR2_STATUS_CTL) &
+			EDP_PSR2_STATUS_STATE_MASK) >>
+			EDP_PSR2_STATUS_STATE_SHIFT;
+
+		seq_printf(m, "PSR2_STATUS_EDP: %x\n",
+			I915_READ(EDP_PSR2_STATUS_CTL));
+
+		if (pos <= EDP_PSR2_STATUS_TG_ON)
+		seq_printf(m, "PSR2 live state %s\n",
+			live_status[pos]);
+	}
 	mutex_unlock(&dev_priv->psr.lock);
 
 	intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cbe564..03a14d9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3624,6 +3624,8 @@ enum {
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
+#define EDP_PSR2_STATUS_STATE_SHIFT    28
+#define EDP_PSR2_STATUS_TG_ON          0xa
 
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
-- 
1.9.1

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[PATCH 10/10] drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2

[vathsala nagaraju]

PSR1 and PSR2 enable sequence are mutually exclusive.
Register SRD_PERF_COUNT increments while system is in psr1.
This register is not valid for psr2.while in psr2,SRD_PERF_COUNT
is always 0.
Reporting psr perfcount from SRD_PERF_COUNT is not valid for psr2 case.
Also, if dc6 is disabled via kernel parameter i915.enable_dc=0,
EDP_PSR_PERF_CNT can be reported for SKL+ platforms for debug
purpose.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8b0e3f9..4136cec 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2539,6 +2539,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 	u32 stat[3];
 	enum pipe pipe;
 	bool enabled = false;
+	bool dc6_enabled = false;
 
 	if (!HAS_PSR(dev_priv)) {
 		seq_puts(m, "PSR not supported\n");
@@ -2598,11 +2599,20 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 	/*
 	 * VLV/CHV PSR has no kind of performance counter
+	 * EDP_PSR_PERF_CNT is not valid for psr2.
 	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
+	 * if we want to read EDP_PSR_PERF_CNT for debug purpose on SKL+,
+	 * disable dc state in kernel parameter i915.enable_dc=0.
 	 */
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+
+	dc6_enabled = ((I915_READ(DC_STATE_EN) &
+			DC_STATE_EN_UPTO_DC5_DC6_MASK) ==
+			DC_STATE_EN_UPTO_DC6);
+
+	if ((!dev_priv->psr.psr2_support && !dc6_enabled) ||
+	     IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
-			EDP_PSR_PERF_CNT_MASK;
+			  EDP_PSR_PERF_CNT_MASK;
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
 	}
-- 
1.9.1

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✓ Fi.CI.BAT: success for enable psr2 for idle_screen on y-cordinate panel (rev2)

[Patchwork]

== Series Details ==

Series: enable psr2 for idle_screen on y-cordinate panel (rev2)
URL   : https://patchwork.freedesktop.org/series/17295/
State : success

== Summary ==

Series 17295v2 enable psr2 for idle_screen on y-cordinate panel
https://patchwork.freedesktop.org/api/1.0/series/17295/revisions/2/mbox/

Test gem_sync:
        Subgroup basic-store-all:
                fail       -> PASS       (fi-ivb-3520m)

fi-bdw-5557u     total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21 
fi-skl-6260u     total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13 
fi-snb-2520m     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32 

a07420cecb721150bc4a75369d9d91bd4efe03f6 drm-tip: 2017y-01m-02d-09h-37m-49s UTC integration manifest
cbd321b drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2
6f0ce69 drm/i915/psr: report live PSR2 State
d653ca9 drm/i915/psr: enable psr2 for y cordinate panels
d3be2ef drm/i915/psr: set PSR_MASK bits for deep sleep
146138d drm/i915/psr: set CHICKEN_TRANS for psr2
f20a21a drm/i915/psr: enable ALPM for psr2
da4dab9 drm/i915/psr: disable aux_frame_sync on psr2 exit
f8fd460 drm/i915/psr: fix blank screen issue for psr2
cc3e57a drm/i915/psr: program vsc header for psr2
dcfb51b drm : adds Y-coordinate and Colorimetry Format

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3417/
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Re: [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[Ilia Mirkin]

On Mon, Jan 2, 2017 at 6:31 AM, vathsala nagaraju
<vathsala.nagaraju@intel.com> wrote:
> Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
> to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
> should report value 8 , if system enters deep sleep state.
>
> Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
> flickering is observed on psr2 panel.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  7 +++++++
>  drivers/gpu/drm/i915/intel_dp.c  |  1 -
>  drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
>  3 files changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5ca506a..0cbe564 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3600,6 +3600,12 @@ enum {
>  #define   EDP_PSR_DEBUG_MASK_LPSP      (1<<27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP     (1<<26)
>  #define   EDP_PSR_DEBUG_MASK_HPD       (1<<25)
> +#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
> +#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
> +#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
> +#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)

Looks like you're defining the above 3 (maybe 4 - not enough context)
a second time.

  -ilia
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Re: [PATCH 02/10] drm/i915/psr: program vsc header for psr2

[Jim Bride]

On Mon, Jan 02, 2017 at 05:00:55PM +0530, vathsala nagaraju wrote:
> Function hsw_psr_setup handles vsc header setup for psr1 and
> skl_psr_setup_vsc handles vsc header setup for psr2.
> 
> Setup VSC header in function skl_psr_setup_vsc for psr2 support,
> as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
> operation.
> 
> v2: (Jani)
> - Initialize variables to 0
> - intel_dp_get_y_cord_status and intel_dp_get_y_cord_status made static
> - Correct indentation for continuation lines
> - Change DP_PSR_Y_COORDINATE to  DP_PSR2_SU_Y_COORDINATE_REQUIRED
> - Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX_*
> - Change VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED to DP_VSC_*
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
>  drivers/gpu/drm/i915/intel_dp.c  | 26 ++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++--
>  3 files changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 22d3f61..36dc835 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1164,6 +1164,8 @@ struct i915_psr {
>  	bool psr2_support;
>  	bool aux_frame_sync;
>  	bool link_standby;
> +	bool y_cord_support;
> +	bool colorimetry_support;
>  };
>  
>  enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fb12896..da577c9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3042,6 +3042,24 @@ static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
>  				DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
>  }
>  
> +static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
> +{
> +	uint8_t psr_caps = 0;
> +
> +	drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
> +	return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> +}
> +
> +static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> +{
> +	uint8_t dprx = 0;
> +
> +	drm_dp_dpcd_readb(&intel_dp->aux,
> +			DP_DPRX_FEATURE_ENUMERATION_LIST,
> +			&dprx);
> +	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
> +}
> +
>  /* These are source-specific values. */
>  uint8_t
>  intel_dp_voltage_max(struct intel_dp *intel_dp)
> @@ -3620,6 +3638,14 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
>  		dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
>  		DRM_DEBUG_KMS("PSR2 %s on sink",
>  			      dev_priv->psr.psr2_support ? "supported" : "not supported");
> +
> +		if (dev_priv->psr.psr2_support) {
> +			dev_priv->psr.y_cord_support =
> +				intel_dp_get_y_cord_status(intel_dp);
> +			dev_priv->psr.colorimetry_support =
> +				intel_dp_get_colorimetry_status(intel_dp);
> +		}
> +
>  	}
>  
>  	/* Read the eDP Display control capabilities registers */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 6aca8ff..c3aa649 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
>  static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
>  {
>  	struct edp_vsc_psr psr_vsc;
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = intel_dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  
>  	/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
>  	memset(&psr_vsc, 0, sizeof(psr_vsc));
>  	psr_vsc.sdp_header.HB0 = 0;
>  	psr_vsc.sdp_header.HB1 = 0x7;
> -	psr_vsc.sdp_header.HB2 = 0x3;
> -	psr_vsc.sdp_header.HB3 = 0xb;
> +	if (dev_priv->psr.colorimetry_support &&
> +		dev_priv->psr.y_cord_support) {
> +		psr_vsc.sdp_header.HB2 = 0x5;
> +		psr_vsc.sdp_header.HB3 = 0x13;
> +	} else if (dev_priv->psr.y_cord_support) {
> +		psr_vsc.sdp_header.HB2 = 0x4;
> +		psr_vsc.sdp_header.HB3 = 0xe;
> +	} else {
> +		psr_vsc.sdp_header.HB2 = 0x3;
> +		psr_vsc.sdp_header.HB3 = 0xc;
> +	}
> +
>  	intel_psr_write_vsc(intel_dp, &psr_vsc);
>  }
>  
> -- 
> 1.9.1
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Re: [PATCH 10/10] drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2

[Rodrigo Vivi]

On Mon, Jan 02, 2017 at 05:01:03PM +0530, vathsala nagaraju wrote:
> PSR1 and PSR2 enable sequence are mutually exclusive.
> Register SRD_PERF_COUNT increments while system is in psr1.
> This register is not valid for psr2.while in psr2,SRD_PERF_COUNT
> is always 0.
> Reporting psr perfcount from SRD_PERF_COUNT is not valid for psr2 case.
> Also, if dc6 is disabled via kernel parameter i915.enable_dc=0,
> EDP_PSR_PERF_CNT can be reported for SKL+ platforms for debug
> purpose.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8b0e3f9..4136cec 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2539,6 +2539,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  	u32 stat[3];
>  	enum pipe pipe;
>  	bool enabled = false;
> +	bool dc6_enabled = false;
>  
>  	if (!HAS_PSR(dev_priv)) {
>  		seq_puts(m, "PSR not supported\n");
> @@ -2598,11 +2599,20 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  
>  	/*
>  	 * VLV/CHV PSR has no kind of performance counter
> +	 * EDP_PSR_PERF_CNT is not valid for psr2.
>  	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
> +	 * if we want to read EDP_PSR_PERF_CNT for debug purpose on SKL+,
> +	 * disable dc state in kernel parameter i915.enable_dc=0.
>  	 */
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> +
> +	dc6_enabled = ((I915_READ(DC_STATE_EN) &
> +			DC_STATE_EN_UPTO_DC5_DC6_MASK) ==
> +			DC_STATE_EN_UPTO_DC6);

I don't like this approach because if here on this line there is no
guarantee anymore that DC state is not enabled.
Ideally DC state is enabled most of the time so let's just avoid
the perf counter 0 that just confuses people.

> +
> +	if ((!dev_priv->psr.psr2_support && !dc6_enabled) ||
> +	     IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>  		psrperf = I915_READ(EDP_PSR_PERF_CNT) &
> -			EDP_PSR_PERF_CNT_MASK;
> +			  EDP_PSR_PERF_CNT_MASK;
>  
>  		seq_printf(m, "Performance_Counter: %u\n", psrperf);
>  	}
> -- 
> 1.9.1
> 
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Re: [PATCH 09/10] drm/i915/psr: report live PSR2 State

[Rodrigo Vivi]

I like this live status!

On Mon, Jan 02, 2017 at 05:01:02PM +0530, vathsala nagaraju wrote:
> Reports  live state of PSR2 form PSR2_STATUS register.
> bit field 31:28 gives the live state of PSR2.
> It can be used to check if system is in deep sleep,
> selective update or selective update standby.
> During video play back, we can use this to check
> if system is entering SU mode or not.
> when system is in idle state, DEEP_SLEEP(8) must be entered.
> When video playback is happening, system must be in
> SLEEP(3 / selective update) or SU_STANDBY( 6 / selective update standby)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 24 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h     |  2 ++
>  2 files changed, 26 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 9d7b5a8..8b0e3f9 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2606,6 +2606,30 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  
>  		seq_printf(m, "Performance_Counter: %u\n", psrperf);
>  	}
> +	if (dev_priv->psr.psr2_support) {
> +		static const char * const live_status[] = {
> +							"IDLE",
> +							"CAPTURE",
> +							"CAPTURE_Fs",

Fs? all others are fully capital

> +							"SLEEP",
> +							"BUFON_FW",
> +							"ML_UP",
> +							"SU_STANDBY",
> +							"FAST_SLEEP",
> +							"DEEP_SLEEP",
> +							"BUF_ON",
> +							"TG_ON" };
> +		u8 pos = (I915_READ(EDP_PSR2_STATUS_CTL) &
> +			EDP_PSR2_STATUS_STATE_MASK) >>
> +			EDP_PSR2_STATUS_STATE_SHIFT;
> +
> +		seq_printf(m, "PSR2_STATUS_EDP: %x\n",
> +			I915_READ(EDP_PSR2_STATUS_CTL));
> +
> +		if (pos <= EDP_PSR2_STATUS_TG_ON)

I like this protection...

> +		seq_printf(m, "PSR2 live state %s\n",
> +			live_status[pos]);
> +	}
>  	mutex_unlock(&dev_priv->psr.lock);
>  
>  	intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0cbe564..03a14d9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3624,6 +3624,8 @@ enum {
>  
>  #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> +#define EDP_PSR2_STATUS_STATE_SHIFT    28
> +#define EDP_PSR2_STATUS_TG_ON          0xa

... but I don't like how this TG_ON is defined,
because following the general style
EDP_PSR2_STATUS_TG_ON should be (0xa<<28)
so it might confuse people...

maybe just remove this and use the protection with size of live_status?


>  
>  /* VGA port control */
>  #define ADPA			_MMIO(0x61100)
> -- 
> 1.9.1
> 
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Re: [PATCH 08/10] drm/i915/psr: enable psr2 for y cordinate panels

[Rodrigo Vivi]

On Mon, Jan 02, 2017 at 05:01:01PM +0530, vathsala nagaraju wrote:
> Psr2 is enabled only for y cordinate panels.Once GTC (global time code)
> is implemented,this restriction is removed so that psr2
> can work on panels without y cordinate support.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 19cd4d7..ca3ef3e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -495,6 +495,15 @@ void intel_psr_enable(struct intel_dp *intel_dp)

I believe the better place for this code is on the match_conditions function...

>  		return;
>  	}
>  
> +	/*
> +	 * FIXME:enable psr2 only for y-cordinate psr2 panels
> +	 * After gtc implementation , remove this restriction.
> +	 */
> +	if (!dev_priv->psr.y_cord_support &&  dev_priv->psr.psr2_support) {
> +		DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n");
> +		return;
> +	}
> +
>  	mutex_lock(&dev_priv->psr.lock);
>  	if (dev_priv->psr.enabled) {
>  		DRM_DEBUG_KMS("PSR already in use\n");
> -- 
> 1.9.1
> 
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Re: [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

[Rodrigo Vivi]

Please don't forget about the bit 11 for KBL. In a separated patch.

This patch is correct and count with my rv-b, but I believe the best place for this is 
on intel_psr_enable, right after setup_vsc.

On Mon, Jan 02, 2017 at 05:00:59PM +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 7 +++++++
>  drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
>  #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>  
> +#define CHICKEN_TRANS_A         0x420c0
> +#define CHICKEN_TRANS_B         0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP              3
> +#define CHICKEN_TRANS_BIT12    (1<<12)
> +#define CHICKEN_TRANS_BIT15    (1<<15)
> +
>  #define DISP_ARB_CTL	_MMIO(0x45000)
>  #define  DISP_FBC_MEMORY_WAKE		(1<<31)
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 494e4b2..2e75ef6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -332,6 +332,7 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	uint32_t val = EDP_PSR_ENABLE;
> +	uint32_t chicken_trans = 0;
>  
>  	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> @@ -349,6 +350,12 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
>  	else
>  		val |= EDP_PSR2_TP2_TIME_50;
>  
> +	/* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
> +	if (dev_priv->psr.y_cord_support)
> +		chicken_trans = CHICKEN_TRANS_BIT15;
> +	/* Set CHICKEN_TRANS_BIT12 for programable header */
> +	chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
> +	I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
>  
> -- 
> 1.9.1
> 
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Re: [PATCH 04/10] drm/i915/psr: disable aux_frame_sync on psr2 exit

[Rodrigo Vivi]

makes sense


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


On Mon, Jan 02, 2017 at 05:00:57PM +0530, vathsala nagaraju wrote:
> Screen freeze observed if AUX_FRAME_SYNC is not disabled
> on psr2 exit.AUX_FRAME_SYNC needed for psr2 is enabled during
> psr2 entry. It must be disabled on psr2 exit.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index ff2ecfd..93eb0f0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -589,6 +589,11 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
>  	if (dev_priv->psr.active) {
> +		if (dev_priv->psr.aux_frame_sync)
> +			drm_dp_dpcd_writeb(&intel_dp->aux,
> +					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
> +					0);
> +
>  		if (dev_priv->psr.psr2_support)
>  			I915_WRITE(EDP_PSR2_CTL,
>  				I915_READ(EDP_PSR2_CTL) &
> @@ -729,6 +734,10 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
>  		return;
>  
>  	if (HAS_DDI(dev_priv)) {
> +		if (dev_priv->psr.aux_frame_sync)
> +			drm_dp_dpcd_writeb(&intel_dp->aux,
> +					DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
> +					0);
>  		if (dev_priv->psr.psr2_support) {
>  			val = I915_READ(EDP_PSR2_CTL);
>  			WARN_ON(!(val & EDP_PSR2_ENABLE));
> -- 
> 1.9.1
> 
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Re: [PATCH 03/10] drm/i915/psr: fix blank screen issue for psr2

[Rodrigo Vivi]

On Mon, Jan 02, 2017 at 05:00:56PM +0530, vathsala nagaraju wrote:
> Psr1 and psr2 are mutually exclusive,ie when psr2 is enabled,
> psr1 should be disabled.When psr2 is exited , bit 31 of reg
> PSR2_CTL must be set to 0 but currently bit 31 of SRD_CTL
> (psr1 control register)is set to 0.
> Also ,PSR2_IDLE state is looked up from SRD_STATUS(psr1 register)
> instead of PSR2_STATUS register, which has wrong data, resulting
> in blankscreen.
> hsw_enable_source is split into hsw_enable_source_psr1 and
> hsw_enable_source_psr2 for easier code review and maintenance,
> as suggested by rodrigo and jim.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   3 +
>  drivers/gpu/drm/i915/intel_psr.c | 124 +++++++++++++++++++++++++++++----------
>  2 files changed, 97 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00970aa..7830e6e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3615,6 +3615,9 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK		0xf
>  
> +#define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
> +#define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> +
>  /* VGA port control */
>  #define ADPA			_MMIO(0x61100)
>  #define PCH_ADPA                _MMIO(0xe1100)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index c3aa649..ff2ecfd 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -261,12 +261,11 @@ static void vlv_psr_activate(struct intel_dp *intel_dp)
>  		   VLV_EDP_PSR_ACTIVE_ENTRY);
>  }
>  
> -static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> +static void hsw_enable_source_psr1(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> -
>  	uint32_t max_sleep_time = 0x1f;
>  	/*
>  	 * Let's respect VBT in case VBT asks a higher idle_frame value.
> @@ -312,14 +311,30 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>  		val |= EDP_PSR_TP1_TP2_SEL;
>  
>  	I915_WRITE(EDP_PSR_CTL, val);
> +}
>  
> -	if (!dev_priv->psr.psr2_support)
> -		return;
> +static void hsw_enable_source_psr2(struct intel_dp *intel_dp)

hm... I believe
skl_enable_source_psr2 is more appropriated because psr2 was introduced on skl
and not on hsw as this might lead people to think...
although when we call this we check for psr2 presence and not platform itself.

maybe just let hsw_ on the main one
hsw_psr_enable_source

 and for these 2 new functions just use

intel_enable_source_psr1
intel_enable_source_psr2

> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +
> +	/*
> +	 * Let's respect VBT in case VBT asks a higher idle_frame value.
> +	 * Let's use 6 as the minimum to cover all known cases including
> +	 * the off-by-one issue that HW has in some cases. Also there are
> +	 * cases where sink should be able to train
> +	 * with the 5 or 6 idle patterns.
> +	 */
> +	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> +	uint32_t val = EDP_PSR_ENABLE;
> +
> +	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
>  	/* FIXME: selective update is probably totally broken because it doesn't
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
> -	val = EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> +	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;
> @@ -333,6 +348,20 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
>  
> +
> +static void hsw_psr_enable_source(struct intel_dp *intel_dp)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_device *dev = dig_port->base.base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +
> +	/* psr1 and psr2 are mutually exclusive.*/
> +	if (dev_priv->psr.psr2_support)
> +		hsw_enable_source_psr2(intel_dp);
> +	else
> +		hsw_enable_source_psr1(intel_dp);
> +}
> +
>  static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> @@ -410,7 +439,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
> -	WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> +	if (dev_priv->psr.psr2_support)
> +		WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
> +	else
> +		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>  	WARN_ON(dev_priv->psr.active);
>  	lockdep_assert_held(&dev_priv->psr.lock);
>  
> @@ -462,8 +494,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  	dev_priv->psr.busy_frontbuffer_bits = 0;
>  
>  	if (HAS_DDI(dev_priv)) {
> -		hsw_psr_setup_vsc(intel_dp);
> -
>  		if (dev_priv->psr.psr2_support) {
>  			/* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
>  			if (crtc->config->pipe_src_w > 3200 ||
> @@ -471,8 +501,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  				dev_priv->psr.psr2_support = false;
>  			else
>  				skl_psr_setup_su_vsc(intel_dp);
> +		} else {
> +			/* set up vsc header for psr1 */
> +			hsw_psr_setup_vsc(intel_dp);
>  		}
> -
>  		/*
>  		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
>  		 * Also mask LPSP to avoid dependency on other drivers that
> @@ -557,20 +589,37 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
>  	if (dev_priv->psr.active) {
> -		I915_WRITE(EDP_PSR_CTL,
> -			   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
> +		if (dev_priv->psr.psr2_support)
> +			I915_WRITE(EDP_PSR2_CTL,
> +				I915_READ(EDP_PSR2_CTL) &
> +					~(EDP_PSR2_ENABLE |
> +					EDP_SU_TRACK_ENABLE));
> +		else
> +			I915_WRITE(EDP_PSR_CTL,
> +				   I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
>  
>  		/* Wait till PSR is idle */
> -		if (intel_wait_for_register(dev_priv,
> -					    EDP_PSR_STATUS_CTL,
> -					    EDP_PSR_STATUS_STATE_MASK,
> -					    0,
> -					    2000))
> +		if (dev_priv->psr.psr2_support) {
> +			if (intel_wait_for_register(dev_priv,
> +						    EDP_PSR2_STATUS_CTL,
> +						    EDP_PSR2_STATUS_STATE_MASK,
> +						    0,
> +						    2000))
> +			DRM_ERROR("Timed out waiting for PSR2 Idle State\n");
> +		} else {
> +			if (intel_wait_for_register(dev_priv,
> +						    EDP_PSR_STATUS_CTL,
> +						    EDP_PSR_STATUS_STATE_MASK,
> +						    0,
> +						    2000))
>  			DRM_ERROR("Timed out waiting for PSR Idle State\n");
> -
> +		}
>  		dev_priv->psr.active = false;
>  	} else {
> -		WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
> +		if (dev_priv->psr.psr2_support)
> +			WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE);
> +		else
> +			WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE);
>  	}
>  }
>  
> @@ -621,13 +670,24 @@ static void intel_psr_work(struct work_struct *work)
>  	 * and be ready for re-enable.
>  	 */
>  	if (HAS_DDI(dev_priv)) {
> -		if (intel_wait_for_register(dev_priv,
> -					    EDP_PSR_STATUS_CTL,
> -					    EDP_PSR_STATUS_STATE_MASK,
> -					    0,
> -					    50)) {
> -			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
> -			return;
> +		if (dev_priv->psr.psr2_support) {
> +			if (intel_wait_for_register(dev_priv,
> +						EDP_PSR2_STATUS_CTL,
> +						EDP_PSR2_STATUS_STATE_MASK,
> +						0,
> +						50)) {
> +				DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
> +				return;
> +			}
> +		} else {
> +			if (intel_wait_for_register(dev_priv,
> +						EDP_PSR_STATUS_CTL,
> +						EDP_PSR_STATUS_STATE_MASK,
> +						0,
> +						50)) {
> +				DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
> +				return;
> +			}
>  		}
>  	} else {
>  		if (intel_wait_for_register(dev_priv,
> @@ -669,11 +729,15 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
>  		return;
>  
>  	if (HAS_DDI(dev_priv)) {
> -		val = I915_READ(EDP_PSR_CTL);
> -
> -		WARN_ON(!(val & EDP_PSR_ENABLE));
> -
> -		I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
> +		if (dev_priv->psr.psr2_support) {
> +			val = I915_READ(EDP_PSR2_CTL);
> +			WARN_ON(!(val & EDP_PSR2_ENABLE));
> +			I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
> +		} else {
> +			val = I915_READ(EDP_PSR_CTL);
> +			WARN_ON(!(val & EDP_PSR_ENABLE));
> +			I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE);
> +		}
>  	} else {
>  		val = I915_READ(VLV_PSRCTL(pipe));
>  
> -- 
> 1.9.1
> 
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Re: [PATCH 05/10] drm/i915/psr: enable ALPM for psr2

[Jim Bride]

On Mon, Jan 02, 2017 at 05:00:58PM +0530, vathsala nagaraju wrote:
> As per edp1.4 spec , alpm is required for psr2 operation as it's
> used for all psr2  main link power down management and alpm enable
> bit must be set for psr2 operation.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>  drivers/gpu/drm/i915/intel_dp.c  | 10 ++++++++++
>  drivers/gpu/drm/i915/intel_psr.c |  6 +++++-
>  3 files changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 36dc835..0742b81 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1166,6 +1166,7 @@ struct i915_psr {
>  	bool link_standby;
>  	bool y_cord_support;
>  	bool colorimetry_support;
> +	bool alpm;
>  };
>  
>  enum intel_pch {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index da577c9..9b313a3 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3060,6 +3060,14 @@ static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>  	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
>  }
>  
> +bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
> +{
> +	uint8_t alpm_caps = 0;
> +
> +	drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
> +	return alpm_caps & DP_ALPM_CAP;
> +}
> +
>  /* These are source-specific values. */
>  uint8_t
>  intel_dp_voltage_max(struct intel_dp *intel_dp)
> @@ -3644,6 +3652,8 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
>  				intel_dp_get_y_cord_status(intel_dp);
>  			dev_priv->psr.colorimetry_support =
>  				intel_dp_get_colorimetry_status(intel_dp);
> +			dev_priv->psr.alpm =
> +				intel_dp_get_alpm_status(intel_dp);
>  		}
>  
>  	}
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 93eb0f0..494e4b2 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -209,7 +209,11 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>  		drm_dp_dpcd_writeb(&intel_dp->aux,
>  				DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
>  				DP_AUX_FRAME_SYNC_ENABLE);
> -
> +	/* Enable ALPM at sink for psr2 */
> +	if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
> +		drm_dp_dpcd_writeb(&intel_dp->aux,
> +				DP_RECEIVER_ALPM_CONFIG,
> +				DP_ALPM_ENABLE);
>  	if (dev_priv->psr.link_standby)
>  		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>  				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
> -- 
> 1.9.1
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Re: [Intel-gfx] [PATCH 01/10] drm : adds Y-coordinate and Colorimetry Format

[Rodrigo Vivi]

[-- Attachment #1.1: Type: text/plain, Size: 3349 bytes --]

patch merged to dinq. thanks for patch and review.

On Mon, Jan 2, 2017 at 3:34 AM vathsala nagaraju <
vathsala.nagaraju@intel.com> wrote:

> PSR2 vsc revision number hb2( as per table 6-11)is updated to
> 4 or 5 based on Y cordinate and Colorimetry Format as below
> 04h = 3D stereo + PSR/PSR2 + Y-coordinate.
> 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
> Format indication. A DP Source device is allowed to indicate the pixel
> encoding/colorimetry format to the DP Sink device with VSC SDP only when
> the DP Sink device supports it (
> i.e.,VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
> DPRX_FEATURE_ENUMERATION_LIST register (DPCD Address 02210h, bit 3;
> is set to 1).
>
> v2: (Jani)
> - Change DP_PSR_Y_COORDINATE to DP_PSR2_SU_Y_COORDINATE_REQUIRED.
> - Add DP_PSR2_SU_GRANULARITY_REQUIRED.
> - Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX.
> - Add GTC_CAP and AV_SYNC_CAP, other bits in DPRX_FEATURE_ENUMERATION_LIST.
>
> v3: (Jani)
> - Add support for bits 7:4 and 1 as per DP v1.4 for
>   DPRX_FEATURE_ENUMERATION_LIST.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 55bbeb0..0468135 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -194,7 +194,8 @@
>  # define DP_PSR_SETUP_TIME_0                (6 << 1)
>  # define DP_PSR_SETUP_TIME_MASK             (7 << 1)
>  # define DP_PSR_SETUP_TIME_SHIFT            1
> -
> +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED   (1 << 4)  /* eDP 1.4a */
> +# define DP_PSR2_SU_GRANULARITY_REQUIRED    (1 << 5)  /* eDP 1.4b */
>  /*
>   * 0x80-0x8f describe downstream port capabilities, but there are two
> layouts
>   * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was
> not,
> @@ -568,6 +569,16 @@
>  #define DP_RECEIVER_ALPM_STATUS                    0x200b  /* eDP 1.4 */
>  # define DP_ALPM_LOCK_TIMEOUT_ERROR        (1 << 0)
>
> +#define DP_DPRX_FEATURE_ENUMERATION_LIST    0x2210  /* DP 1.3 */
> +# define DP_GTC_CAP                                    (1 << 0)  /* DP
> 1.3 */
> +# define DP_SST_SPLIT_SDP_CAP                          (1 << 1)  /* DP
> 1.4 */
> +# define DP_AV_SYNC_CAP                                        (1 << 2)
> /* DP 1.3 */
> +# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED      (1 << 3)  /* DP
> 1.3 */
> +# define DP_VSC_EXT_VESA_SDP_SUPPORTED                 (1 << 4)  /* DP
> 1.4 */
> +# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED                (1 << 5)
> /* DP 1.4 */
> +# define DP_VSC_EXT_CEA_SDP_SUPPORTED                  (1 << 6)  /* DP
> 1.4 */
> +# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED         (1 << 7)  /* DP
> 1.4 */
> +
>  /* DP 1.2 Sideband message defines */
>  /* peer device type - DP 1.2a Table 2-92 */
>  #define DP_PEER_DEVICE_NONE            0x0
> --
> 1.9.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 02/10] drm/i915/psr: program vsc header for psr2

[Rodrigo Vivi]

[-- Attachment #1.1: Type: text/plain, Size: 5269 bytes --]

patch merged to dinq. thanks for patch and review.

On Wed, Jan 4, 2017 at 3:48 PM Jim Bride <jim.bride@linux.intel.com> wrote:

> On Mon, Jan 02, 2017 at 05:00:55PM +0530, vathsala nagaraju wrote:
> > Function hsw_psr_setup handles vsc header setup for psr1 and
> > skl_psr_setup_vsc handles vsc header setup for psr2.
> >
> > Setup VSC header in function skl_psr_setup_vsc for psr2 support,
> > as per edp 1.4 spec, table 6-11:VSC SDP HEADER Extension for psr2
> > operation.
> >
> > v2: (Jani)
> > - Initialize variables to 0
> > - intel_dp_get_y_cord_status and intel_dp_get_y_cord_status made static
> > - Correct indentation for continuation lines
> > - Change DP_PSR_Y_COORDINATE to  DP_PSR2_SU_Y_COORDINATE_REQUIRED
> > - Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX_*
> > - Change VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED to DP_VSC_*
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jim Bride <jim.bride@linux.intel.com>
> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > Signed-off-by: Patil Deepti <deepti.patil@intel.com>
>
> Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h  |  2 ++
> >  drivers/gpu/drm/i915/intel_dp.c  | 26 ++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_psr.c | 17 +++++++++++++++--
> >  3 files changed, 43 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> > index 22d3f61..36dc835 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1164,6 +1164,8 @@ struct i915_psr {
> >       bool psr2_support;
> >       bool aux_frame_sync;
> >       bool link_standby;
> > +     bool y_cord_support;
> > +     bool colorimetry_support;
> >  };
> >
> >  enum intel_pch {
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> > index fb12896..da577c9 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3042,6 +3042,24 @@ static void chv_dp_post_pll_disable(struct
> intel_encoder *encoder,
> >                               DP_LINK_STATUS_SIZE) ==
> DP_LINK_STATUS_SIZE;
> >  }
> >
> > +static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
> > +{
> > +     uint8_t psr_caps = 0;
> > +
> > +     drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps);
> > +     return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
> > +}
> > +
> > +static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
> > +{
> > +     uint8_t dprx = 0;
> > +
> > +     drm_dp_dpcd_readb(&intel_dp->aux,
> > +                     DP_DPRX_FEATURE_ENUMERATION_LIST,
> > +                     &dprx);
> > +     return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
> > +}
> > +
> >  /* These are source-specific values. */
> >  uint8_t
> >  intel_dp_voltage_max(struct intel_dp *intel_dp)
> > @@ -3620,6 +3638,14 @@ void intel_dp_set_idle_link_train(struct intel_dp
> *intel_dp)
> >               dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
> >               DRM_DEBUG_KMS("PSR2 %s on sink",
> >                             dev_priv->psr.psr2_support ? "supported" :
> "not supported");
> > +
> > +             if (dev_priv->psr.psr2_support) {
> > +                     dev_priv->psr.y_cord_support =
> > +                             intel_dp_get_y_cord_status(intel_dp);
> > +                     dev_priv->psr.colorimetry_support =
> > +                             intel_dp_get_colorimetry_status(intel_dp);
> > +             }
> > +
> >       }
> >
> >       /* Read the eDP Display control capabilities registers */
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> > index 6aca8ff..c3aa649 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -122,13 +122,26 @@ static void vlv_psr_setup_vsc(struct intel_dp
> *intel_dp)
> >  static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
> >  {
> >       struct edp_vsc_psr psr_vsc;
> > +     struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> > +     struct drm_device *dev = intel_dig_port->base.base.dev;
> > +     struct drm_i915_private *dev_priv = to_i915(dev);
> >
> >       /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
> >       memset(&psr_vsc, 0, sizeof(psr_vsc));
> >       psr_vsc.sdp_header.HB0 = 0;
> >       psr_vsc.sdp_header.HB1 = 0x7;
> > -     psr_vsc.sdp_header.HB2 = 0x3;
> > -     psr_vsc.sdp_header.HB3 = 0xb;
> > +     if (dev_priv->psr.colorimetry_support &&
> > +             dev_priv->psr.y_cord_support) {
> > +             psr_vsc.sdp_header.HB2 = 0x5;
> > +             psr_vsc.sdp_header.HB3 = 0x13;
> > +     } else if (dev_priv->psr.y_cord_support) {
> > +             psr_vsc.sdp_header.HB2 = 0x4;
> > +             psr_vsc.sdp_header.HB3 = 0xe;
> > +     } else {
> > +             psr_vsc.sdp_header.HB2 = 0x3;
> > +             psr_vsc.sdp_header.HB3 = 0xc;
> > +     }
> > +
> >       intel_psr_write_vsc(intel_dp, &psr_vsc);
> >  }
> >
> > --
> > 1.9.1
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH 01/10] drm : adds Y-coordinate and Colorimetry Format

[Daniel Vetter]

On Tue, Jan 10, 2017 at 11:43:51PM +0000, Rodrigo Vivi wrote:
> patch merged to dinq. thanks for patch and review.

I already pinged Rodrigo about this on irc, but drm core patches need an
ack from Dave for merging through a driver git tree. I've asked Rodrigo to
update the dim scripting to catch this so it won't happen in the future
again.

Thanks, Daniel

> 
> On Mon, Jan 2, 2017 at 3:34 AM vathsala nagaraju <
> vathsala.nagaraju@intel.com> wrote:
> 
> > PSR2 vsc revision number hb2( as per table 6-11)is updated to
> > 4 or 5 based on Y cordinate and Colorimetry Format as below
> > 04h = 3D stereo + PSR/PSR2 + Y-coordinate.
> > 05h = -3D stereo- + PSR/PSR2 + Y-coordinate + Pixel Encoding/Colorimetry
> > Format indication. A DP Source device is allowed to indicate the pixel
> > encoding/colorimetry format to the DP Sink device with VSC SDP only when
> > the DP Sink device supports it (
> > i.e.,VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the
> > DPRX_FEATURE_ENUMERATION_LIST register (DPCD Address 02210h, bit 3;
> > is set to 1).
> >
> > v2: (Jani)
> > - Change DP_PSR_Y_COORDINATE to DP_PSR2_SU_Y_COORDINATE_REQUIRED.
> > - Add DP_PSR2_SU_GRANULARITY_REQUIRED.
> > - Change DPRX_FEATURE_ENUMERATION_LIST to DP_DPRX.
> > - Add GTC_CAP and AV_SYNC_CAP, other bits in DPRX_FEATURE_ENUMERATION_LIST.
> >
> > v3: (Jani)
> > - Add support for bits 7:4 and 1 as per DP v1.4 for
> >   DPRX_FEATURE_ENUMERATION_LIST.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Jim Bride <jim.bride@linux.intel.com>
> > Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> > Signed-off-by: Patil Deepti <deepti.patil@intel.com>
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > ---
> >  include/drm/drm_dp_helper.h | 13 ++++++++++++-
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 55bbeb0..0468135 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -194,7 +194,8 @@
> >  # define DP_PSR_SETUP_TIME_0                (6 << 1)
> >  # define DP_PSR_SETUP_TIME_MASK             (7 << 1)
> >  # define DP_PSR_SETUP_TIME_SHIFT            1
> > -
> > +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED   (1 << 4)  /* eDP 1.4a */
> > +# define DP_PSR2_SU_GRANULARITY_REQUIRED    (1 << 5)  /* eDP 1.4b */
> >  /*
> >   * 0x80-0x8f describe downstream port capabilities, but there are two
> > layouts
> >   * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was
> > not,
> > @@ -568,6 +569,16 @@
> >  #define DP_RECEIVER_ALPM_STATUS                    0x200b  /* eDP 1.4 */
> >  # define DP_ALPM_LOCK_TIMEOUT_ERROR        (1 << 0)
> >
> > +#define DP_DPRX_FEATURE_ENUMERATION_LIST    0x2210  /* DP 1.3 */
> > +# define DP_GTC_CAP                                    (1 << 0)  /* DP
> > 1.3 */
> > +# define DP_SST_SPLIT_SDP_CAP                          (1 << 1)  /* DP
> > 1.4 */
> > +# define DP_AV_SYNC_CAP                                        (1 << 2)
> > /* DP 1.3 */
> > +# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED      (1 << 3)  /* DP
> > 1.3 */
> > +# define DP_VSC_EXT_VESA_SDP_SUPPORTED                 (1 << 4)  /* DP
> > 1.4 */
> > +# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED                (1 << 5)
> > /* DP 1.4 */
> > +# define DP_VSC_EXT_CEA_SDP_SUPPORTED                  (1 << 6)  /* DP
> > 1.4 */
> > +# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED         (1 << 7)  /* DP
> > 1.4 */
> > +
> >  /* DP 1.2 Sideband message defines */
> >  /* peer device type - DP 1.2a Table 2-92 */
> >  #define DP_PEER_DEVICE_NONE            0x0
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >

> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 05/10] drm/i915/psr: enable ALPM for psr2

[Rodrigo Vivi]

patches 3, 4 and 5 merged to dinq.
Thanks for patches and reviews.

On Thu, Jan 5, 2017 at 12:38 PM, Jim Bride <jim.bride@linux.intel.com> wrote:
> On Mon, Jan 02, 2017 at 05:00:58PM +0530, vathsala nagaraju wrote:
>> As per edp1.4 spec , alpm is required for psr2 operation as it's
>> used for all psr2  main link power down management and alpm enable
>> bit must be set for psr2 operation.
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Jim Bride <jim.bride@linux.intel.com>
>> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
>> Signed-off-by: Patil Deepti <deepti.patil@intel.com>
>
> Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h  |  1 +
>>  drivers/gpu/drm/i915/intel_dp.c  | 10 ++++++++++
>>  drivers/gpu/drm/i915/intel_psr.c |  6 +++++-
>>  3 files changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 36dc835..0742b81 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1166,6 +1166,7 @@ struct i915_psr {
>>       bool link_standby;
>>       bool y_cord_support;
>>       bool colorimetry_support;
>> +     bool alpm;
>>  };
>>
>>  enum intel_pch {
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index da577c9..9b313a3 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -3060,6 +3060,14 @@ static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
>>       return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
>>  }
>>
>> +bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
>> +{
>> +     uint8_t alpm_caps = 0;
>> +
>> +     drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps);
>> +     return alpm_caps & DP_ALPM_CAP;
>> +}
>> +
>>  /* These are source-specific values. */
>>  uint8_t
>>  intel_dp_voltage_max(struct intel_dp *intel_dp)
>> @@ -3644,6 +3652,8 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
>>                               intel_dp_get_y_cord_status(intel_dp);
>>                       dev_priv->psr.colorimetry_support =
>>                               intel_dp_get_colorimetry_status(intel_dp);
>> +                     dev_priv->psr.alpm =
>> +                             intel_dp_get_alpm_status(intel_dp);
>>               }
>>
>>       }
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 93eb0f0..494e4b2 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -209,7 +209,11 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
>>               drm_dp_dpcd_writeb(&intel_dp->aux,
>>                               DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
>>                               DP_AUX_FRAME_SYNC_ENABLE);
>> -
>> +     /* Enable ALPM at sink for psr2 */
>> +     if (dev_priv->psr.psr2_support && dev_priv->psr.alpm)
>> +             drm_dp_dpcd_writeb(&intel_dp->aux,
>> +                             DP_RECEIVER_ALPM_CONFIG,
>> +                             DP_ALPM_ENABLE);
>>       if (dev_priv->psr.link_standby)
>>               drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
>>                                  DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
>> --
>> 1.9.1
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
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[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[vathsala nagaraju]

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

v2: (Ilia Mirkin)
- Remove duplicate bit definition 25:27

v3: rebase

v4: rebase

v5: rebase

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 10 +++++++---
 drivers/gpu/drm/i915/intel_psr.c | 30 ++++++++++++++++++++----------
 2 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9c1ccd..ca76887 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3597,9 +3597,12 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
 #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -3614,6 +3617,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 935402e..3611c42 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -338,7 +338,9 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE |
+		EDP_SU_TRACK_ENABLE |
+		EDP_FRAMES_BEFORE_SU_ENTRY;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
@@ -512,20 +514,28 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 			if (dev_priv->psr.y_cord_support)
 				chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
 			I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP |
+				   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+				   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 		} else {
 			/* set up vsc header for psr1 */
 			hsw_psr_setup_vsc(intel_dp);
+			/*
+			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+			 * and HPD. also mask LPSP to avoid dependency on other
+			 * drivers that might block runtime_pm besides
+			 * preventing  other hw tracking issues now we can rely
+			 * on frontbuffer tracking.
+			 */
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP);
 		}
 
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-		 * Also mask LPSP to avoid dependency on other drivers that
-		 * might block runtime_pm besides preventing other hw tracking
-		 * issues now we can rely on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
-
 		/* Enable PSR on the panel */
 		hsw_psr_enable_sink(intel_dp);
 
-- 
1.9.1

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[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[vathsala nagaraju]

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

v2: (Ilia Mirkin)
- Remove duplicate bit definition 25:27

v3: rebase

v4: rebase

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 10 +++++++---
 drivers/gpu/drm/i915/intel_psr.c | 31 ++++++++++++++++++++-----------
 2 files changed, 27 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7a325fb..6ad9f06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3597,9 +3597,12 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
 #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -3614,6 +3617,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b582220..f9d620b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -338,7 +338,9 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE |
+		EDP_SU_TRACK_ENABLE |
+		EDP_FRAMES_BEFORE_SU_ENTRY;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
@@ -510,20 +512,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 			if (dev_priv->psr.y_cord_support)
 				chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
 			I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken);
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP |
+				   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+				   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 		} else {
 			/* set up vsc header for psr1 */
 			hsw_psr_setup_vsc(intel_dp);
+			/*
+			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+			 * and HPD. also mask LPSP to avoid dependency on other
+			 * drivers that might block runtime_pm besides
+			 * preventing  other hw tracking issues now we can rely
+			 * on frontbuffer tracking.
+			 */
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP);
 		}
-
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-		 * Also mask LPSP to avoid dependency on other drivers that
-		 * might block runtime_pm besides preventing other hw tracking
-		 * issues now we can rely on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
-
 		/* Enable PSR on the panel */
 		hsw_psr_enable_sink(intel_dp);
 
-- 
1.9.1

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[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[vathsala nagaraju]

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

v2: (Ilia Mirkin)
- Remove duplicate bit definition 25:27

v3: rebase

v4: rebase

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 10 +++++++---
 drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
 2 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca506a..272a283 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3597,9 +3597,12 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
 #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -3614,6 +3617,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7573c2f..fd151b9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -338,7 +338,9 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE |
+		EDP_SU_TRACK_ENABLE |
+		EDP_FRAMES_BEFORE_SU_ENTRY;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
@@ -511,18 +513,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 			if (dev_priv->psr.y_cord_support)
 				chicken_trans |= CHICKEN_TRANS_BIT15;
 			I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP |
+				   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+				   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 		} else {
 			/* set up vsc header for psr1 */
 			hsw_psr_setup_vsc(intel_dp);
+			/*
+			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+			 * and HPD. also mask LPSP to avoid dependency on other
+			 * drivers that might block runtime_pm besides
+			 * preventing  other hw tracking issues now we can rely
+			 * on frontbuffer tracking.
+			 */
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP);
 		}
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-		 * Also mask LPSP to avoid dependency on other drivers that
-		 * might block runtime_pm besides preventing other hw tracking
-		 * issues now we can rely on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 
 		/* Enable PSR on the panel */
 		hsw_psr_enable_sink(intel_dp);
-- 
1.9.1

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[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[vathsala nagaraju]

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

v2: (Ilia Mirkin)
- Remove duplicate bit definition 25:27

v3: rebase

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
Reviewed-by: Jim Bride <jim.bride@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 10 +++++++---
 drivers/gpu/drm/i915/intel_psr.c | 22 ++++++++++++++++++++--
 2 files changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca506a..272a283 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3597,9 +3597,12 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
 #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -3614,6 +3617,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index bcfe0db..05efd4e 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -338,8 +338,9 @@ static void intel_enable_source_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
-
+	val |= EDP_PSR2_ENABLE |
+		EDP_SU_TRACK_ENABLE |
+		EDP_FRAMES_BEFORE_SU_ENTRY;
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
@@ -512,9 +513,26 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 			/* Set CHICKEN_TRANS_BIT12 for programable header */
 			chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
 			I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP |
+				   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+				   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 		} else {
 			/* set up vsc header for psr1 */
 			hsw_psr_setup_vsc(intel_dp);
+			/*
+			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+			 * and HPD. also mask LPSP to avoid dependency on other
+			 * drivers that might block runtime_pm besides
+			 * preventing  other hw tracking issues now we can rely
+			 * on frontbuffer tracking.
+			 */
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP);
 		}
 		/*
 		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-- 
1.9.1

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Re: [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[Jim Bride]

On Tue, Jan 03, 2017 at 10:27:51PM +0530, vathsala nagaraju wrote:
> Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
> to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
> should report value 8 , if system enters deep sleep state.
> 
> Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
> flickering is observed on psr2 panel.
> 
> v2: (Ilia Mirkin)
> - Remove duplicate bit definition 25:27
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Jim Bride <jim.bride@linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
> Signed-off-by: Patil Deepti <deepti.patil@intel.com>

Reviewed-by: Jim Bride <jim.bride@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 10 +++++++---
>  drivers/gpu/drm/i915/intel_dp.c  |  1 -
>  drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
>  3 files changed, 27 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5ca506a..272a283 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3597,9 +3597,12 @@ enum {
>  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
>  
>  #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
> -#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
> -#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
> -#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
> +#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
> +#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
> +#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
> +#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
> +#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
> +#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
>  
>  #define EDP_PSR2_CTL			_MMIO(0x6f900)
>  #define   EDP_PSR2_ENABLE		(1<<31)
> @@ -3614,6 +3617,7 @@ enum {
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
>  #define   EDP_PSR2_IDLE_MASK		0xf
> +#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
>  
>  #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 9b313a3..0a10858 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3655,7 +3655,6 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
>  			dev_priv->psr.alpm =
>  				intel_dp_get_alpm_status(intel_dp);
>  		}
> -
>  	}
>  
>  	/* Read the eDP Display control capabilities registers */
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2e75ef6..19cd4d7 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -339,7 +339,9 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
>  	/* FIXME: selective update is probably totally broken because it doesn't
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
> -	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
> +	val |= EDP_PSR2_ENABLE |
> +		EDP_SU_TRACK_ENABLE |
> +		EDP_FRAMES_BEFORE_SU_ENTRY;
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;
> @@ -512,18 +514,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  				dev_priv->psr.psr2_support = false;
>  			else
>  				skl_psr_setup_su_vsc(intel_dp);
> +				I915_WRITE(EDP_PSR_DEBUG_CTL,
> +					   EDP_PSR_DEBUG_MASK_MEMUP |
> +					   EDP_PSR_DEBUG_MASK_HPD |
> +					   EDP_PSR_DEBUG_MASK_LPSP |
> +					   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
> +					   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
>  		} else {
>  			/* set up vsc header for psr1 */
>  			hsw_psr_setup_vsc(intel_dp);
> +			/*
> +			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
> +			 * and HPD. also mask LPSP to avoid dependency on other
> +			 * drivers that might block runtime_pm besides
> +			 * preventing  other hw tracking issues now we can rely
> +			 * on frontbuffer tracking.
> +			 */
> +			I915_WRITE(EDP_PSR_DEBUG_CTL,
> +				   EDP_PSR_DEBUG_MASK_MEMUP |
> +				   EDP_PSR_DEBUG_MASK_HPD |
> +				   EDP_PSR_DEBUG_MASK_LPSP);
>  		}
> -		/*
> -		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
> -		 * Also mask LPSP to avoid dependency on other drivers that
> -		 * might block runtime_pm besides preventing other hw tracking
> -		 * issues now we can rely on frontbuffer tracking.
> -		 */
> -		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
> -			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
>  
>  		/* Enable PSR on the panel */
>  		hsw_psr_enable_sink(intel_dp);
> -- 
> 1.9.1
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[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[vathsala nagaraju]

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

v2: (Ilia Mirkin)
- Remove duplicate bit definition 25:27

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 10 +++++++---
 drivers/gpu/drm/i915/intel_dp.c  |  1 -
 drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
 3 files changed, 27 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca506a..272a283 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3597,9 +3597,12 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
 #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -3614,6 +3617,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9b313a3..0a10858 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3655,7 +3655,6 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 			dev_priv->psr.alpm =
 				intel_dp_get_alpm_status(intel_dp);
 		}
-
 	}
 
 	/* Read the eDP Display control capabilities registers */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2e75ef6..19cd4d7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -339,7 +339,9 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE |
+		EDP_SU_TRACK_ENABLE |
+		EDP_FRAMES_BEFORE_SU_ENTRY;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
@@ -512,18 +514,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 				dev_priv->psr.psr2_support = false;
 			else
 				skl_psr_setup_su_vsc(intel_dp);
+				I915_WRITE(EDP_PSR_DEBUG_CTL,
+					   EDP_PSR_DEBUG_MASK_MEMUP |
+					   EDP_PSR_DEBUG_MASK_HPD |
+					   EDP_PSR_DEBUG_MASK_LPSP |
+					   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+					   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 		} else {
 			/* set up vsc header for psr1 */
 			hsw_psr_setup_vsc(intel_dp);
+			/*
+			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+			 * and HPD. also mask LPSP to avoid dependency on other
+			 * drivers that might block runtime_pm besides
+			 * preventing  other hw tracking issues now we can rely
+			 * on frontbuffer tracking.
+			 */
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP);
 		}
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-		 * Also mask LPSP to avoid dependency on other drivers that
-		 * might block runtime_pm besides preventing other hw tracking
-		 * issues now we can rely on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 
 		/* Enable PSR on the panel */
 		hsw_psr_enable_sink(intel_dp);
-- 
1.9.1

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[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[vathsala nagaraju]

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Patil Deepti <deepti.patil@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  7 +++++++
 drivers/gpu/drm/i915/intel_dp.c  |  1 -
 drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
 3 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca506a..0cbe564 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3600,6 +3600,12 @@ enum {
 #define   EDP_PSR_DEBUG_MASK_LPSP	(1<<27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP	(1<<26)
 #define   EDP_PSR_DEBUG_MASK_HPD	(1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -3614,6 +3620,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK		0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)
 
 #define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9b313a3..0a10858 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3655,7 +3655,6 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
 			dev_priv->psr.alpm =
 				intel_dp_get_alpm_status(intel_dp);
 		}
-
 	}
 
 	/* Read the eDP Display control capabilities registers */
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2e75ef6..19cd4d7 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -339,7 +339,9 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
 	/* FIXME: selective update is probably totally broken because it doesn't
 	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 	 * good enough. */
-	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+	val |= EDP_PSR2_ENABLE |
+		EDP_SU_TRACK_ENABLE |
+		EDP_FRAMES_BEFORE_SU_ENTRY;
 
 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
 		val |= EDP_PSR2_TP2_TIME_2500;
@@ -512,18 +514,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 				dev_priv->psr.psr2_support = false;
 			else
 				skl_psr_setup_su_vsc(intel_dp);
+				I915_WRITE(EDP_PSR_DEBUG_CTL,
+					   EDP_PSR_DEBUG_MASK_MEMUP |
+					   EDP_PSR_DEBUG_MASK_HPD |
+					   EDP_PSR_DEBUG_MASK_LPSP |
+					   EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+					   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
 		} else {
 			/* set up vsc header for psr1 */
 			hsw_psr_setup_vsc(intel_dp);
+			/*
+			 * Per Spec: Avoid continuous PSR exit by masking MEMUP
+			 * and HPD. also mask LPSP to avoid dependency on other
+			 * drivers that might block runtime_pm besides
+			 * preventing  other hw tracking issues now we can rely
+			 * on frontbuffer tracking.
+			 */
+			I915_WRITE(EDP_PSR_DEBUG_CTL,
+				   EDP_PSR_DEBUG_MASK_MEMUP |
+				   EDP_PSR_DEBUG_MASK_HPD |
+				   EDP_PSR_DEBUG_MASK_LPSP);
 		}
-		/*
-		 * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-		 * Also mask LPSP to avoid dependency on other drivers that
-		 * might block runtime_pm besides preventing other hw tracking
-		 * issues now we can rely on frontbuffer tracking.
-		 */
-		I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-			   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
 
 		/* Enable PSR on the panel */
 		hsw_psr_enable_sink(intel_dp);
-- 
1.9.1

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