* [PATCH 0/6] Some more display uncore prep work
@ 2019-08-16 1:23 Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h Daniele Ceraolo Spurio
` (9 more replies)
0 siblings, 10 replies; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 1:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Since we want to tag registers as belonging to display, I believe it'd
be nice to move them to a dedicated header in the display folder and
include just that in .c files, to make sure we get the split right.
The first 4 patches of the series prepare i915_drv.h for being able to
not use definition from i915_reg.h (apart from i915_reg_t) and the
include is then replaced.
The last patch adds some wrappers to hide usage dev_priv->uncore in
register waits in the display code, to make it simpler to replace it
later.
I initially wanted to send this series together with the register move,
but that is proving to be more complex than anticipated due to the mess
in i915_reg.h, so I believe it warrants its own separate series
(assuming I do manage to sort the file out in the end).
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Daniele Ceraolo Spurio (6):
drm/i915: Move i915_power_well_id out of i915_reg.h
drm/i915: Move engine IDs out of i915_reg.h
drm/i915: Move gmbus definitions out of i915_reg.h
drm/i915: Dynamically allocate s0ix struct for VLV
drm/i915: Introduce i915_reg_types.h
drm/i915: Wrappers for display register waits
Documentation/gpu/i915.rst | 4 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_audio.c | 1 +
drivers/gpu/drm/i915/display/intel_bw.c | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 19 +-
drivers/gpu/drm/i915/display/intel_color.c | 1 +
.../gpu/drm/i915/display/intel_combo_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 18 +-
drivers/gpu/drm/i915/display/intel_crt.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +-
drivers/gpu/drm/i915/display/intel_display.c | 46 +--
.../drm/i915/display/intel_display_power.c | 34 +--
.../drm/i915/display/intel_display_power.h | 23 +-
drivers/gpu/drm/i915/display/intel_dp.c | 11 +-
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 6 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 45 +--
drivers/gpu/drm/i915/display/intel_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 +
drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 5 +-
.../drm/i915/display/intel_fifo_underrun.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.h | 22 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 33 +--
drivers/gpu/drm/i915/display/intel_hdmi.c | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.h | 2 +-
.../gpu/drm/i915/display/intel_lpe_audio.c | 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 1 +
drivers/gpu/drm/i915/display/intel_lvds.c | 7 +-
drivers/gpu/drm/i915/display/intel_lvds.h | 2 +-
drivers/gpu/drm/i915/display/intel_opregion.c | 1 +
drivers/gpu/drm/i915/display/intel_panel.c | 1 +
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.h | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
drivers/gpu/drm/i915/display/intel_tc.c | 1 +
drivers/gpu/drm/i915/display/intel_tv.c | 1 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 81 ++----
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 15 +-
drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 1 +
.../drm/i915/gem/selftests/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 20 ++
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
.../gpu/drm/i915/gt/intel_workarounds_types.h | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 2 +-
drivers/gpu/drm/i915/gvt/aperture_gm.c | 1 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/dmabuf.c | 1 +
drivers/gpu/drm/i915/gvt/edid.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/gtt.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
drivers/gpu/drm/i915/gvt/mmio.c | 1 +
drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
drivers/gpu/drm/i915/gvt/scheduler.c | 1 +
drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_drv.c | 108 ++++++-
drivers/gpu/drm/i915/i915_drv.h | 78 +----
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_irq.c | 1 +
drivers/gpu/drm/i915/i915_irq.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 274 +-----------------
drivers/gpu/drm/i915/i915_reg_types.h | 213 ++++++++++++++
drivers/gpu/drm/i915/i915_sysfs.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_pm.h | 2 +-
drivers/gpu/drm/i915/intel_sideband.c | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 1 +
drivers/gpu/drm/i915/intel_uncore.h | 2 +-
105 files changed, 597 insertions(+), 592 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_reg_types.h
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
@ 2019-08-16 1:23 ` Daniele Ceraolo Spurio
2019-08-16 4:52 ` Lucas De Marchi
2019-08-16 1:23 ` [PATCH 2/6] drm/i915: Move engine IDs " Daniele Ceraolo Spurio
` (8 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 1:23 UTC (permalink / raw)
To: intel-gfx
It has nothing to do with registers, so move it to the more appropriate
intel_display_power.h
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 1 +
.../drm/i915/display/intel_display_power.h | 21 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 21 -------------------
4 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 374b75602141..1caae2f61216 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -13,6 +13,7 @@
#include "intel_cdclk.h"
#include "intel_combo_phy.h"
#include "intel_csr.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 97f2562fc5d3..a50605b8b1ad 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -92,6 +92,27 @@ enum intel_display_power_domain {
POWER_DOMAIN_NUM,
};
+/*
+ * i915_power_well_id:
+ *
+ * IDs used to look up power wells. Power wells accessed directly bypassing
+ * the power domains framework must be assigned a unique ID. The rest of power
+ * wells must be assigned DISP_PW_ID_NONE.
+ */
+enum i915_power_well_id {
+ DISP_PW_ID_NONE,
+
+ VLV_DISP_PW_DISP2D,
+ BXT_DISP_PW_DPIO_CMN_A,
+ VLV_DISP_PW_DPIO_CMN_BC,
+ GLK_DISP_PW_DPIO_CMN_C,
+ CHV_DISP_PW_DPIO_CMN_D,
+ HSW_DISP_PW_GLOBAL,
+ SKL_DISP_PW_MISC_IO,
+ SKL_DISP_PW_1,
+ SKL_DISP_PW_2,
+};
+
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index dc4aaec2e04c..0beb954b5318 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -14,6 +14,7 @@
#include <drm/i915_component.h>
#include "i915_reg.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b7ccebf6550..14165d619175 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1163,27 +1163,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define PUNIT_REG_ISPSSPM0 0x39
#define PUNIT_REG_ISPSSPM1 0x3a
-/*
- * i915_power_well_id:
- *
- * IDs used to look up power wells. Power wells accessed directly bypassing
- * the power domains framework must be assigned a unique ID. The rest of power
- * wells must be assigned DISP_PW_ID_NONE.
- */
-enum i915_power_well_id {
- DISP_PW_ID_NONE,
-
- VLV_DISP_PW_DISP2D,
- BXT_DISP_PW_DPIO_CMN_A,
- VLV_DISP_PW_DPIO_CMN_BC,
- GLK_DISP_PW_DPIO_CMN_C,
- CHV_DISP_PW_DPIO_CMN_D,
- HSW_DISP_PW_GLOBAL,
- SKL_DISP_PW_MISC_IO,
- SKL_DISP_PW_1,
- SKL_DISP_PW_2,
-};
-
#define PUNIT_REG_PWRGT_CTRL 0x60
#define PUNIT_REG_PWRGT_STATUS 0x61
#define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 2/6] drm/i915: Move engine IDs out of i915_reg.h
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h Daniele Ceraolo Spurio
@ 2019-08-16 1:23 ` Daniele Ceraolo Spurio
2019-08-16 4:56 ` Lucas De Marchi
2019-08-16 1:23 ` [PATCH 3/6] drm/i915: Move gmbus definitions " Daniele Ceraolo Spurio
` (7 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 1:23 UTC (permalink / raw)
To: intel-gfx
To remove the dependency between the GT headers and i915_reg.h, move the
definition of the engine IDs/classes to intel_engine_types.h
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 20 +++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 27 +++-----------------
3 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index a0f372807dd4..8f10c5ffd68d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -26,6 +26,26 @@
#include "intel_wakeref.h"
#include "intel_workarounds_types.h"
+/* Legacy HW Engine ID */
+
+#define RCS0_HW 0
+#define VCS0_HW 1
+#define BCS0_HW 2
+#define VECS0_HW 3
+#define VCS1_HW 4
+#define VCS2_HW 6
+#define VCS3_HW 7
+#define VECS1_HW 12
+
+/* Gen11+ HW Engine class + instance */
+#define RENDER_CLASS 0
+#define VIDEO_DECODE_CLASS 1
+#define VIDEO_ENHANCEMENT_CLASS 2
+#define COPY_ENGINE_CLASS 3
+#define OTHER_CLASS 4
+#define MAX_ENGINE_CLASS 4
+#define MAX_ENGINE_INSTANCE 3
+
#define I915_MAX_SLICES 3
#define I915_MAX_SUBSLICES 8
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index adab4d2c29ac..81f9de45ab36 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -16,6 +16,7 @@
#include "uc/intel_uc.h"
#include "i915_vma.h"
+#include "intel_engine_types.h"
#include "intel_reset_types.h"
#include "intel_wakeref.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 14165d619175..827795262d68 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -272,30 +272,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
-/* Engine ID */
-
-#define RCS0_HW 0
-#define VCS0_HW 1
-#define BCS0_HW 2
-#define VECS0_HW 3
-#define VCS1_HW 4
-#define VCS2_HW 6
-#define VCS3_HW 7
-#define VECS1_HW 12
-
-/* Engine class */
-
-#define RENDER_CLASS 0
-#define VIDEO_DECODE_CLASS 1
-#define VIDEO_ENHANCEMENT_CLASS 2
-#define COPY_ENGINE_CLASS 3
-#define OTHER_CLASS 4
-#define MAX_ENGINE_CLASS 4
-
-#define OTHER_GUC_INSTANCE 0
-#define OTHER_GTPM_INSTANCE 1
-#define MAX_ENGINE_INSTANCE 3
-
/* PCI config space */
#define MCHBAR_I915 0x44
@@ -7505,6 +7481,9 @@ enum {
#define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
#define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
#define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
+/* irq instances for OTHER_CLASS */
+#define OTHER_GUC_INSTANCE 0
+#define OTHER_GTPM_INSTANCE 1
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
--
2.22.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 3/6] drm/i915: Move gmbus definitions out of i915_reg.h
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 2/6] drm/i915: Move engine IDs " Daniele Ceraolo Spurio
@ 2019-08-16 1:23 ` Daniele Ceraolo Spurio
2019-08-16 5:03 ` Lucas De Marchi
2019-08-16 1:23 ` [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV Daniele Ceraolo Spurio
` (6 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 1:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
They're not related to registers, so move them to the more appropriate
intel_gmbus.h
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_gmbus.h | 22 ++++++++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 22 +---------------------
3 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
index d989085b8d22..b96212b85425 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
@@ -11,6 +11,28 @@
struct drm_i915_private;
struct i2c_adapter;
+#define GMBUS_PIN_DISABLED 0
+#define GMBUS_PIN_SSC 1
+#define GMBUS_PIN_VGADDC 2
+#define GMBUS_PIN_PANEL 3
+#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
+#define GMBUS_PIN_DPC 4 /* HDMIC */
+#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
+#define GMBUS_PIN_DPD 6 /* HDMID */
+#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
+#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
+#define GMBUS_PIN_2_BXT 2
+#define GMBUS_PIN_3_BXT 3
+#define GMBUS_PIN_4_CNP 4
+#define GMBUS_PIN_9_TC1_ICP 9
+#define GMBUS_PIN_10_TC2_ICP 10
+#define GMBUS_PIN_11_TC3_ICP 11
+#define GMBUS_PIN_12_TC4_ICP 12
+#define GMBUS_PIN_13_TC5_TGP 13
+#define GMBUS_PIN_14_TC6_TGP 14
+
+#define GMBUS_NUM_PINS 15 /* including 0 */
+
int intel_gmbus_setup(struct drm_i915_private *dev_priv);
void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4406a60f3e4..c6722d54ccd5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -68,6 +68,7 @@
#include "display/intel_display_power.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_frontbuffer.h"
+#include "display/intel_gmbus.h"
#include "display/intel_opregion.h"
#include "gem/i915_gem_context_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 827795262d68..ea2f0fa2402d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3207,27 +3207,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
-#define GMBUS_PIN_DISABLED 0
-#define GMBUS_PIN_SSC 1
-#define GMBUS_PIN_VGADDC 2
-#define GMBUS_PIN_PANEL 3
-#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
-#define GMBUS_PIN_DPC 4 /* HDMIC */
-#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
-#define GMBUS_PIN_DPD 6 /* HDMID */
-#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
-#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
-#define GMBUS_PIN_2_BXT 2
-#define GMBUS_PIN_3_BXT 3
-#define GMBUS_PIN_4_CNP 4
-#define GMBUS_PIN_9_TC1_ICP 9
-#define GMBUS_PIN_10_TC2_ICP 10
-#define GMBUS_PIN_11_TC3_ICP 11
-#define GMBUS_PIN_12_TC4_ICP 12
-#define GMBUS_PIN_13_TC5_TGP 13
-#define GMBUS_PIN_14_TC6_TGP 14
-
-#define GMBUS_NUM_PINS 15 /* including 0 */
+
#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2019-08-16 1:23 ` [PATCH 3/6] drm/i915: Move gmbus definitions " Daniele Ceraolo Spurio
@ 2019-08-16 1:23 ` Daniele Ceraolo Spurio
2019-08-16 5:09 ` Lucas De Marchi
2019-08-16 9:35 ` Jani Nikula
2019-08-16 1:23 ` [PATCH 5/6] drm/i915: Introduce i915_reg_types.h Daniele Ceraolo Spurio
` (5 subsequent siblings)
9 siblings, 2 replies; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 1:23 UTC (permalink / raw)
To: intel-gfx
This is only required for a single platform so no need to reserve the
memory on all of them.
This removes the last direct dependency of i915_drv.h on i915_reg.h
(apart from the i915_reg_t definition).
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 107 +++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/i915_drv.h | 64 +------------------
2 files changed, 100 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2541a3a1c229..1723b2ddfccd 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -80,6 +80,68 @@
static struct drm_driver driver;
+struct vlv_s0ix_state {
+ /* GAM */
+ u32 wr_watermark;
+ u32 gfx_prio_ctrl;
+ u32 arb_mode;
+ u32 gfx_pend_tlb0;
+ u32 gfx_pend_tlb1;
+ u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
+ u32 media_max_req_count;
+ u32 gfx_max_req_count;
+ u32 render_hwsp;
+ u32 ecochk;
+ u32 bsd_hwsp;
+ u32 blt_hwsp;
+ u32 tlb_rd_addr;
+
+ /* MBC */
+ u32 g3dctl;
+ u32 gsckgctl;
+ u32 mbctl;
+
+ /* GCP */
+ u32 ucgctl1;
+ u32 ucgctl3;
+ u32 rcgctl1;
+ u32 rcgctl2;
+ u32 rstctl;
+ u32 misccpctl;
+
+ /* GPM */
+ u32 gfxpause;
+ u32 rpdeuhwtc;
+ u32 rpdeuc;
+ u32 ecobus;
+ u32 pwrdwnupctl;
+ u32 rp_down_timeout;
+ u32 rp_deucsw;
+ u32 rcubmabdtmr;
+ u32 rcedata;
+ u32 spare2gh;
+
+ /* Display 1 CZ domain */
+ u32 gt_imr;
+ u32 gt_ier;
+ u32 pm_imr;
+ u32 pm_ier;
+ u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
+
+ /* GT SA CZ domain */
+ u32 tilectl;
+ u32 gt_fifoctl;
+ u32 gtlc_wake_ctrl;
+ u32 gtlc_survive;
+ u32 pmwgicz;
+
+ /* Display 2 CZ domain */
+ u32 gu_ctl0;
+ u32 gu_ctl1;
+ u32 pcbr;
+ u32 clock_gate_dis2;
+};
+
static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
{
int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
@@ -466,6 +528,28 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
}
}
+static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
+{
+ if (!IS_VALLEYVIEW(i915))
+ return 0;
+
+ /* we write all the values in the structure, so no need to zero it out */
+ i915->s0ix_state = kmalloc(sizeof(struct vlv_s0ix_state), GFP_KERNEL);
+ if (!i915->s0ix_state)
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void vlv_free_s0ix_state(struct drm_i915_private *i915)
+{
+ if (!i915->s0ix_state)
+ return;
+
+ kfree(i915->s0ix_state);
+ i915->s0ix_state = NULL;
+}
+
/**
* i915_driver_early_probe - setup state not requiring device access
* @dev_priv: device private
@@ -508,13 +592,17 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
if (ret < 0)
return ret;
+ ret = vlv_alloc_s0ix_state(dev_priv);
+ if (ret < 0)
+ goto err_workqueues;
+
intel_wopcm_init_early(&dev_priv->wopcm);
intel_gt_init_early(&dev_priv->gt, dev_priv);
ret = i915_gem_init_early(dev_priv);
if (ret < 0)
- goto err_workqueues;
+ goto err_gt;
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev_priv);
@@ -536,8 +624,10 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
err_gem:
i915_gem_cleanup_early(dev_priv);
-err_workqueues:
+err_gt:
intel_gt_driver_late_release(&dev_priv->gt);
+ vlv_free_s0ix_state(dev_priv);
+err_workqueues:
i915_workqueues_cleanup(dev_priv);
return ret;
}
@@ -553,6 +643,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
intel_gt_driver_late_release(&dev_priv->gt);
+ vlv_free_s0ix_state(dev_priv);
i915_workqueues_cleanup(dev_priv);
pm_qos_remove_request(&dev_priv->sb_qos);
@@ -2137,7 +2228,7 @@ static int i915_pm_restore(struct device *kdev)
*/
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
- struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
+ struct vlv_s0ix_state *s = dev_priv->s0ix_state;
int i;
/* GAM 0x4000-0x4770 */
@@ -2147,7 +2238,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
- for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
+ for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
@@ -2191,7 +2282,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
s->pm_imr = I915_READ(GEN6_PMIMR);
s->pm_ier = I915_READ(GEN6_PMIER);
- for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
+ for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
/* GT SA CZ domain, 0x100000-0x138124 */
@@ -2218,7 +2309,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
{
- struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
+ struct vlv_s0ix_state *s = dev_priv->s0ix_state;
u32 val;
int i;
@@ -2229,7 +2320,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
- for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
+ for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
@@ -2273,7 +2364,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_PMIMR, s->pm_imr);
I915_WRITE(GEN6_PMIER, s->pm_ier);
- for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
+ for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
/* GT SA CZ domain, 0x100000-0x138124 */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c6722d54ccd5..9b41f2209b69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -527,68 +527,6 @@ struct i915_suspend_saved_registers {
u16 saveGCDGMBUS;
};
-struct vlv_s0ix_state {
- /* GAM */
- u32 wr_watermark;
- u32 gfx_prio_ctrl;
- u32 arb_mode;
- u32 gfx_pend_tlb0;
- u32 gfx_pend_tlb1;
- u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
- u32 media_max_req_count;
- u32 gfx_max_req_count;
- u32 render_hwsp;
- u32 ecochk;
- u32 bsd_hwsp;
- u32 blt_hwsp;
- u32 tlb_rd_addr;
-
- /* MBC */
- u32 g3dctl;
- u32 gsckgctl;
- u32 mbctl;
-
- /* GCP */
- u32 ucgctl1;
- u32 ucgctl3;
- u32 rcgctl1;
- u32 rcgctl2;
- u32 rstctl;
- u32 misccpctl;
-
- /* GPM */
- u32 gfxpause;
- u32 rpdeuhwtc;
- u32 rpdeuc;
- u32 ecobus;
- u32 pwrdwnupctl;
- u32 rp_down_timeout;
- u32 rp_deucsw;
- u32 rcubmabdtmr;
- u32 rcedata;
- u32 spare2gh;
-
- /* Display 1 CZ domain */
- u32 gt_imr;
- u32 gt_ier;
- u32 pm_imr;
- u32 pm_ier;
- u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
-
- /* GT SA CZ domain */
- u32 tilectl;
- u32 gt_fifoctl;
- u32 gtlc_wake_ctrl;
- u32 gtlc_survive;
- u32 pmwgicz;
-
- /* Display 2 CZ domain */
- u32 gu_ctl0;
- u32 gu_ctl1;
- u32 pcbr;
- u32 clock_gate_dis2;
-};
-
struct intel_rps_ei {
ktime_t ktime;
u32 render_c0;
@@ -1622,7 +1560,7 @@ struct drm_i915_private {
u32 suspend_count;
bool power_domains_suspended;
struct i915_suspend_saved_registers regfile;
- struct vlv_s0ix_state vlv_s0ix_state;
+ void *s0ix_state;
enum {
I915_SAGV_UNKNOWN = 0,
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 5/6] drm/i915: Introduce i915_reg_types.h
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2019-08-16 1:23 ` [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV Daniele Ceraolo Spurio
@ 2019-08-16 1:23 ` Daniele Ceraolo Spurio
2019-08-16 9:40 ` Michal Wajdeczko
2019-08-16 1:23 ` [PATCH 6/6] drm/i915: Wrappers for display register waits Daniele Ceraolo Spurio
` (4 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 1:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
With the introduction of display uncore, we want to categorize registers
between display and non-display. To help us getting it right, it will
be useful to move the display registers to a new file that can be used
without including i915_reg.h. To allow that, move all the basic register
type definitions and helpers to i915_reg_types.h and include that
instead of i915_reg.h from header files in the driver. We'll then
be able to replace i915_reg.h with the new display-only header in
display files and make sure the registers are correctly
compartmentalized.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
Documentation/gpu/i915.rst | 4 +-
drivers/gpu/drm/i915/display/icl_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_audio.c | 1 +
drivers/gpu/drm/i915/display/intel_bw.c | 1 +
drivers/gpu/drm/i915/display/intel_cdclk.c | 1 +
drivers/gpu/drm/i915/display/intel_color.c | 1 +
.../gpu/drm/i915/display/intel_combo_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_crt.c | 1 +
drivers/gpu/drm/i915/display/intel_crt.h | 2 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_power.c | 1 +
.../drm/i915/display/intel_display_power.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 1 +
drivers/gpu/drm/i915/display/intel_dp.h | 2 +-
.../drm/i915/display/intel_dp_link_training.c | 1 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 +
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
drivers/gpu/drm/i915/display/intel_dsi.c | 1 +
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 1 +
drivers/gpu/drm/i915/display/intel_dvo.c | 1 +
drivers/gpu/drm/i915/display/intel_dvo_dev.h | 2 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../drm/i915/display/intel_fifo_underrun.c | 1 +
drivers/gpu/drm/i915/display/intel_gmbus.c | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.c | 1 +
drivers/gpu/drm/i915/display/intel_hdmi.h | 2 +-
.../gpu/drm/i915/display/intel_lpe_audio.c | 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 1 +
drivers/gpu/drm/i915/display/intel_lvds.c | 1 +
drivers/gpu/drm/i915/display/intel_lvds.h | 2 +-
drivers/gpu/drm/i915/display/intel_opregion.c | 1 +
drivers/gpu/drm/i915/display/intel_panel.c | 1 +
drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.c | 1 +
drivers/gpu/drm/i915/display/intel_sdvo.h | 2 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 1 +
drivers/gpu/drm/i915/display/intel_tc.c | 1 +
drivers/gpu/drm/i915/display/intel_tv.c | 1 +
drivers/gpu/drm/i915/display/intel_vdsc.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 +
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_context.c | 1 +
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 1 +
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 1 +
.../drm/i915/gem/selftests/i915_gem_context.c | 1 +
drivers/gpu/drm/i915/gt/intel_engine.h | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 1 +
drivers/gpu/drm/i915/gt/intel_hangcheck.c | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_mocs.c | 1 +
drivers/gpu/drm/i915/gt/intel_reset.c | 1 +
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 1 +
drivers/gpu/drm/i915/gt/intel_sseu.c | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 1 +
.../gpu/drm/i915/gt/intel_workarounds_types.h | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 2 +-
drivers/gpu/drm/i915/gvt/aperture_gm.c | 1 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/dmabuf.c | 1 +
drivers/gpu/drm/i915/gvt/edid.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/gtt.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
drivers/gpu/drm/i915/gvt/mmio.c | 1 +
drivers/gpu/drm/i915/gvt/mmio_context.c | 1 +
drivers/gpu/drm/i915/gvt/scheduler.c | 1 +
drivers/gpu/drm/i915/i915_cmd_parser.c | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 1 +
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 1 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_irq.c | 1 +
drivers/gpu/drm/i915/i915_irq.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_perf.c | 1 +
drivers/gpu/drm/i915/i915_pmu.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 204 +----------------
drivers/gpu/drm/i915/i915_reg_types.h | 213 ++++++++++++++++++
drivers/gpu/drm/i915/i915_sysfs.c | 1 +
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_pm.h | 2 +-
drivers/gpu/drm/i915/intel_sideband.c | 1 +
drivers/gpu/drm/i915/intel_uncore.c | 1 +
drivers/gpu/drm/i915/intel_uncore.h | 2 +-
101 files changed, 314 insertions(+), 220 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_reg_types.h
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 0e322688be5c..9561fd7617a5 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -579,7 +579,7 @@ cases, deviating from) the kernel coding style.
Register macro definition style
-------------------------------
-The style guide for ``i915_reg.h``.
+The style guide for register definitions in header files.
-.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h
+.. kernel-doc:: drivers/gpu/drm/i915/i915_reg_types.h
:doc: The i915 register macro definition style guide
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ae33639d48ba..27b031a1774f 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -28,6 +28,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_mipi_dsi.h>
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_combo_phy.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index d3fb75bb9eb1..89d494ada0d5 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -34,6 +34,7 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_plane_helper.h>
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_display_types.h"
#include "intel_hdcp.h"
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index ddcccf4408c3..8b02e4c61ab2 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -28,6 +28,7 @@
#include <drm/i915_component.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_display_types.h"
#include "intel_lpe_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 688858ebe4d0..25c864e4ed3a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,6 +5,7 @@
#include <drm/drm_atomic_state_helper.h>
+#include "i915_reg.h"
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 59c0ceb21aac..a02e8404d6ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "i915_reg.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 71a0201437a9..18c346ac567e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -22,6 +22,7 @@
*
*/
+#include "i915_reg.h"
#include "intel_color.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 44bbc7e74fc3..4f545cb08936 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -3,6 +3,7 @@
* Copyright © 2018 Intel Corporation
*/
+#include "i915_reg.h"
#include "intel_combo_phy.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 067eb14dbf80..7045d939096f 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -35,6 +35,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_crt.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h
index 1b3fba359efc..1f0e876bdfa2 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.h
+++ b/drivers/gpu/drm/i915/display/intel_crt.h
@@ -6,7 +6,7 @@
#ifndef __INTEL_CRT_H__
#define __INTEL_CRT_H__
-#include "i915_reg.h"
+#include "i915_reg_types.h"
enum pipe;
struct drm_encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 647ba5140656..9647425b2301 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -28,6 +28,7 @@
#include <drm/drm_scdc_helper.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_combo_phy.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5b733e38eae3..1c4548ecf6e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -57,6 +57,7 @@
#include "display/intel_vdsc.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_acpi.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1caae2f61216..db9685888b1c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -10,6 +10,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "intel_cdclk.h"
#include "intel_combo_phy.h"
#include "intel_csr.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index a50605b8b1ad..674480d09880 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -8,7 +8,7 @@
#include "intel_display.h"
#include "intel_runtime_pm.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_i915_private;
struct intel_encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4884c87c8ed7..faf87ecdc213 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -44,6 +44,7 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_atomic.h"
#include "intel_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 657bbb1f5ed0..e48eb368e4f5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -10,7 +10,7 @@
#include <drm/i915_drm.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
enum pipe;
struct drm_connector_state;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 2a1130dd1ad0..6816195d8d09 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b1a3df185f4c..071a976c1219 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -28,6 +28,7 @@
#include <drm/drm_probe_helper.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 749e5a74825f..887454793490 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -23,6 +23,7 @@
#include "display/intel_dp.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 84a09d96d52f..4b3c5aaeba83 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -21,6 +21,7 @@
* DEALINGS IN THE SOFTWARE.
*/
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_dpll_mgr.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index 5fec02aceaed..067ba8a09968 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -4,6 +4,7 @@
*/
#include <drm/drm_mipi_dsi.h>
+#include "i915_reg.h"
#include "intel_dsi.h"
int intel_dsi_bitrate(const struct intel_dsi *intel_dsi)
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index f90946c912ee..ef9764446963 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -38,6 +38,7 @@
#include <video/mipi_display.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 93baf366692e..c32294552cea 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -33,6 +33,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_display_types.h"
#include "intel_dvo.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dvo_dev.h b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
index 94a6ae1e0292..9af298d545c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo_dev.h
+++ b/drivers/gpu/drm/i915/display/intel_dvo_dev.h
@@ -27,7 +27,7 @@
#include <drm/drm_crtc.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct intel_dvo_device {
const char *name;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index f007f667315e..5579b4eb4563 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -41,6 +41,7 @@
#include <drm/drm_fourcc.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
#include "intel_frontbuffer.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index ab61f88d1d33..38e56043e6e1 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -26,6 +26,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 1e27b18aa3fc..3341b3f27a5b 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -35,6 +35,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_gmbus.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b1ca8e5bdb56..238f42c84bcc 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -41,6 +41,7 @@
#include "i915_debugfs.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 106c2e0bc3c9..037ea41f2f7e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -11,7 +11,7 @@
#include <drm/i915_drm.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_connector;
struct drm_encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index b19800b58442..dc252de6eeb8 100644
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -71,6 +71,7 @@
#include <drm/intel_lpe_audio.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_lpe_audio.h"
#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL)
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index f8f1308643a9..64bfd55d4542 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -27,6 +27,7 @@
#include <drm/drm_dp_dual_mode_helper.h>
#include <drm/drm_edid.h>
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_lspcon.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 78c9ee5230ea..915e94718a23 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -40,6 +40,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.h b/drivers/gpu/drm/i915/display/intel_lvds.h
index bc9c8b84ba2f..912a6ac88a6e 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.h
+++ b/drivers/gpu/drm/i915/display/intel_lvds.h
@@ -8,7 +8,7 @@
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
enum pipe;
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 969ade623691..982dccea65a9 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -35,6 +35,7 @@
#include "display/intel_panel.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_opregion.h"
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index bc14e9c0285a..8ea9b4d038da 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -39,6 +39,7 @@
#include "intel_dp_aux_backlight.h"
#include "intel_dsi_dcs_backlight.h"
#include "intel_panel.h"
+#include "i915_reg.h"
#define CRC_PMIC_PWM_PERIOD_NS 21333
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
index 6260a2082719..2178d66a4c10 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c
@@ -29,6 +29,7 @@
#include <linux/debugfs.h>
#include <linux/seq_file.h>
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_display_types.h"
#include "intel_pipe_crc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index ad7044ea1efe..119a2fb8d781 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -26,6 +26,7 @@
#include "display/intel_dp.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_psr.h"
#include "intel_sprite.h"
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index adeb1c840976..455389f57b1b 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -37,6 +37,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h
index c9e05bcdd141..1908e88b2a17 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.h
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.h
@@ -10,7 +10,7 @@
#include <drm/i915_drm.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_i915_private;
enum pipe;
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index dea63be1964f..dba6dc8162ce 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -40,6 +40,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_atomic_plane.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 85743a43bee2..641f363b1f3c 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display.h"
#include "intel_display_types.h"
#include "intel_dp_mst.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c
index b70221f5112a..1d8d55fdcee5 100644
--- a/drivers/gpu/drm/i915/display/intel_tv.c
+++ b/drivers/gpu/drm/i915/display/intel_tv.c
@@ -36,6 +36,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_display_types.h"
#include "intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 598ddb60f9fb..5c47749622e1 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -9,6 +9,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_vdsc.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 6d535855e64e..db9b5ab6c80f 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -32,6 +32,7 @@
#include <drm/drm_mipi_dsi.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index 126edbaa814c..aa64e6501f3b 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -28,6 +28,7 @@
#include <linux/kernel.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_display_types.h"
#include "intel_dsi.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a6b0cb714292..12f40fb93eac 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -74,6 +74,7 @@
#include "i915_gem_context.h"
#include "i915_globals.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_user_extensions.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 91512cc6d7a6..ee46fbd20cb4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -21,6 +21,7 @@
#include "gt/intel_gt_pm.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_gem_ioctls.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
index 1e7311493530..65f0ef3da589 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
@@ -13,6 +13,7 @@
#include "i915_gem_gtt.h"
#include "i915_gem_ioctls.h"
#include "i915_gem_object.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vma.h"
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index aa533b4ab5f5..47feb94e043a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -11,6 +11,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_gem_stolen.h"
/*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index ca0c2f451742..2269de21f0e5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -12,6 +12,7 @@
#include "i915_gem.h"
#include "i915_gem_ioctls.h"
#include "i915_gem_object.h"
+#include "i915_reg.h"
/**
* DOC: buffer object tiling
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index dd87e6cd612e..ffa26c8108cf 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -9,6 +9,7 @@
#include "gem/i915_gem_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_reset.h"
+#include "i915_reg.h"
#include "i915_selftest.h"
#include "gem/selftests/igt_gem_utils.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index d3c6993f4f46..1c52ce81259a 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -10,7 +10,7 @@
#include <linux/seqlock.h>
#include "i915_pmu.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
#include "i915_request.h"
#include "i915_selftest.h"
#include "gt/intel_timeline.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index d20750e420c0..204c46e260f6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -27,6 +27,7 @@
#include "gem/i915_gem_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gt/intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 914bd2db3bc7..4c633511e4ee 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,6 +4,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_uncore.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 34a4fb624bf7..98e725b66082 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -7,6 +7,7 @@
#include <linux/sched/clock.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_irq.h"
#include "intel_gt.h"
#include "intel_gt_irq.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_hangcheck.c b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
index 05d042cdefe2..bb417c2fc6dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/intel_hangcheck.c
@@ -23,6 +23,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_engine.h"
#include "intel_gt.h"
#include "intel_reset.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a5d9b902d6e3..fbb38a1cfb73 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -137,6 +137,7 @@
#include "i915_drv.h"
#include "i915_perf.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_engine_pm.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 728704bbbe18..2b6d1893a625 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -21,6 +21,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_engine.h"
#include "intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index ec85740de942..5c0f926ccd89 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -15,6 +15,7 @@
#include "i915_drv.h"
#include "i915_gpu_error.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "intel_engine_pm.h"
#include "intel_gt.h"
#include "intel_gt_pm.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 409d764f8c6d..52fecc280918 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -34,6 +34,7 @@
#include "gem/i915_gem_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_context.h"
#include "intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index 6bf2d87da109..d7792a729a6b 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -5,6 +5,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_lrc_reg.h"
#include "intel_sseu.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..05a6eef3d57f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -5,6 +5,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_context.h"
#include "intel_gt.h"
#include "intel_workarounds.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
index e27ab1b710b3..5792d5c085ab 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
@@ -9,7 +9,7 @@
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct i915_wa {
i915_reg_t reg;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 5528224448f6..67fd3f3b0778 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -12,6 +12,7 @@
#include "gt/intel_gt.h"
#include "intel_guc_fw.h"
#include "i915_drv.h"
+#include "i915_reg.h"
/**
* intel_guc_fw_init_early() - initializes GuC firmware struct
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
index edf194d23c6b..e35cedd0bf1c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
@@ -9,7 +9,7 @@
#include <linux/compiler.h>
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
/* Definitions of GuC H/W registers, bits, etc */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index f325d3dd564f..633daae576f6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -15,6 +15,7 @@
#include "intel_guc_submission.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
enum {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index f8a4557c8d6d..0830e5026975 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -6,7 +6,7 @@
#ifndef _INTEL_HUC_H_
#define _INTEL_HUC_H_
-#include "i915_reg.h"
+#include "i915_reg_types.h"
#include "intel_uc_fw.h"
#include "intel_huc_fw.h"
diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index c3d19d88da40..7113786629a7 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -36,6 +36,7 @@
#include "i915_drv.h"
#include "i915_gem_fence_reg.h"
+#include "i915_reg.h"
#include "gvt.h"
static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index e753b1e706e2..c4609f8c37bf 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -38,6 +38,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
#include "trace.h"
#define INVALID_OP (~0U)
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index e1c313da6c00..4386cb3709f5 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -33,6 +33,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
static int get_edp_pipe(struct intel_vgpu *vgpu)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c
index 13044c027f27..ffe257e59a6f 100644
--- a/drivers/gpu/drm/i915/gvt/dmabuf.c
+++ b/drivers/gpu/drm/i915/gvt/dmabuf.c
@@ -32,6 +32,7 @@
#include <linux/vfio.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 1fe6124918f1..e450f3af1ee7 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -33,6 +33,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#define GMBUS1_TOTAL_BYTES_SHIFT 16
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 8bb292b01271..92433aed342c 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -37,6 +37,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 4b04af569c05..10a28fb8692d 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -36,6 +36,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
#include "trace.h"
#if defined(VERBOSE_DEBUG)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 25f78196b964..b97a72d4e93b 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -39,6 +39,7 @@
#include "i915_drv.h"
#include "gvt.h"
#include "i915_pvinfo.h"
+#include "i915_reg.h"
/* XXX FIXME i915 has changed PP_XXX definition */
#define PCH_PP_STATUS _MMIO(0xc7200)
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 11accd3e1023..bd8e2d5d2d77 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -30,6 +30,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#include "trace.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index a55178884d67..929f6bedec9c 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -34,6 +34,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
/**
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 4208e40445b1..1b276bdd8513 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -34,6 +34,7 @@
*/
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gt/intel_context.h"
#include "gvt.h"
#include "trace.h"
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 8940fa8d391a..2c476f9a0262 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -40,6 +40,7 @@
#include "gt/intel_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "gvt.h"
#define RING_CTX_OFF(x) \
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 24555102e198..0526214e301c 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -28,6 +28,7 @@
#include "gt/intel_engine.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_memcpy.h"
/**
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ef4f84e060ee..ad690a376185 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -46,6 +46,7 @@
#include "i915_debugfs.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_csr.h"
#include "intel_pm.h"
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1723b2ddfccd..d46163696bbf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -71,6 +71,7 @@
#include "i915_memcpy.h"
#include "i915_perf.h"
#include "i915_query.h"
+#include "i915_reg.h"
#include "i915_suspend.h"
#include "i915_sysfs.h"
#include "i915_trace.h"
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b41f2209b69..35db81d66785 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -60,7 +60,7 @@
#include "i915_fixed.h"
#include "i915_params.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
#include "i915_utils.h"
#include "display/intel_bios.h"
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index b4c39a06fee5..8d065fe5800a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -55,6 +55,7 @@
#include "gt/intel_workarounds.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index c9654f1a468f..2721e00865c7 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -24,6 +24,7 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_scatterlist.h"
#include "i915_vgpu.h"
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index fcf05c213b0a..6b3620a1f3b3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -39,6 +39,7 @@
#include "gt/intel_gt.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_scatterlist.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b0ae055b6c82..3bd0e65e9565 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -42,6 +42,7 @@
#include "gem/i915_gem_context.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_gpu_error.h"
#include "i915_memcpy.h"
#include "i915_scatterlist.h"
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 37e3dd3c1a9d..2e76898fd257 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -49,6 +49,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_pm.h"
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 8e7e6071777e..1b835fa98840 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -10,7 +10,7 @@
#include <linux/types.h>
#include "display/intel_display.h"
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_crtc;
struct drm_device;
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1974e4c78a43..ef369b938cc1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -32,6 +32,7 @@
#include "i915_drv.h"
#include "i915_globals.h"
+#include "i915_reg.h"
#include "i915_selftest.h"
#define PLATFORM(x) .platform = (x)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e42b86827d6b..7f0ec6757484 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -200,6 +200,7 @@
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_perf.h"
#include "oa/i915_oa_hsw.h"
#include "oa/i915_oa_bdw.h"
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 8e251e719390..a7fa4a9a31d4 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -14,6 +14,7 @@
#include "i915_drv.h"
#include "i915_pmu.h"
+#include "i915_reg.h"
#include "intel_pm.h"
/* Frequency for the sampling timer for events which need it. */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea2f0fa2402d..d99b0f600717 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,181 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
-#include <linux/bitfield.h>
-#include <linux/bits.h>
-
-/**
- * DOC: The i915 register macro definition style guide
- *
- * Follow the style described here for new macros, and while changing existing
- * macros. Do **not** mass change existing definitions just to update the style.
- *
- * Layout
- * ~~~~~~
- *
- * Keep helper macros near the top. For example, _PIPE() and friends.
- *
- * Prefix macros that generally should not be used outside of this file with
- * underscore '_'. For example, _PIPE() and friends, single instances of
- * registers that are defined solely for the use by function-like macros.
- *
- * Avoid using the underscore prefixed macros outside of this file. There are
- * exceptions, but keep them to a minimum.
- *
- * There are two basic types of register definitions: Single registers and
- * register groups. Register groups are registers which have two or more
- * instances, for example one per pipe, port, transcoder, etc. Register groups
- * should be defined using function-like macros.
- *
- * For single registers, define the register offset first, followed by register
- * contents.
- *
- * For register groups, define the register instance offsets first, prefixed
- * with underscore, followed by a function-like macro choosing the right
- * instance based on the parameter, followed by register contents.
- *
- * Define the register contents (i.e. bit and bit field macros) from most
- * significant to least significant bit. Indent the register content macros
- * using two extra spaces between ``#define`` and the macro name.
- *
- * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
- * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
- * shifted in place, so they can be directly OR'd together. For convenience,
- * function-like macros may be used to define bit fields, but do note that the
- * macros may be needed to read as well as write the register contents.
- *
- * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
- *
- * Group the register and its contents together without blank lines, separate
- * from other registers and their contents with one blank line.
- *
- * Indent macro values from macro names using TABs. Align values vertically. Use
- * braces in macro values as needed to avoid unintended precedence after macro
- * substitution. Use spaces in macro values according to kernel coding
- * style. Use lower case in hexadecimal values.
- *
- * Naming
- * ~~~~~~
- *
- * Try to name registers according to the specs. If the register name changes in
- * the specs from platform to another, stick to the original name.
- *
- * Try to re-use existing register macro definitions. Only add new macros for
- * new register offsets, or when the register contents have changed enough to
- * warrant a full redefinition.
- *
- * When a register macro changes for a new platform, prefix the new macro using
- * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
- * prefix signifies the start platform/generation using the register.
- *
- * When a bit (field) macro changes or gets added for a new platform, while
- * retaining the existing register macro, add a platform acronym or generation
- * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
- *
- * Examples
- * ~~~~~~~~
- *
- * (Note that the values in the example are indented using spaces instead of
- * TABs to avoid misalignment in generated documentation. Use TABs in the
- * definitions.)::
- *
- * #define _FOO_A 0xf000
- * #define _FOO_B 0xf001
- * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
- * #define FOO_ENABLE REG_BIT(31)
- * #define FOO_MODE_MASK REG_GENMASK(19, 16)
- * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
- * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
- * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
- *
- * #define BAR _MMIO(0xb000)
- * #define GEN8_BAR _MMIO(0xb888)
- */
-
-/**
- * REG_BIT() - Prepare a u32 bit value
- * @__n: 0-based bit number
- *
- * Local wrapper for BIT() to force u32, with compile time checks.
- *
- * @return: Value with bit @__n set.
- */
-#define REG_BIT(__n) \
- ((u32)(BIT(__n) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
- ((__n) < 0 || (__n) > 31))))
-
-/**
- * REG_GENMASK() - Prepare a continuous u32 bitmask
- * @__high: 0-based high bit
- * @__low: 0-based low bit
- *
- * Local wrapper for GENMASK() to force u32, with compile time checks.
- *
- * @return: Continuous bitmask from @__high to @__low, inclusive.
- */
-#define REG_GENMASK(__high, __low) \
- ((u32)(GENMASK(__high, __low) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
- __is_constexpr(__low) && \
- ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-
-/*
- * Local integer constant expression version of is_power_of_2().
- */
-#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-
-/**
- * REG_FIELD_PREP() - Prepare a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to put in the field
- *
- * Local copy of FIELD_PREP() to generate an integer constant expression, force
- * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
- *
- * @return: @__val masked and shifted into the field defined by @__mask.
- */
-#define REG_FIELD_PREP(__mask, __val) \
- ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
- BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
- BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
- BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
- BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-
-/**
- * REG_FIELD_GET() - Extract a u32 bitfield value
- * @__mask: shifted mask defining the field's length and position
- * @__val: value to extract the bitfield value from
- *
- * Local wrapper for FIELD_GET() to force u32 and for consistency with
- * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
- *
- * @return: Masked and shifted value of the field defined by @__mask in @__val.
- */
-#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
-
-typedef struct {
- u32 reg;
-} i915_reg_t;
-
-#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
-
-#define INVALID_MMIO_REG _MMIO(0)
-
-static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
-{
- return reg.reg;
-}
-
-static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
-{
- return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
-}
-
-static inline bool i915_mmio_reg_valid(i915_reg_t reg)
-{
- return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
-}
+#include "i915_reg_types.h"
#define VLV_DISPLAY_BASE 0x180000
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
@@ -207,21 +33,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
-/*
- * Given the first two numbers __a and __b of arbitrarily many evenly spaced
- * numbers, pick the 0-based __index'th value.
- *
- * Always prefer this over _PICK() if the numbers are evenly spaced.
- */
-#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
-
-/*
- * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
- *
- * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
- */
-#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
-
/*
* Named helper wrappers around _PICK_EVEN() and _PICK().
*/
@@ -259,19 +70,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
-#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
-#define _MASKED_FIELD(mask, value) ({ \
- if (__builtin_constant_p(mask)) \
- BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
- if (__builtin_constant_p(value)) \
- BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
- if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
- BUILD_BUG_ON_MSG((value) & ~(mask), \
- "Incorrect value for mask"); \
- __MASKED_FIELD(mask, value); })
-#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
-#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
-
/* PCI config space */
#define MCHBAR_I915 0x44
diff --git a/drivers/gpu/drm/i915/i915_reg_types.h b/drivers/gpu/drm/i915/i915_reg_types.h
new file mode 100644
index 000000000000..980c7fc251a8
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_reg_types.h
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2014 Intel Corporation
+ */
+
+#ifndef _I915_REG_TYPES_H_
+#define _I915_REG_TYPES_H_
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+
+/**
+ * DOC: The i915 register macro definition style guide
+ *
+ * Follow the style described here for new macros, and while changing existing
+ * macros. Do **not** mass change existing definitions just to update the style.
+ *
+ * Layout
+ * ~~~~~~
+ *
+ * Keep helper macros near the top. For example, _PIPE() and friends.
+ *
+ * Prefix macros that generally should not be used outside of this file with
+ * underscore '_'. For example, _PIPE() and friends, single instances of
+ * registers that are defined solely for the use by function-like macros.
+ *
+ * Avoid using the underscore prefixed macros outside of this file. There are
+ * exceptions, but keep them to a minimum.
+ *
+ * There are two basic types of register definitions: Single registers and
+ * register groups. Register groups are registers which have two or more
+ * instances, for example one per pipe, port, transcoder, etc. Register groups
+ * should be defined using function-like macros.
+ *
+ * For single registers, define the register offset first, followed by register
+ * contents.
+ *
+ * For register groups, define the register instance offsets first, prefixed
+ * with underscore, followed by a function-like macro choosing the right
+ * instance based on the parameter, followed by register contents.
+ *
+ * Define the register contents (i.e. bit and bit field macros) from most
+ * significant to least significant bit. Indent the register content macros
+ * using two extra spaces between ``#define`` and the macro name.
+ *
+ * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
+ * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
+ * shifted in place, so they can be directly OR'd together. For convenience,
+ * function-like macros may be used to define bit fields, but do note that the
+ * macros may be needed to read as well as write the register contents.
+ *
+ * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
+ *
+ * Group the register and its contents together without blank lines, separate
+ * from other registers and their contents with one blank line.
+ *
+ * Indent macro values from macro names using TABs. Align values vertically. Use
+ * braces in macro values as needed to avoid unintended precedence after macro
+ * substitution. Use spaces in macro values according to kernel coding
+ * style. Use lower case in hexadecimal values.
+ *
+ * Naming
+ * ~~~~~~
+ *
+ * Try to name registers according to the specs. If the register name changes in
+ * the specs from platform to another, stick to the original name.
+ *
+ * Try to re-use existing register macro definitions. Only add new macros for
+ * new register offsets, or when the register contents have changed enough to
+ * warrant a full redefinition.
+ *
+ * When a register macro changes for a new platform, prefix the new macro using
+ * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
+ * prefix signifies the start platform/generation using the register.
+ *
+ * When a bit (field) macro changes or gets added for a new platform, while
+ * retaining the existing register macro, add a platform acronym or generation
+ * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
+ *
+ * Examples
+ * ~~~~~~~~
+ *
+ * (Note that the values in the example are indented using spaces instead of
+ * TABs to avoid misalignment in generated documentation. Use TABs in the
+ * definitions.)::
+ *
+ * #define _FOO_A 0xf000
+ * #define _FOO_B 0xf001
+ * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
+ * #define FOO_ENABLE REG_BIT(31)
+ * #define FOO_MODE_MASK REG_GENMASK(19, 16)
+ * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
+ * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
+ * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
+ *
+ * #define BAR _MMIO(0xb000)
+ * #define GEN8_BAR _MMIO(0xb888)
+ */
+
+/**
+ * REG_BIT() - Prepare a u32 bit value
+ * @__n: 0-based bit number
+ *
+ * Local wrapper for BIT() to force u32, with compile time checks.
+ *
+ * @return: Value with bit @__n set.
+ */
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+
+/*
+ * Local integer constant expression version of is_power_of_2().
+ */
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
+
+/**
+ * REG_FIELD_PREP() - Prepare a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to put in the field
+ *
+ * Local copy of FIELD_PREP() to generate an integer constant expression, force
+ * u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: @__val masked and shifted into the field defined by @__mask.
+ */
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+
+/**
+ * REG_FIELD_GET() - Extract a u32 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u32 and for consistency with
+ * REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+
+/*
+ * Given the first two numbers __a and __b of arbitrarily many evenly spaced
+ * numbers, pick the 0-based __index'th value.
+ *
+ * Always prefer this over _PICK() if the numbers are evenly spaced.
+ */
+#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
+
+/*
+ * Given the arbitrary numbers in varargs, pick the 0-based __index'th number.
+ *
+ * Always prefer _PICK_EVEN() over this if the numbers are evenly spaced.
+ */
+#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index])
+
+#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask)) \
+ BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask), \
+ "Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
+#define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
+#define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
+
+typedef struct {
+ u32 reg;
+} i915_reg_t;
+
+#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
+
+#define INVALID_MMIO_REG _MMIO(0)
+
+static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
+{
+ return reg.reg;
+}
+
+static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
+{
+ return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
+}
+
+static inline bool i915_mmio_reg_valid(i915_reg_t reg)
+{
+ return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
+}
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index d8a3b180c084..74edf3c68551 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -31,6 +31,7 @@
#include <linux/sysfs.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_sysfs.h"
#include "intel_pm.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f99c9fd497b2..5b1c6280332e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -26,6 +26,7 @@
#include "intel_device_info.h"
#include "i915_drv.h"
+#include "i915_reg.h"
#define PLATFORM_NAME(x) [INTEL_##x] = #x
static const char * const platform_names[] = {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aca676e79948..25e72c107873 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -40,6 +40,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "intel_pm.h"
#include "intel_sideband.h"
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index e3573e1e16e3..4e8221f403f4 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,7 +8,7 @@
#include <linux/types.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_device;
struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index e06b35b844a0..b6d96eec9e5b 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -25,6 +25,7 @@
#include <asm/iosf_mbi.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "intel_sideband.h"
/*
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 9e583f13a9e4..1024adf4dcef 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -25,6 +25,7 @@
#include <asm/iosf_mbi.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_pm.h"
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 414fc2cb0459..7a0ffbe966f7 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -30,7 +30,7 @@
#include <linux/hrtimer.h>
#include <linux/io-64-nonatomic-lo-hi.h>
-#include "i915_reg.h"
+#include "i915_reg_types.h"
struct drm_i915_private;
struct intel_runtime_pm;
--
2.22.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 6/6] drm/i915: Wrappers for display register waits
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2019-08-16 1:23 ` [PATCH 5/6] drm/i915: Introduce i915_reg_types.h Daniele Ceraolo Spurio
@ 2019-08-16 1:23 ` Daniele Ceraolo Spurio
2019-08-16 7:17 ` Chris Wilson
2019-08-16 1:46 ` ✗ Fi.CI.CHECKPATCH: warning for Some more display uncore prep work Patchwork
` (3 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 1:23 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
To reduce the number of explicit dev_priv->uncore calls in the display
code ahead of the introduction of dev_priv->de_uncore, this patch
introduces a wrapper for one of the main usages of it, the register
waits. When we transition to the new uncore, we can just update the
wrapper to point to the appropriate structure.
Since the vast majority of waits are on a set or clear of a bit or mask,
add set & clear flavours of the wrapper to simplify the code.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 11 +--
drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +----
drivers/gpu/drm/i915/display/intel_crt.c | 17 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 45 +++--------
.../drm/i915/display/intel_display_power.c | 32 +++-----
drivers/gpu/drm/i915/display/intel_dp.c | 10 +--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 5 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 44 +++-------
drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 32 +++-----
drivers/gpu/drm/i915/display/intel_lvds.c | 6 +-
drivers/gpu/drm/i915/display/intel_psr.c | 5 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 80 ++++++-------------
drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 14 +---
drivers/gpu/drm/i915/i915_drv.h | 11 +++
17 files changed, 112 insertions(+), 235 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 27b031a1774f..8e887c2a572b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -899,10 +899,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
I915_WRITE(PIPECONF(dsi_trans), tmp);
/* wait for transcoder to be enabled */
- if (intel_wait_for_register(&dev_priv->uncore,
- PIPECONF(dsi_trans),
- I965_PIPECONF_ACTIVE,
- I965_PIPECONF_ACTIVE, 10))
+ if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
+ I965_PIPECONF_ACTIVE, 10))
DRM_ERROR("DSI transcoder not enabled\n");
}
}
@@ -1081,9 +1079,8 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
I915_WRITE(PIPECONF(dsi_trans), tmp);
/* wait for transcoder to be disabled */
- if (intel_wait_for_register(&dev_priv->uncore,
- PIPECONF(dsi_trans),
- I965_PIPECONF_ACTIVE, 0, 50))
+ if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
+ I965_PIPECONF_ACTIVE, 50))
DRM_ERROR("DSI trancoder not disabled\n");
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a02e8404d6ec..2c38a58db4bb 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -970,9 +970,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
- if (intel_wait_for_register(&dev_priv->uncore,
- LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
- 5))
+ if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
DRM_ERROR("DPLL0 not locked\n");
dev_priv->cdclk.hw.vco = vco;
@@ -984,9 +982,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
{
I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
- if (intel_wait_for_register(&dev_priv->uncore,
- LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
- 1))
+ if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
DRM_ERROR("Couldn't disable DPLL0\n");
dev_priv->cdclk.hw.vco = 0;
@@ -1310,9 +1306,7 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
I915_WRITE(BXT_DE_PLL_ENABLE, 0);
/* Timeout 200us */
- if (intel_wait_for_register(&dev_priv->uncore,
- BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
- 1))
+ if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
DRM_ERROR("timeout waiting for DE PLL unlock\n");
dev_priv->cdclk.hw.vco = 0;
@@ -1331,11 +1325,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
/* Timeout 200us */
- if (intel_wait_for_register(&dev_priv->uncore,
- BXT_DE_PLL_ENABLE,
- BXT_DE_PLL_LOCK,
- BXT_DE_PLL_LOCK,
- 1))
+ if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
DRM_ERROR("timeout waiting for DE PLL lock\n");
dev_priv->cdclk.hw.vco = vco;
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 7045d939096f..4ba5e8da972f 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -444,10 +444,8 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
I915_WRITE(crt->adpa_reg, adpa);
- if (intel_wait_for_register(&dev_priv->uncore,
- crt->adpa_reg,
- ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
- 1000))
+ if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
+ ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000))
DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
if (turn_off_dac) {
@@ -498,10 +496,8 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
I915_WRITE(crt->adpa_reg, adpa);
- if (intel_wait_for_register(&dev_priv->uncore,
- crt->adpa_reg,
- ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
- 1000)) {
+ if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
+ ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
I915_WRITE(crt->adpa_reg, save_adpa);
}
@@ -551,9 +547,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
CRT_HOTPLUG_FORCE_DETECT,
CRT_HOTPLUG_FORCE_DETECT);
/* wait for FORCE_DETECT to go off */
- if (intel_wait_for_register(&dev_priv->uncore, PORT_HOTPLUG_EN,
- CRT_HOTPLUG_FORCE_DETECT, 0,
- 1000))
+ if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
+ CRT_HOTPLUG_FORCE_DETECT, 1000))
DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9647425b2301..75fa4e287d7e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3140,10 +3140,8 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
val |= DP_TP_CTL_FEC_ENABLE;
I915_WRITE(DP_TP_CTL(port), val);
- if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
- DP_TP_STATUS_FEC_ENABLE_LIVE,
- DP_TP_STATUS_FEC_ENABLE_LIVE,
- 1))
+ if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
DRM_ERROR("Timed out waiting for FEC Enable Status\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1c4548ecf6e1..ab63af08be6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1078,9 +1078,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
i915_reg_t reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */
- if (intel_wait_for_register(&dev_priv->uncore,
- reg, I965_PIPECONF_ACTIVE, 0,
- 100))
+ if (intel_de_wait_for_clear(dev_priv, reg, I965_PIPECONF_ACTIVE, 100))
WARN(1, "pipe_off wait timed out\n");
} else {
intel_wait_for_pipe_scanline_stopped(crtc);
@@ -1384,11 +1382,7 @@ static void _vlv_enable_pll(struct intel_crtc *crtc,
POSTING_READ(DPLL(pipe));
udelay(150);
- if (intel_wait_for_register(&dev_priv->uncore,
- DPLL(pipe),
- DPLL_LOCK_VLV,
- DPLL_LOCK_VLV,
- 1))
+ if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
DRM_ERROR("DPLL %d failed to lock\n", pipe);
}
@@ -1437,9 +1431,7 @@ static void _chv_enable_pll(struct intel_crtc *crtc,
I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
/* Check PLL is locked */
- if (intel_wait_for_register(&dev_priv->uncore,
- DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
- 1))
+ if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1))
DRM_ERROR("PLL %d failed to lock\n", pipe);
}
@@ -1618,9 +1610,8 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
BUG();
}
- if (intel_wait_for_register(&dev_priv->uncore,
- dpll_reg, port_mask, expected_mask,
- 1000))
+ if (intel_de_wait_for_register(dev_priv, dpll_reg,
+ port_mask, expected_mask, 1000))
WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
port_name(dport->base.port),
I915_READ(dpll_reg) & port_mask, expected_mask);
@@ -1679,9 +1670,7 @@ static void ironlake_enable_pch_transcoder(const struct intel_crtc_state *crtc_s
}
I915_WRITE(reg, val | TRANS_ENABLE);
- if (intel_wait_for_register(&dev_priv->uncore,
- reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
- 100))
+ if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
}
@@ -1709,11 +1698,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
val |= TRANS_PROGRESSIVE;
I915_WRITE(LPT_TRANSCONF, val);
- if (intel_wait_for_register(&dev_priv->uncore,
- LPT_TRANSCONF,
- TRANS_STATE_ENABLE,
- TRANS_STATE_ENABLE,
- 100))
+ if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, TRANS_STATE_ENABLE, 100))
DRM_ERROR("Failed to enable PCH transcoder\n");
}
@@ -1735,9 +1720,7 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
val &= ~TRANS_ENABLE;
I915_WRITE(reg, val);
/* wait for PCH transcoder off, transcoder state */
- if (intel_wait_for_register(&dev_priv->uncore,
- reg, TRANS_STATE_ENABLE, 0,
- 50))
+ if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
if (HAS_PCH_CPT(dev_priv)) {
@@ -1757,9 +1740,7 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
val &= ~TRANS_ENABLE;
I915_WRITE(LPT_TRANSCONF, val);
/* wait for PCH transcoder off, transcoder state */
- if (intel_wait_for_register(&dev_priv->uncore,
- LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
- 50))
+ if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, TRANS_STATE_ENABLE, 50))
DRM_ERROR("Failed to disable PCH transcoder\n");
/* Workaround: clear timing override bit. */
@@ -5694,9 +5675,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
* and don't wait for vblanks until the end of crtc_enable, then
* the HW state readout code will complain that the expected
* IPS_CTL value is not the one we read. */
- if (intel_wait_for_register(&dev_priv->uncore,
- IPS_CTL, IPS_ENABLE, IPS_ENABLE,
- 50))
+ if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50))
DRM_ERROR("Timed out waiting for IPS enable\n");
}
}
@@ -5717,9 +5696,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
* 42ms timeout value leads to occasional timeouts so use 100ms
* instead.
*/
- if (intel_wait_for_register(&dev_priv->uncore,
- IPS_CTL, IPS_ENABLE, 0,
- 100))
+ if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100))
DRM_ERROR("Timed out waiting for IPS disable\n");
} else {
I915_WRITE(IPS_CTL, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index db9685888b1c..d1f2ff373473 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -320,11 +320,8 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
int pw_idx = power_well->desc->hsw.idx;
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
- if (intel_wait_for_register(&dev_priv->uncore,
- regs->driver,
- HSW_PWR_WELL_CTL_STATE(pw_idx),
- HSW_PWR_WELL_CTL_STATE(pw_idx),
- 1)) {
+ if (intel_de_wait_for_set(dev_priv, regs->driver,
+ HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
DRM_DEBUG_KMS("%s power well enable timeout\n",
power_well->desc->name);
@@ -381,9 +378,8 @@ static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
enum skl_power_gate pg)
{
/* Timeout 5us for PG#0, for other PGs 1us */
- WARN_ON(intel_wait_for_register(&dev_priv->uncore, SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(pg),
- SKL_FUSE_PG_DIST_STATUS(pg), 1));
+ WARN_ON(intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(pg), 1));
}
static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
@@ -1381,11 +1377,8 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* The PHY may be busy with some initial calibration and whatnot,
* so the power state can take a while to actually change.
*/
- if (intel_wait_for_register(&dev_priv->uncore,
- DISPLAY_PHY_STATUS,
- phy_status_mask,
- phy_status,
- 10))
+ if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
+ phy_status_mask, phy_status, 10))
DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
phy_status, dev_priv->chv_phy_control);
@@ -1416,11 +1409,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, true);
/* Poll for phypwrgood signal */
- if (intel_wait_for_register(&dev_priv->uncore,
- DISPLAY_PHY_STATUS,
- PHY_POWERGOOD(phy),
- PHY_POWERGOOD(phy),
- 1))
+ if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
+ PHY_POWERGOOD(phy), 1))
DRM_ERROR("Display PHY %d is not power up\n", phy);
vlv_dpio_get(dev_priv);
@@ -4333,8 +4323,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
I915_WRITE(LCPLL_CTL, val);
POSTING_READ(LCPLL_CTL);
- if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
- LCPLL_PLL_LOCK, 0, 1))
+ if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1))
DRM_ERROR("LCPLL still locked\n");
val = hsw_read_dcomp(dev_priv);
@@ -4389,8 +4378,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
val &= ~LCPLL_PLL_DISABLE;
I915_WRITE(LCPLL_CTL, val);
- if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
- LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 5))
+ if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5))
DRM_ERROR("LCPLL not locked yet\n");
if (val & LCPLL_CD_SOURCE_FCLK) {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index faf87ecdc213..fbea8ed83795 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2372,9 +2372,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
I915_READ(pp_stat_reg),
I915_READ(pp_ctrl_reg));
- if (intel_wait_for_register(&dev_priv->uncore,
- pp_stat_reg, mask, value,
- 5000))
+ if (intel_de_wait_for_register(dev_priv, pp_stat_reg, mask, value, 5000))
DRM_ERROR("Panel status timeout: status %08x control %08x\n",
I915_READ(pp_stat_reg),
I915_READ(pp_ctrl_reg));
@@ -3961,10 +3959,8 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
if (port == PORT_A)
return;
- if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port),
- DP_TP_STATUS_IDLE_DONE,
- DP_TP_STATUS_IDLE_DONE,
- 1))
+ if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_IDLE_DONE, 1))
DRM_ERROR("Timed out waiting for DP idle patterns\n");
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 071a976c1219..5c1829a97cf3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -339,11 +339,8 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
- if (intel_wait_for_register(&dev_priv->uncore,
- DP_TP_STATUS(port),
- DP_TP_STATUS_ACT_SENT,
- DP_TP_STATUS_ACT_SENT,
- 1))
+ if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+ DP_TP_STATUS_ACT_SENT, 1))
DRM_ERROR("Timed out waiting for ACT sent\n");
drm_dp_check_act_status(&intel_dp->mst_mgr);
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 887454793490..18f84c4ad611 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -346,10 +346,7 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
enum dpio_phy phy)
{
- if (intel_wait_for_register(&dev_priv->uncore,
- BXT_PORT_REF_DW3(phy),
- GRC_DONE, GRC_DONE,
- 10))
+ if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 4b3c5aaeba83..79b333bafc6a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1001,11 +1001,7 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(regs[id].ctl,
I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE);
- if (intel_wait_for_register(&dev_priv->uncore,
- DPLL_STATUS,
- DPLL_LOCK(id),
- DPLL_LOCK(id),
- 5))
+ if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5))
DRM_ERROR("DPLL %d not locked\n", id);
}
@@ -2017,11 +2013,8 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */
- if (intel_wait_for_register(&dev_priv->uncore,
- CNL_DPLL_ENABLE(id),
- PLL_POWER_STATE,
- PLL_POWER_STATE,
- 5))
+ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id),
+ PLL_POWER_STATE, 5))
DRM_ERROR("PLL %d Power not enabled\n", id);
/*
@@ -2058,11 +2051,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 7. Wait for PLL lock status in DPLL_ENABLE. */
- if (intel_wait_for_register(&dev_priv->uncore,
- CNL_DPLL_ENABLE(id),
- PLL_LOCK,
- PLL_LOCK,
- 5))
+ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
DRM_ERROR("PLL %d not locked\n", id);
/*
@@ -2106,11 +2095,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 4. Wait for PLL not locked status in DPLL_ENABLE. */
- if (intel_wait_for_register(&dev_priv->uncore,
- CNL_DPLL_ENABLE(id),
- PLL_LOCK,
- 0,
- 5))
+ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5))
DRM_ERROR("PLL %d locked\n", id);
/*
@@ -2128,11 +2113,8 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
I915_WRITE(CNL_DPLL_ENABLE(id), val);
/* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */
- if (intel_wait_for_register(&dev_priv->uncore,
- CNL_DPLL_ENABLE(id),
- PLL_POWER_STATE,
- 0,
- 5))
+ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id),
+ PLL_POWER_STATE, 5))
DRM_ERROR("PLL %d Power not disabled\n", id);
}
@@ -3253,8 +3235,7 @@ static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
- PLL_POWER_STATE, PLL_POWER_STATE, 1))
+ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1))
DRM_ERROR("PLL %d Power not enabled\n", pll->info->id);
}
@@ -3269,8 +3250,7 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv,
I915_WRITE(enable_reg, val);
/* Timeout is actually 600us. */
- if (intel_wait_for_register(&dev_priv->uncore, enable_reg,
- PLL_LOCK, PLL_LOCK, 1))
+ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1))
DRM_ERROR("PLL %d not locked\n", pll->info->id);
}
@@ -3365,8 +3345,7 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
I915_WRITE(enable_reg, val);
/* Timeout is actually 1us. */
- if (intel_wait_for_register(&dev_priv->uncore,
- enable_reg, PLL_LOCK, 0, 1))
+ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1))
DRM_ERROR("PLL %d locked\n", pll->info->id);
/* DVFS post sequence would be here. See the comment above. */
@@ -3379,8 +3358,7 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv,
* The spec says we need to "wait" but it also says it should be
* immediate.
*/
- if (intel_wait_for_register(&dev_priv->uncore,
- enable_reg, PLL_POWER_STATE, 0, 1))
+ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1))
DRM_ERROR("PLL %d Power not disabled\n", pll->info->id);
}
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 5579b4eb4563..9c29b82d3500 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -111,9 +111,7 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
I915_WRITE(FBC_CONTROL, fbc_ctl);
/* Wait for compressing bit to clear */
- if (intel_wait_for_register(&dev_priv->uncore,
- FBC_STATUS, FBC_STAT_COMPRESSING, 0,
- 10)) {
+ if (intel_de_wait_for_clear(dev_priv, FBC_STATUS, FBC_STAT_COMPRESSING, 10)) {
DRM_DEBUG_KMS("FBC idle timed out\n");
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 0beb954b5318..83e485b2e6d5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -245,8 +245,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text)
{
I915_WRITE(HDCP_SHA_TEXT, sha_text);
- if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL,
- HDCP_SHA1_READY, HDCP_SHA1_READY, 1)) {
+ if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) {
DRM_ERROR("Timed out waiting for SHA1 ready\n");
return -ETIMEDOUT;
}
@@ -476,9 +475,7 @@ int intel_hdcp_validate_v_prime(struct intel_digital_port *intel_dig_port,
/* Tell the HW we're done with the hash and wait for it to ACK */
I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH);
- if (intel_wait_for_register(&dev_priv->uncore, HDCP_REP_CTL,
- HDCP_SHA1_COMPLETE,
- HDCP_SHA1_COMPLETE, 1)) {
+ if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_COMPLETE, 1)) {
DRM_ERROR("Timed out waiting for SHA1 complete\n");
return -ETIMEDOUT;
}
@@ -621,9 +618,8 @@ static int intel_hdcp_auth(struct intel_connector *connector)
I915_WRITE(PORT_HDCP_CONF(port), HDCP_CONF_CAPTURE_AN);
/* Wait for An to be acquired */
- if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
- HDCP_STATUS_AN_READY,
- HDCP_STATUS_AN_READY, 1)) {
+ if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
+ HDCP_STATUS_AN_READY, 1)) {
DRM_ERROR("Timed out waiting for An\n");
return -ETIMEDOUT;
}
@@ -707,9 +703,9 @@ static int intel_hdcp_auth(struct intel_connector *connector)
}
/* Wait for encryption confirmation */
- if (intel_wait_for_register(&dev_priv->uncore, PORT_HDCP_STATUS(port),
- HDCP_STATUS_ENC, HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ if (intel_de_wait_for_set(dev_priv, PORT_HDCP_STATUS(port),
+ HDCP_STATUS_ENC,
+ ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -739,8 +735,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
hdcp->hdcp_encrypted = false;
I915_WRITE(PORT_HDCP_CONF(port), 0);
- if (intel_wait_for_register(&dev_priv->uncore,
- PORT_HDCP_STATUS(port), ~0, 0,
+ if (intel_de_wait_for_clear(dev_priv, PORT_HDCP_STATUS(port), ~0,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
DRM_ERROR("Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1517,10 +1512,9 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
CTL_LINK_ENCRYPTION_REQ);
}
- ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
- LINK_ENCRYPTION_STATUS,
- LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ ret = intel_de_wait_for_set(dev_priv, HDCP2_STATUS_DDI(port),
+ LINK_ENCRYPTION_STATUS,
+ ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1538,8 +1532,8 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
I915_WRITE(HDCP2_CTL_DDI(port),
I915_READ(HDCP2_CTL_DDI(port)) & ~CTL_LINK_ENCRYPTION_REQ);
- ret = intel_wait_for_register(&dev_priv->uncore, HDCP2_STATUS_DDI(port),
- LINK_ENCRYPTION_STATUS, 0x0,
+ ret = intel_de_wait_for_clear(dev_priv, HDCP2_STATUS_DDI(port),
+ LINK_ENCRYPTION_STATUS,
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
DRM_DEBUG_KMS("Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 915e94718a23..fe64fb4987b0 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -319,8 +319,7 @@ static void intel_enable_lvds(struct intel_encoder *encoder,
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
POSTING_READ(lvds_encoder->reg);
- if (intel_wait_for_register(&dev_priv->uncore,
- PP_STATUS(0), PP_ON, PP_ON, 5000))
+ if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
DRM_ERROR("timed out waiting for panel to power on\n");
intel_panel_enable_backlight(pipe_config, conn_state);
@@ -334,8 +333,7 @@ static void intel_disable_lvds(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
- if (intel_wait_for_register(&dev_priv->uncore,
- PP_STATUS(0), PP_ON, 0, 1000))
+ if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
DRM_ERROR("timed out waiting for panel to power off\n");
I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 119a2fb8d781..4b340d7657e0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -826,8 +826,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
}
/* Wait till PSR is idle */
- if (intel_wait_for_register(&dev_priv->uncore,
- psr_status, psr_status_mask, 0, 2000))
+ if (intel_de_wait_for_clear(dev_priv, psr_status, psr_status_mask, 2000))
DRM_ERROR("Timed out waiting PSR idle state\n");
/* Disable PSR on Sink */
@@ -989,7 +988,7 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)
mutex_unlock(&dev_priv->psr.lock);
- err = intel_wait_for_register(&dev_priv->uncore, reg, mask, 0, 50);
+ err = intel_de_wait_for_clear(dev_priv, reg, mask, 50);
if (err)
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index db9b5ab6c80f..87bdabd743b0 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -85,9 +85,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_GEN_FIFO_STAT(port), mask, mask,
- 100))
+ if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), mask, 100))
DRM_ERROR("DPI FIFOs are not empty\n");
}
@@ -155,10 +153,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
/* note: this is never true for reads */
if (packet.payload_length) {
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_GEN_FIFO_STAT(port),
- data_mask, 0,
- 50))
+ if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
+ data_mask, 50))
DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
write_data(dev_priv, data_reg, packet.payload,
@@ -169,10 +165,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
}
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_GEN_FIFO_STAT(port),
- ctrl_mask, 0,
- 50)) {
+ if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port),
+ ctrl_mask, 50)) {
DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
}
@@ -181,10 +175,8 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
/* ->rx_len is set only for reads */
if (msg->rx_len) {
data_mask = GEN_READ_DATA_AVAIL;
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_INTR_STAT(port),
- data_mask, data_mask,
- 50))
+ if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port),
+ data_mask, 50))
DRM_ERROR("Timeout waiting for read data.\n");
read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
@@ -241,9 +233,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
mask = SPL_PKT_SENT_INTERRUPT;
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_INTR_STAT(port), mask, mask,
- 100))
+ if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100))
DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
return 0;
@@ -360,11 +350,8 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder)
/* Wait for Pwr ACK */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_CTRL(port),
- GLK_MIPIIO_PORT_POWERED,
- GLK_MIPIIO_PORT_POWERED,
- 20))
+ if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
+ GLK_MIPIIO_PORT_POWERED, 20))
DRM_ERROR("MIPIO port is powergated\n");
}
@@ -386,11 +373,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to set */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_CTRL(port),
- GLK_PHY_STATUS_PORT_READY,
- GLK_PHY_STATUS_PORT_READY,
- 20))
+ if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
+ GLK_PHY_STATUS_PORT_READY, 20))
DRM_ERROR("PHY is not ON\n");
}
@@ -414,11 +398,8 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
I915_WRITE(MIPI_DEVICE_READY(port), val);
/* Wait for ULPS active */
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_CTRL(port),
- GLK_ULPS_NOT_ACTIVE,
- 0,
- 20))
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ GLK_ULPS_NOT_ACTIVE, 20))
DRM_ERROR("ULPS not active\n");
/* Exit ULPS */
@@ -441,21 +422,15 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder)
/* Wait for Stop state */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_CTRL(port),
- GLK_DATA_LANE_STOP_STATE,
- GLK_DATA_LANE_STOP_STATE,
- 20))
+ if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port),
+ GLK_DATA_LANE_STOP_STATE, 20))
DRM_ERROR("Date lane not in STOP state\n");
}
/* Wait for AFE LATCH */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(&dev_priv->uncore,
- BXT_MIPI_PORT_CTRL(port),
- AFE_LATCHOUT,
- AFE_LATCHOUT,
- 20))
+ if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port),
+ AFE_LATCHOUT, 20))
DRM_ERROR("D-PHY not entering LP-11 state\n");
}
}
@@ -555,17 +530,15 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_CTRL(port),
- GLK_PHY_STATUS_PORT_READY, 0, 20))
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ GLK_PHY_STATUS_PORT_READY, 20))
DRM_ERROR("PHY is not turning OFF\n");
}
/* Wait for Pwr ACK bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_CTRL(port),
- GLK_MIPIIO_PORT_POWERED, 0, 20))
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ GLK_MIPIIO_PORT_POWERED, 20))
DRM_ERROR("MIPI IO Port is not powergated\n");
}
}
@@ -584,9 +557,8 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
/* Wait for MIPI PHY status bit to unset */
for_each_dsi_port(port, intel_dsi->ports) {
- if (intel_wait_for_register(&dev_priv->uncore,
- MIPI_CTRL(port),
- GLK_PHY_STATUS_PORT_READY, 0, 20))
+ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port),
+ GLK_PHY_STATUS_PORT_READY, 20))
DRM_ERROR("PHY is not turning OFF\n");
}
@@ -634,9 +606,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
* Port A only. MIPI Port C has no similar bit for checking.
*/
if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
- intel_wait_for_register(&dev_priv->uncore,
- port_ctrl, AFE_LATCHOUT, 0,
- 30))
+ intel_de_wait_for_clear(dev_priv, port_ctrl, AFE_LATCHOUT, 30))
DRM_ERROR("DSI LP not going Low\n");
/* Disable MIPI PHY transparent latch */
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index aa64e6501f3b..8d77d2f8236d 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -247,11 +247,8 @@ void bxt_dsi_pll_disable(struct intel_encoder *encoder)
* PLL lock should deassert within 200us.
* Wait up to 1ms before timing out.
*/
- if (intel_wait_for_register(&dev_priv->uncore,
- BXT_DSI_PLL_ENABLE,
- BXT_DSI_PLL_LOCKED,
- 0,
- 1))
+ if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE,
+ BXT_DSI_PLL_LOCKED, 1))
DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
}
@@ -531,11 +528,8 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder,
I915_WRITE(BXT_DSI_PLL_ENABLE, val);
/* Timeout and fail if PLL not locked */
- if (intel_wait_for_register(&dev_priv->uncore,
- BXT_DSI_PLL_ENABLE,
- BXT_DSI_PLL_LOCKED,
- BXT_DSI_PLL_LOCKED,
- 1)) {
+ if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE,
+ BXT_DSI_PLL_LOCKED, 1)) {
DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
return;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 35db81d66785..9578f1c1f099 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2446,6 +2446,17 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data,
#define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
+/* register wait wrappers for display regs */
+#define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
+ intel_wait_for_register(&(dev_priv_)->uncore, \
+ (reg_), (mask_), (value_), (timeout_))
+
+#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) \
+ intel_de_wait_for_register(dev_priv_, reg_, mask_, mask_, timeout_)
+
+#define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
+ intel_de_wait_for_register(dev_priv_, reg_, mask_, 0, timeout_)
+
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn, unsigned long size,
--
2.22.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Some more display uncore prep work
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2019-08-16 1:23 ` [PATCH 6/6] drm/i915: Wrappers for display register waits Daniele Ceraolo Spurio
@ 2019-08-16 1:46 ` Patchwork
2019-08-16 2:19 ` ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-08-16 1:46 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Some more display uncore prep work
URL : https://patchwork.freedesktop.org/series/65281/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
683fe77978b3 drm/i915: Move i915_power_well_id out of i915_reg.h
54c3dc873f33 drm/i915: Move engine IDs out of i915_reg.h
2fd5c6189863 drm/i915: Move gmbus definitions out of i915_reg.h
d24c490ba03f drm/i915: Dynamically allocate s0ix struct for VLV
-:98: CHECK:ALLOC_SIZEOF_STRUCT: Prefer kmalloc(sizeof(*i915->s0ix_state)...) over kmalloc(sizeof(struct vlv_s0ix_state)...)
#98: FILE: drivers/gpu/drm/i915/i915_drv.c:537:
+ i915->s0ix_state = kmalloc(sizeof(struct vlv_s0ix_state), GFP_KERNEL);
total: 0 errors, 0 warnings, 1 checks, 256 lines checked
6eac8d3be838 drm/i915: Introduce i915_reg_types.h
-:1369: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#1369:
new file mode 100644
-:1374: WARNING:SPDX_LICENSE_TAG: Improper SPDX comment style for 'drivers/gpu/drm/i915/i915_reg_types.h', please use '/*' instead
#1374: FILE: drivers/gpu/drm/i915/i915_reg_types.h:1:
+// SPDX-License-Identifier: MIT
-:1374: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#1374: FILE: drivers/gpu/drm/i915/i915_reg_types.h:1:
+// SPDX-License-Identifier: MIT
-:1481: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__n' - possible side-effects?
#1481: FILE: drivers/gpu/drm/i915/i915_reg_types.h:108:
+#define REG_BIT(__n) \
+ ((u32)(BIT(__n) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
+ ((__n) < 0 || (__n) > 31))))
-:1495: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#1495: FILE: drivers/gpu/drm/i915/i915_reg_types.h:122:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:1495: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#1495: FILE: drivers/gpu/drm/i915/i915_reg_types.h:122:
+#define REG_GENMASK(__high, __low) \
+ ((u32)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
-:1504: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__x' - possible side-effects?
#1504: FILE: drivers/gpu/drm/i915/i915_reg_types.h:131:
+#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
-:1516: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__mask' - possible side-effects?
#1516: FILE: drivers/gpu/drm/i915/i915_reg_types.h:143:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1516: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__val' - possible side-effects?
#1516: FILE: drivers/gpu/drm/i915/i915_reg_types.h:143:
+#define REG_FIELD_PREP(__mask, __val) \
+ ((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
+ BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
+ BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
+ BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1521: WARNING:LONG_LINE: line over 100 characters
#1521: FILE: drivers/gpu/drm/i915/i915_reg_types.h:148:
+ BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
-:1541: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__a' - possible side-effects?
#1541: FILE: drivers/gpu/drm/i915/i915_reg_types.h:168:
+#define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
-:1551: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#1551: FILE: drivers/gpu/drm/i915/i915_reg_types.h:178:
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask)) \
+ BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask), \
+ "Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
-:1551: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'value' - possible side-effects?
#1551: FILE: drivers/gpu/drm/i915/i915_reg_types.h:178:
+#define _MASKED_FIELD(mask, value) ({ \
+ if (__builtin_constant_p(mask)) \
+ BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+ if (__builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+ if (__builtin_constant_p(mask) && __builtin_constant_p(value)) \
+ BUILD_BUG_ON_MSG((value) & ~(mask), \
+ "Incorrect value for mask"); \
+ __MASKED_FIELD(mask, value); })
-:1563: WARNING:NEW_TYPEDEFS: do not add new typedefs
#1563: FILE: drivers/gpu/drm/i915/i915_reg_types.h:190:
+typedef struct {
total: 0 errors, 5 warnings, 9 checks, 1145 lines checked
a2070d35d167 drm/i915: Wrappers for display register waits
-:900: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask_' - possible side-effects?
#900: FILE: drivers/gpu/drm/i915/i915_drv.h:2454:
+#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) \
+ intel_de_wait_for_register(dev_priv_, reg_, mask_, mask_, timeout_)
total: 0 errors, 0 warnings, 1 checks, 753 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.BAT: success for Some more display uncore prep work
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2019-08-16 1:46 ` ✗ Fi.CI.CHECKPATCH: warning for Some more display uncore prep work Patchwork
@ 2019-08-16 2:19 ` Patchwork
2019-08-16 17:30 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-16 21:22 ` [PATCH 0/6] " Chris Wilson
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-08-16 2:19 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Some more display uncore prep work
URL : https://patchwork.freedesktop.org/series/65281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6714 -> Patchwork_14043
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/
Known issues
------------
Here are the changes found in Patchwork_14043 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@bad-flink:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@gem_flink_basic@bad-flink.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/fi-icl-u3/igt@gem_flink_basic@bad-flink.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- fi-icl-u3: [DMESG-WARN][3] ([fdo#107724]) -> [PASS][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
* igt@kms_busy@basic-flip-a:
- fi-kbl-7567u: [SKIP][5] ([fdo#109271] / [fdo#109278]) -> [PASS][6] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
Participating hosts (52 -> 46)
------------------------------
Missing (6): fi-kbl-soraka fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6714 -> Patchwork_14043
CI-20190529: 20190529
CI_DRM_6714: 9198974f9fa309c4c74197365844971e0940b227 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14043: a2070d35d167f5323e8cdbdf74c569ddcdc5a112 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
a2070d35d167 drm/i915: Wrappers for display register waits
6eac8d3be838 drm/i915: Introduce i915_reg_types.h
d24c490ba03f drm/i915: Dynamically allocate s0ix struct for VLV
2fd5c6189863 drm/i915: Move gmbus definitions out of i915_reg.h
54c3dc873f33 drm/i915: Move engine IDs out of i915_reg.h
683fe77978b3 drm/i915: Move i915_power_well_id out of i915_reg.h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h
2019-08-16 1:23 ` [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h Daniele Ceraolo Spurio
@ 2019-08-16 4:52 ` Lucas De Marchi
2019-08-16 15:27 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 25+ messages in thread
From: Lucas De Marchi @ 2019-08-16 4:52 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Intel Graphics
On Thu, Aug 15, 2019 at 6:24 PM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> It has nothing to do with registers, so move it to the more appropriate
> intel_display_power.h
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 1 +
> .../drm/i915/display/intel_display_power.h | 21 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 21 -------------------
> 4 files changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 374b75602141..1caae2f61216 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -13,6 +13,7 @@
> #include "intel_cdclk.h"
> #include "intel_combo_phy.h"
> #include "intel_csr.h"
> +#include "intel_display_power.h"
> #include "intel_display_types.h"
> #include "intel_dpio_phy.h"
> #include "intel_hotplug.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 97f2562fc5d3..a50605b8b1ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -92,6 +92,27 @@ enum intel_display_power_domain {
> POWER_DOMAIN_NUM,
> };
>
> +/*
> + * i915_power_well_id:
> + *
> + * IDs used to look up power wells. Power wells accessed directly bypassing
> + * the power domains framework must be assigned a unique ID. The rest of power
> + * wells must be assigned DISP_PW_ID_NONE.
> + */
> +enum i915_power_well_id {
> + DISP_PW_ID_NONE,
> +
> + VLV_DISP_PW_DISP2D,
> + BXT_DISP_PW_DPIO_CMN_A,
> + VLV_DISP_PW_DPIO_CMN_BC,
> + GLK_DISP_PW_DPIO_CMN_C,
> + CHV_DISP_PW_DPIO_CMN_D,
> + HSW_DISP_PW_GLOBAL,
> + SKL_DISP_PW_MISC_IO,
> + SKL_DISP_PW_1,
> + SKL_DISP_PW_2,
> +};
> +
> #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
> #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
> ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index dc4aaec2e04c..0beb954b5318 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -14,6 +14,7 @@
> #include <drm/i915_component.h>
>
> #include "i915_reg.h"
> +#include "intel_display_power.h"
> #include "intel_display_types.h"
> #include "intel_hdcp.h"
> #include "intel_sideband.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2b7ccebf6550..14165d619175 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1163,27 +1163,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define PUNIT_REG_ISPSSPM0 0x39
> #define PUNIT_REG_ISPSSPM1 0x3a
>
> -/*
> - * i915_power_well_id:
> - *
> - * IDs used to look up power wells. Power wells accessed directly bypassing
> - * the power domains framework must be assigned a unique ID. The rest of power
> - * wells must be assigned DISP_PW_ID_NONE.
> - */
> -enum i915_power_well_id {
> - DISP_PW_ID_NONE,
> -
> - VLV_DISP_PW_DISP2D,
> - BXT_DISP_PW_DPIO_CMN_A,
> - VLV_DISP_PW_DPIO_CMN_BC,
> - GLK_DISP_PW_DPIO_CMN_C,
> - CHV_DISP_PW_DPIO_CMN_D,
> - HSW_DISP_PW_GLOBAL,
> - SKL_DISP_PW_MISC_IO,
> - SKL_DISP_PW_1,
> - SKL_DISP_PW_2,
> -};
drivers/gpu/drm/i915/display/intel_hdcp.c also uses this enum, so it
should also include the header
in which it's defined.
other than that
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> -
> #define PUNIT_REG_PWRGT_CTRL 0x60
> #define PUNIT_REG_PWRGT_STATUS 0x61
> #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/6] drm/i915: Move engine IDs out of i915_reg.h
2019-08-16 1:23 ` [PATCH 2/6] drm/i915: Move engine IDs " Daniele Ceraolo Spurio
@ 2019-08-16 4:56 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2019-08-16 4:56 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Intel Graphics
On Thu, Aug 15, 2019 at 6:23 PM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> To remove the dependency between the GT headers and i915_reg.h, move the
> definition of the engine IDs/classes to intel_engine_types.h
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/gt/intel_engine_types.h | 20 +++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 27 +++-----------------
> 3 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> index a0f372807dd4..8f10c5ffd68d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
> @@ -26,6 +26,26 @@
> #include "intel_wakeref.h"
> #include "intel_workarounds_types.h"
>
> +/* Legacy HW Engine ID */
> +
> +#define RCS0_HW 0
> +#define VCS0_HW 1
> +#define BCS0_HW 2
> +#define VECS0_HW 3
> +#define VCS1_HW 4
> +#define VCS2_HW 6
> +#define VCS3_HW 7
> +#define VECS1_HW 12
> +
> +/* Gen11+ HW Engine class + instance */
> +#define RENDER_CLASS 0
> +#define VIDEO_DECODE_CLASS 1
> +#define VIDEO_ENHANCEMENT_CLASS 2
> +#define COPY_ENGINE_CLASS 3
> +#define OTHER_CLASS 4
> +#define MAX_ENGINE_CLASS 4
> +#define MAX_ENGINE_INSTANCE 3
> +
> #define I915_MAX_SLICES 3
> #define I915_MAX_SUBSLICES 8
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index adab4d2c29ac..81f9de45ab36 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -16,6 +16,7 @@
> #include "uc/intel_uc.h"
>
> #include "i915_vma.h"
> +#include "intel_engine_types.h"
> #include "intel_reset_types.h"
> #include "intel_wakeref.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 14165d619175..827795262d68 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -272,30 +272,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
> #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
>
> -/* Engine ID */
> -
> -#define RCS0_HW 0
> -#define VCS0_HW 1
> -#define BCS0_HW 2
> -#define VECS0_HW 3
> -#define VCS1_HW 4
> -#define VCS2_HW 6
> -#define VCS3_HW 7
> -#define VECS1_HW 12
> -
> -/* Engine class */
> -
> -#define RENDER_CLASS 0
> -#define VIDEO_DECODE_CLASS 1
> -#define VIDEO_ENHANCEMENT_CLASS 2
> -#define COPY_ENGINE_CLASS 3
> -#define OTHER_CLASS 4
> -#define MAX_ENGINE_CLASS 4
> -
> -#define OTHER_GUC_INSTANCE 0
> -#define OTHER_GTPM_INSTANCE 1
> -#define MAX_ENGINE_INSTANCE 3
> -
> /* PCI config space */
>
> #define MCHBAR_I915 0x44
> @@ -7505,6 +7481,9 @@ enum {
> #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16)
> #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20)
> #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff)
> +/* irq instances for OTHER_CLASS */
> +#define OTHER_GUC_INSTANCE 0
> +#define OTHER_GTPM_INSTANCE 1
>
> #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
>
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/6] drm/i915: Move gmbus definitions out of i915_reg.h
2019-08-16 1:23 ` [PATCH 3/6] drm/i915: Move gmbus definitions " Daniele Ceraolo Spurio
@ 2019-08-16 5:03 ` Lucas De Marchi
0 siblings, 0 replies; 25+ messages in thread
From: Lucas De Marchi @ 2019-08-16 5:03 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Jani Nikula, Intel Graphics
On Thu, Aug 15, 2019 at 6:24 PM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> They're not related to registers, so move them to the more appropriate
> intel_gmbus.h
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_gmbus.h | 22 ++++++++++++++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 22 +---------------------
> 3 files changed, 24 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index d989085b8d22..b96212b85425 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -11,6 +11,28 @@
> struct drm_i915_private;
> struct i2c_adapter;
>
> +#define GMBUS_PIN_DISABLED 0
> +#define GMBUS_PIN_SSC 1
> +#define GMBUS_PIN_VGADDC 2
> +#define GMBUS_PIN_PANEL 3
> +#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
> +#define GMBUS_PIN_DPC 4 /* HDMIC */
> +#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
> +#define GMBUS_PIN_DPD 6 /* HDMID */
> +#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
> +#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
> +#define GMBUS_PIN_2_BXT 2
> +#define GMBUS_PIN_3_BXT 3
> +#define GMBUS_PIN_4_CNP 4
> +#define GMBUS_PIN_9_TC1_ICP 9
> +#define GMBUS_PIN_10_TC2_ICP 10
> +#define GMBUS_PIN_11_TC3_ICP 11
> +#define GMBUS_PIN_12_TC4_ICP 12
> +#define GMBUS_PIN_13_TC5_TGP 13
> +#define GMBUS_PIN_14_TC6_TGP 14
> +
> +#define GMBUS_NUM_PINS 15 /* including 0 */
> +
> int intel_gmbus_setup(struct drm_i915_private *dev_priv);
> void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
> bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c4406a60f3e4..c6722d54ccd5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -68,6 +68,7 @@
> #include "display/intel_display_power.h"
> #include "display/intel_dpll_mgr.h"
> #include "display/intel_frontbuffer.h"
> +#include "display/intel_gmbus.h"
if it wasn't GMBUS_NUM_PINS we could include-what-you-use rather than
adding the include here.
Alternative would be to leave the GMBUS_NUM_PINS here, which would be
ugly. Or dynamically allocate
the array, that would deserve a more careful thought.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> #include "display/intel_opregion.h"
>
> #include "gem/i915_gem_context_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 827795262d68..ea2f0fa2402d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3207,27 +3207,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */
> #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
> #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
> -#define GMBUS_PIN_DISABLED 0
> -#define GMBUS_PIN_SSC 1
> -#define GMBUS_PIN_VGADDC 2
> -#define GMBUS_PIN_PANEL 3
> -#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
> -#define GMBUS_PIN_DPC 4 /* HDMIC */
> -#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
> -#define GMBUS_PIN_DPD 6 /* HDMID */
> -#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
> -#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
> -#define GMBUS_PIN_2_BXT 2
> -#define GMBUS_PIN_3_BXT 3
> -#define GMBUS_PIN_4_CNP 4
> -#define GMBUS_PIN_9_TC1_ICP 9
> -#define GMBUS_PIN_10_TC2_ICP 10
> -#define GMBUS_PIN_11_TC3_ICP 11
> -#define GMBUS_PIN_12_TC4_ICP 12
> -#define GMBUS_PIN_13_TC5_TGP 13
> -#define GMBUS_PIN_14_TC6_TGP 14
> -
> -#define GMBUS_NUM_PINS 15 /* including 0 */
> +
> #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
> #define GMBUS_SW_CLR_INT (1 << 31)
> #define GMBUS_SW_RDY (1 << 30)
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
2019-08-16 1:23 ` [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV Daniele Ceraolo Spurio
@ 2019-08-16 5:09 ` Lucas De Marchi
2019-08-16 15:30 ` Daniele Ceraolo Spurio
2019-08-16 9:35 ` Jani Nikula
1 sibling, 1 reply; 25+ messages in thread
From: Lucas De Marchi @ 2019-08-16 5:09 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Intel Graphics
On Thu, Aug 15, 2019 at 6:24 PM Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
>
> This is only required for a single platform so no need to reserve the
> memory on all of them.
>
> This removes the last direct dependency of i915_drv.h on i915_reg.h
> (apart from the i915_reg_t definition).
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 107 +++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/i915_drv.h | 64 +------------------
> 2 files changed, 100 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2541a3a1c229..1723b2ddfccd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -80,6 +80,68 @@
>
> static struct drm_driver driver;
>
> +struct vlv_s0ix_state {
> + /* GAM */
> + u32 wr_watermark;
> + u32 gfx_prio_ctrl;
> + u32 arb_mode;
> + u32 gfx_pend_tlb0;
> + u32 gfx_pend_tlb1;
> + u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
> + u32 media_max_req_count;
> + u32 gfx_max_req_count;
> + u32 render_hwsp;
> + u32 ecochk;
> + u32 bsd_hwsp;
> + u32 blt_hwsp;
> + u32 tlb_rd_addr;
> +
> + /* MBC */
> + u32 g3dctl;
> + u32 gsckgctl;
> + u32 mbctl;
> +
> + /* GCP */
> + u32 ucgctl1;
> + u32 ucgctl3;
> + u32 rcgctl1;
> + u32 rcgctl2;
> + u32 rstctl;
> + u32 misccpctl;
> +
> + /* GPM */
> + u32 gfxpause;
> + u32 rpdeuhwtc;
> + u32 rpdeuc;
> + u32 ecobus;
> + u32 pwrdwnupctl;
> + u32 rp_down_timeout;
> + u32 rp_deucsw;
> + u32 rcubmabdtmr;
> + u32 rcedata;
> + u32 spare2gh;
> +
> + /* Display 1 CZ domain */
> + u32 gt_imr;
> + u32 gt_ier;
> + u32 pm_imr;
> + u32 pm_ier;
> + u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
> +
> + /* GT SA CZ domain */
> + u32 tilectl;
> + u32 gt_fifoctl;
> + u32 gtlc_wake_ctrl;
> + u32 gtlc_survive;
> + u32 pmwgicz;
> +
> + /* Display 2 CZ domain */
> + u32 gu_ctl0;
> + u32 gu_ctl1;
> + u32 pcbr;
> + u32 clock_gate_dis2;
> +};
> +
> static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
> {
> int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
> @@ -466,6 +528,28 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> }
> }
>
> +static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
> +{
> + if (!IS_VALLEYVIEW(i915))
> + return 0;
> +
> + /* we write all the values in the structure, so no need to zero it out */
> + i915->s0ix_state = kmalloc(sizeof(struct vlv_s0ix_state), GFP_KERNEL);
> + if (!i915->s0ix_state)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +
> +static void vlv_free_s0ix_state(struct drm_i915_private *i915)
> +{
> + if (!i915->s0ix_state)
> + return;
> +
> + kfree(i915->s0ix_state);
> + i915->s0ix_state = NULL;
> +}
> +
> /**
> * i915_driver_early_probe - setup state not requiring device access
> * @dev_priv: device private
> @@ -508,13 +592,17 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> if (ret < 0)
> return ret;
>
> + ret = vlv_alloc_s0ix_state(dev_priv);
> + if (ret < 0)
> + goto err_workqueues;
> +
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> intel_gt_init_early(&dev_priv->gt, dev_priv);
>
> ret = i915_gem_init_early(dev_priv);
> if (ret < 0)
> - goto err_workqueues;
> + goto err_gt;
>
> /* This must be called before any calls to HAS_PCH_* */
> intel_detect_pch(dev_priv);
> @@ -536,8 +624,10 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> err_gem:
> i915_gem_cleanup_early(dev_priv);
> -err_workqueues:
> +err_gt:
> intel_gt_driver_late_release(&dev_priv->gt);
> + vlv_free_s0ix_state(dev_priv);
> +err_workqueues:
> i915_workqueues_cleanup(dev_priv);
> return ret;
> }
> @@ -553,6 +643,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
> intel_power_domains_cleanup(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> intel_gt_driver_late_release(&dev_priv->gt);
> + vlv_free_s0ix_state(dev_priv);
> i915_workqueues_cleanup(dev_priv);
>
> pm_qos_remove_request(&dev_priv->sb_qos);
> @@ -2137,7 +2228,7 @@ static int i915_pm_restore(struct device *kdev)
> */
> static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> {
> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
> + struct vlv_s0ix_state *s = dev_priv->s0ix_state;
> int i;
>
> /* GAM 0x4000-0x4770 */
> @@ -2147,7 +2238,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
> s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
>
> - for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> + for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
> s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
>
> s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
> @@ -2191,7 +2282,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> s->pm_imr = I915_READ(GEN6_PMIMR);
> s->pm_ier = I915_READ(GEN6_PMIER);
>
> - for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> + for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
> s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
>
> /* GT SA CZ domain, 0x100000-0x138124 */
> @@ -2218,7 +2309,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>
> static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> {
> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
> + struct vlv_s0ix_state *s = dev_priv->s0ix_state;
> u32 val;
> int i;
>
> @@ -2229,7 +2320,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
> I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
>
> - for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> + for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
why?
Lucas De Marchi
> I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
>
> I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
> @@ -2273,7 +2364,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_PMIMR, s->pm_imr);
> I915_WRITE(GEN6_PMIER, s->pm_ier);
>
> - for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> + for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
> I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
>
> /* GT SA CZ domain, 0x100000-0x138124 */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c6722d54ccd5..9b41f2209b69 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -527,68 +527,6 @@ struct i915_suspend_saved_registers {
> u16 saveGCDGMBUS;
> };
>
> -struct vlv_s0ix_state {
> - /* GAM */
> - u32 wr_watermark;
> - u32 gfx_prio_ctrl;
> - u32 arb_mode;
> - u32 gfx_pend_tlb0;
> - u32 gfx_pend_tlb1;
> - u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
> - u32 media_max_req_count;
> - u32 gfx_max_req_count;
> - u32 render_hwsp;
> - u32 ecochk;
> - u32 bsd_hwsp;
> - u32 blt_hwsp;
> - u32 tlb_rd_addr;
> -
> - /* MBC */
> - u32 g3dctl;
> - u32 gsckgctl;
> - u32 mbctl;
> -
> - /* GCP */
> - u32 ucgctl1;
> - u32 ucgctl3;
> - u32 rcgctl1;
> - u32 rcgctl2;
> - u32 rstctl;
> - u32 misccpctl;
> -
> - /* GPM */
> - u32 gfxpause;
> - u32 rpdeuhwtc;
> - u32 rpdeuc;
> - u32 ecobus;
> - u32 pwrdwnupctl;
> - u32 rp_down_timeout;
> - u32 rp_deucsw;
> - u32 rcubmabdtmr;
> - u32 rcedata;
> - u32 spare2gh;
> -
> - /* Display 1 CZ domain */
> - u32 gt_imr;
> - u32 gt_ier;
> - u32 pm_imr;
> - u32 pm_ier;
> - u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
> -
> - /* GT SA CZ domain */
> - u32 tilectl;
> - u32 gt_fifoctl;
> - u32 gtlc_wake_ctrl;
> - u32 gtlc_survive;
> - u32 pmwgicz;
> -
> - /* Display 2 CZ domain */
> - u32 gu_ctl0;
> - u32 gu_ctl1;
> - u32 pcbr;
> - u32 clock_gate_dis2;
> -};
> -
> struct intel_rps_ei {
> ktime_t ktime;
> u32 render_c0;
> @@ -1622,7 +1560,7 @@ struct drm_i915_private {
> u32 suspend_count;
> bool power_domains_suspended;
> struct i915_suspend_saved_registers regfile;
> - struct vlv_s0ix_state vlv_s0ix_state;
> + void *s0ix_state;
>
> enum {
> I915_SAGV_UNKNOWN = 0,
> --
> 2.22.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 6/6] drm/i915: Wrappers for display register waits
2019-08-16 1:23 ` [PATCH 6/6] drm/i915: Wrappers for display register waits Daniele Ceraolo Spurio
@ 2019-08-16 7:17 ` Chris Wilson
0 siblings, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2019-08-16 7:17 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Jani Nikula
Quoting Daniele Ceraolo Spurio (2019-08-16 02:23:43)
> To reduce the number of explicit dev_priv->uncore calls in the display
> code ahead of the introduction of dev_priv->de_uncore, this patch
> introduces a wrapper for one of the main usages of it, the register
> waits. When we transition to the new uncore, we can just update the
> wrapper to point to the appropriate structure.
>
> Since the vast majority of waits are on a set or clear of a bit or mask,
> add set & clear flavours of the wrapper to simplify the code.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 11 +--
> drivers/gpu/drm/i915/display/intel_cdclk.c | 18 +----
> drivers/gpu/drm/i915/display/intel_crt.c | 17 ++--
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
> drivers/gpu/drm/i915/display/intel_display.c | 45 +++--------
> .../drm/i915/display/intel_display_power.c | 32 +++-----
> drivers/gpu/drm/i915/display/intel_dp.c | 10 +--
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 5 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 44 +++-------
> drivers/gpu/drm/i915/display/intel_fbc.c | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 32 +++-----
> drivers/gpu/drm/i915/display/intel_lvds.c | 6 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 5 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 80 ++++++-------------
> drivers/gpu/drm/i915/display/vlv_dsi_pll.c | 14 +---
> drivers/gpu/drm/i915/i915_drv.h | 11 +++
> 17 files changed, 112 insertions(+), 235 deletions(-)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 35db81d66785..9578f1c1f099 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2446,6 +2446,17 @@ int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> #define I915_READ_FW(reg__) __I915_REG_OP(read_fw, dev_priv, (reg__))
> #define I915_WRITE_FW(reg__, val__) __I915_REG_OP(write_fw, dev_priv, (reg__), (val__))
>
> +/* register wait wrappers for display regs */
> +#define intel_de_wait_for_register(dev_priv_, reg_, mask_, value_, timeout_) \
> + intel_wait_for_register(&(dev_priv_)->uncore, \
> + (reg_), (mask_), (value_), (timeout_))
> +
> +#define intel_de_wait_for_set(dev_priv_, reg_, mask_, timeout_) \
> + intel_de_wait_for_register(dev_priv_, reg_, mask_, mask_, timeout_)
> +
> +#define intel_de_wait_for_clear(dev_priv_, reg_, mask_, timeout_) \
> + intel_de_wait_for_register(dev_priv_, reg_, mask_, 0, timeout_)
wait_for_set & wait_for_clear was a nice improvement in clarity.
I didn't see any incorrect conversions,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
2019-08-16 1:23 ` [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV Daniele Ceraolo Spurio
2019-08-16 5:09 ` Lucas De Marchi
@ 2019-08-16 9:35 ` Jani Nikula
2019-08-16 9:40 ` Chris Wilson
2019-08-16 15:33 ` Daniele Ceraolo Spurio
1 sibling, 2 replies; 25+ messages in thread
From: Jani Nikula @ 2019-08-16 9:35 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On Thu, 15 Aug 2019, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote:
> This is only required for a single platform so no need to reserve the
> memory on all of them.
>
> This removes the last direct dependency of i915_drv.h on i915_reg.h
> (apart from the i915_reg_t definition).
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
Heh, I've already sent a version of this [1], but I don't mind you
finishing the job. Especially because I think it's better to handle the
alloc/free explicitly instead of the way I do it.
I do have some nitpicks on this one though, inline.
[1] http://patchwork.freedesktop.org/patch/msgid/20190807144939.32123-1-jani.nikula@intel.com
> ---
> drivers/gpu/drm/i915/i915_drv.c | 107 +++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/i915_drv.h | 64 +------------------
> 2 files changed, 100 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2541a3a1c229..1723b2ddfccd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -80,6 +80,68 @@
>
> static struct drm_driver driver;
>
> +struct vlv_s0ix_state {
> + /* GAM */
> + u32 wr_watermark;
> + u32 gfx_prio_ctrl;
> + u32 arb_mode;
> + u32 gfx_pend_tlb0;
> + u32 gfx_pend_tlb1;
> + u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
> + u32 media_max_req_count;
> + u32 gfx_max_req_count;
> + u32 render_hwsp;
> + u32 ecochk;
> + u32 bsd_hwsp;
> + u32 blt_hwsp;
> + u32 tlb_rd_addr;
> +
> + /* MBC */
> + u32 g3dctl;
> + u32 gsckgctl;
> + u32 mbctl;
> +
> + /* GCP */
> + u32 ucgctl1;
> + u32 ucgctl3;
> + u32 rcgctl1;
> + u32 rcgctl2;
> + u32 rstctl;
> + u32 misccpctl;
> +
> + /* GPM */
> + u32 gfxpause;
> + u32 rpdeuhwtc;
> + u32 rpdeuc;
> + u32 ecobus;
> + u32 pwrdwnupctl;
> + u32 rp_down_timeout;
> + u32 rp_deucsw;
> + u32 rcubmabdtmr;
> + u32 rcedata;
> + u32 spare2gh;
> +
> + /* Display 1 CZ domain */
> + u32 gt_imr;
> + u32 gt_ier;
> + u32 pm_imr;
> + u32 pm_ier;
> + u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
> +
> + /* GT SA CZ domain */
> + u32 tilectl;
> + u32 gt_fifoctl;
> + u32 gtlc_wake_ctrl;
> + u32 gtlc_survive;
> + u32 pmwgicz;
> +
> + /* Display 2 CZ domain */
> + u32 gu_ctl0;
> + u32 gu_ctl1;
> + u32 pcbr;
> + u32 clock_gate_dis2;
> +};
> +
> static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
> {
> int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
> @@ -466,6 +528,28 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
> }
> }
>
> +static int vlv_alloc_s0ix_state(struct drm_i915_private *i915)
> +{
> + if (!IS_VALLEYVIEW(i915))
> + return 0;
> +
> + /* we write all the values in the structure, so no need to zero it out */
> + i915->s0ix_state = kmalloc(sizeof(struct vlv_s0ix_state), GFP_KERNEL);
> + if (!i915->s0ix_state)
> + return -ENOMEM;
> +
> + return 0;
> +}
> +
> +static void vlv_free_s0ix_state(struct drm_i915_private *i915)
> +{
> + if (!i915->s0ix_state)
> + return;
> +
> + kfree(i915->s0ix_state);
> + i915->s0ix_state = NULL;
> +}
> +
> /**
> * i915_driver_early_probe - setup state not requiring device access
> * @dev_priv: device private
> @@ -508,13 +592,17 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> if (ret < 0)
> return ret;
>
> + ret = vlv_alloc_s0ix_state(dev_priv);
> + if (ret < 0)
> + goto err_workqueues;
> +
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> intel_gt_init_early(&dev_priv->gt, dev_priv);
>
> ret = i915_gem_init_early(dev_priv);
> if (ret < 0)
> - goto err_workqueues;
> + goto err_gt;
>
> /* This must be called before any calls to HAS_PCH_* */
> intel_detect_pch(dev_priv);
> @@ -536,8 +624,10 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> err_gem:
> i915_gem_cleanup_early(dev_priv);
> -err_workqueues:
> +err_gt:
> intel_gt_driver_late_release(&dev_priv->gt);
> + vlv_free_s0ix_state(dev_priv);
> +err_workqueues:
> i915_workqueues_cleanup(dev_priv);
> return ret;
> }
> @@ -553,6 +643,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
> intel_power_domains_cleanup(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> intel_gt_driver_late_release(&dev_priv->gt);
> + vlv_free_s0ix_state(dev_priv);
> i915_workqueues_cleanup(dev_priv);
>
> pm_qos_remove_request(&dev_priv->sb_qos);
> @@ -2137,7 +2228,7 @@ static int i915_pm_restore(struct device *kdev)
> */
> static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> {
> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
> + struct vlv_s0ix_state *s = dev_priv->s0ix_state;
I think I'd now call this function unconditionally, and return early if
(!s). This puts the decision to do this or not in one place only, in
vlv_alloc_s0ix_state(), instead of duplicating the conditions.
> int i;
>
> /* GAM 0x4000-0x4770 */
> @@ -2147,7 +2238,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
> s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
>
> - for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> + for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
> s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
>
> s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
> @@ -2191,7 +2282,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> s->pm_imr = I915_READ(GEN6_PMIMR);
> s->pm_ier = I915_READ(GEN6_PMIER);
>
> - for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> + for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
> s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
The above two hunks are in the wrong patch.
>
> /* GT SA CZ domain, 0x100000-0x138124 */
> @@ -2218,7 +2309,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>
> static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> {
> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
> + struct vlv_s0ix_state *s = dev_priv->s0ix_state;
Early return on !s here as well, and call the function unconditionally.
> u32 val;
> int i;
>
> @@ -2229,7 +2320,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
> I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
>
> - for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
> + for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
> I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
>
> I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
> @@ -2273,7 +2364,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_PMIMR, s->pm_imr);
> I915_WRITE(GEN6_PMIER, s->pm_ier);
>
> - for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
> + for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
> I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
The above two hunks are in the wrong patch.
>
> /* GT SA CZ domain, 0x100000-0x138124 */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c6722d54ccd5..9b41f2209b69 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -527,68 +527,6 @@ struct i915_suspend_saved_registers {
> u16 saveGCDGMBUS;
> };
>
> -struct vlv_s0ix_state {
> - /* GAM */
> - u32 wr_watermark;
> - u32 gfx_prio_ctrl;
> - u32 arb_mode;
> - u32 gfx_pend_tlb0;
> - u32 gfx_pend_tlb1;
> - u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
> - u32 media_max_req_count;
> - u32 gfx_max_req_count;
> - u32 render_hwsp;
> - u32 ecochk;
> - u32 bsd_hwsp;
> - u32 blt_hwsp;
> - u32 tlb_rd_addr;
> -
> - /* MBC */
> - u32 g3dctl;
> - u32 gsckgctl;
> - u32 mbctl;
> -
> - /* GCP */
> - u32 ucgctl1;
> - u32 ucgctl3;
> - u32 rcgctl1;
> - u32 rcgctl2;
> - u32 rstctl;
> - u32 misccpctl;
> -
> - /* GPM */
> - u32 gfxpause;
> - u32 rpdeuhwtc;
> - u32 rpdeuc;
> - u32 ecobus;
> - u32 pwrdwnupctl;
> - u32 rp_down_timeout;
> - u32 rp_deucsw;
> - u32 rcubmabdtmr;
> - u32 rcedata;
> - u32 spare2gh;
> -
> - /* Display 1 CZ domain */
> - u32 gt_imr;
> - u32 gt_ier;
> - u32 pm_imr;
> - u32 pm_ier;
> - u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
> -
> - /* GT SA CZ domain */
> - u32 tilectl;
> - u32 gt_fifoctl;
> - u32 gtlc_wake_ctrl;
> - u32 gtlc_survive;
> - u32 pmwgicz;
> -
> - /* Display 2 CZ domain */
> - u32 gu_ctl0;
> - u32 gu_ctl1;
> - u32 pcbr;
> - u32 clock_gate_dis2;
> -};
> -
> struct intel_rps_ei {
> ktime_t ktime;
> u32 render_c0;
> @@ -1622,7 +1560,7 @@ struct drm_i915_private {
> u32 suspend_count;
> bool power_domains_suspended;
> struct i915_suspend_saved_registers regfile;
> - struct vlv_s0ix_state vlv_s0ix_state;
> + void *s0ix_state;
I'd keep the vlv_ prefix in the member name.
BR,
Jani.
>
> enum {
> I915_SAGV_UNKNOWN = 0,
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
2019-08-16 9:35 ` Jani Nikula
@ 2019-08-16 9:40 ` Chris Wilson
2019-08-16 10:32 ` Jani Nikula
2019-08-16 15:33 ` Daniele Ceraolo Spurio
1 sibling, 1 reply; 25+ messages in thread
From: Chris Wilson @ 2019-08-16 9:40 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, Jani Nikula, intel-gfx
Quoting Jani Nikula (2019-08-16 10:35:08)
> On Thu, 15 Aug 2019, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote:
> > @@ -1622,7 +1560,7 @@ struct drm_i915_private {
> > u32 suspend_count;
> > bool power_domains_suspended;
> > struct i915_suspend_saved_registers regfile;
> > - struct vlv_s0ix_state vlv_s0ix_state;
> > + void *s0ix_state;
>
> I'd keep the vlv_ prefix in the member name.
And forward decl to avoid a naked void *
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/6] drm/i915: Introduce i915_reg_types.h
2019-08-16 1:23 ` [PATCH 5/6] drm/i915: Introduce i915_reg_types.h Daniele Ceraolo Spurio
@ 2019-08-16 9:40 ` Michal Wajdeczko
2019-08-16 15:35 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 25+ messages in thread
From: Michal Wajdeczko @ 2019-08-16 9:40 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio; +Cc: Jani Nikula
On Fri, 16 Aug 2019 03:23:42 +0200, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> With the introduction of display uncore, we want to categorize registers
> between display and non-display. To help us getting it right, it will
> be useful to move the display registers to a new file that can be used
> without including i915_reg.h. To allow that, move all the basic register
> type definitions and helpers to i915_reg_types.h and include that
> instead of i915_reg.h from header files in the driver. We'll then
> be able to replace i915_reg.h with the new display-only header in
> display files and make sure the registers are correctly
> compartmentalized.
>
maybe this split should another way:
i915_reg.h = basic typedefs and macros
intel_reg.h = register definitions
and
intel_display_reg.h = display related regs (your goal)
intel_guc_reg.h = GuC related regs (we already have that!)
then we follow the rule to use i915_ prefix for driver specific
code and intel_ prefix for hardware originated definitions
Michal
_______________________________________________
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
2019-08-16 9:40 ` Chris Wilson
@ 2019-08-16 10:32 ` Jani Nikula
0 siblings, 0 replies; 25+ messages in thread
From: Jani Nikula @ 2019-08-16 10:32 UTC (permalink / raw)
To: Chris Wilson, Daniele Ceraolo Spurio, intel-gfx
On Fri, 16 Aug 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Jani Nikula (2019-08-16 10:35:08)
>> On Thu, 15 Aug 2019, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote:
>> > @@ -1622,7 +1560,7 @@ struct drm_i915_private {
>> > u32 suspend_count;
>> > bool power_domains_suspended;
>> > struct i915_suspend_saved_registers regfile;
>> > - struct vlv_s0ix_state vlv_s0ix_state;
>> > + void *s0ix_state;
>>
>> I'd keep the vlv_ prefix in the member name.
>
> And forward decl to avoid a naked void *
Oh yes absolutely, I had that in my version of the patch, and didn't
even spot it here!
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h
2019-08-16 4:52 ` Lucas De Marchi
@ 2019-08-16 15:27 ` Daniele Ceraolo Spurio
2019-08-16 15:28 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 15:27 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Intel Graphics
On 8/15/19 9:52 PM, Lucas De Marchi wrote:
> On Thu, Aug 15, 2019 at 6:24 PM Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>>
>> It has nothing to do with registers, so move it to the more appropriate
>> intel_display_power.h
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>> ---
>> .../drm/i915/display/intel_display_power.c | 1 +
>> .../drm/i915/display/intel_display_power.h | 21 +++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
>> drivers/gpu/drm/i915/i915_reg.h | 21 -------------------
>> 4 files changed, 23 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 374b75602141..1caae2f61216 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -13,6 +13,7 @@
>> #include "intel_cdclk.h"
>> #include "intel_combo_phy.h"
>> #include "intel_csr.h"
>> +#include "intel_display_power.h"
>> #include "intel_display_types.h"
>> #include "intel_dpio_phy.h"
>> #include "intel_hotplug.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 97f2562fc5d3..a50605b8b1ad 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -92,6 +92,27 @@ enum intel_display_power_domain {
>> POWER_DOMAIN_NUM,
>> };
>>
>> +/*
>> + * i915_power_well_id:
>> + *
>> + * IDs used to look up power wells. Power wells accessed directly bypassing
>> + * the power domains framework must be assigned a unique ID. The rest of power
>> + * wells must be assigned DISP_PW_ID_NONE.
>> + */
>> +enum i915_power_well_id {
>> + DISP_PW_ID_NONE,
>> +
>> + VLV_DISP_PW_DISP2D,
>> + BXT_DISP_PW_DPIO_CMN_A,
>> + VLV_DISP_PW_DPIO_CMN_BC,
>> + GLK_DISP_PW_DPIO_CMN_C,
>> + CHV_DISP_PW_DPIO_CMN_D,
>> + HSW_DISP_PW_GLOBAL,
>> + SKL_DISP_PW_MISC_IO,
>> + SKL_DISP_PW_1,
>> + SKL_DISP_PW_2,
>> +};
>> +
>> #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
>> #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
>> ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
>> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> index dc4aaec2e04c..0beb954b5318 100644
>> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
>> @@ -14,6 +14,7 @@
>> #include <drm/i915_component.h>
>>
>> #include "i915_reg.h"
>> +#include "intel_display_power.h"
>> #include "intel_display_types.h"
>> #include "intel_hdcp.h"
>> #include "intel_sideband.h"
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 2b7ccebf6550..14165d619175 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1163,27 +1163,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>> #define PUNIT_REG_ISPSSPM0 0x39
>> #define PUNIT_REG_ISPSSPM1 0x3a
>>
>> -/*
>> - * i915_power_well_id:
>> - *
>> - * IDs used to look up power wells. Power wells accessed directly bypassing
>> - * the power domains framework must be assigned a unique ID. The rest of power
>> - * wells must be assigned DISP_PW_ID_NONE.
>> - */
>> -enum i915_power_well_id {
>> - DISP_PW_ID_NONE,
>> -
>> - VLV_DISP_PW_DISP2D,
>> - BXT_DISP_PW_DPIO_CMN_A,
>> - VLV_DISP_PW_DPIO_CMN_BC,
>> - GLK_DISP_PW_DPIO_CMN_C,
>> - CHV_DISP_PW_DPIO_CMN_D,
>> - HSW_DISP_PW_GLOBAL,
>> - SKL_DISP_PW_MISC_IO,
>> - SKL_DISP_PW_1,
>> - SKL_DISP_PW_2,
>> -};
>
> drivers/gpu/drm/i915/display/intel_hdcp.c also uses this enum, so it
> should also include the header
> in which it's defined.
>
That's already done in this patch. Were you thinking of another header?
Daniele
> other than that
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
> Lucas De Marchi
>
>> -
>> #define PUNIT_REG_PWRGT_CTRL 0x60
>> #define PUNIT_REG_PWRGT_STATUS 0x61
>> #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
>> --
>> 2.22.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h
2019-08-16 15:27 ` Daniele Ceraolo Spurio
@ 2019-08-16 15:28 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 15:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Intel Graphics
On 8/16/19 8:27 AM, Daniele Ceraolo Spurio wrote:
>
>
> On 8/15/19 9:52 PM, Lucas De Marchi wrote:
>> On Thu, Aug 15, 2019 at 6:24 PM Daniele Ceraolo Spurio
>> <daniele.ceraolospurio@intel.com> wrote:
>>>
>>> It has nothing to do with registers, so move it to the more appropriate
>>> intel_display_power.h
>>>
>>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>> Cc: Imre Deak <imre.deak@intel.com>
>>> ---
>>> .../drm/i915/display/intel_display_power.c | 1 +
>>> .../drm/i915/display/intel_display_power.h | 21 +++++++++++++++++++
>>> drivers/gpu/drm/i915/display/intel_hdcp.c | 1 +
>>> drivers/gpu/drm/i915/i915_reg.h | 21 -------------------
>>> 4 files changed, 23 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> index 374b75602141..1caae2f61216 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>>> @@ -13,6 +13,7 @@
>>> #include "intel_cdclk.h"
>>> #include "intel_combo_phy.h"
>>> #include "intel_csr.h"
>>> +#include "intel_display_power.h"
>>> #include "intel_display_types.h"
>>> #include "intel_dpio_phy.h"
>>> #include "intel_hotplug.h"
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
>>> b/drivers/gpu/drm/i915/display/intel_display_power.h
>>> index 97f2562fc5d3..a50605b8b1ad 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>>> @@ -92,6 +92,27 @@ enum intel_display_power_domain {
>>> POWER_DOMAIN_NUM,
>>> };
>>>
>>> +/*
>>> + * i915_power_well_id:
>>> + *
>>> + * IDs used to look up power wells. Power wells accessed directly
>>> bypassing
>>> + * the power domains framework must be assigned a unique ID. The
>>> rest of power
>>> + * wells must be assigned DISP_PW_ID_NONE.
>>> + */
>>> +enum i915_power_well_id {
>>> + DISP_PW_ID_NONE,
>>> +
>>> + VLV_DISP_PW_DISP2D,
>>> + BXT_DISP_PW_DPIO_CMN_A,
>>> + VLV_DISP_PW_DPIO_CMN_BC,
>>> + GLK_DISP_PW_DPIO_CMN_C,
>>> + CHV_DISP_PW_DPIO_CMN_D,
>>> + HSW_DISP_PW_GLOBAL,
>>> + SKL_DISP_PW_MISC_IO,
>>> + SKL_DISP_PW_1,
>>> + SKL_DISP_PW_2,
>>> +};
>>> +
>>> #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
>>> #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
>>> ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
>>> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
>>> b/drivers/gpu/drm/i915/display/intel_hdcp.c
>>> index dc4aaec2e04c..0beb954b5318 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
>>> @@ -14,6 +14,7 @@
>>> #include <drm/i915_component.h>
>>>
>>> #include "i915_reg.h"
>>> +#include "intel_display_power.h"
>>> #include "intel_display_types.h"
>>> #include "intel_hdcp.h"
>>> #include "intel_sideband.h"
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>>> b/drivers/gpu/drm/i915/i915_reg.h
>>> index 2b7ccebf6550..14165d619175 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -1163,27 +1163,6 @@ static inline bool
>>> i915_mmio_reg_valid(i915_reg_t reg)
>>> #define PUNIT_REG_ISPSSPM0 0x39
>>> #define PUNIT_REG_ISPSSPM1 0x3a
>>>
>>> -/*
>>> - * i915_power_well_id:
>>> - *
>>> - * IDs used to look up power wells. Power wells accessed directly
>>> bypassing
>>> - * the power domains framework must be assigned a unique ID. The
>>> rest of power
>>> - * wells must be assigned DISP_PW_ID_NONE.
>>> - */
>>> -enum i915_power_well_id {
>>> - DISP_PW_ID_NONE,
>>> -
>>> - VLV_DISP_PW_DISP2D,
>>> - BXT_DISP_PW_DPIO_CMN_A,
>>> - VLV_DISP_PW_DPIO_CMN_BC,
>>> - GLK_DISP_PW_DPIO_CMN_C,
>>> - CHV_DISP_PW_DPIO_CMN_D,
>>> - HSW_DISP_PW_GLOBAL,
>>> - SKL_DISP_PW_MISC_IO,
>>> - SKL_DISP_PW_1,
>>> - SKL_DISP_PW_2,
>>> -};
>>
>> drivers/gpu/drm/i915/display/intel_hdcp.c also uses this enum, so it
>> should also include the header
>> in which it's defined.
>>
>
> That's already done in this patch. Were you thinking of another header?
Sorry, I meant another .c file (I haven't had my coffee yet...)
Daniele
> > Daniele
>
>> other than that
>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>> Lucas De Marchi
>>
>>> -
>>> #define PUNIT_REG_PWRGT_CTRL 0x60
>>> #define PUNIT_REG_PWRGT_STATUS 0x61
>>> #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2))
>>> --
>>> 2.22.0
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
2019-08-16 5:09 ` Lucas De Marchi
@ 2019-08-16 15:30 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 15:30 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: Intel Graphics
<snip>
>>
>> @@ -2229,7 +2320,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
>> I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
>>
>> - for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
>> + for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
>
> why?
Leftover from the first version I had locally where I was trying to
dynamically allocate just the arrays instead of the whole thing. Will
get rid of it.
Daniele
>
> Lucas De Marchi
>
>> I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
>>
>> I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
>> @@ -2273,7 +2364,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN6_PMIMR, s->pm_imr);
>> I915_WRITE(GEN6_PMIER, s->pm_ier);
>>
>> - for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
>> + for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
>> I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
>>
>> /* GT SA CZ domain, 0x100000-0x138124 */
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index c6722d54ccd5..9b41f2209b69 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -527,68 +527,6 @@ struct i915_suspend_saved_registers {
>> u16 saveGCDGMBUS;
>> };
>>
>> -struct vlv_s0ix_state {
>> - /* GAM */
>> - u32 wr_watermark;
>> - u32 gfx_prio_ctrl;
>> - u32 arb_mode;
>> - u32 gfx_pend_tlb0;
>> - u32 gfx_pend_tlb1;
>> - u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
>> - u32 media_max_req_count;
>> - u32 gfx_max_req_count;
>> - u32 render_hwsp;
>> - u32 ecochk;
>> - u32 bsd_hwsp;
>> - u32 blt_hwsp;
>> - u32 tlb_rd_addr;
>> -
>> - /* MBC */
>> - u32 g3dctl;
>> - u32 gsckgctl;
>> - u32 mbctl;
>> -
>> - /* GCP */
>> - u32 ucgctl1;
>> - u32 ucgctl3;
>> - u32 rcgctl1;
>> - u32 rcgctl2;
>> - u32 rstctl;
>> - u32 misccpctl;
>> -
>> - /* GPM */
>> - u32 gfxpause;
>> - u32 rpdeuhwtc;
>> - u32 rpdeuc;
>> - u32 ecobus;
>> - u32 pwrdwnupctl;
>> - u32 rp_down_timeout;
>> - u32 rp_deucsw;
>> - u32 rcubmabdtmr;
>> - u32 rcedata;
>> - u32 spare2gh;
>> -
>> - /* Display 1 CZ domain */
>> - u32 gt_imr;
>> - u32 gt_ier;
>> - u32 pm_imr;
>> - u32 pm_ier;
>> - u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
>> -
>> - /* GT SA CZ domain */
>> - u32 tilectl;
>> - u32 gt_fifoctl;
>> - u32 gtlc_wake_ctrl;
>> - u32 gtlc_survive;
>> - u32 pmwgicz;
>> -
>> - /* Display 2 CZ domain */
>> - u32 gu_ctl0;
>> - u32 gu_ctl1;
>> - u32 pcbr;
>> - u32 clock_gate_dis2;
>> -};
>> -
>> struct intel_rps_ei {
>> ktime_t ktime;
>> u32 render_c0;
>> @@ -1622,7 +1560,7 @@ struct drm_i915_private {
>> u32 suspend_count;
>> bool power_domains_suspended;
>> struct i915_suspend_saved_registers regfile;
>> - struct vlv_s0ix_state vlv_s0ix_state;
>> + void *s0ix_state;
>>
>> enum {
>> I915_SAGV_UNKNOWN = 0,
>> --
>> 2.22.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV
2019-08-16 9:35 ` Jani Nikula
2019-08-16 9:40 ` Chris Wilson
@ 2019-08-16 15:33 ` Daniele Ceraolo Spurio
1 sibling, 0 replies; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 15:33 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 8/16/19 2:35 AM, Jani Nikula wrote:
> On Thu, 15 Aug 2019, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote:
>> This is only required for a single platform so no need to reserve the
>> memory on all of them.
>>
>> This removes the last direct dependency of i915_drv.h on i915_reg.h
>> (apart from the i915_reg_t definition).
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Imre Deak <imre.deak@intel.com>
>
> Heh, I've already sent a version of this [1], but I don't mind you
> finishing the job. Especially because I think it's better to handle the
> alloc/free explicitly instead of the way I do it.
D'oh! I completely missed that
>
> I do have some nitpicks on this one though, inline.
>
>
> [1] http://patchwork.freedesktop.org/patch/msgid/20190807144939.32123-1-jani.nikula@intel.com
>
>
<snip>
>> @@ -2137,7 +2228,7 @@ static int i915_pm_restore(struct device *kdev)
>> */
>> static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> {
>> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
>> + struct vlv_s0ix_state *s = dev_priv->s0ix_state;
>
> I think I'd now call this function unconditionally, and return early if
> (!s). This puts the decision to do this or not in one place only, in
> vlv_alloc_s0ix_state(), instead of duplicating the conditions.
ack
>
>
>> int i;
>>
>> /* GAM 0x4000-0x4770 */
>> @@ -2147,7 +2238,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
>> s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
>>
>> - for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
>> + for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
>> s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
>>
>> s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
>> @@ -2191,7 +2282,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> s->pm_imr = I915_READ(GEN6_PMIMR);
>> s->pm_ier = I915_READ(GEN6_PMIER);
>>
>> - for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
>> + for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
>> s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
>
> The above two hunks are in the wrong patch.
>
Yup, leftovers from a previous version.
>>
>> /* GT SA CZ domain, 0x100000-0x138124 */
>> @@ -2218,7 +2309,7 @@ static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>>
>> static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> {
>> - struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
>> + struct vlv_s0ix_state *s = dev_priv->s0ix_state;
>
> Early return on !s here as well, and call the function unconditionally.
>
ok
>> u32 val;
>> int i;
>>
>> @@ -2229,7 +2320,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
>> I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
>>
>> - for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
>> + for (i = 0; i < GEN7_LRA_LIMITS_REG_NUM; i++)
>> I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
>>
>> I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
>> @@ -2273,7 +2364,7 @@ static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
>> I915_WRITE(GEN6_PMIMR, s->pm_imr);
>> I915_WRITE(GEN6_PMIER, s->pm_ier);
>>
>> - for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
>> + for (i = 0; i < GEN7_GT_SCRATCH_REG_NUM; i++)
>> I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
>
> The above two hunks are in the wrong patch.
>
>>
>> /* GT SA CZ domain, 0x100000-0x138124 */
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index c6722d54ccd5..9b41f2209b69 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -527,68 +527,6 @@ struct i915_suspend_saved_registers {
>> u16 saveGCDGMBUS;
>> };
>>
>> -struct vlv_s0ix_state {
>> - /* GAM */
>> - u32 wr_watermark;
>> - u32 gfx_prio_ctrl;
>> - u32 arb_mode;
>> - u32 gfx_pend_tlb0;
>> - u32 gfx_pend_tlb1;
>> - u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
>> - u32 media_max_req_count;
>> - u32 gfx_max_req_count;
>> - u32 render_hwsp;
>> - u32 ecochk;
>> - u32 bsd_hwsp;
>> - u32 blt_hwsp;
>> - u32 tlb_rd_addr;
>> -
>> - /* MBC */
>> - u32 g3dctl;
>> - u32 gsckgctl;
>> - u32 mbctl;
>> -
>> - /* GCP */
>> - u32 ucgctl1;
>> - u32 ucgctl3;
>> - u32 rcgctl1;
>> - u32 rcgctl2;
>> - u32 rstctl;
>> - u32 misccpctl;
>> -
>> - /* GPM */
>> - u32 gfxpause;
>> - u32 rpdeuhwtc;
>> - u32 rpdeuc;
>> - u32 ecobus;
>> - u32 pwrdwnupctl;
>> - u32 rp_down_timeout;
>> - u32 rp_deucsw;
>> - u32 rcubmabdtmr;
>> - u32 rcedata;
>> - u32 spare2gh;
>> -
>> - /* Display 1 CZ domain */
>> - u32 gt_imr;
>> - u32 gt_ier;
>> - u32 pm_imr;
>> - u32 pm_ier;
>> - u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
>> -
>> - /* GT SA CZ domain */
>> - u32 tilectl;
>> - u32 gt_fifoctl;
>> - u32 gtlc_wake_ctrl;
>> - u32 gtlc_survive;
>> - u32 pmwgicz;
>> -
>> - /* Display 2 CZ domain */
>> - u32 gu_ctl0;
>> - u32 gu_ctl1;
>> - u32 pcbr;
>> - u32 clock_gate_dis2;
>> -};
>> -
>> struct intel_rps_ei {
>> ktime_t ktime;
>> u32 render_c0;
>> @@ -1622,7 +1560,7 @@ struct drm_i915_private {
>> u32 suspend_count;
>> bool power_domains_suspended;
>> struct i915_suspend_saved_registers regfile;
>> - struct vlv_s0ix_state vlv_s0ix_state;
>> + void *s0ix_state;
>
> I'd keep the vlv_ prefix in the member name.
ok (including the fwd decl mentioned in the other reply)
Daniele
>
> BR,
> Jani.
>
>
>>
>> enum {
>> I915_SAGV_UNKNOWN = 0,
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/6] drm/i915: Introduce i915_reg_types.h
2019-08-16 9:40 ` Michal Wajdeczko
@ 2019-08-16 15:35 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 25+ messages in thread
From: Daniele Ceraolo Spurio @ 2019-08-16 15:35 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx; +Cc: Jani Nikula
On 8/16/19 2:40 AM, Michal Wajdeczko wrote:
> On Fri, 16 Aug 2019 03:23:42 +0200, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>
>> With the introduction of display uncore, we want to categorize registers
>> between display and non-display. To help us getting it right, it will
>> be useful to move the display registers to a new file that can be used
>> without including i915_reg.h. To allow that, move all the basic register
>> type definitions and helpers to i915_reg_types.h and include that
>> instead of i915_reg.h from header files in the driver. We'll then
>> be able to replace i915_reg.h with the new display-only header in
>> display files and make sure the registers are correctly
>> compartmentalized.
>>
>
> maybe this split should another way:
>
> i915_reg.h = basic typedefs and macros
> intel_reg.h = register definitions
> and
> intel_display_reg.h = display related regs (your goal)
> intel_guc_reg.h = GuC related regs (we already have that!)
>
> then we follow the rule to use i915_ prefix for driver specific
> code and intel_ prefix for hardware originated definitions
>
Around the code we're using the *_types.h format for the headers with
the basic defs, so I'd prefer to stick with that. But I can go with
intel_* prefix and rename i915_reg.h to intel_reg.h.
Daniele
> Michal
_______________________________________________
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^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Fi.CI.IGT: success for Some more display uncore prep work
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2019-08-16 2:19 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-08-16 17:30 ` Patchwork
2019-08-16 21:22 ` [PATCH 0/6] " Chris Wilson
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-08-16 17:30 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Some more display uncore prep work
URL : https://patchwork.freedesktop.org/series/65281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6714_full -> Patchwork_14043_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14043_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +5 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110841])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd2:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276]) +10 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb2/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb6/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
* igt@i915_pm_rc6_residency@rc6-accuracy:
- shard-snb: [PASS][9] -> [SKIP][10] ([fdo#109271])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-snb5/igt@i915_pm_rc6_residency@rc6-accuracy.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-snb1/igt@i915_pm_rc6_residency@rc6-accuracy.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#103232]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-skl7/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-iclb: [PASS][13] -> [INCOMPLETE][14] ([fdo#107713])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][15] -> [FAIL][16] ([fdo#103167]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-glk: [PASS][17] -> [INCOMPLETE][18] ([fdo#103359] / [k.org#198133])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-glk5/igt@kms_plane@pixel-format-pipe-b-planes.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-glk2/igt@kms_plane@pixel-format-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109642] / [fdo#111068]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][23] -> [FAIL][24] ([fdo#108341])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb6/igt@kms_psr@no_drrs.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb4/igt@kms_psr@psr2_sprite_plane_move.html
#### Possible fixes ####
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][27] ([fdo#111325]) -> [PASS][28] +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb4/igt@gem_exec_schedule@in-order-bsd.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb7/igt@gem_exec_schedule@in-order-bsd.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-kbl: [DMESG-WARN][29] ([fdo#103313] / [fdo#103558] / [fdo#105079] / [fdo#105602]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-kbl1/igt@i915_pm_rpm@system-suspend-execbuf.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-kbl1/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [FAIL][33] ([fdo#102670]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@bo-too-big:
- shard-kbl: [DMESG-WARN][35] ([fdo#103313] / [fdo#103558] / [fdo#105602]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-kbl1/igt@kms_flip@bo-too-big.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-kbl1/igt@kms_flip@bo-too-big.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][37] ([fdo#103167]) -> [PASS][38] +6 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [INCOMPLETE][39] ([fdo#104108] / [fdo#106978]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-skl1/igt@kms_frontbuffer_tracking@psr-suspend.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-skl3/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_lease@master-vs-lease:
- shard-kbl: [DMESG-WARN][41] ([fdo#103558] / [fdo#105602]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-kbl1/igt@kms_lease@master-vs-lease.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-kbl1/igt@kms_lease@master-vs-lease.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [FAIL][43] ([fdo#103166]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][45] ([fdo#109441]) -> [PASS][46] +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-skl: [FAIL][47] ([fdo#99912]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-skl1/igt@kms_setmode@basic.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-skl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-wait-forked-busy-hang:
- shard-skl: [INCOMPLETE][49] -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-skl3/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-skl8/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][51] ([fdo#109276]) -> [PASS][52] +15 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb8/igt@prime_vgem@fence-wait-bsd2.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_mocs_settings@mocs-settings-bsd2:
- shard-iclb: [FAIL][53] ([fdo#111330]) -> [SKIP][54] ([fdo#109276]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-iclb1/igt@gem_mocs_settings@mocs-settings-bsd2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-iclb3/igt@gem_mocs_settings@mocs-settings-bsd2.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [INCOMPLETE][55] ([fdo#103927]) -> [DMESG-WARN][56] ([fdo#108566])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-kbl: [SKIP][57] ([fdo#105602] / [fdo#109271]) -> [SKIP][58] ([fdo#109271]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-kbl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-kbl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-kbl: [DMESG-FAIL][59] ([fdo#103313] / [fdo#103558] / [fdo#105602] / [fdo#108145]) -> [FAIL][60] ([fdo#108145])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb.html
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105079]: https://bugs.freedesktop.org/show_bug.cgi?id=105079
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
[fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6714 -> Patchwork_14043
CI-20190529: 20190529
CI_DRM_6714: 9198974f9fa309c4c74197365844971e0940b227 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14043: a2070d35d167f5323e8cdbdf74c569ddcdc5a112 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14043/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 0/6] Some more display uncore prep work
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
` (8 preceding siblings ...)
2019-08-16 17:30 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-08-16 21:22 ` Chris Wilson
9 siblings, 0 replies; 25+ messages in thread
From: Chris Wilson @ 2019-08-16 21:22 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Jani Nikula
Quoting Daniele Ceraolo Spurio (2019-08-16 02:23:37)
> drm/i915: Move i915_power_well_id out of i915_reg.h
> drm/i915: Move engine IDs out of i915_reg.h
> drm/i915: Move gmbus definitions out of i915_reg.h
> drm/i915: Wrappers for display register waits
I pushed the simple and uncontroversial ones. Thanks,
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2019-08-16 21:22 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-16 1:23 [PATCH 0/6] Some more display uncore prep work Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 1/6] drm/i915: Move i915_power_well_id out of i915_reg.h Daniele Ceraolo Spurio
2019-08-16 4:52 ` Lucas De Marchi
2019-08-16 15:27 ` Daniele Ceraolo Spurio
2019-08-16 15:28 ` Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 2/6] drm/i915: Move engine IDs " Daniele Ceraolo Spurio
2019-08-16 4:56 ` Lucas De Marchi
2019-08-16 1:23 ` [PATCH 3/6] drm/i915: Move gmbus definitions " Daniele Ceraolo Spurio
2019-08-16 5:03 ` Lucas De Marchi
2019-08-16 1:23 ` [PATCH 4/6] drm/i915: Dynamically allocate s0ix struct for VLV Daniele Ceraolo Spurio
2019-08-16 5:09 ` Lucas De Marchi
2019-08-16 15:30 ` Daniele Ceraolo Spurio
2019-08-16 9:35 ` Jani Nikula
2019-08-16 9:40 ` Chris Wilson
2019-08-16 10:32 ` Jani Nikula
2019-08-16 15:33 ` Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 5/6] drm/i915: Introduce i915_reg_types.h Daniele Ceraolo Spurio
2019-08-16 9:40 ` Michal Wajdeczko
2019-08-16 15:35 ` Daniele Ceraolo Spurio
2019-08-16 1:23 ` [PATCH 6/6] drm/i915: Wrappers for display register waits Daniele Ceraolo Spurio
2019-08-16 7:17 ` Chris Wilson
2019-08-16 1:46 ` ✗ Fi.CI.CHECKPATCH: warning for Some more display uncore prep work Patchwork
2019-08-16 2:19 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-16 17:30 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-16 21:22 ` [PATCH 0/6] " Chris Wilson
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