* [PATCH v2 0/4] riscv: Add enhanced PMP support
@ 2020-08-11 0:23 ` Hou Weiying
0 siblings, 0 replies; 4+ messages in thread
From: Hou Weiying @ 2020-08-11 0:23 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: Alistair.Francis, palmer, sagark, kbastian
v1 -> v2 :
* regenerate this patch based on the latest upstream
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2 0/4] riscv: Add enhanced PMP support
@ 2020-08-11 0:23 ` Hou Weiying
0 siblings, 0 replies; 4+ messages in thread
From: Hou Weiying @ 2020-08-11 0:23 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: palmer, Alistair.Francis, sagark, kbastian
v1 -> v2 :
* regenerate this patch based on the latest upstream
Hou Weiying (4):
Define ePMP mseccfg
Implementation of enhanced PMP(ePMP) support
Add ePMP CSR accesses
Add a config option for ePMP.
target/riscv/cpu.c | 9 ++
target/riscv/cpu.h | 3 +
target/riscv/cpu_bits.h | 3 +
target/riscv/csr.c | 18 ++++
target/riscv/gdbstub.c | 2 +
target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
target/riscv/pmp.h | 12 +++
target/riscv/trace-events | 4 +
8 files changed, 213 insertions(+), 12 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 0/4] riscv: Add enhanced PMP support
2020-08-11 0:23 ` Hou Weiying
@ 2021-02-10 20:13 ` Alistair Francis
-1 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2021-02-10 20:13 UTC (permalink / raw)
To: Hou Weiying
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Mon, Aug 10, 2020 at 5:23 PM Hou Weiying <weiying_hou@outlook.com> wrote:
>
> v1 -> v2 :
> * regenerate this patch based on the latest upstream
>
> Hou Weiying (4):
> Define ePMP mseccfg
> Implementation of enhanced PMP(ePMP) support
> Add ePMP CSR accesses
> Add a config option for ePMP.
Thanks for the patches.
Sorry again it has taken so long to get to. I kept hoping that next
week the CSRs would be reserved, but it still hasn't happened.
I have rebased all of the patches and fixed the compile issues. If you
want to pick these up feel free to, otherwise I'll send out the
rebased versions and work on getting them merged.
Alistair
>
> target/riscv/cpu.c | 9 ++
> target/riscv/cpu.h | 3 +
> target/riscv/cpu_bits.h | 3 +
> target/riscv/csr.c | 18 ++++
> target/riscv/gdbstub.c | 2 +
> target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
> target/riscv/pmp.h | 12 +++
> target/riscv/trace-events | 4 +
> 8 files changed, 213 insertions(+), 12 deletions(-)
>
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 0/4] riscv: Add enhanced PMP support
@ 2021-02-10 20:13 ` Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2021-02-10 20:13 UTC (permalink / raw)
To: Hou Weiying
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
On Mon, Aug 10, 2020 at 5:23 PM Hou Weiying <weiying_hou@outlook.com> wrote:
>
> v1 -> v2 :
> * regenerate this patch based on the latest upstream
>
> Hou Weiying (4):
> Define ePMP mseccfg
> Implementation of enhanced PMP(ePMP) support
> Add ePMP CSR accesses
> Add a config option for ePMP.
Thanks for the patches.
Sorry again it has taken so long to get to. I kept hoping that next
week the CSRs would be reserved, but it still hasn't happened.
I have rebased all of the patches and fixed the compile issues. If you
want to pick these up feel free to, otherwise I'll send out the
rebased versions and work on getting them merged.
Alistair
>
> target/riscv/cpu.c | 9 ++
> target/riscv/cpu.h | 3 +
> target/riscv/cpu_bits.h | 3 +
> target/riscv/csr.c | 18 ++++
> target/riscv/gdbstub.c | 2 +
> target/riscv/pmp.c | 174 +++++++++++++++++++++++++++++++++++---
> target/riscv/pmp.h | 12 +++
> target/riscv/trace-events | 4 +
> 8 files changed, 213 insertions(+), 12 deletions(-)
>
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-02-10 20:16 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-11 0:23 [PATCH v2 0/4] riscv: Add enhanced PMP support Hou Weiying
2020-08-11 0:23 ` Hou Weiying
2021-02-10 20:13 ` Alistair Francis
2021-02-10 20:13 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.