* [PATCH] RISC-V: Allow both Zmmul and M
@ 2022-07-14 18:00 Palmer Dabbelt
2022-07-18 0:44 ` Alistair Francis
2022-07-18 1:19 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2022-07-14 18:00 UTC (permalink / raw)
To: Alistair Francis, qemu-riscv, qemu-devel; +Cc: Palmer Dabbelt
We got to talking about how Zmmul and M interact with each other
https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
combination, it just means that the multiplication instructions are
supported even when M is disabled at runtime via misa.
This just stops overriding M from Zmmul, with that the other checks for
the multiplication instructions work as per the ISA.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/cpu.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index db2b8e4d30..cab74faaca 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -709,11 +709,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.ext_ifencei = true;
}
- if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
- warn_report("Zmmul will override M");
- cpu->cfg.ext_m = false;
- }
-
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
"I and E extensions are incompatible");
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Allow both Zmmul and M
2022-07-14 18:00 [PATCH] RISC-V: Allow both Zmmul and M Palmer Dabbelt
@ 2022-07-18 0:44 ` Alistair Francis
2022-07-18 1:19 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-07-18 0:44 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, open list:RISC-V, qemu-devel@nongnu.org Developers
On Fri, Jul 15, 2022 at 4:13 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> We got to talking about how Zmmul and M interact with each other
> https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
> that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
> combination, it just means that the multiplication instructions are
> supported even when M is disabled at runtime via misa.
>
> This just stops overriding M from Zmmul, with that the other checks for
> the multiplication instructions work as per the ISA.
>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db2b8e4d30..cab74faaca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -709,11 +709,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> cpu->cfg.ext_ifencei = true;
> }
>
> - if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
> - warn_report("Zmmul will override M");
> - cpu->cfg.ext_m = false;
> - }
> -
> if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> error_setg(errp,
> "I and E extensions are incompatible");
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] RISC-V: Allow both Zmmul and M
2022-07-14 18:00 [PATCH] RISC-V: Allow both Zmmul and M Palmer Dabbelt
2022-07-18 0:44 ` Alistair Francis
@ 2022-07-18 1:19 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-07-18 1:19 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Alistair Francis, open list:RISC-V, qemu-devel@nongnu.org Developers
On Fri, Jul 15, 2022 at 4:13 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> We got to talking about how Zmmul and M interact with each other
> https://github.com/riscv/riscv-isa-manual/issues/869 , and it turns out
> that QEMU's behavior is slightly wrong: having Zmmul and M is a legal
> combination, it just means that the multiplication instructions are
> supported even when M is disabled at runtime via misa.
>
> This just stops overriding M from Zmmul, with that the other checks for
> the multiplication instructions work as per the ISA.
>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index db2b8e4d30..cab74faaca 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -709,11 +709,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> cpu->cfg.ext_ifencei = true;
> }
>
> - if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) {
> - warn_report("Zmmul will override M");
> - cpu->cfg.ext_m = false;
> - }
> -
> if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> error_setg(errp,
> "I and E extensions are incompatible");
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-07-18 1:21 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-14 18:00 [PATCH] RISC-V: Allow both Zmmul and M Palmer Dabbelt
2022-07-18 0:44 ` Alistair Francis
2022-07-18 1:19 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.