From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: git@xen0n.name, "Alistair Francis" <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [PATCH 8/8] target/riscv: Support TCG_TARGET_SIGNED_ADDR32
Date: Wed, 13 Oct 2021 17:08:14 +1000 [thread overview]
Message-ID: <CAKmqyKM8pcgQUV-d2VMkCh0mSo8K9foUtVbN+t1LF7DpFUgiHw@mail.gmail.com> (raw)
In-Reply-To: <20211010174401.141339-9-richard.henderson@linaro.org>
On Mon, Oct 11, 2021 at 3:50 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> All RV64 32-bit operations sign-extend the output, so we are easily
> able to keep TCG_TYPE_I32 values sign-extended in host registers.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> tcg/riscv/tcg-target-sa32.h | 6 +++++-
> tcg/riscv/tcg-target.c.inc | 8 ++------
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
> index cb185b1526..703467b37a 100644
> --- a/tcg/riscv/tcg-target-sa32.h
> +++ b/tcg/riscv/tcg-target-sa32.h
> @@ -1 +1,5 @@
> -#define TCG_TARGET_SIGNED_ADDR32 0
> +/*
> + * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32;
> + * TCG expects this to only be set for 64-bit hosts.
> + */
> +#define TCG_TARGET_SIGNED_ADDR32 (__riscv_xlen == 64)
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 9b13a46fb4..9426ef8926 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -952,10 +952,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
> tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
>
> /* TLB Hit - translate address using addend. */
> - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
> - tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
> - addrl = TCG_REG_TMP0;
> - }
> tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
> }
>
> @@ -1126,7 +1122,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
> data_regl, data_regh, addr_regl, addr_regh,
> s->code_ptr, label_ptr);
> #else
> - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
> + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
> tcg_out_ext32u(s, base, addr_regl);
> addr_regl = base;
> }
> @@ -1192,7 +1188,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
> data_regl, data_regh, addr_regl, addr_regh,
> s->code_ptr, label_ptr);
> #else
> - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
> + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
> tcg_out_ext32u(s, base, addr_regl);
> addr_regl = base;
> }
> --
> 2.25.1
>
>
prev parent reply other threads:[~2021-10-13 7:10 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-10 17:43 [PATCH 0/8] tcg: support 32-bit guest addresses as signed Richard Henderson
2021-10-10 17:43 ` [PATCH 1/8] tcg: Add TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2021-10-11 4:21 ` WANG Xuerui
2021-10-11 9:55 ` Alex Bennée
2021-10-11 22:07 ` Philippe Mathieu-Daudé
2021-10-11 23:16 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 2/8] accel/tcg: Split out g2h_tlbe Richard Henderson
2021-10-11 4:22 ` WANG Xuerui
2021-10-11 9:55 ` Alex Bennée
2021-10-11 21:48 ` Philippe Mathieu-Daudé
2021-10-11 23:19 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 3/8] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Richard Henderson
2021-10-11 4:30 ` WANG Xuerui
2021-10-11 15:27 ` Richard Henderson
2021-10-10 17:43 ` [PATCH 4/8] accel/tcg: Add guest_base_signed_addr32 for user-only Richard Henderson
2021-10-11 22:06 ` Philippe Mathieu-Daudé
2021-10-13 7:07 ` Alistair Francis
2021-10-10 17:43 ` [PATCH 5/8] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2021-10-11 10:22 ` Alex Bennée
2021-10-11 15:32 ` Richard Henderson
2021-10-10 17:43 ` [PATCH 6/8] tcg/aarch64: " Richard Henderson
2021-10-11 10:28 ` Alex Bennée
2021-10-11 15:24 ` Richard Henderson
2021-10-13 21:05 ` Richard Henderson
2021-10-10 17:44 ` [PATCH 7/8] target/mips: " Richard Henderson
2021-10-11 4:20 ` WANG Xuerui
2021-10-13 22:24 ` Richard Henderson
2021-10-10 17:44 ` [PATCH 8/8] target/riscv: " Richard Henderson
2021-10-11 22:00 ` Philippe Mathieu-Daudé
2021-10-13 7:08 ` Alistair Francis [this message]
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