* [PATCH] target/riscv: make H-extension non-experimental
@ 2021-12-21 17:21 ` Vineet Gupta
0 siblings, 0 replies; 4+ messages in thread
From: Vineet Gupta @ 2021-12-21 17:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, Palmer Dabbelt, Vineet Gupta
H-ext v1.0 was ratified recently as part of Privileged Spec 1.12.
So move it out of experimental.
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6ef3314bced8..a582179b1773 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -640,12 +640,12 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
- /* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
- DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
+ /* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] target/riscv: make H-extension non-experimental
@ 2021-12-21 17:21 ` Vineet Gupta
0 siblings, 0 replies; 4+ messages in thread
From: Vineet Gupta @ 2021-12-21 17:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Palmer Dabbelt, Alistair Francis, Vineet Gupta
H-ext v1.0 was ratified recently as part of Privileged Spec 1.12.
So move it out of experimental.
[1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6ef3314bced8..a582179b1773 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -640,12 +640,12 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
- /* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
- DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
+ DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
+ /* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
--
2.30.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: make H-extension non-experimental
2021-12-21 17:21 ` Vineet Gupta
@ 2021-12-21 22:19 ` Alistair Francis
-1 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2021-12-21 22:19 UTC (permalink / raw)
To: Vineet Gupta
Cc: Alistair Francis, Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers
On Wed, Dec 22, 2021 at 3:22 AM Vineet Gupta <vineetg@rivosinc.com> wrote:
>
> H-ext v1.0 was ratified recently as part of Privileged Spec 1.12.
> So move it out of experimental.
>
> [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Thanks for the patch!
There is already a similar patch on the mailing list though.
Alistair
> ---
> target/riscv/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6ef3314bced8..a582179b1773 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -640,12 +640,12 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> - /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
> + /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: make H-extension non-experimental
@ 2021-12-21 22:19 ` Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2021-12-21 22:19 UTC (permalink / raw)
To: Vineet Gupta
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt
On Wed, Dec 22, 2021 at 3:22 AM Vineet Gupta <vineetg@rivosinc.com> wrote:
>
> H-ext v1.0 was ratified recently as part of Privileged Spec 1.12.
> So move it out of experimental.
>
> [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions
>
> Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Thanks for the patch!
There is already a similar patch on the mailing list though.
Alistair
> ---
> target/riscv/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6ef3314bced8..a582179b1773 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -640,12 +640,12 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> - /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
> + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
> + /* These are experimental so mark with 'x-' */
> DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
> /* ePMP 0.9.3 */
> DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
> --
> 2.30.2
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-12-21 22:22 UTC | newest]
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2021-12-21 17:21 [PATCH] target/riscv: make H-extension non-experimental Vineet Gupta
2021-12-21 17:21 ` Vineet Gupta
2021-12-21 22:19 ` Alistair Francis
2021-12-21 22:19 ` Alistair Francis
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