* [PATCH] riscv: Fix defination of csr operations
@ 2020-01-19 10:52 jiangzhiying
2020-01-20 23:08 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: jiangzhiying @ 2020-01-19 10:52 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair.Francis, palmer, Ian Jiang, sagark, kbastian
From: Ian Jiang <ianjiang.ict@gmail.com>
There is a mistake in defining CSR operations for pmpcfg registers.
This patch fixes the bug.
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..e07b5267be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -948,7 +948,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SATP] = { smode, read_satp, write_satp },
/* Physical Memory Protection */
- [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
+ [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
/* Performance Counters */
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] riscv: Fix defination of csr operations
2020-01-19 10:52 [PATCH] riscv: Fix defination of csr operations jiangzhiying
@ 2020-01-20 23:08 ` Alistair Francis
0 siblings, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2020-01-20 23:08 UTC (permalink / raw)
To: jiangzhiying
Cc: Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Ian Jiang
On Sun, Jan 19, 2020 at 11:55 PM <jiangzhiying@ict.ac.cn> wrote:
>
> From: Ian Jiang <ianjiang.ict@gmail.com>
>
> There is a mistake in defining CSR operations for pmpcfg registers.
> This patch fixes the bug.
>
> Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Looks good! Thanks for the patch.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index da02f9f0b1..e07b5267be 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -948,7 +948,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_SATP] = { smode, read_satp, write_satp },
>
> /* Physical Memory Protection */
> - [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
> + [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
> [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
>
> /* Performance Counters */
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] riscv: Fix defination of csr operations
@ 2020-01-19 1:43 Ian Jiang
0 siblings, 0 replies; 3+ messages in thread
From: Ian Jiang @ 2020-01-19 1:43 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair Francis, Palmer Dabbelt, Sagar Karandikar, Bastian Koppelmann
[-- Attachment #1: Type: text/plain, Size: 841 bytes --]
There is a mistake in defining CSR operations for pmpcfg registers.
This patch fixes the bug.
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f0b1..e07b5267be 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -948,7 +948,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SATP] = { smode, read_satp, write_satp
},
/* Physical Memory Protection */
- [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg
},
+ [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg
},
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr,
write_pmpaddr },
/* Performance Counters */
--
2.17.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
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2020-01-19 10:52 [PATCH] riscv: Fix defination of csr operations jiangzhiying
2020-01-20 23:08 ` Alistair Francis
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2020-01-19 1:43 Ian Jiang
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