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From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 3/3] hw/riscv: opentitan: Add the flash alias
Date: Mon, 12 Jul 2021 15:13:37 +1000	[thread overview]
Message-ID: <CAKmqyKMK5UkaGuH05vjUfAfuFhAebGWErmMc6MbboWR7jEMTtw@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmUP9fWzZHEc3hir2fJ15k07VmDcmrc=FzbRy_CZMC6_fg@mail.gmail.com>

On Fri, Jul 9, 2021 at 10:21 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Jul 9, 2021 at 11:38 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > OpenTitan has an alias of flash avaliable which is called virtual flash.
>
> typo: available
>
> > Add support for that in the QEMU model.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  include/hw/riscv/opentitan.h | 2 ++
> >  hw/riscv/opentitan.c         | 6 ++++++
> >  2 files changed, 8 insertions(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Thanks!

Applied to riscv-to-apply.next

Alistair


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2 3/3] hw/riscv: opentitan: Add the flash alias
Date: Mon, 12 Jul 2021 15:13:37 +1000	[thread overview]
Message-ID: <CAKmqyKMK5UkaGuH05vjUfAfuFhAebGWErmMc6MbboWR7jEMTtw@mail.gmail.com> (raw)
In-Reply-To: <CAEUhbmUP9fWzZHEc3hir2fJ15k07VmDcmrc=FzbRy_CZMC6_fg@mail.gmail.com>

On Fri, Jul 9, 2021 at 10:21 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, Jul 9, 2021 at 11:38 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > OpenTitan has an alias of flash avaliable which is called virtual flash.
>
> typo: available
>
> > Add support for that in the QEMU model.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  include/hw/riscv/opentitan.h | 2 ++
> >  hw/riscv/opentitan.c         | 6 ++++++
> >  2 files changed, 8 insertions(+)
> >
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Thanks!

Applied to riscv-to-apply.next

Alistair


  reply	other threads:[~2021-07-12  5:15 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-09  3:38 [PATCH v2 0/3] Updates to the OpenTitan machine Alistair Francis
2021-07-09  3:38 ` Alistair Francis
2021-07-09  3:38 ` [PATCH v2 1/3] char: ibex_uart: Update the register layout Alistair Francis
2021-07-09  3:38   ` Alistair Francis
2021-07-09  3:38 ` [PATCH v2 2/3] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri Alistair Francis
2021-07-09  3:38   ` Alistair Francis
2021-07-09  3:38 ` [PATCH v2 3/3] hw/riscv: opentitan: Add the flash alias Alistair Francis
2021-07-09  3:38   ` Alistair Francis
2021-07-09 12:21   ` Bin Meng
2021-07-09 12:21     ` Bin Meng
2021-07-12  5:13     ` Alistair Francis [this message]
2021-07-12  5:13       ` Alistair Francis

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