From: Alistair Francis <alistair23@gmail.com> To: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com>, Paul Walmsley <paul.walmsley@sifive.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Atish Patra <Atish.Patra@wdc.com> Subject: Re: [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings Date: Wed, 7 Aug 2019 10:54:52 -0700 [thread overview] Message-ID: <CAKmqyKMKBsHO2QCYC1qeGTQa0cUMEpke17dgkB=hgQC-Nd9upw@mail.gmail.com> (raw) In-Reply-To: <20190807145939.1281-1-palmer@sifive.com> On Wed, Aug 7, 2019 at 8:00 AM Palmer Dabbelt <palmer@sifive.com> wrote: > > The ISA strings we're providing from QEMU aren't actually legal RISC-V > ISA strings, as both the S and U extensions cannot exist as > single-letter extensions and must instead be multi-letter strings. > We're still using the ISA strings inside QEMU to track the availiable s/availiable/available/g > extensions, so this patch just strips out the S and U extensions when > formatting ISA strings. Atish and I were talking about this and we concluded that S and U aren't extensions, but should be reported in the misa CSR. > > This boots Linux on top of 4.1-rc3, which no longer has the U extension > in /proc/cpuinfo. > > Signed-off-by: Palmer Dabbelt <palmer@sifive.com> > --- > This is another late one, but I'd like to target it for 4.1 as we're > providing illegal ISA strings and I don't want to bake that into a bunch > of other code. > --- > target/riscv/cpu.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f8d07bd20ad7..4df14433d789 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -501,7 +501,22 @@ char *riscv_isa_string(RISCVCPU *cpu) > char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > for (i = 0; i < sizeof(riscv_exts); i++) { > if (cpu->env.misa & RV(riscv_exts[i])) { > - *p++ = qemu_tolower(riscv_exts[i]); > + char lower = qemu_tolower(riscv_exts[i]); > + switch (lower) { > + case 's': > + case 'u': > + /* > + * The 's' and 'u' extensions shouldn't be passed in the device > + * tree, but we still use them internally to track extension > + * sets. Here we just explicitly remove them when formatting > + * an ISA string. This should be updated to note mention 's' and 'u' as extensions, but clarify that they are correctly include in the misa CSR. Alistair > + */ > + break; > + > + default: > + *p++ = qemu_tolower(riscv_exts[i]); > + break; > + } > } > } > *p = '\0'; > -- > 2.21.0 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Palmer Dabbelt <palmer@sifive.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, Alistair Francis <Alistair.Francis@wdc.com>, Atish Patra <Atish.Patra@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Paul Walmsley <paul.walmsley@sifive.com> Subject: Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings Date: Wed, 7 Aug 2019 10:54:52 -0700 [thread overview] Message-ID: <CAKmqyKMKBsHO2QCYC1qeGTQa0cUMEpke17dgkB=hgQC-Nd9upw@mail.gmail.com> (raw) In-Reply-To: <20190807145939.1281-1-palmer@sifive.com> On Wed, Aug 7, 2019 at 8:00 AM Palmer Dabbelt <palmer@sifive.com> wrote: > > The ISA strings we're providing from QEMU aren't actually legal RISC-V > ISA strings, as both the S and U extensions cannot exist as > single-letter extensions and must instead be multi-letter strings. > We're still using the ISA strings inside QEMU to track the availiable s/availiable/available/g > extensions, so this patch just strips out the S and U extensions when > formatting ISA strings. Atish and I were talking about this and we concluded that S and U aren't extensions, but should be reported in the misa CSR. > > This boots Linux on top of 4.1-rc3, which no longer has the U extension > in /proc/cpuinfo. > > Signed-off-by: Palmer Dabbelt <palmer@sifive.com> > --- > This is another late one, but I'd like to target it for 4.1 as we're > providing illegal ISA strings and I don't want to bake that into a bunch > of other code. > --- > target/riscv/cpu.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f8d07bd20ad7..4df14433d789 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -501,7 +501,22 @@ char *riscv_isa_string(RISCVCPU *cpu) > char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > for (i = 0; i < sizeof(riscv_exts); i++) { > if (cpu->env.misa & RV(riscv_exts[i])) { > - *p++ = qemu_tolower(riscv_exts[i]); > + char lower = qemu_tolower(riscv_exts[i]); > + switch (lower) { > + case 's': > + case 'u': > + /* > + * The 's' and 'u' extensions shouldn't be passed in the device > + * tree, but we still use them internally to track extension > + * sets. Here we just explicitly remove them when formatting > + * an ISA string. This should be updated to note mention 's' and 'u' as extensions, but clarify that they are correctly include in the misa CSR. Alistair > + */ > + break; > + > + default: > + *p++ = qemu_tolower(riscv_exts[i]); > + break; > + } > } > } > *p = '\0'; > -- > 2.21.0 > >
next prev parent reply other threads:[~2019-08-07 17:59 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-07 14:59 [Qemu-devel] [PATCH for 4.1] RISC-V: Ignore the S and U extensions when formatting ISA strings Palmer Dabbelt 2019-08-07 14:59 ` [Qemu-riscv] " Palmer Dabbelt 2019-08-07 15:27 ` [Qemu-devel] " Paul Walmsley 2019-08-07 15:27 ` [Qemu-riscv] " Paul Walmsley 2019-08-07 16:08 ` [Qemu-devel] " Peter Maydell 2019-08-07 16:08 ` [Qemu-riscv] " Peter Maydell 2019-08-07 16:20 ` Palmer Dabbelt 2019-08-07 16:20 ` [Qemu-riscv] " Palmer Dabbelt 2019-08-07 16:41 ` Peter Maydell 2019-08-07 16:41 ` [Qemu-riscv] " Peter Maydell 2019-08-07 17:25 ` Palmer Dabbelt 2019-08-07 17:25 ` [Qemu-riscv] " Palmer Dabbelt 2019-08-07 17:54 ` Alistair Francis [this message] 2019-08-07 17:54 ` Alistair Francis 2019-08-13 22:54 ` Palmer Dabbelt 2019-08-13 22:54 ` [Qemu-riscv] " Palmer Dabbelt
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