* [PATCH v3 0/3] RISC-V Spike machine improvements
@ 2020-04-27 8:06 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs
Changes since v2:
- Rebased on QEMU v5.0-rc4
Changes since v1:
- Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)
Anup Patel (3):
hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
hw/riscv/spike: Allow loading firmware separately using -bios option
hw/riscv/spike: Allow more than one CPUs
hw/riscv/boot.c | 13 ++++++++-----
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 26 ++++++++++++++++++++++++--
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 6 ++++--
5 files changed, 38 insertions(+), 11 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 0/3] RISC-V Spike machine improvements
@ 2020-04-27 8:06 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs
Changes since v2:
- Rebased on QEMU v5.0-rc4
Changes since v1:
- Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)
Anup Patel (3):
hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
hw/riscv/spike: Allow loading firmware separately using -bios option
hw/riscv/spike: Allow more than one CPUs
hw/riscv/boot.c | 13 ++++++++-----
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 26 ++++++++++++++++++++++++--
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 6 ++++--
5 files changed, 38 insertions(+), 11 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
2020-04-27 8:06 ` Anup Patel
@ 2020-04-27 8:06 ` Anup Patel
-1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
This patch adds an optional function pointer, "sym_cb", to
riscv_load_firmware() which provides the possibility to access
the symbol table during kernel loading.
The pointer is ignored, if supplied with flat (non-elf) firmware image.
The Spike board requires it locate the HTIF symbols from firmware ELF
passed via "-bios" option.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/boot.c | 13 ++++++++-----
hw/riscv/sifive_u.c | 2 +-
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 6 ++++--
4 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index b8e765277d..726300a171 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -36,7 +36,8 @@
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
- hwaddr firmware_load_addr)
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb)
{
char *firmware_filename = NULL;
@@ -76,7 +77,7 @@ void riscv_find_and_load_firmware(MachineState *machine,
if (firmware_filename) {
/* If not "none" load the firmware */
- riscv_load_firmware(firmware_filename, firmware_load_addr);
+ riscv_load_firmware(firmware_filename, firmware_load_addr, sym_cb);
g_free(firmware_filename);
}
}
@@ -96,12 +97,14 @@ char *riscv_find_firmware(const char *firmware_filename)
}
target_ulong riscv_load_firmware(const char *firmware_filename,
- hwaddr firmware_load_addr)
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb)
{
uint64_t firmware_entry, firmware_start, firmware_end;
- if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry,
- &firmware_start, &firmware_end, NULL, 0, EM_RISCV, 1, 0) > 0) {
+ if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
+ &firmware_entry, &firmware_start, &firmware_end, NULL,
+ 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
return firmware_entry;
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 56351c4faa..54bb9eb1bf 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -345,7 +345,7 @@ static void riscv_sifive_u_init(MachineState *machine)
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
riscv_find_and_load_firmware(machine, BIOS_FILENAME,
- memmap[SIFIVE_U_DRAM].base);
+ memmap[SIFIVE_U_DRAM].base, NULL);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 85ec9e22aa..24f851e895 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -507,7 +507,7 @@ static void riscv_virt_board_init(MachineState *machine)
mask_rom);
riscv_find_and_load_firmware(machine, BIOS_FILENAME,
- memmap[VIRT_DRAM].base);
+ memmap[VIRT_DRAM].base, NULL);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index df80051fbc..474a940ad5 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -24,10 +24,12 @@
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
- hwaddr firmware_load_addr);
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb);
char *riscv_find_firmware(const char *firmware_filename);
target_ulong riscv_load_firmware(const char *firmware_filename,
- hwaddr firmware_load_addr);
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb);
target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
@ 2020-04-27 8:06 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
This patch adds an optional function pointer, "sym_cb", to
riscv_load_firmware() which provides the possibility to access
the symbol table during kernel loading.
The pointer is ignored, if supplied with flat (non-elf) firmware image.
The Spike board requires it locate the HTIF symbols from firmware ELF
passed via "-bios" option.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/boot.c | 13 ++++++++-----
hw/riscv/sifive_u.c | 2 +-
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 6 ++++--
4 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index b8e765277d..726300a171 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -36,7 +36,8 @@
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
- hwaddr firmware_load_addr)
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb)
{
char *firmware_filename = NULL;
@@ -76,7 +77,7 @@ void riscv_find_and_load_firmware(MachineState *machine,
if (firmware_filename) {
/* If not "none" load the firmware */
- riscv_load_firmware(firmware_filename, firmware_load_addr);
+ riscv_load_firmware(firmware_filename, firmware_load_addr, sym_cb);
g_free(firmware_filename);
}
}
@@ -96,12 +97,14 @@ char *riscv_find_firmware(const char *firmware_filename)
}
target_ulong riscv_load_firmware(const char *firmware_filename,
- hwaddr firmware_load_addr)
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb)
{
uint64_t firmware_entry, firmware_start, firmware_end;
- if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry,
- &firmware_start, &firmware_end, NULL, 0, EM_RISCV, 1, 0) > 0) {
+ if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
+ &firmware_entry, &firmware_start, &firmware_end, NULL,
+ 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
return firmware_entry;
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 56351c4faa..54bb9eb1bf 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -345,7 +345,7 @@ static void riscv_sifive_u_init(MachineState *machine)
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
riscv_find_and_load_firmware(machine, BIOS_FILENAME,
- memmap[SIFIVE_U_DRAM].base);
+ memmap[SIFIVE_U_DRAM].base, NULL);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 85ec9e22aa..24f851e895 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -507,7 +507,7 @@ static void riscv_virt_board_init(MachineState *machine)
mask_rom);
riscv_find_and_load_firmware(machine, BIOS_FILENAME,
- memmap[VIRT_DRAM].base);
+ memmap[VIRT_DRAM].base, NULL);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index df80051fbc..474a940ad5 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -24,10 +24,12 @@
void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
- hwaddr firmware_load_addr);
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb);
char *riscv_find_firmware(const char *firmware_filename);
target_ulong riscv_load_firmware(const char *firmware_filename,
- hwaddr firmware_load_addr);
+ hwaddr firmware_load_addr,
+ symbol_fn_t sym_cb);
target_ulong riscv_load_kernel(const char *kernel_filename,
symbol_fn_t sym_cb);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
2020-04-27 8:06 ` Anup Patel
@ 2020-04-27 8:06 ` Anup Patel
-1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
This patch extends Spike machine support to allow loading OpenSBI
firmware (fw_jump.elf) separately using -bios option.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/spike.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 5053fe4590..b0395e227c 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -45,6 +45,12 @@
#include <libfdt.h>
+#if defined(TARGET_RISCV32)
+# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
+#else
+# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
+#endif
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@@ -183,8 +189,24 @@ static void spike_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
mask_rom);
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME,
+ memmap[SPIKE_DRAM].base,
+ htif_symbol_callback);
+
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
+ uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
+ htif_symbol_callback);
+
+ if (machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
}
/* reset vector */
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
@ 2020-04-27 8:06 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
This patch extends Spike machine support to allow loading OpenSBI
firmware (fw_jump.elf) separately using -bios option.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/spike.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 5053fe4590..b0395e227c 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -45,6 +45,12 @@
#include <libfdt.h>
+#if defined(TARGET_RISCV32)
+# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
+#else
+# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
+#endif
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@@ -183,8 +189,24 @@ static void spike_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
mask_rom);
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME,
+ memmap[SPIKE_DRAM].base,
+ htif_symbol_callback);
+
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
+ uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
+ htif_symbol_callback);
+
+ if (machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
}
/* reset vector */
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs
2020-04-27 8:06 ` Anup Patel
@ 2020-04-27 8:06 ` Anup Patel
-1 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.
The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/spike.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index b0395e227c..1799b9291c 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -472,7 +472,7 @@ static void spike_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Spike Board";
mc->init = spike_board_init;
- mc->max_cpus = 1;
+ mc->max_cpus = 8;
mc->is_default = true;
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs
@ 2020-04-27 8:06 ` Anup Patel
0 siblings, 0 replies; 16+ messages in thread
From: Anup Patel @ 2020-04-27 8:06 UTC (permalink / raw)
To: Peter Maydell, Palmer Dabbelt, Alistair Francis, Sagar Karandikar
Cc: Atish Patra, Anup Patel, qemu-riscv, qemu-devel, Anup Patel
Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.
The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
hw/riscv/spike.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index b0395e227c..1799b9291c 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -472,7 +472,7 @@ static void spike_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Spike Board";
mc->init = spike_board_init;
- mc->max_cpus = 1;
+ mc->max_cpus = 8;
mc->is_default = true;
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs
2020-04-27 8:06 ` Anup Patel
@ 2020-04-27 15:00 ` Alistair Francis
-1 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:00 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Mon, Apr 27, 2020 at 1:09 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> Currently, the upstream Spike ISA simulator allows more than
> one CPUs so we update QEMU Spike machine on similar lines to
> allow more than one CPUs.
>
> The maximum number of CPUs for QEMU Spike machine is kept
> same as QEMU Virt machine.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/spike.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index b0395e227c..1799b9291c 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -472,7 +472,7 @@ static void spike_machine_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Spike Board";
> mc->init = spike_board_init;
> - mc->max_cpus = 1;
> + mc->max_cpus = 8;
> mc->is_default = true;
> mc->default_cpu_type = SPIKE_V1_10_0_CPU;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs
@ 2020-04-27 15:00 ` Alistair Francis
0 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:00 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Atish Patra, open list:RISC-V,
qemu-devel@nongnu.org Developers, Anup Patel
On Mon, Apr 27, 2020 at 1:09 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> Currently, the upstream Spike ISA simulator allows more than
> one CPUs so we update QEMU Spike machine on similar lines to
> allow more than one CPUs.
>
> The maximum number of CPUs for QEMU Spike machine is kept
> same as QEMU Virt machine.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/spike.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index b0395e227c..1799b9291c 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -472,7 +472,7 @@ static void spike_machine_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Spike Board";
> mc->init = spike_board_init;
> - mc->max_cpus = 1;
> + mc->max_cpus = 8;
> mc->is_default = true;
> mc->default_cpu_type = SPIKE_V1_10_0_CPU;
> }
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
2020-04-27 8:06 ` Anup Patel
@ 2020-04-27 15:03 ` Alistair Francis
-1 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:03 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Mon, Apr 27, 2020 at 1:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This patch extends Spike machine support to allow loading OpenSBI
> firmware (fw_jump.elf) separately using -bios option.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/spike.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 5053fe4590..b0395e227c 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -45,6 +45,12 @@
>
> #include <libfdt.h>
>
> +#if defined(TARGET_RISCV32)
> +# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
> +#else
> +# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
> +#endif
> +
> static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> @@ -183,8 +189,24 @@ static void spike_board_init(MachineState *machine)
> memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
> mask_rom);
>
> + riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> + memmap[SPIKE_DRAM].base,
> + htif_symbol_callback);
> +
> if (machine->kernel_filename) {
> - riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
> + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> + htif_symbol_callback);
> +
> + if (machine->initrd_filename) {
> + hwaddr start;
> + hwaddr end = riscv_load_initrd(machine->initrd_filename,
> + machine->ram_size, kernel_entry,
> + &start);
> + qemu_fdt_setprop_cell(s->fdt, "/chosen",
> + "linux,initrd-start", start);
> + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
> + end);
> + }
> }
>
> /* reset vector */
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option
@ 2020-04-27 15:03 ` Alistair Francis
0 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:03 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Atish Patra, open list:RISC-V,
qemu-devel@nongnu.org Developers, Anup Patel
On Mon, Apr 27, 2020 at 1:08 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This patch extends Spike machine support to allow loading OpenSBI
> firmware (fw_jump.elf) separately using -bios option.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/spike.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 5053fe4590..b0395e227c 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -45,6 +45,12 @@
>
> #include <libfdt.h>
>
> +#if defined(TARGET_RISCV32)
> +# define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf"
> +#else
> +# define BIOS_FILENAME "opensbi-riscv64-spike-fw_jump.elf"
> +#endif
> +
> static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> @@ -183,8 +189,24 @@ static void spike_board_init(MachineState *machine)
> memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
> mask_rom);
>
> + riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> + memmap[SPIKE_DRAM].base,
> + htif_symbol_callback);
> +
> if (machine->kernel_filename) {
> - riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
> + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> + htif_symbol_callback);
> +
> + if (machine->initrd_filename) {
> + hwaddr start;
> + hwaddr end = riscv_load_initrd(machine->initrd_filename,
> + machine->ram_size, kernel_entry,
> + &start);
> + qemu_fdt_setprop_cell(s->fdt, "/chosen",
> + "linux,initrd-start", start);
> + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
> + end);
> + }
> }
>
> /* reset vector */
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
2020-04-27 8:06 ` Anup Patel
@ 2020-04-27 15:05 ` Alistair Francis
-1 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:05 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Mon, Apr 27, 2020 at 1:09 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This patch adds an optional function pointer, "sym_cb", to
> riscv_load_firmware() which provides the possibility to access
> the symbol table during kernel loading.
>
> The pointer is ignored, if supplied with flat (non-elf) firmware image.
>
> The Spike board requires it locate the HTIF symbols from firmware ELF
> passed via "-bios" option.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/boot.c | 13 ++++++++-----
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/virt.c | 2 +-
> include/hw/riscv/boot.h | 6 ++++--
> 4 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index b8e765277d..726300a171 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -36,7 +36,8 @@
>
> void riscv_find_and_load_firmware(MachineState *machine,
> const char *default_machine_firmware,
> - hwaddr firmware_load_addr)
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb)
> {
> char *firmware_filename = NULL;
>
> @@ -76,7 +77,7 @@ void riscv_find_and_load_firmware(MachineState *machine,
>
> if (firmware_filename) {
> /* If not "none" load the firmware */
> - riscv_load_firmware(firmware_filename, firmware_load_addr);
> + riscv_load_firmware(firmware_filename, firmware_load_addr, sym_cb);
> g_free(firmware_filename);
> }
> }
> @@ -96,12 +97,14 @@ char *riscv_find_firmware(const char *firmware_filename)
> }
>
> target_ulong riscv_load_firmware(const char *firmware_filename,
> - hwaddr firmware_load_addr)
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb)
> {
> uint64_t firmware_entry, firmware_start, firmware_end;
>
> - if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry,
> - &firmware_start, &firmware_end, NULL, 0, EM_RISCV, 1, 0) > 0) {
> + if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
> + &firmware_entry, &firmware_start, &firmware_end, NULL,
> + 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
> return firmware_entry;
> }
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 56351c4faa..54bb9eb1bf 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -345,7 +345,7 @@ static void riscv_sifive_u_init(MachineState *machine)
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> - memmap[SIFIVE_U_DRAM].base);
> + memmap[SIFIVE_U_DRAM].base, NULL);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 85ec9e22aa..24f851e895 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -507,7 +507,7 @@ static void riscv_virt_board_init(MachineState *machine)
> mask_rom);
>
> riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> - memmap[VIRT_DRAM].base);
> + memmap[VIRT_DRAM].base, NULL);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index df80051fbc..474a940ad5 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -24,10 +24,12 @@
>
> void riscv_find_and_load_firmware(MachineState *machine,
> const char *default_machine_firmware,
> - hwaddr firmware_load_addr);
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb);
> char *riscv_find_firmware(const char *firmware_filename);
> target_ulong riscv_load_firmware(const char *firmware_filename,
> - hwaddr firmware_load_addr);
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb);
> target_ulong riscv_load_kernel(const char *kernel_filename,
> symbol_fn_t sym_cb);
> hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
@ 2020-04-27 15:05 ` Alistair Francis
0 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:05 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Atish Patra, open list:RISC-V,
qemu-devel@nongnu.org Developers, Anup Patel
On Mon, Apr 27, 2020 at 1:09 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This patch adds an optional function pointer, "sym_cb", to
> riscv_load_firmware() which provides the possibility to access
> the symbol table during kernel loading.
>
> The pointer is ignored, if supplied with flat (non-elf) firmware image.
>
> The Spike board requires it locate the HTIF symbols from firmware ELF
> passed via "-bios" option.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/boot.c | 13 ++++++++-----
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/virt.c | 2 +-
> include/hw/riscv/boot.h | 6 ++++--
> 4 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index b8e765277d..726300a171 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -36,7 +36,8 @@
>
> void riscv_find_and_load_firmware(MachineState *machine,
> const char *default_machine_firmware,
> - hwaddr firmware_load_addr)
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb)
> {
> char *firmware_filename = NULL;
>
> @@ -76,7 +77,7 @@ void riscv_find_and_load_firmware(MachineState *machine,
>
> if (firmware_filename) {
> /* If not "none" load the firmware */
> - riscv_load_firmware(firmware_filename, firmware_load_addr);
> + riscv_load_firmware(firmware_filename, firmware_load_addr, sym_cb);
> g_free(firmware_filename);
> }
> }
> @@ -96,12 +97,14 @@ char *riscv_find_firmware(const char *firmware_filename)
> }
>
> target_ulong riscv_load_firmware(const char *firmware_filename,
> - hwaddr firmware_load_addr)
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb)
> {
> uint64_t firmware_entry, firmware_start, firmware_end;
>
> - if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry,
> - &firmware_start, &firmware_end, NULL, 0, EM_RISCV, 1, 0) > 0) {
> + if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
> + &firmware_entry, &firmware_start, &firmware_end, NULL,
> + 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
> return firmware_entry;
> }
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 56351c4faa..54bb9eb1bf 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -345,7 +345,7 @@ static void riscv_sifive_u_init(MachineState *machine)
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> - memmap[SIFIVE_U_DRAM].base);
> + memmap[SIFIVE_U_DRAM].base, NULL);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 85ec9e22aa..24f851e895 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -507,7 +507,7 @@ static void riscv_virt_board_init(MachineState *machine)
> mask_rom);
>
> riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> - memmap[VIRT_DRAM].base);
> + memmap[VIRT_DRAM].base, NULL);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> index df80051fbc..474a940ad5 100644
> --- a/include/hw/riscv/boot.h
> +++ b/include/hw/riscv/boot.h
> @@ -24,10 +24,12 @@
>
> void riscv_find_and_load_firmware(MachineState *machine,
> const char *default_machine_firmware,
> - hwaddr firmware_load_addr);
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb);
> char *riscv_find_firmware(const char *firmware_filename);
> target_ulong riscv_load_firmware(const char *firmware_filename,
> - hwaddr firmware_load_addr);
> + hwaddr firmware_load_addr,
> + symbol_fn_t sym_cb);
> target_ulong riscv_load_kernel(const char *kernel_filename,
> symbol_fn_t sym_cb);
> hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/3] RISC-V Spike machine improvements
2020-04-27 8:06 ` Anup Patel
@ 2020-04-27 15:05 ` Alistair Francis
-1 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:05 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, open list:RISC-V, Sagar Karandikar, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Palmer Dabbelt
On Mon, Apr 27, 2020 at 1:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This series improves QEMU Spike machine to:
> 1. Allow loading OpenBI firmware using -bios option
> 2. Allow more than one CPUs
>
> Changes since v2:
> - Rebased on QEMU v5.0-rc4
>
> Changes since v1:
> - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)
Applied to the RISC-V tree for 5.1.
Alistair
>
> Anup Patel (3):
> hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
> hw/riscv/spike: Allow loading firmware separately using -bios option
> hw/riscv/spike: Allow more than one CPUs
>
> hw/riscv/boot.c | 13 ++++++++-----
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 26 ++++++++++++++++++++++++--
> hw/riscv/virt.c | 2 +-
> include/hw/riscv/boot.h | 6 ++++--
> 5 files changed, 38 insertions(+), 11 deletions(-)
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/3] RISC-V Spike machine improvements
@ 2020-04-27 15:05 ` Alistair Francis
0 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2020-04-27 15:05 UTC (permalink / raw)
To: Anup Patel
Cc: Peter Maydell, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Atish Patra, open list:RISC-V,
qemu-devel@nongnu.org Developers, Anup Patel
On Mon, Apr 27, 2020 at 1:07 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> This series improves QEMU Spike machine to:
> 1. Allow loading OpenBI firmware using -bios option
> 2. Allow more than one CPUs
>
> Changes since v2:
> - Rebased on QEMU v5.0-rc4
>
> Changes since v1:
> - Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)
Applied to the RISC-V tree for 5.1.
Alistair
>
> Anup Patel (3):
> hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
> hw/riscv/spike: Allow loading firmware separately using -bios option
> hw/riscv/spike: Allow more than one CPUs
>
> hw/riscv/boot.c | 13 ++++++++-----
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 26 ++++++++++++++++++++++++--
> hw/riscv/virt.c | 2 +-
> include/hw/riscv/boot.h | 6 ++++--
> 5 files changed, 38 insertions(+), 11 deletions(-)
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-04-27 15:15 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-27 8:06 [PATCH v3 0/3] RISC-V Spike machine improvements Anup Patel
2020-04-27 8:06 ` Anup Patel
2020-04-27 8:06 ` [PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() Anup Patel
2020-04-27 8:06 ` Anup Patel
2020-04-27 15:05 ` Alistair Francis
2020-04-27 15:05 ` Alistair Francis
2020-04-27 8:06 ` [PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option Anup Patel
2020-04-27 8:06 ` Anup Patel
2020-04-27 15:03 ` Alistair Francis
2020-04-27 15:03 ` Alistair Francis
2020-04-27 8:06 ` [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs Anup Patel
2020-04-27 8:06 ` Anup Patel
2020-04-27 15:00 ` Alistair Francis
2020-04-27 15:00 ` Alistair Francis
2020-04-27 15:05 ` [PATCH v3 0/3] RISC-V Spike machine improvements Alistair Francis
2020-04-27 15:05 ` Alistair Francis
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