From: Alistair Francis <alistair23@gmail.com> To: Anup Patel <anup.patel@wdc.com> Cc: Peter Maydell <peter.maydell@linaro.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Date: Wed, 11 Nov 2020 13:59:30 -0800 [thread overview] Message-ID: <CAKmqyKMTFpptBQpR86w4GLEwNMUoqaJAHip+-Abs81KkM-H0jw@mail.gmail.com> (raw) In-Reply-To: <20201111094725.3768755-1-anup.patel@wdc.com> On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote: > > The sifive_u machine emulates two UARTs but we have only UART0 DT > node in the generated DTB so this patch adds UART1 DT node in the > generated DTB. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/riscv/sifive_u.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2f19a9cda2..146944a293 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); > g_free(nodename); > > + nodename = g_strdup_printf("/soc/serial@%lx", > + (long)memmap[SIFIVE_U_DEV_UART1].base); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); > + qemu_fdt_setprop_cells(fdt, nodename, "reg", > + 0x0, memmap[SIFIVE_U_DEV_UART1].base, > + 0x0, memmap[SIFIVE_U_DEV_UART1].size); > + qemu_fdt_setprop_cells(fdt, nodename, "clocks", > + prci_phandle, PRCI_CLK_TLCLK); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); > + > + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); > + g_free(nodename); > + > nodename = g_strdup_printf("/soc/serial@%lx", > (long)memmap[SIFIVE_U_DEV_UART0].base); > qemu_fdt_add_subnode(fdt, nodename); > -- > 2.25.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Anup Patel <anup.patel@wdc.com> Cc: Peter Maydell <peter.maydell@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Atish Patra <atish.patra@wdc.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, Anup Patel <anup@brainfault.org> Subject: Re: [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Date: Wed, 11 Nov 2020 13:59:30 -0800 [thread overview] Message-ID: <CAKmqyKMTFpptBQpR86w4GLEwNMUoqaJAHip+-Abs81KkM-H0jw@mail.gmail.com> (raw) In-Reply-To: <20201111094725.3768755-1-anup.patel@wdc.com> On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote: > > The sifive_u machine emulates two UARTs but we have only UART0 DT > node in the generated DTB so this patch adds UART1 DT node in the > generated DTB. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/riscv/sifive_u.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2f19a9cda2..146944a293 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); > g_free(nodename); > > + nodename = g_strdup_printf("/soc/serial@%lx", > + (long)memmap[SIFIVE_U_DEV_UART1].base); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); > + qemu_fdt_setprop_cells(fdt, nodename, "reg", > + 0x0, memmap[SIFIVE_U_DEV_UART1].base, > + 0x0, memmap[SIFIVE_U_DEV_UART1].size); > + qemu_fdt_setprop_cells(fdt, nodename, "clocks", > + prci_phandle, PRCI_CLK_TLCLK); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); > + > + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); > + g_free(nodename); > + > nodename = g_strdup_printf("/soc/serial@%lx", > (long)memmap[SIFIVE_U_DEV_UART0].base); > qemu_fdt_add_subnode(fdt, nodename); > -- > 2.25.1 > >
next prev parent reply other threads:[~2020-11-11 22:12 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-11-11 9:47 [PATCH] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB Anup Patel 2020-11-11 9:47 ` Anup Patel 2020-11-11 16:50 ` Alistair Francis 2020-11-11 16:50 ` Alistair Francis 2020-11-11 21:59 ` Alistair Francis [this message] 2020-11-11 21:59 ` Alistair Francis
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