* [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V
@ 2018-08-16 16:11 Alistair Francis
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus Alistair Francis
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Alistair Francis @ 2018-08-16 16:11 UTC (permalink / raw)
To: qemu-devel, mjc; +Cc: alistair.francis, alistair23
V3:
- Remove Makefile config changes
- Connect a network adapter to the virt device
V2:
- Use the gpex PCIe host for virt
- Add support for SiFive U PCIe
Alistair Francis (6):
hw/riscv/virtio: Set the soc device tree node as a simple-bus
hw/riscv/virt: Increase the number of interrupts
hw/riscv/virt: Connect the gpex PCIe
hw/riscv/virt: Connect a VGA PCIe device
hw/riscv/sifive_u: Connect the Xilinx PCIe
hw/riscv/virt: Connect a VirtIO net PCIe device
default-configs/riscv32-softmmu.mak | 8 +++
default-configs/riscv64-softmmu.mak | 8 +++
hw/riscv/sifive_u.c | 64 ++++++++++++++++++++++++
hw/riscv/virt.c | 76 ++++++++++++++++++++++++++++-
include/hw/riscv/sifive_u.h | 4 +-
include/hw/riscv/virt.h | 6 ++-
6 files changed, 162 insertions(+), 4 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus
2018-08-16 16:11 [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V Alistair Francis
@ 2018-08-16 16:11 ` Alistair Francis
2018-08-17 23:08 ` Philippe Mathieu-Daudé
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts Alistair Francis
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Alistair Francis @ 2018-08-16 16:11 UTC (permalink / raw)
To: qemu-devel, mjc; +Cc: alistair.francis, alistair23
To allow Linux to ennumerate devices on the /soc/ node set it as a
"simple-bus".
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 248bbdffd3..e8ba4d192d 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -121,7 +121,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/soc");
qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
- qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts
2018-08-16 16:11 [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V Alistair Francis
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus Alistair Francis
@ 2018-08-16 16:11 ` Alistair Francis
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 3/6] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2018-08-16 16:11 UTC (permalink / raw)
To: qemu-devel, mjc; +Cc: alistair.francis, alistair23
Increase the number of interrupts to match the HiFive Unleashed board.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 91163d6cbf..7cb2742070 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -45,7 +45,7 @@ enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
- VIRTIO_NDEV = 10
+ VIRTIO_NDEV = 0x35
};
enum {
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH v3 3/6] hw/riscv/virt: Connect the gpex PCIe
2018-08-16 16:11 [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V Alistair Francis
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus Alistair Francis
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts Alistair Francis
@ 2018-08-16 16:11 ` Alistair Francis
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device Alistair Francis
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2018-08-16 16:11 UTC (permalink / raw)
To: qemu-devel, mjc; +Cc: alistair.francis, alistair23
Connect the gpex PCIe device based on the device tree included in the
HiFive Unleashed ROM.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
default-configs/riscv32-softmmu.mak | 3 ++
default-configs/riscv64-softmmu.mak | 3 ++
hw/riscv/virt.c | 58 +++++++++++++++++++++++++++++
include/hw/riscv/virt.h | 4 +-
4 files changed, 67 insertions(+), 1 deletion(-)
diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 7937c69e22..2c943e2669 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -5,3 +5,6 @@ CONFIG_VIRTIO_MMIO=y
include virtio.mak
CONFIG_CADENCE=y
+
+CONFIG_PCI=y
+CONFIG_PCI_GENERIC=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 7937c69e22..2c943e2669 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -5,3 +5,6 @@ CONFIG_VIRTIO_MMIO=y
include virtio.mak
CONFIG_CADENCE=y
+
+CONFIG_PCI=y
+CONFIG_PCI_GENERIC=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index e8ba4d192d..9bdeea38f2 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -39,6 +39,8 @@
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
#include "elf.h"
#include <libfdt.h>
@@ -55,6 +57,7 @@ static const struct MemmapEntry {
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
[VIRT_DRAM] = { 0x80000000, 0x0 },
+ [VIRT_PCIE] = { 0x2000000000, 0x4000000 },
};
static uint64_t load_kernel(const char *kernel_filename)
@@ -233,6 +236,32 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
+ nodename = g_strdup_printf("/pci@%lx",
+ (long) memmap[VIRT_PCIE].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x3);
+ qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+ qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "pci-host-ecam-generic");
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x20, 0x0, 0x0,
+ memmap[VIRT_PCIE].size);
+ qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
+ qemu_fdt_setprop_cells(fdt, nodename, "ranges", 0x2000000, 0x0,
+ 0x40000000, 0x0, 0x40000000, 0x0, 0x20000000);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts", PCIE_IRQ);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/pci@%lx/interrupt-controller",
+ (long) memmap[VIRT_PCIE].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x00);
+ qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/test@%lx",
(long)memmap[VIRT_TEST].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -260,6 +289,31 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
return fdt;
}
+
+static inline DeviceState *
+gpex_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
+ hwaddr cfg_base, uint64_t cfg_size,
+ hwaddr mmio_base, uint64_t mmio_size,
+ qemu_irq irq, bool link_up)
+{
+ DeviceState *dev;
+ MemoryRegion *cfg, *mmio;
+
+ dev = qdev_create(NULL, TYPE_GPEX_HOST);
+
+ qdev_init_nofail(dev);
+
+ cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
+
+ mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
+
+ return dev;
+}
+
static void riscv_virt_board_init(MachineState *machine)
{
const struct MemmapEntry *memmap = virt_memmap;
@@ -382,6 +436,10 @@ static void riscv_virt_board_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
}
+ gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
+ memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
+ qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7cb2742070..d0129c2ca5 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -38,13 +38,15 @@ enum {
VIRT_PLIC,
VIRT_UART0,
VIRT_VIRTIO,
- VIRT_DRAM
+ VIRT_DRAM,
+ VIRT_PCIE
};
enum {
UART0_IRQ = 10,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
+ PCIE_IRQ = 0x20,
VIRTIO_NDEV = 0x35
};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device
2018-08-16 16:11 [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V Alistair Francis
` (2 preceding siblings ...)
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 3/6] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
@ 2018-08-16 16:12 ` Alistair Francis
2018-08-17 6:36 ` Gerd Hoffmann
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device Alistair Francis
5 siblings, 1 reply; 10+ messages in thread
From: Alistair Francis @ 2018-08-16 16:12 UTC (permalink / raw)
To: qemu-devel, mjc; +Cc: alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
default-configs/riscv32-softmmu.mak | 3 +++
default-configs/riscv64-softmmu.mak | 3 +++
hw/riscv/virt.c | 7 ++++++-
3 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 2c943e2669..fcefa68f1e 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -8,3 +8,6 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 2c943e2669..fcefa68f1e 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -8,3 +8,6 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
+
+CONFIG_VGA=y
+CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 9bdeea38f2..02652e44ee 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -322,6 +322,8 @@ static void riscv_virt_board_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ PCIBus *pci_bus;
+ DeviceState *dev;
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
@@ -436,9 +438,12 @@ static void riscv_virt_board_init(MachineState *machine)
qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i));
}
- gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
+ dev = gpex_pcie_init(system_memory, 0, memmap[VIRT_PCIE].base,
memmap[VIRT_PCIE].size, 0x40000000, 0x20000000,
qdev_get_gpio_in(DEVICE(s->plic), PCIE_IRQ), true);
+ pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+ pci_vga_init(pci_bus);
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH v3 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe
2018-08-16 16:11 [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V Alistair Francis
` (3 preceding siblings ...)
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device Alistair Francis
@ 2018-08-16 16:12 ` Alistair Francis
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device Alistair Francis
5 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2018-08-16 16:12 UTC (permalink / raw)
To: qemu-devel, mjc; +Cc: alistair.francis, alistair23
Connect the Xilinx PCIe device based on the information in the device
tree stored in the ROM of the HiFish Unleashed board.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/sifive_u.c | 64 +++++++++++++++++++++++++++++
include/hw/riscv/sifive_u.h | 4 +-
4 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index fcefa68f1e..35e74bebe9 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -8,6 +8,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
+CONFIG_PCI_XILINX=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index fcefa68f1e..35e74bebe9 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -8,6 +8,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
+CONFIG_PCI_XILINX=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 59ae1ce24a..9a8dd8eade 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -45,6 +45,8 @@
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/xilinx-pcie.h"
#include "elf.h"
#include <libfdt.h>
@@ -61,6 +63,7 @@ static const struct MemmapEntry {
[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
+ [SIFIVE_U_PCIE] = { 0x2000000000, 0x4000000 },
};
#define GEM_REVISION 0x10070109
@@ -218,6 +221,32 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
g_free(nodename);
+ nodename = g_strdup_printf("/pci@%lx",
+ (long) memmap[SIFIVE_U_PCIE].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x3);
+ qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+ qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "xlnx,axi-pcie-host-1.00.a");
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x20, 0x0, 0x0,
+ memmap[SIFIVE_U_PCIE].size);
+ qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
+ qemu_fdt_setprop_cells(fdt, nodename, "ranges", 0x2000000, 0x0,
+ 0x40000000, 0x0, 0x40000000, 0x0, 0x20000000);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_PCIE_IRQ);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/pci@%lx/interrupt-controller",
+ (long) memmap[SIFIVE_U_PCIE].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 0x00);
+ qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", 0x1);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/uart@%lx",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -234,6 +263,37 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
+static inline DeviceState *
+xilinx_pcie_init(MemoryRegion *sys_mem, uint32_t bus_nr,
+ hwaddr cfg_base, uint64_t cfg_size,
+ hwaddr mmio_base, uint64_t mmio_size,
+ qemu_irq irq, bool link_up)
+{
+ DeviceState *dev;
+ MemoryRegion *cfg, *mmio;
+
+ dev = qdev_create(NULL, TYPE_XILINX_PCIE_HOST);
+
+ qdev_prop_set_uint32(dev, "bus_nr", bus_nr);
+ qdev_prop_set_uint64(dev, "cfg_base", cfg_base);
+ qdev_prop_set_uint64(dev, "cfg_size", cfg_size);
+ qdev_prop_set_uint64(dev, "mmio_base", mmio_base);
+ qdev_prop_set_uint64(dev, "mmio_size", mmio_size);
+ qdev_prop_set_bit(dev, "link_up", link_up);
+
+ qdev_init_nofail(dev);
+
+ cfg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_add_subregion_overlap(sys_mem, cfg_base, cfg, 0);
+
+ mmio = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_add_subregion_overlap(sys_mem, 0, mmio, 0);
+
+ qdev_connect_gpio_out_named(dev, "interrupt_out", 0, irq);
+
+ return dev;
+}
+
static void riscv_sifive_u_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
@@ -373,6 +433,10 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
plic_gpios[SIFIVE_U_GEM_IRQ]);
+
+ xilinx_pcie_init(system_memory, 0, memmap[SIFIVE_U_PCIE].base,
+ memmap[SIFIVE_U_PCIE].size, 0x40000000, 0x20000000,
+ qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_PCIE_IRQ), true);
}
static void riscv_sifive_u_machine_init(MachineClass *mc)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e8b4d9ffa3..e7292ea83b 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -53,12 +53,14 @@ enum {
SIFIVE_U_UART0,
SIFIVE_U_UART1,
SIFIVE_U_DRAM,
- SIFIVE_U_GEM
+ SIFIVE_U_GEM,
+ SIFIVE_U_PCIE
};
enum {
SIFIVE_U_UART0_IRQ = 3,
SIFIVE_U_UART1_IRQ = 4,
+ SIFIVE_U_PCIE_IRQ = 0x20,
SIFIVE_U_GEM_IRQ = 0x35
};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device
2018-08-16 16:11 [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V Alistair Francis
` (4 preceding siblings ...)
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
@ 2018-08-16 16:12 ` Alistair Francis
5 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2018-08-16 16:12 UTC (permalink / raw)
To: qemu-devel, mjc; +Cc: alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/virt.c | 11 +++++++++++
3 files changed, 13 insertions(+)
diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index 35e74bebe9..6e19fdc935 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index 35e74bebe9..6e19fdc935 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_CADENCE=y
CONFIG_PCI=y
CONFIG_PCI_GENERIC=y
CONFIG_PCI_XILINX=y
+CONFIG_VIRTIO_PCI=y
CONFIG_VGA=y
CONFIG_VGA_PCI=y
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 02652e44ee..28bf35ea56 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,6 +36,7 @@
#include "hw/riscv/sifive_test.h"
#include "hw/riscv/virt.h"
#include "chardev/char.h"
+#include "net/net.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
#include "exec/address-spaces.h"
@@ -445,6 +446,16 @@ static void riscv_virt_board_init(MachineState *machine)
pci_vga_init(pci_bus);
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!nd->model) {
+ nd->model = g_strdup("virtio");
+ }
+
+ pci_nic_init_nofail(nd, pci_bus, nd->model, NULL);
+ }
+
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device Alistair Francis
@ 2018-08-17 6:36 ` Gerd Hoffmann
2018-08-20 23:50 ` Alistair Francis
0 siblings, 1 reply; 10+ messages in thread
From: Gerd Hoffmann @ 2018-08-17 6:36 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, mjc, alistair23
Hi,
> + pci_bus = PCI_HOST_BRIDGE(dev)->bus;
> +
> + pci_vga_init(pci_bus);
I'd suggest to use "-device bochs-display" instead, unless you need all
the legacy vga cruft (text mode, ...). The bochs-drm kms driver can
handle this one just fine too, it is much smaller (in terms of code
lines and attack surface), and it has pcie support.
cheers,
Gerd
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus Alistair Francis
@ 2018-08-17 23:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-08-17 23:08 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, mjc; +Cc: alistair23
Hi Alistair,
On 08/16/2018 01:11 PM, Alistair Francis wrote:
> To allow Linux to ennumerate devices on the /soc/ node set it as a
enumerate
> "simple-bus".
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/virt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 248bbdffd3..e8ba4d192d 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -121,7 +121,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
>
> qemu_fdt_add_subnode(fdt, "/soc");
> qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
> - qemu_fdt_setprop_string(fdt, "/soc", "compatible", "riscv-virtio-soc");
> + qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
For consistency can you do the same patch for the Spike board?
> qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
> qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device
2018-08-17 6:36 ` Gerd Hoffmann
@ 2018-08-20 23:50 ` Alistair Francis
0 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2018-08-20 23:50 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: Alistair Francis, qemu-devel@nongnu.org Developers, Michael Clark
On Thu, Aug 16, 2018 at 11:36 PM, Gerd Hoffmann <kraxel@redhat.com> wrote:
> Hi,
>
>> + pci_bus = PCI_HOST_BRIDGE(dev)->bus;
>> +
>> + pci_vga_init(pci_bus);
>
> I'd suggest to use "-device bochs-display" instead, unless you need all
> the legacy vga cruft (text mode, ...). The bochs-drm kms driver can
> handle this one just fine too, it is much smaller (in terms of code
> lines and attack surface), and it has pcie support.
I gave this a quick try and the kernel didn't see the device with the
bochs-drm driver enabled.
I'll dig in a little more.
Alistair
>
> cheers,
> Gerd
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-08-20 23:51 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-16 16:11 [Qemu-devel] [PATCH v3 0/6] Connect a PCIe host and graphics support to RISC-V Alistair Francis
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 1/6] hw/riscv/virtio: Set the soc device tree node as a simple-bus Alistair Francis
2018-08-17 23:08 ` Philippe Mathieu-Daudé
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 2/6] hw/riscv/virt: Increase the number of interrupts Alistair Francis
2018-08-16 16:11 ` [Qemu-devel] [PATCH v3 3/6] hw/riscv/virt: Connect the gpex PCIe Alistair Francis
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 4/6] hw/riscv/virt: Connect a VGA PCIe device Alistair Francis
2018-08-17 6:36 ` Gerd Hoffmann
2018-08-20 23:50 ` Alistair Francis
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 5/6] hw/riscv/sifive_u: Connect the Xilinx PCIe Alistair Francis
2018-08-16 16:12 ` [Qemu-devel] [PATCH v3 6/6] hw/riscv/virt: Connect a VirtIO net PCIe device Alistair Francis
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