* [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property
2020-04-17 19:10 [PATCH v1 0/6] target-microblaze: Misc configurability #2 Edgar E. Iglesias
@ 2020-04-17 19:10 ` Edgar E. Iglesias
2020-04-17 21:30 ` Alistair Francis
2020-04-19 19:07 ` Luc Michel
2020-04-17 19:10 ` [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property Edgar E. Iglesias
` (5 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Edgar E. Iglesias @ 2020-04-17 19:10 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the opcode-0x0-illegal CPU property to control if the core
should trap opcode zero as illegal.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.c | 6 +++++-
target/microblaze/cpu.h | 1 +
target/microblaze/translate.c | 2 +-
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index a2c2f271df..1044120702 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -206,7 +206,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.dopb_bus_exception ?
PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ?
- PVR2_IOPB_BUS_EXC_MASK : 0);
+ PVR2_IOPB_BUS_EXC_MASK : 0) |
+ (cpu->cfg.opcode_0_illegal ?
+ PVR2_OPCODE_0x0_ILL_MASK : 0);
env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
PVR5_DCACHE_WRITEBACK_MASK : 0;
@@ -274,6 +276,8 @@ static Property mb_properties[] = {
/* Enables bus exceptions on failed instruction fetches. */
DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
cfg.iopb_bus_exception, false),
+ DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
+ cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_END_OF_LIST(),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 1a700a880c..d51587b342 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -303,6 +303,7 @@ struct MicroBlazeCPU {
bool endi;
bool dopb_bus_exception;
bool iopb_bus_exception;
+ bool opcode_0_illegal;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 37a844db99..222632b670 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
LOG_DIS("%8.8x\t", dc->ir);
if (ir == 0) {
- trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
+ trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
/* Don't decode nop/zero instructions any further. */
return;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property
2020-04-17 19:10 ` [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property Edgar E. Iglesias
@ 2020-04-17 21:30 ` Alistair Francis
2020-04-19 19:07 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2020-04-17 21:30 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Fri, Apr 17, 2020 at 12:12 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the opcode-0x0-illegal CPU property to control if the core
> should trap opcode zero as illegal.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/cpu.c | 6 +++++-
> target/microblaze/cpu.h | 1 +
> target/microblaze/translate.c | 2 +-
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index a2c2f271df..1044120702 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -206,7 +206,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> (cpu->cfg.dopb_bus_exception ?
> PVR2_DOPB_BUS_EXC_MASK : 0) |
> (cpu->cfg.iopb_bus_exception ?
> - PVR2_IOPB_BUS_EXC_MASK : 0);
> + PVR2_IOPB_BUS_EXC_MASK : 0) |
> + (cpu->cfg.opcode_0_illegal ?
> + PVR2_OPCODE_0x0_ILL_MASK : 0);
>
> env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
> PVR5_DCACHE_WRITEBACK_MASK : 0;
> @@ -274,6 +276,8 @@ static Property mb_properties[] = {
> /* Enables bus exceptions on failed instruction fetches. */
> DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
> cfg.iopb_bus_exception, false),
> + DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> + cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
> DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 1a700a880c..d51587b342 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -303,6 +303,7 @@ struct MicroBlazeCPU {
> bool endi;
> bool dopb_bus_exception;
> bool iopb_bus_exception;
> + bool opcode_0_illegal;
> char *version;
> uint8_t pvr;
> } cfg;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 37a844db99..222632b670 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
> LOG_DIS("%8.8x\t", dc->ir);
>
> if (ir == 0) {
> - trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
> + trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
> /* Don't decode nop/zero instructions any further. */
> return;
> }
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property
2020-04-17 19:10 ` [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property Edgar E. Iglesias
2020-04-17 21:30 ` Alistair Francis
@ 2020-04-19 19:07 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Luc Michel @ 2020-04-19 19:07 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the opcode-0x0-illegal CPU property to control if the core
> should trap opcode zero as illegal.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> ---
> target/microblaze/cpu.c | 6 +++++-
> target/microblaze/cpu.h | 1 +
> target/microblaze/translate.c | 2 +-
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index a2c2f271df..1044120702 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -206,7 +206,9 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> (cpu->cfg.dopb_bus_exception ?
> PVR2_DOPB_BUS_EXC_MASK : 0) |
> (cpu->cfg.iopb_bus_exception ?
> - PVR2_IOPB_BUS_EXC_MASK : 0);
> + PVR2_IOPB_BUS_EXC_MASK : 0) |
> + (cpu->cfg.opcode_0_illegal ?
> + PVR2_OPCODE_0x0_ILL_MASK : 0);
>
> env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
> PVR5_DCACHE_WRITEBACK_MASK : 0;
> @@ -274,6 +276,8 @@ static Property mb_properties[] = {
> /* Enables bus exceptions on failed instruction fetches. */
> DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
> cfg.iopb_bus_exception, false),
> + DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> + cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
> DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 1a700a880c..d51587b342 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -303,6 +303,7 @@ struct MicroBlazeCPU {
> bool endi;
> bool dopb_bus_exception;
> bool iopb_bus_exception;
> + bool opcode_0_illegal;
> char *version;
> uint8_t pvr;
> } cfg;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 37a844db99..222632b670 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
> LOG_DIS("%8.8x\t", dc->ir);
>
> if (ir == 0) {
> - trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK);
> + trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
> /* Don't decode nop/zero instructions any further. */
> return;
> }
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property
2020-04-17 19:10 [PATCH v1 0/6] target-microblaze: Misc configurability #2 Edgar E. Iglesias
2020-04-17 19:10 ` [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property Edgar E. Iglesias
@ 2020-04-17 19:10 ` Edgar E. Iglesias
2020-04-17 21:31 ` Alistair Francis
2020-04-19 19:08 ` Luc Michel
2020-04-17 19:10 ` [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property Edgar E. Iglesias
` (4 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Edgar E. Iglesias @ 2020-04-17 19:10 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the ill-opcode-exception property to control if illegal
instructions will raise exceptions.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.c | 4 ++++
target/microblaze/cpu.h | 1 +
target/microblaze/translate.c | 2 +-
3 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 1044120702..36c20d9724 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_DOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.iopb_bus_exception ?
PVR2_IOPB_BUS_EXC_MASK : 0) |
+ (cpu->cfg.illegal_opcode_exception ?
+ PVR2_ILL_OPCODE_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
PVR2_OPCODE_0x0_ILL_MASK : 0);
@@ -276,6 +278,8 @@ static Property mb_properties[] = {
/* Enables bus exceptions on failed instruction fetches. */
DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
cfg.iopb_bus_exception, false),
+ DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
+ cfg.illegal_opcode_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index d51587b342..71d7317a58 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -303,6 +303,7 @@ struct MicroBlazeCPU {
bool endi;
bool dopb_bus_exception;
bool iopb_bus_exception;
+ bool illegal_opcode_exception;
bool opcode_0_illegal;
char *version;
uint8_t pvr;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 222632b670..b4a78551ef 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry)
static bool trap_illegal(DisasContext *dc, bool cond)
{
if (cond && (dc->tb_flags & MSR_EE_FLAG)
- && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
+ && dc->cpu->cfg.illegal_opcode_exception) {
tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property
2020-04-17 19:10 ` [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property Edgar E. Iglesias
@ 2020-04-17 21:31 ` Alistair Francis
2020-04-19 19:08 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2020-04-17 21:31 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Fri, Apr 17, 2020 at 12:14 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the ill-opcode-exception property to control if illegal
> instructions will raise exceptions.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/cpu.c | 4 ++++
> target/microblaze/cpu.h | 1 +
> target/microblaze/translate.c | 2 +-
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 1044120702..36c20d9724 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> PVR2_DOPB_BUS_EXC_MASK : 0) |
> (cpu->cfg.iopb_bus_exception ?
> PVR2_IOPB_BUS_EXC_MASK : 0) |
> + (cpu->cfg.illegal_opcode_exception ?
> + PVR2_ILL_OPCODE_EXC_MASK : 0) |
> (cpu->cfg.opcode_0_illegal ?
> PVR2_OPCODE_0x0_ILL_MASK : 0);
>
> @@ -276,6 +278,8 @@ static Property mb_properties[] = {
> /* Enables bus exceptions on failed instruction fetches. */
> DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
> cfg.iopb_bus_exception, false),
> + DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
> + cfg.illegal_opcode_exception, false),
> DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index d51587b342..71d7317a58 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -303,6 +303,7 @@ struct MicroBlazeCPU {
> bool endi;
> bool dopb_bus_exception;
> bool iopb_bus_exception;
> + bool illegal_opcode_exception;
> bool opcode_0_illegal;
> char *version;
> uint8_t pvr;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 222632b670..b4a78551ef 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry)
> static bool trap_illegal(DisasContext *dc, bool cond)
> {
> if (cond && (dc->tb_flags & MSR_EE_FLAG)
> - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
> + && dc->cpu->cfg.illegal_opcode_exception) {
> tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
> t_gen_raise_exception(dc, EXCP_HW_EXCP);
> }
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property
2020-04-17 19:10 ` [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property Edgar E. Iglesias
2020-04-17 21:31 ` Alistair Francis
@ 2020-04-19 19:08 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Luc Michel @ 2020-04-19 19:08 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the ill-opcode-exception property to control if illegal
> instructions will raise exceptions.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> ---
> target/microblaze/cpu.c | 4 ++++
> target/microblaze/cpu.h | 1 +
> target/microblaze/translate.c | 2 +-
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 1044120702..36c20d9724 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -207,6 +207,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> PVR2_DOPB_BUS_EXC_MASK : 0) |
> (cpu->cfg.iopb_bus_exception ?
> PVR2_IOPB_BUS_EXC_MASK : 0) |
> + (cpu->cfg.illegal_opcode_exception ?
> + PVR2_ILL_OPCODE_EXC_MASK : 0) |
> (cpu->cfg.opcode_0_illegal ?
> PVR2_OPCODE_0x0_ILL_MASK : 0);
>
> @@ -276,6 +278,8 @@ static Property mb_properties[] = {
> /* Enables bus exceptions on failed instruction fetches. */
> DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
> cfg.iopb_bus_exception, false),
> + DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
> + cfg.illegal_opcode_exception, false),
> DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index d51587b342..71d7317a58 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -303,6 +303,7 @@ struct MicroBlazeCPU {
> bool endi;
> bool dopb_bus_exception;
> bool iopb_bus_exception;
> + bool illegal_opcode_exception;
> bool opcode_0_illegal;
> char *version;
> uint8_t pvr;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 222632b670..b4a78551ef 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry)
> static bool trap_illegal(DisasContext *dc, bool cond)
> {
> if (cond && (dc->tb_flags & MSR_EE_FLAG)
> - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
> + && dc->cpu->cfg.illegal_opcode_exception) {
> tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
> t_gen_raise_exception(dc, EXCP_HW_EXCP);
> }
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property
2020-04-17 19:10 [PATCH v1 0/6] target-microblaze: Misc configurability #2 Edgar E. Iglesias
2020-04-17 19:10 ` [PATCH v1 1/6] target/microblaze: Add the opcode-0x0-illegal CPU property Edgar E. Iglesias
2020-04-17 19:10 ` [PATCH v1 2/6] target/microblaze: Add the ill-opcode-exception property Edgar E. Iglesias
@ 2020-04-17 19:10 ` Edgar E. Iglesias
2020-04-17 21:35 ` Alistair Francis
2020-04-19 19:25 ` Luc Michel
2020-04-17 19:10 ` [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property Edgar E. Iglesias
` (3 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Edgar E. Iglesias @ 2020-04-17 19:10 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the div-zero-exception property to control if the core
traps divizions by zero.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.c | 2 ++
target/microblaze/cpu.h | 1 +
target/microblaze/op_helper.c | 5 +++--
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 36c20d9724..7a40e2fbad 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -280,6 +280,8 @@ static Property mb_properties[] = {
cfg.iopb_bus_exception, false),
DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
cfg.illegal_opcode_exception, false),
+ DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
+ cfg.div_zero_exception, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 71d7317a58..3c07f9b3f7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -305,6 +305,7 @@ struct MicroBlazeCPU {
bool iopb_bus_exception;
bool illegal_opcode_exception;
bool opcode_0_illegal;
+ bool div_zero_exception;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
index 18677ddfca..f3b17a95b3 100644
--- a/target/microblaze/op_helper.c
+++ b/target/microblaze/op_helper.c
@@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
+ MicroBlazeCPU *cpu = env_archcpu(env);
+
if (b == 0) {
env->sregs[SR_MSR] |= MSR_DZ;
- if ((env->sregs[SR_MSR] & MSR_EE)
- && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
+ if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO;
helper_raise_exception(env, EXCP_HW_EXCP);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property
2020-04-17 19:10 ` [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property Edgar E. Iglesias
@ 2020-04-17 21:35 ` Alistair Francis
2020-04-19 19:25 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2020-04-17 21:35 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Fri, Apr 17, 2020 at 12:15 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the div-zero-exception property to control if the core
> traps divizions by zero.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/cpu.c | 2 ++
> target/microblaze/cpu.h | 1 +
> target/microblaze/op_helper.c | 5 +++--
> 3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 36c20d9724..7a40e2fbad 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -280,6 +280,8 @@ static Property mb_properties[] = {
> cfg.iopb_bus_exception, false),
> DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
> cfg.illegal_opcode_exception, false),
> + DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
> + cfg.div_zero_exception, false),
> DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 71d7317a58..3c07f9b3f7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -305,6 +305,7 @@ struct MicroBlazeCPU {
> bool iopb_bus_exception;
> bool illegal_opcode_exception;
> bool opcode_0_illegal;
> + bool div_zero_exception;
> char *version;
> uint8_t pvr;
> } cfg;
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index 18677ddfca..f3b17a95b3 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
>
> static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
> {
> + MicroBlazeCPU *cpu = env_archcpu(env);
> +
> if (b == 0) {
> env->sregs[SR_MSR] |= MSR_DZ;
>
> - if ((env->sregs[SR_MSR] & MSR_EE)
> - && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
> + if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
> env->sregs[SR_ESR] = ESR_EC_DIVZERO;
> helper_raise_exception(env, EXCP_HW_EXCP);
> }
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property
2020-04-17 19:10 ` [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property Edgar E. Iglesias
2020-04-17 21:35 ` Alistair Francis
@ 2020-04-19 19:25 ` Luc Michel
2020-04-20 17:20 ` Edgar E. Iglesias
1 sibling, 1 reply; 21+ messages in thread
From: Luc Michel @ 2020-04-19 19:25 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
Hi Edgar,
On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the div-zero-exception property to control if the core
> traps divizions by zero.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/cpu.c | 2 ++
> target/microblaze/cpu.h | 1 +
> target/microblaze/op_helper.c | 5 +++--
> 3 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 36c20d9724..7a40e2fbad 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -280,6 +280,8 @@ static Property mb_properties[] = {
> cfg.iopb_bus_exception, false),
> DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
> cfg.illegal_opcode_exception, false),
> + DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
> + cfg.div_zero_exception, false),
> DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 71d7317a58..3c07f9b3f7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -305,6 +305,7 @@ struct MicroBlazeCPU {
> bool iopb_bus_exception;
> bool illegal_opcode_exception;
> bool opcode_0_illegal;
> + bool div_zero_exception;
> char *version;
> uint8_t pvr;
> } cfg;
> diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c
> index 18677ddfca..f3b17a95b3 100644
> --- a/target/microblaze/op_helper.c
> +++ b/target/microblaze/op_helper.c
> @@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
>
> static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
> {
> + MicroBlazeCPU *cpu = env_archcpu(env);
> +
> if (b == 0) {
> env->sregs[SR_MSR] |= MSR_DZ;
>
> - if ((env->sregs[SR_MSR] & MSR_EE)
> - && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
> + if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) {
> env->sregs[SR_ESR] = ESR_EC_DIVZERO;
> helper_raise_exception(env, EXCP_HW_EXCP);
> }
>
I don't know the Microblaze but don't you need to set pvr.regs[2] in
mb_cpu_realizefn as you do in previous patches?
Something like:
env->pvr.regs[2] |=
...
(cpu->cfg.div_zero_exception ?
PVR2_DIV_ZERO_EXC_MASK : 0) |
...
--
Luc
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property
2020-04-19 19:25 ` Luc Michel
@ 2020-04-20 17:20 ` Edgar E. Iglesias
0 siblings, 0 replies; 21+ messages in thread
From: Edgar E. Iglesias @ 2020-04-20 17:20 UTC (permalink / raw)
To: Luc Michel
Cc: figlesia, peter.maydell, sstabellini, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
frederic.konrad, Edgar E. Iglesias, philmd
On Sun, Apr 19, 2020 at 09:25:28PM +0200, Luc Michel wrote:
> Hi Edgar,
>
> On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Add the div-zero-exception property to control if the core
> > traps divizions by zero.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
...
> > }
> >
>
> I don't know the Microblaze but don't you need to set pvr.regs[2] in
> mb_cpu_realizefn as you do in previous patches?
>
> Something like:
>
> env->pvr.regs[2] |=
> ...
> (cpu->cfg.div_zero_exception ?
> PVR2_DIV_ZERO_EXC_MASK : 0) |
> ...
Yes you're right Luc. I'll post a v2 shortly.
Thanks,
Edgar
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property
2020-04-17 19:10 [PATCH v1 0/6] target-microblaze: Misc configurability #2 Edgar E. Iglesias
` (2 preceding siblings ...)
2020-04-17 19:10 ` [PATCH v1 3/6] target/microblaze: Add the div-zero-exception property Edgar E. Iglesias
@ 2020-04-17 19:10 ` Edgar E. Iglesias
2020-04-17 21:35 ` Alistair Francis
2020-04-19 19:26 ` Luc Michel
2020-04-17 19:10 ` [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property Edgar E. Iglesias
` (2 subsequent siblings)
6 siblings, 2 replies; 21+ messages in thread
From: Edgar E. Iglesias @ 2020-04-17 19:10 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the unaligned-exceptions property to control if the core
traps unaligned memory accesses.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.c | 4 ++++
target/microblaze/cpu.h | 1 +
target/microblaze/translate.c | 4 ++--
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 7a40e2fbad..a850c7b23c 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -209,6 +209,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_IOPB_BUS_EXC_MASK : 0) |
(cpu->cfg.illegal_opcode_exception ?
PVR2_ILL_OPCODE_EXC_MASK : 0) |
+ (cpu->cfg.unaligned_exceptions ?
+ PVR2_UNALIGNED_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
PVR2_OPCODE_0x0_ILL_MASK : 0);
@@ -282,6 +284,8 @@ static Property mb_properties[] = {
cfg.illegal_opcode_exception, false),
DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
cfg.div_zero_exception, false),
+ DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
+ cfg.unaligned_exceptions, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3c07f9b3f7..ef9081db40 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -306,6 +306,7 @@ struct MicroBlazeCPU {
bool illegal_opcode_exception;
bool opcode_0_illegal;
bool div_zero_exception;
+ bool unaligned_exceptions;
char *version;
uint8_t pvr;
} cfg;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b4a78551ef..20b7427811 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
v = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
- if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
TCGv_i32 t0 = tcg_const_i32(0);
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);
@@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
/* Verify alignment if needed. */
- if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
TCGv_i32 t1 = tcg_const_i32(1);
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property
2020-04-17 19:10 ` [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property Edgar E. Iglesias
@ 2020-04-17 21:35 ` Alistair Francis
2020-04-19 19:26 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2020-04-17 21:35 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Fri, Apr 17, 2020 at 12:10 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the unaligned-exceptions property to control if the core
> traps unaligned memory accesses.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/cpu.c | 4 ++++
> target/microblaze/cpu.h | 1 +
> target/microblaze/translate.c | 4 ++--
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 7a40e2fbad..a850c7b23c 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -209,6 +209,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> PVR2_IOPB_BUS_EXC_MASK : 0) |
> (cpu->cfg.illegal_opcode_exception ?
> PVR2_ILL_OPCODE_EXC_MASK : 0) |
> + (cpu->cfg.unaligned_exceptions ?
> + PVR2_UNALIGNED_EXC_MASK : 0) |
> (cpu->cfg.opcode_0_illegal ?
> PVR2_OPCODE_0x0_ILL_MASK : 0);
>
> @@ -282,6 +284,8 @@ static Property mb_properties[] = {
> cfg.illegal_opcode_exception, false),
> DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
> cfg.div_zero_exception, false),
> + DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
> + cfg.unaligned_exceptions, false),
> DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 3c07f9b3f7..ef9081db40 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -306,6 +306,7 @@ struct MicroBlazeCPU {
> bool illegal_opcode_exception;
> bool opcode_0_illegal;
> bool div_zero_exception;
> + bool unaligned_exceptions;
> char *version;
> uint8_t pvr;
> } cfg;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index b4a78551ef..20b7427811 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
> v = tcg_temp_new_i32();
> tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>
> - if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
> TCGv_i32 t0 = tcg_const_i32(0);
> TCGv_i32 treg = tcg_const_i32(dc->rd);
> TCGv_i32 tsize = tcg_const_i32(size - 1);
> @@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
> tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
>
> /* Verify alignment if needed. */
> - if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
> TCGv_i32 t1 = tcg_const_i32(1);
> TCGv_i32 treg = tcg_const_i32(dc->rd);
> TCGv_i32 tsize = tcg_const_i32(size - 1);
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property
2020-04-17 19:10 ` [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property Edgar E. Iglesias
2020-04-17 21:35 ` Alistair Francis
@ 2020-04-19 19:26 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Luc Michel @ 2020-04-19 19:26 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the unaligned-exceptions property to control if the core
> traps unaligned memory accesses.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> ---
> target/microblaze/cpu.c | 4 ++++
> target/microblaze/cpu.h | 1 +
> target/microblaze/translate.c | 4 ++--
> 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 7a40e2fbad..a850c7b23c 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -209,6 +209,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> PVR2_IOPB_BUS_EXC_MASK : 0) |
> (cpu->cfg.illegal_opcode_exception ?
> PVR2_ILL_OPCODE_EXC_MASK : 0) |
> + (cpu->cfg.unaligned_exceptions ?
> + PVR2_UNALIGNED_EXC_MASK : 0) |
> (cpu->cfg.opcode_0_illegal ?
> PVR2_OPCODE_0x0_ILL_MASK : 0);
>
> @@ -282,6 +284,8 @@ static Property mb_properties[] = {
> cfg.illegal_opcode_exception, false),
> DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
> cfg.div_zero_exception, false),
> + DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
> + cfg.unaligned_exceptions, false),
> DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 3c07f9b3f7..ef9081db40 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -306,6 +306,7 @@ struct MicroBlazeCPU {
> bool illegal_opcode_exception;
> bool opcode_0_illegal;
> bool div_zero_exception;
> + bool unaligned_exceptions;
> char *version;
> uint8_t pvr;
> } cfg;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index b4a78551ef..20b7427811 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
> v = tcg_temp_new_i32();
> tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>
> - if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
> TCGv_i32 t0 = tcg_const_i32(0);
> TCGv_i32 treg = tcg_const_i32(dc->rd);
> TCGv_i32 tsize = tcg_const_i32(size - 1);
> @@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
> tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
>
> /* Verify alignment if needed. */
> - if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
> TCGv_i32 t1 = tcg_const_i32(1);
> TCGv_i32 treg = tcg_const_i32(dc->rd);
> TCGv_i32 tsize = tcg_const_i32(size - 1);
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property
2020-04-17 19:10 [PATCH v1 0/6] target-microblaze: Misc configurability #2 Edgar E. Iglesias
` (3 preceding siblings ...)
2020-04-17 19:10 ` [PATCH v1 4/6] target/microblaze: Add the unaligned-exceptions property Edgar E. Iglesias
@ 2020-04-17 19:10 ` Edgar E. Iglesias
2020-04-17 21:36 ` Alistair Francis
2020-04-19 19:28 ` Luc Michel
2020-04-17 19:10 ` [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property Edgar E. Iglesias
2020-04-17 23:42 ` [PATCH v1 0/6] target-microblaze: Misc configurability #2 no-reply
6 siblings, 2 replies; 21+ messages in thread
From: Edgar E. Iglesias @ 2020-04-17 19:10 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the pvr-user1 property to control the user-defined
PVR0 User1 field.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.c | 4 +++-
target/microblaze/cpu.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index a850c7b23c..0759b23a83 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -193,7 +193,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
(version_code << PVR0_VERSION_SHIFT) |
- (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
+ (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
+ cpu->cfg.pvr_user1;
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
@@ -290,6 +291,7 @@ static Property mb_properties[] = {
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
+ DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index ef9081db40..7bb5a3d6c6 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -307,6 +307,7 @@ struct MicroBlazeCPU {
bool opcode_0_illegal;
bool div_zero_exception;
bool unaligned_exceptions;
+ uint8_t pvr_user1;
char *version;
uint8_t pvr;
} cfg;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property
2020-04-17 19:10 ` [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property Edgar E. Iglesias
@ 2020-04-17 21:36 ` Alistair Francis
2020-04-19 19:28 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2020-04-17 21:36 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Fri, Apr 17, 2020 at 12:17 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the pvr-user1 property to control the user-defined
> PVR0 User1 field.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/cpu.c | 4 +++-
> target/microblaze/cpu.h | 1 +
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index a850c7b23c..0759b23a83 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -193,7 +193,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
> (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
> (version_code << PVR0_VERSION_SHIFT) |
> - (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
> + (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
> + cpu->cfg.pvr_user1;
>
> env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
> @@ -290,6 +291,7 @@ static Property mb_properties[] = {
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
> + DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index ef9081db40..7bb5a3d6c6 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -307,6 +307,7 @@ struct MicroBlazeCPU {
> bool opcode_0_illegal;
> bool div_zero_exception;
> bool unaligned_exceptions;
> + uint8_t pvr_user1;
> char *version;
> uint8_t pvr;
> } cfg;
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property
2020-04-17 19:10 ` [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property Edgar E. Iglesias
2020-04-17 21:36 ` Alistair Francis
@ 2020-04-19 19:28 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Luc Michel @ 2020-04-19 19:28 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the pvr-user1 property to control the user-defined
> PVR0 User1 field.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> ---
> target/microblaze/cpu.c | 4 +++-
> target/microblaze/cpu.h | 1 +
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index a850c7b23c..0759b23a83 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -193,7 +193,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
> (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
> (version_code << PVR0_VERSION_SHIFT) |
> - (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
> + (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
> + cpu->cfg.pvr_user1;
>
> env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
> @@ -290,6 +291,7 @@ static Property mb_properties[] = {
> cfg.opcode_0_illegal, false),
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
> + DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index ef9081db40..7bb5a3d6c6 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -307,6 +307,7 @@ struct MicroBlazeCPU {
> bool opcode_0_illegal;
> bool div_zero_exception;
> bool unaligned_exceptions;
> + uint8_t pvr_user1;
> char *version;
> uint8_t pvr;
> } cfg;
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property
2020-04-17 19:10 [PATCH v1 0/6] target-microblaze: Misc configurability #2 Edgar E. Iglesias
` (4 preceding siblings ...)
2020-04-17 19:10 ` [PATCH v1 5/6] target/microblaze: Add the pvr-user1 property Edgar E. Iglesias
@ 2020-04-17 19:10 ` Edgar E. Iglesias
2020-04-17 21:36 ` Alistair Francis
2020-04-19 19:30 ` Luc Michel
2020-04-17 23:42 ` [PATCH v1 0/6] target-microblaze: Misc configurability #2 no-reply
6 siblings, 2 replies; 21+ messages in thread
From: Edgar E. Iglesias @ 2020-04-17 19:10 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add the pvr-user2 property to control the user-defined
PVR1 User2 register.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/cpu.c | 2 ++
target/microblaze/cpu.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 0759b23a83..d024ec80eb 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -196,6 +196,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
cpu->cfg.pvr_user1;
+ env->pvr.regs[1] = cpu->cfg.pvr_user2;
env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
(cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
@@ -292,6 +293,7 @@ static Property mb_properties[] = {
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
+ DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 7bb5a3d6c6..a31134b65c 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -308,6 +308,7 @@ struct MicroBlazeCPU {
bool div_zero_exception;
bool unaligned_exceptions;
uint8_t pvr_user1;
+ uint32_t pvr_user2;
char *version;
uint8_t pvr;
} cfg;
--
2.20.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property
2020-04-17 19:10 ` [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property Edgar E. Iglesias
@ 2020-04-17 21:36 ` Alistair Francis
2020-04-19 19:30 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Alistair Francis @ 2020-04-17 21:36 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Fri, Apr 17, 2020 at 12:13 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the pvr-user2 property to control the user-defined
> PVR1 User2 register.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/cpu.c | 2 ++
> target/microblaze/cpu.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 0759b23a83..d024ec80eb 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -196,6 +196,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
> cpu->cfg.pvr_user1;
>
> + env->pvr.regs[1] = cpu->cfg.pvr_user2;
> env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
> (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
> @@ -292,6 +293,7 @@ static Property mb_properties[] = {
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
> DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
> + DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 7bb5a3d6c6..a31134b65c 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -308,6 +308,7 @@ struct MicroBlazeCPU {
> bool div_zero_exception;
> bool unaligned_exceptions;
> uint8_t pvr_user1;
> + uint32_t pvr_user2;
> char *version;
> uint8_t pvr;
> } cfg;
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property
2020-04-17 19:10 ` [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property Edgar E. Iglesias
2020-04-17 21:36 ` Alistair Francis
@ 2020-04-19 19:30 ` Luc Michel
1 sibling, 0 replies; 21+ messages in thread
From: Luc Michel @ 2020-04-19 19:30 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the pvr-user2 property to control the user-defined
> PVR1 User2 register.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> ---
> target/microblaze/cpu.c | 2 ++
> target/microblaze/cpu.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 0759b23a83..d024ec80eb 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -196,6 +196,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
> (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
> cpu->cfg.pvr_user1;
>
> + env->pvr.regs[1] = cpu->cfg.pvr_user2;
> env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
> (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
> @@ -292,6 +293,7 @@ static Property mb_properties[] = {
> DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
> DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
> + DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 7bb5a3d6c6..a31134b65c 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -308,6 +308,7 @@ struct MicroBlazeCPU {
> bool div_zero_exception;
> bool unaligned_exceptions;
> uint8_t pvr_user1;
> + uint32_t pvr_user2;
> char *version;
> uint8_t pvr;
> } cfg;
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v1 0/6] target-microblaze: Misc configurability #2
2020-04-17 19:10 [PATCH v1 0/6] target-microblaze: Misc configurability #2 Edgar E. Iglesias
` (5 preceding siblings ...)
2020-04-17 19:10 ` [PATCH v1 6/6] target/microblaze: Add the pvr-user2 property Edgar E. Iglesias
@ 2020-04-17 23:42 ` no-reply
6 siblings, 0 replies; 21+ messages in thread
From: no-reply @ 2020-04-17 23:42 UTC (permalink / raw)
To: edgar.iglesias
Cc: figlesia, peter.maydell, edgar.iglesias, sai.pavan.boddu,
frasse.iglesias, alistair, richard.henderson, qemu-devel,
frederic.konrad, sstabellini, philmd, luc.michel
Patchew URL: https://patchew.org/QEMU/20200417191022.5247-1-edgar.iglesias@gmail.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
+++ /tmp/qemu-test/build/tests/qemu-iotests/041.out.bad 2020-04-17 23:35:33.298867907 +0000
@@ -1,5 +1,30 @@
-..............................................................................................
+WARNING:qemu.machine:qemu received signal 9: /tmp/qemu-test/build/tests/qemu-iotests/../../x86_64-softmmu/qemu-system-x86_64 -display none -vga none -chardev socket,id=mon,path=/tmp/tmp.dKXJUamDRC/qemu-22174-monitor.sock -mon chardev=mon,mode=control -qtest unix:path=/tmp/tmp.dKXJUamDRC/qemu-22174-qtest.sock -accel qtest -nodefaults -display none -accel qtest -drive if=virtio,id=drive0,file=/tmp/qemu-test/test.img,format=qcow2,cache=writeback,aio=threads,node-name=top,backing.node-name=base -drive if=ide,id=drive1,media=cdrom
+...........................................................................E..................
+======================================================================
+ERROR: test_pause (__main__.TestSingleDriveUnalignedLength)
+----------------------------------------------------------------------
+Traceback (most recent call last):
+ File "041", line 108, in test_pause
---
Ran 94 tests
-OK
+FAILED (errors=1)
TEST iotest-qcow2: 042
TEST iotest-qcow2: 043
qemu-system-aarch64: -accel kvm: invalid accelerator kvm
---
Not run: 259
Failures: 041
Failed 1 of 117 iotests
make: *** [check-tests/check-block.sh] Error 1
make: *** Waiting for unfinished jobs....
TEST check-qtest-aarch64: tests/qtest/qos-test
Traceback (most recent call last):
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=795821883a8946209b375c64277f6a7b', '-u', '1001', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-o9tqlkps/src/docker-src.2020-04-17-19.28.05.2438:/var/tmp/qemu:z,ro', 'qemu:centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=795821883a8946209b375c64277f6a7b
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-o9tqlkps/src'
make: *** [docker-run-test-quick@centos7] Error 2
real 14m21.991s
user 0m8.768s
The full log is available at
http://patchew.org/logs/20200417191022.5247-1-edgar.iglesias@gmail.com/testing.docker-quick@centos7/?type=message.
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