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From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	"open list:Overall" <kvm@vger.kernel.org>,
	libvir-list@redhat.com,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Anup Patel <anup.patel@wdc.com>,
	yinyipeng <yinyipeng1@huawei.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	kvm-riscv@lists.infradead.org,
	Palmer Dabbelt <palmer@dabbelt.com>,
	fanliang@huawei.com, "Wubin (H)" <wu.wubin@huawei.com>,
	Zhanghailiang <zhang.zhanghailiang@huawei.com>
Subject: Re: [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
Date: Thu, 15 Apr 2021 08:32:09 +1000	[thread overview]
Message-ID: <CAKmqyKN-eiDw3Ufo1QyLg5ELP-JY+aq3Bi1cPJVf8gQtsu+qkw@mail.gmail.com> (raw)
In-Reply-To: <20210412065246.1853-4-jiangyifei@huawei.com>

On Mon, Apr 12, 2021 at 4:53 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Get isa info from kvm while kvm init.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  target/riscv/kvm.c | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 687dd4b621..0d924be33f 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -38,6 +38,18 @@
>  #include "qemu/log.h"
>  #include "hw/loader.h"
>
> +static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
> +{
> +    __u64 id = KVM_REG_RISCV | type | idx;

Can you use uint64_t instead of __u64?

Once that is fixed:

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> +
> +    if (riscv_cpu_is_32bit(env)) {
> +        id |= KVM_REG_SIZE_U32;
> +    } else {
> +        id |= KVM_REG_SIZE_U64;
> +    }
> +    return id;
> +}
> +
>  const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
>      KVM_CAP_LAST_INFO
>  };
> @@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s)
>
>  int kvm_arch_init_vcpu(CPUState *cs)
>  {
> -    return 0;
> +    int ret = 0;
> +    target_ulong isa;
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +    CPURISCVState *env = &cpu->env;
> +    __u64 id;
> +
> +    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
> +    ret = kvm_get_one_reg(cs, id, &isa);
> +    if (ret) {
> +        return ret;
> +    }
> +    env->misa = isa | RVXLEN;
> +
> +    return ret;
>  }
>
>  int kvm_arch_msi_data_to_gsi(uint32_t data)
> --
> 2.19.1
>
>

WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Yifei Jiang <jiangyifei@huawei.com>
Cc: kvm-riscv@lists.infradead.org, Anup Patel <anup.patel@wdc.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"open list:Overall" <kvm@vger.kernel.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	libvir-list@redhat.com,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Bin Meng <bin.meng@windriver.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	yinyipeng <yinyipeng1@huawei.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	fanliang@huawei.com, "Wubin \(H\)" <wu.wubin@huawei.com>,
	Zhanghailiang <zhang.zhanghailiang@huawei.com>
Subject: Re: [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu
Date: Thu, 15 Apr 2021 08:32:09 +1000	[thread overview]
Message-ID: <CAKmqyKN-eiDw3Ufo1QyLg5ELP-JY+aq3Bi1cPJVf8gQtsu+qkw@mail.gmail.com> (raw)
In-Reply-To: <20210412065246.1853-4-jiangyifei@huawei.com>

On Mon, Apr 12, 2021 at 4:53 PM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Get isa info from kvm while kvm init.
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
> ---
>  target/riscv/kvm.c | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
> index 687dd4b621..0d924be33f 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -38,6 +38,18 @@
>  #include "qemu/log.h"
>  #include "hw/loader.h"
>
> +static __u64 kvm_riscv_reg_id(CPURISCVState *env, __u64 type, __u64 idx)
> +{
> +    __u64 id = KVM_REG_RISCV | type | idx;

Can you use uint64_t instead of __u64?

Once that is fixed:

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> +
> +    if (riscv_cpu_is_32bit(env)) {
> +        id |= KVM_REG_SIZE_U32;
> +    } else {
> +        id |= KVM_REG_SIZE_U64;
> +    }
> +    return id;
> +}
> +
>  const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
>      KVM_CAP_LAST_INFO
>  };
> @@ -79,7 +91,20 @@ void kvm_arch_init_irq_routing(KVMState *s)
>
>  int kvm_arch_init_vcpu(CPUState *cs)
>  {
> -    return 0;
> +    int ret = 0;
> +    target_ulong isa;
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +    CPURISCVState *env = &cpu->env;
> +    __u64 id;
> +
> +    id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
> +    ret = kvm_get_one_reg(cs, id, &isa);
> +    if (ret) {
> +        return ret;
> +    }
> +    env->misa = isa | RVXLEN;
> +
> +    return ret;
>  }
>
>  int kvm_arch_msi_data_to_gsi(uint32_t data)
> --
> 2.19.1
>
>


  reply	other threads:[~2021-04-14 22:32 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-12  6:52 [PATCH RFC v5 00/12] Add riscv kvm accel support Yifei Jiang
2021-04-12  6:52 ` Yifei Jiang
2021-04-12  6:52 ` [PATCH RFC v5 01/12] linux-header: Update linux/kvm.h Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-12  6:52 ` [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-12  6:52 ` [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-14 22:32   ` Alistair Francis [this message]
2021-04-14 22:32     ` Alistair Francis
2021-04-12  6:52 ` [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-14 22:39   ` Alistair Francis
2021-04-14 22:39     ` Alistair Francis
2021-04-12  6:52 ` [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-14 22:46   ` Alistair Francis
2021-04-14 22:46     ` Alistair Francis
2021-04-12  6:52 ` [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-14 22:48   ` Alistair Francis
2021-04-14 22:48     ` Alistair Francis
2021-04-12  6:52 ` [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-14 22:50   ` Alistair Francis
2021-04-14 22:50     ` Alistair Francis
2021-04-30  4:53   ` Anup Patel
2021-04-30  4:53     ` Anup Patel
2021-05-06  7:59     ` Jiangyifei
2021-05-06  7:59       ` Jiangyifei
2021-04-12  6:52 ` [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-12  6:52 ` [PATCH RFC v5 09/12] target/riscv: Add host cpu type Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-14 22:33   ` Alistair Francis
2021-04-14 22:33     ` Alistair Francis
2021-04-12  6:52 ` [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-12  6:52 ` [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang
2021-04-12  6:52 ` [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization Yifei Jiang
2021-04-12  6:52   ` Yifei Jiang

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