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From: Alistair Francis <alistair23@gmail.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	 Bin Meng <bin.meng@windriver.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	 Frank Chang <frank.chang@sifive.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool
Date: Tue, 24 Jan 2023 10:02:29 +1000	[thread overview]
Message-ID: <CAKmqyKN-w7tXj7kenvsTir3tn2-96Vtb6gFYECcBbWddxhgd+w@mail.gmail.com> (raw)
In-Reply-To: <20230123090324.732681-3-alexghiti@rivosinc.com>

On Mon, Jan 23, 2023 at 7:06 PM Alexandre Ghiti <alexghiti@rivosinc.com> wrote:
>
> This array is actually used as a boolean so swap its current char type
> to a boolean and at the same time, change the type of validate_vm to
> bool since it returns valid_vm_1_10_[32|64].
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 21 +++++++++++----------
>  1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 0db2c233e5..6b157806a5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP;
>  static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
>  static const target_ulong vsip_writable_mask = MIP_VSSIP;
>
> -static const char valid_vm_1_10_32[16] = {
> -    [VM_1_10_MBARE] = 1,
> -    [VM_1_10_SV32] = 1
> +static const bool valid_vm_1_10_32[16] = {
> +    [VM_1_10_MBARE] = true,
> +    [VM_1_10_SV32] = true
>  };
>
> -static const char valid_vm_1_10_64[16] = {
> -    [VM_1_10_MBARE] = 1,
> -    [VM_1_10_SV39] = 1,
> -    [VM_1_10_SV48] = 1,
> -    [VM_1_10_SV57] = 1
> +static const bool valid_vm_1_10_64[16] = {
> +    [VM_1_10_MBARE] = true,
> +    [VM_1_10_SV39] = true,
> +    [VM_1_10_SV48] = true,
> +    [VM_1_10_SV57] = true
>  };
>
>  /* Machine Information Registers */
> @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
>      return RISCV_EXCP_NONE;
>  }
>
> -static int validate_vm(CPURISCVState *env, target_ulong vm)
> +static bool validate_vm(CPURISCVState *env, target_ulong vm)
>  {
>      if (riscv_cpu_mxl(env) == MXL_RV32) {
>          return valid_vm_1_10_32[vm & 0xf];
> @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
>  static RISCVException write_satp(CPURISCVState *env, int csrno,
>                                   target_ulong val)
>  {
> -    target_ulong vm, mask;
> +    target_ulong mask;
> +    bool vm;
>
>      if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
>          return RISCV_EXCP_NONE;
> --
> 2.37.2
>
>


  parent reply	other threads:[~2023-01-24  0:06 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-23  9:03 [PATCH v6 0/5] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-01-23  9:03 ` [PATCH v6 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Alexandre Ghiti
2023-01-23  9:03 ` [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Alexandre Ghiti
2023-01-23  9:48   ` Andrew Jones
2023-01-24  0:02   ` Alistair Francis [this message]
2023-01-23  9:03 ` [PATCH v6 3/5] riscv: Allow user to set the satp mode Alexandre Ghiti
2023-01-23 10:11   ` Andrew Jones
2023-01-24  9:56     ` Alexandre Ghiti
2023-01-23 10:14   ` Andrew Jones
2023-01-24  9:56     ` Alexandre Ghiti
2023-01-23 10:29   ` Andrew Jones
2023-01-24 10:00     ` Alexandre Ghiti
2023-01-23  9:03 ` [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type' Alexandre Ghiti
2023-01-23 10:12   ` Andrew Jones
2023-01-24  0:35   ` Alistair Francis
2023-01-23  9:03 ` [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Alexandre Ghiti
2023-01-23 10:51   ` Andrew Jones
2023-01-23 11:15     ` Alexandre Ghiti
2023-01-23 13:31       ` Andrew Jones
2023-01-24 13:13         ` Alexandre Ghiti
2023-01-24 10:07     ` Alexandre Ghiti
2023-01-24 15:31       ` Andrew Jones
2023-01-23 13:51   ` Andrew Jones
2023-01-24 13:24     ` Alexandre Ghiti
2023-01-24  0:41   ` Alistair Francis
2023-01-24  9:13     ` Alexandre Ghiti

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