* [PATCH] target/riscv: fix a typo with interrupt names
@ 2021-04-21 13:32 ` Emmanuel Blot
0 siblings, 0 replies; 3+ messages in thread
From: Emmanuel Blot @ 2021-04-21 13:32 UTC (permalink / raw)
Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
open list:All patches CC here, Alistair Francis, Emmanuel Blot,
Palmer Dabbelt
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b6..c79503ce967 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
"vs_timer",
"m_timer",
"u_external",
+ "s_external",
"vs_external",
- "h_external",
"m_external",
"reserved",
"reserved",
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] target/riscv: fix a typo with interrupt names
@ 2021-04-21 13:32 ` Emmanuel Blot
0 siblings, 0 replies; 3+ messages in thread
From: Emmanuel Blot @ 2021-04-21 13:32 UTC (permalink / raw)
Cc: Emmanuel Blot, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, open list:RISC-V TCG CPUs,
open list:All patches CC here
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.
Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d6ed80f6b6..c79503ce967 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
"vs_timer",
"m_timer",
"u_external",
+ "s_external",
"vs_external",
- "h_external",
"m_external",
"reserved",
"reserved",
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] target/riscv: fix a typo with interrupt names
2021-04-21 13:32 ` Emmanuel Blot
(?)
@ 2021-04-22 0:24 ` Alistair Francis
-1 siblings, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2021-04-22 0:24 UTC (permalink / raw)
To: Emmanuel Blot
Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
open list:All patches CC here, Alistair Francis, Palmer Dabbelt
On Wed, Apr 21, 2021 at 11:33 PM Emmanuel Blot <emmanuel.blot@sifive.com> wrote:
>
> Interrupt names have been swapped in 205377f8 and do not follow
> IRQ_*_EXT definition order.
>
> Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 7d6ed80f6b6..c79503ce967 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
> "vs_timer",
> "m_timer",
> "u_external",
> + "s_external",
> "vs_external",
> - "h_external",
> "m_external",
> "reserved",
> "reserved",
> --
> 2.31.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-04-22 0:26 UTC | newest]
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2021-04-21 13:32 [PATCH] target/riscv: fix a typo with interrupt names Emmanuel Blot
2021-04-21 13:32 ` Emmanuel Blot
2021-04-22 0:24 ` Alistair Francis
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