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From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Atish Patra <atish.patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 3/3] hw/riscv/spike: Allow more than one CPUs
Date: Fri, 14 Feb 2020 12:42:55 -0800	[thread overview]
Message-ID: <CAKmqyKNGEp7vzihmG6m3uTsWL2sL+eD6UaTaO8iro3PDvmwMTQ@mail.gmail.com> (raw)
In-Reply-To: <20200214072127.64330-4-anup.patel@wdc.com>

On Thu, Feb 13, 2020 at 11:24 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> Currently, the upstream Spike ISA simulator allows more than
> one CPUs so we update QEMU Spike machine on similar lines to
> allow more than one CPUs.
>
> The maximum number of CPUs for QEMU Spike machine is kept
> same as QEMU Virt machine.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/spike.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 060a86f922..1eac0d9a83 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -469,7 +469,7 @@ static void spike_machine_init(MachineClass *mc)
>  {
>      mc->desc = "RISC-V Spike Board";
>      mc->init = spike_board_init;
> -    mc->max_cpus = 1;
> +    mc->max_cpus = 8;
>      mc->is_default = 1;
>      mc->default_cpu_type = SPIKE_V1_10_0_CPU;
>  }
> --
> 2.17.1
>
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	 Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	 Atish Patra <atish.patra@wdc.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH 3/3] hw/riscv/spike: Allow more than one CPUs
Date: Fri, 14 Feb 2020 12:42:55 -0800	[thread overview]
Message-ID: <CAKmqyKNGEp7vzihmG6m3uTsWL2sL+eD6UaTaO8iro3PDvmwMTQ@mail.gmail.com> (raw)
In-Reply-To: <20200214072127.64330-4-anup.patel@wdc.com>

On Thu, Feb 13, 2020 at 11:24 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> Currently, the upstream Spike ISA simulator allows more than
> one CPUs so we update QEMU Spike machine on similar lines to
> allow more than one CPUs.
>
> The maximum number of CPUs for QEMU Spike machine is kept
> same as QEMU Virt machine.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/spike.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 060a86f922..1eac0d9a83 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -469,7 +469,7 @@ static void spike_machine_init(MachineClass *mc)
>  {
>      mc->desc = "RISC-V Spike Board";
>      mc->init = spike_board_init;
> -    mc->max_cpus = 1;
> +    mc->max_cpus = 8;
>      mc->is_default = 1;
>      mc->default_cpu_type = SPIKE_V1_10_0_CPU;
>  }
> --
> 2.17.1
>
>


  reply	other threads:[~2020-02-14 20:51 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14  7:21 [PATCH 0/3] RISC-V Spike machine improvements Anup Patel
2020-02-14  7:21 ` Anup Patel
2020-02-14  7:21 ` [PATCH 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() Anup Patel
2020-02-14  7:21   ` Anup Patel
2020-02-21 19:48   ` Alistair Francis
2020-02-21 19:48     ` Alistair Francis
2020-02-14  7:21 ` [PATCH 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option Anup Patel
2020-02-14  7:21   ` Anup Patel
2020-02-21 19:49   ` Alistair Francis
2020-02-21 19:49     ` Alistair Francis
2020-02-14  7:21 ` [PATCH 3/3] hw/riscv/spike: Allow more than one CPUs Anup Patel
2020-02-14  7:21   ` Anup Patel
2020-02-14 20:42   ` Alistair Francis [this message]
2020-02-14 20:42     ` Alistair Francis

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