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From: Alistair Francis <alistair23@gmail.com>
To: Jose Martins <josemartins90@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/riscv: fix check of guest pa top bits
Date: Thu, 30 Apr 2020 12:45:45 -0700	[thread overview]
Message-ID: <CAKmqyKNMiD6VJ1D-ty-q_HMyiZ7oj7F0XraKTaYy78-xjhAN4A@mail.gmail.com> (raw)
In-Reply-To: <CAC41xo2LfTQZnor5haAgBg=h34qv50xf8Bs1bgSeGESfr-E2ng@mail.gmail.com>

On Fri, Apr 24, 2020 at 8:10 AM Jose Martins <josemartins90@gmail.com> wrote:
>
> The spec states that on sv39x4 guest physical  "address bits 63:41
> must all be zeros, or else a guest-page-fault exception occurs.".
> However, the check performed for these top bits of the virtual address
> on the second stage is the same as the one performed for virtual
> addresses on the first stage except with the 2-bit extension,
> effectively creating the same kind of "hole" in the guest's physical
> address space. I believe the following patch fixes this issue:
>
> Signed-off-by: Jose Martins <josemartins90@gmail.com>

Thanks for the patch.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

> ---
>  target/riscv/cpu_helper.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d3ba9efb02..da879f5656 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -421,15 +421,21 @@ static int get_physical_address(CPURISCVState
> *env, hwaddr *physical,

There seems to be a strange wrapping here, that corrupts the patch.
For future patches can you please check your git send-email setup?

Applied to the RISC-V tree with the above line fixed up.

Alistair

>      int va_bits = PGSHIFT + levels * ptidxbits + widened;
>      target_ulong mask, masked_msbs;
>
> -    if (TARGET_LONG_BITS > (va_bits - 1)) {
> -        mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
> +    if(!first_stage){
> +        if ((addr >> va_bits) != 0) {
> +            return TRANSLATE_FAIL;
> +        }
>      } else {
> -        mask = 0;
> -    }
> -    masked_msbs = (addr >> (va_bits - 1)) & mask;
> +        if (TARGET_LONG_BITS > (va_bits - 1)) {
> +            mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
> +        } else {
> +            mask = 0;
> +        }
> +        masked_msbs = (addr >> (va_bits - 1)) & mask;
>
> -    if (masked_msbs != 0 && masked_msbs != mask) {
> -        return TRANSLATE_FAIL;
> +        if (masked_msbs != 0 && masked_msbs != mask) {
> +            return TRANSLATE_FAIL;
> +        }
>      }
>
>      int ptshift = (levels - 1) * ptidxbits;
> --
> 2.17.1
>
> Jose
>


WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Jose Martins <josemartins90@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/riscv: fix check of guest pa top bits
Date: Thu, 30 Apr 2020 12:45:45 -0700	[thread overview]
Message-ID: <CAKmqyKNMiD6VJ1D-ty-q_HMyiZ7oj7F0XraKTaYy78-xjhAN4A@mail.gmail.com> (raw)
In-Reply-To: <CAC41xo2LfTQZnor5haAgBg=h34qv50xf8Bs1bgSeGESfr-E2ng@mail.gmail.com>

On Fri, Apr 24, 2020 at 8:10 AM Jose Martins <josemartins90@gmail.com> wrote:
>
> The spec states that on sv39x4 guest physical  "address bits 63:41
> must all be zeros, or else a guest-page-fault exception occurs.".
> However, the check performed for these top bits of the virtual address
> on the second stage is the same as the one performed for virtual
> addresses on the first stage except with the 2-bit extension,
> effectively creating the same kind of "hole" in the guest's physical
> address space. I believe the following patch fixes this issue:
>
> Signed-off-by: Jose Martins <josemartins90@gmail.com>

Thanks for the patch.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

> ---
>  target/riscv/cpu_helper.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index d3ba9efb02..da879f5656 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -421,15 +421,21 @@ static int get_physical_address(CPURISCVState
> *env, hwaddr *physical,

There seems to be a strange wrapping here, that corrupts the patch.
For future patches can you please check your git send-email setup?

Applied to the RISC-V tree with the above line fixed up.

Alistair

>      int va_bits = PGSHIFT + levels * ptidxbits + widened;
>      target_ulong mask, masked_msbs;
>
> -    if (TARGET_LONG_BITS > (va_bits - 1)) {
> -        mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
> +    if(!first_stage){
> +        if ((addr >> va_bits) != 0) {
> +            return TRANSLATE_FAIL;
> +        }
>      } else {
> -        mask = 0;
> -    }
> -    masked_msbs = (addr >> (va_bits - 1)) & mask;
> +        if (TARGET_LONG_BITS > (va_bits - 1)) {
> +            mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1;
> +        } else {
> +            mask = 0;
> +        }
> +        masked_msbs = (addr >> (va_bits - 1)) & mask;
>
> -    if (masked_msbs != 0 && masked_msbs != mask) {
> -        return TRANSLATE_FAIL;
> +        if (masked_msbs != 0 && masked_msbs != mask) {
> +            return TRANSLATE_FAIL;
> +        }
>      }
>
>      int ptshift = (levels - 1) * ptidxbits;
> --
> 2.17.1
>
> Jose
>


  reply	other threads:[~2020-04-30 20:00 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-24 15:09 [PATCH] target/riscv: fix check of guest pa top bits Jose Martins
2020-04-24 15:09 ` Jose Martins
2020-04-30 19:45 ` Alistair Francis [this message]
2020-04-30 19:45   ` Alistair Francis
2020-04-30 21:28   ` Alistair Francis
2020-04-30 21:28     ` Alistair Francis
2020-05-01 18:54     ` Jose Martins
2020-05-01 18:54       ` Jose Martins
2020-05-01 19:14       ` Jonathan Behrens

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