* [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
This series updates the experimental QEMU RISC-V Hypervisor spec to the
v0.6.1 draft implementation.
THis includes support for the new 2-stage lookup instructions and the new
CSRs.
It also includes the new 0.6.1 support for the virtual instruction
fault.
This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
Linux guests.
v3:
- Rebase on master
v2:
- Update to v0.6.1
Alistair Francis (13):
target/riscv: Allow setting a two-stage lookup in the virt status
target/riscv: Allow generating hlv/hlvx/hsv instructions
target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
target/riscv: Don't allow guest to write to htinst
target/riscv: Convert MSTATUS MTL to GVA
target/riscv: Fix the interrupt cause code
target/riscv: Update the Hypervisor trap return/entry
target/riscv: Update the CSRs to the v0.6 Hyp extension
target/riscv: Only support a single VSXL length
target/riscv: Only support little endian guests
target/riscv: Support the v0.6 Hypervisor extension CRSs
target/riscv: Return the exception from invalid CSR accesses
target/riscv: Support the Virtual Instruction fault
target/riscv/cpu.h | 2 +
target/riscv/cpu_bits.h | 25 +-
target/riscv/helper.h | 4 +
target/riscv/insn32-64.decode | 5 +
target/riscv/insn32.decode | 11 +
target/riscv/cpu_helper.c | 123 +++++----
target/riscv/csr.c | 171 ++++++++++--
target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
target/riscv/op_helper.c | 176 +++++++++++-
target/riscv/translate.c | 10 -
10 files changed, 761 insertions(+), 108 deletions(-)
--
2.27.0
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH v3 01/13] target/riscv: Allow setting a two-stage lookup in the virt status
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 21 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a804a5d0ba..383808bf88 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -321,6 +321,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8117e8b5a7..ba0a5b50ff 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -467,6 +467,7 @@
* page table fault.
*/
#define FORCE_HS_EXCEP 2
+#define HS_TWO_STAGE 4
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..68abccc993 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, HS_TWO_STAGE);
+}
+
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 01/13] target/riscv: Allow setting a two-stage lookup in the virt status
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 21 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a804a5d0ba..383808bf88 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -321,6 +321,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8117e8b5a7..ba0a5b50ff 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -467,6 +467,7 @@
* page table fault.
*/
#define FORCE_HS_EXCEP 2
+#define HS_TWO_STAGE 4
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..68abccc993 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable)
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, HS_TWO_STAGE);
+}
+
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/helper.h | 3 +
target/riscv/insn32-64.decode | 5 +
target/riscv/insn32.decode | 11 +
target/riscv/insn_trans/trans_rvh.inc.c | 340 ++++++++++++++++++++++++
target/riscv/op_helper.c | 114 ++++++++
6 files changed, 474 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ba0a5b50ff..7abae4267f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -443,6 +443,7 @@
#define HSTATUS_SP2V 0x00000200
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
+#define HSTATUS_HU 0x00000200
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index acc298219d..c8029d83f9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -80,6 +80,9 @@ DEF_HELPER_1(tlb_flush, void, env)
/* Hypervisor functions */
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
+DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
+DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
#endif
/* Vector functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 86153d93fa..8157dee8b7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -81,3 +81,8 @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV32H Base Instruction Set ***
+hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
+hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
+hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bdd8563067..84080dd18c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -78,6 +78,7 @@
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -223,6 +224,16 @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
# *** RV32H Base Instruction Set ***
+hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
+hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
+hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
+hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
+hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
+hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
+hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
+hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
+hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
+hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
index 263b652d90..db650ae62a 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -16,6 +16,346 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_SB);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESW);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESL);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_UB);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUW);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_SB);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESW);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESL);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUL);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEQ);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEQ);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+#endif
+
+static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUW);
+
+ gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUL);
+
+ gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
REQUIRE_EXT(ctx, RVH);
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 7cccd42a1e..3d306c343c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -207,4 +207,118 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
+ target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ target_ulong pte;
+
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_SB:
+ pte = cpu_ldsb_data_ra(env, address, GETPC());
+ break;
+ case MO_UB:
+ pte = cpu_ldub_data_ra(env, address, GETPC());
+ break;
+ case MO_TESW:
+ pte = cpu_ldsw_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUW:
+ pte = cpu_lduw_data_ra(env, address, GETPC());
+ break;
+ case MO_TESL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
+ case MO_TEQ:
+ pte = cpu_ldq_data_ra(env, address, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return pte;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ return 0;
+}
+
+void helper_hyp_store(CPURISCVState *env, target_ulong address,
+ target_ulong val, target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_SB:
+ case MO_UB:
+ cpu_stb_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TESW:
+ case MO_TEUW:
+ cpu_stw_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TESL:
+ case MO_TEUL:
+ cpu_stl_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TEQ:
+ cpu_stq_data_ra(env, address, val, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
+target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
+ target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ target_ulong pte;
+
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_TEUL:
+ pte = cpu_ldub_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUW:
+ pte = cpu_lduw_data_ra(env, address, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return pte;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ return 0;
+}
+
#endif /* !CONFIG_USER_ONLY */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 02/13] target/riscv: Allow generating hlv/hlvx/hsv instructions
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/helper.h | 3 +
target/riscv/insn32-64.decode | 5 +
target/riscv/insn32.decode | 11 +
target/riscv/insn_trans/trans_rvh.inc.c | 340 ++++++++++++++++++++++++
target/riscv/op_helper.c | 114 ++++++++
6 files changed, 474 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ba0a5b50ff..7abae4267f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -443,6 +443,7 @@
#define HSTATUS_SP2V 0x00000200
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
+#define HSTATUS_HU 0x00000200
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index acc298219d..c8029d83f9 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -80,6 +80,9 @@ DEF_HELPER_1(tlb_flush, void, env)
/* Hypervisor functions */
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
+DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
+DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
#endif
/* Vector functions */
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 86153d93fa..8157dee8b7 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -81,3 +81,8 @@ fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
+
+# *** RV32H Base Instruction Set ***
+hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
+hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
+hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index bdd8563067..84080dd18c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -78,6 +78,7 @@
@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
+@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -223,6 +224,16 @@ fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
# *** RV32H Base Instruction Set ***
+hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
+hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
+hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
+hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
+hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
+hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
+hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
+hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
+hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
+hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
index 263b652d90..db650ae62a 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -16,6 +16,346 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_SB);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESW);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESL);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_bu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_UB);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_hu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUW);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_SB);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESW);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TESL);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_wu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUL);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEQ);
+
+ gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv dat = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ gen_get_gpr(dat, a->rs2);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEQ);
+
+ gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(dat);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+#endif
+
+static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx_hu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUW);
+
+ gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
+static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx_wu *a)
+{
+ REQUIRE_EXT(ctx, RVH);
+#ifndef CONFIG_USER_ONLY
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv mem_idx = tcg_temp_new();
+ TCGv memop = tcg_temp_new();
+
+ gen_get_gpr(t0, a->rs1);
+ tcg_gen_movi_tl(mem_idx, ctx->mem_idx);
+ tcg_gen_movi_tl(memop, MO_TEUL);
+
+ gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop);
+ gen_set_gpr(a->rd, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(mem_idx);
+ tcg_temp_free(memop);
+ return true;
+#else
+ return false;
+#endif
+}
+
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
REQUIRE_EXT(ctx, RVH);
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 7cccd42a1e..3d306c343c 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -207,4 +207,118 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
+ target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ target_ulong pte;
+
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_SB:
+ pte = cpu_ldsb_data_ra(env, address, GETPC());
+ break;
+ case MO_UB:
+ pte = cpu_ldub_data_ra(env, address, GETPC());
+ break;
+ case MO_TESW:
+ pte = cpu_ldsw_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUW:
+ pte = cpu_lduw_data_ra(env, address, GETPC());
+ break;
+ case MO_TESL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
+ case MO_TEQ:
+ pte = cpu_ldq_data_ra(env, address, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return pte;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ return 0;
+}
+
+void helper_hyp_store(CPURISCVState *env, target_ulong address,
+ target_ulong val, target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_SB:
+ case MO_UB:
+ cpu_stb_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TESW:
+ case MO_TEUW:
+ cpu_stw_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TESL:
+ case MO_TEUL:
+ cpu_stl_data_ra(env, address, val, GETPC());
+ break;
+ case MO_TEQ:
+ cpu_stq_data_ra(env, address, val, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+}
+
+target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
+ target_ulong attrs, target_ulong memop)
+{
+ if (env->priv == PRV_M ||
+ (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
+ (env->priv == PRV_U && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_HU))) {
+ target_ulong pte;
+
+ riscv_cpu_set_two_stage_lookup(env, true);
+
+ switch (memop) {
+ case MO_TEUL:
+ pte = cpu_ldub_data_ra(env, address, GETPC());
+ break;
+ case MO_TEUW:
+ pte = cpu_lduw_data_ra(env, address, GETPC());
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ riscv_cpu_set_two_stage_lookup(env, false);
+
+ return pte;
+ }
+
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ return 0;
+}
+
#endif /* !CONFIG_USER_ONLY */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 60 ++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 68abccc993..10c9f8b63b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
+ if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
+ use_background = true;
+ }
+
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
-
- if (riscv_has_ext(env, RVH) &&
- MSTATUS_MPV_ISSET(env)) {
- use_background = true;
- }
- }
- }
-
- if (mode == PRV_S && access_type != MMU_INST_FETCH &&
- riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
- if (get_field(env->hstatus, HSTATUS_SPRV)) {
- mode = get_field(env->mstatus, SSTATUS_SPP);
- use_background = true;
}
}
@@ -607,7 +598,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
}
break;
case MMU_DATA_LOAD:
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+ !first_stage) {
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@@ -615,7 +607,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
}
break;
case MMU_DATA_STORE:
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+ !first_stage) {
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@@ -705,8 +698,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
hwaddr pa = 0;
int prot, prot2;
bool pmp_violation = false;
- bool m_mode_two_stage = false;
- bool hs_mode_two_stage = false;
bool first_stage_error = true;
int ret = TRANSLATE_FAIL;
int mode = mmu_idx;
@@ -716,30 +707,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- /*
- * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
- * set and we want to access a virtulisation address.
- */
- if (riscv_has_ext(env, RVH)) {
- m_mode_two_stage = env->priv == PRV_M &&
- access_type != MMU_INST_FETCH &&
- get_field(env->mstatus, MSTATUS_MPRV) &&
- MSTATUS_MPV_ISSET(env);
-
- hs_mode_two_stage = env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env) &&
- access_type != MMU_INST_FETCH &&
- get_field(env->hstatus, HSTATUS_SPRV) &&
- get_field(env->hstatus, HSTATUS_SPV);
- }
-
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
- if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, true);
+ }
+
+ if (riscv_cpu_virt_enabled(env) ||
+ (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address, access_type,
mmu_idx, true, true);
@@ -791,6 +773,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
__func__, address, ret, pa, prot);
}
+ /* We did the two stage lookup based on MPRV, unset the lookup */
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, false);
+ }
+
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 03/13] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 60 ++++++++++++++++-----------------------
1 file changed, 25 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 68abccc993..10c9f8b63b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -340,22 +340,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
+ if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
+ use_background = true;
+ }
+
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
-
- if (riscv_has_ext(env, RVH) &&
- MSTATUS_MPV_ISSET(env)) {
- use_background = true;
- }
- }
- }
-
- if (mode == PRV_S && access_type != MMU_INST_FETCH &&
- riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
- if (get_field(env->hstatus, HSTATUS_SPRV)) {
- mode = get_field(env->mstatus, SSTATUS_SPP);
- use_background = true;
}
}
@@ -607,7 +598,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
}
break;
case MMU_DATA_LOAD:
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+ !first_stage) {
cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@@ -615,7 +607,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
}
break;
case MMU_DATA_STORE:
- if (riscv_cpu_virt_enabled(env) && !first_stage) {
+ if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
+ !first_stage) {
cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
} else {
cs->exception_index = page_fault_exceptions ?
@@ -705,8 +698,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
hwaddr pa = 0;
int prot, prot2;
bool pmp_violation = false;
- bool m_mode_two_stage = false;
- bool hs_mode_two_stage = false;
bool first_stage_error = true;
int ret = TRANSLATE_FAIL;
int mode = mmu_idx;
@@ -716,30 +707,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- /*
- * Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
- * set and we want to access a virtulisation address.
- */
- if (riscv_has_ext(env, RVH)) {
- m_mode_two_stage = env->priv == PRV_M &&
- access_type != MMU_INST_FETCH &&
- get_field(env->mstatus, MSTATUS_MPRV) &&
- MSTATUS_MPV_ISSET(env);
-
- hs_mode_two_stage = env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env) &&
- access_type != MMU_INST_FETCH &&
- get_field(env->hstatus, HSTATUS_SPRV) &&
- get_field(env->hstatus, HSTATUS_SPV);
- }
-
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
mode = get_field(env->mstatus, MSTATUS_MPP);
}
}
- if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, true);
+ }
+
+ if (riscv_cpu_virt_enabled(env) ||
+ (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address, access_type,
mmu_idx, true, true);
@@ -791,6 +773,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
__func__, address, ret, pa, prot);
}
+ /* We did the two stage lookup based on MPRV, unset the lookup */
+ if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
+ access_type != MMU_INST_FETCH &&
+ get_field(env->mstatus, MSTATUS_MPRV) &&
+ MSTATUS_MPV_ISSET(env)) {
+ riscv_cpu_set_two_stage_lookup(env, false);
+ }
+
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
(ret == TRANSLATE_SUCCESS) &&
!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6a96a01b1c..0f035d33b1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -922,7 +922,6 @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
{
- env->htinst = val;
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 04/13] target/riscv: Don't allow guest to write to htinst
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6a96a01b1c..0f035d33b1 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -922,7 +922,6 @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
{
- env->htinst = val;
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 5 +++--
target/riscv/cpu_helper.c | 24 ++++++++++++++++++++----
target/riscv/csr.c | 6 +++---
3 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7abae4267f..43617e7c1f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -379,10 +379,10 @@
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
#if defined(TARGET_RISCV64)
-#define MSTATUS_MTL 0x4000000000ULL
+#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
#elif defined(TARGET_RISCV32)
-#define MSTATUS_MTL 0x00000040
+#define MSTATUS_GVA 0x00000040
#define MSTATUS_MPV 0x00000080
#endif
@@ -444,6 +444,7 @@
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HU 0x00000200
+#define HSTATUS_GVA 0x00000040
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10c9f8b63b..b5f4264525 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -894,6 +894,19 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+ if ((riscv_cpu_virt_enabled(env) ||
+ riscv_cpu_two_stage_lookup(env)) && tval) {
+ /*
+ * If we are writing a guest virtual address to stval, set
+ * this to 1. If we are trapping to VS we will set this to 0
+ * later.
+ */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1);
+ } else {
+ /* For other HS-mode traps, we set this to 0. */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
+ }
+
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
/*
@@ -904,6 +917,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
cause == IRQ_VS_EXT)
cause = cause - 1;
/* Trap to VS mode */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
@@ -952,13 +966,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
#ifdef TARGET_RISCV32
env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
- env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
- riscv_cpu_force_hs_excep_enabled(env));
+ if (riscv_cpu_virt_enabled(env) && tval) {
+ env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
+ }
#else
env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
- env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
- riscv_cpu_force_hs_excep_enabled(env));
+ if (riscv_cpu_virt_enabled(env) && tval) {
+ env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
+ }
#endif
mtval2 = env->guest_phys_fault_addr;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0f035d33b1..f9ac21d687 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -403,10 +403,10 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
MSTATUS_TW;
#if defined(TARGET_RISCV64)
/*
- * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MTL | MSTATUS_MPV;
+ mask |= MSTATUS_MPV | MSTATUS_GVA;
#endif
mstatus = (mstatus & ~mask) | (val & mask);
@@ -432,7 +432,7 @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
tlb_flush(env_cpu(env));
}
- val &= MSTATUS_MPV | MSTATUS_MTL;
+ val &= MSTATUS_MPV | MSTATUS_GVA;
env->mstatush = val;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 05/13] target/riscv: Convert MSTATUS MTL to GVA
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 5 +++--
target/riscv/cpu_helper.c | 24 ++++++++++++++++++++----
target/riscv/csr.c | 6 +++---
3 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7abae4267f..43617e7c1f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -379,10 +379,10 @@
#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
#if defined(TARGET_RISCV64)
-#define MSTATUS_MTL 0x4000000000ULL
+#define MSTATUS_GVA 0x4000000000ULL
#define MSTATUS_MPV 0x8000000000ULL
#elif defined(TARGET_RISCV32)
-#define MSTATUS_MTL 0x00000040
+#define MSTATUS_GVA 0x00000040
#define MSTATUS_MPV 0x00000080
#endif
@@ -444,6 +444,7 @@
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HU 0x00000200
+#define HSTATUS_GVA 0x00000040
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 10c9f8b63b..b5f4264525 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -894,6 +894,19 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_has_ext(env, RVH)) {
target_ulong hdeleg = async ? env->hideleg : env->hedeleg;
+ if ((riscv_cpu_virt_enabled(env) ||
+ riscv_cpu_two_stage_lookup(env)) && tval) {
+ /*
+ * If we are writing a guest virtual address to stval, set
+ * this to 1. If we are trapping to VS we will set this to 0
+ * later.
+ */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 1);
+ } else {
+ /* For other HS-mode traps, we set this to 0. */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
+ }
+
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
/*
@@ -904,6 +917,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
cause == IRQ_VS_EXT)
cause = cause - 1;
/* Trap to VS mode */
+ env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
@@ -952,13 +966,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
#ifdef TARGET_RISCV32
env->mstatush = set_field(env->mstatush, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
- env->mstatush = set_field(env->mstatush, MSTATUS_MTL,
- riscv_cpu_force_hs_excep_enabled(env));
+ if (riscv_cpu_virt_enabled(env) && tval) {
+ env->mstatush = set_field(env->mstatush, MSTATUS_GVA, 1);
+ }
#else
env->mstatus = set_field(env->mstatus, MSTATUS_MPV,
riscv_cpu_virt_enabled(env));
- env->mstatus = set_field(env->mstatus, MSTATUS_MTL,
- riscv_cpu_force_hs_excep_enabled(env));
+ if (riscv_cpu_virt_enabled(env) && tval) {
+ env->mstatus = set_field(env->mstatus, MSTATUS_GVA, 1);
+ }
#endif
mtval2 = env->guest_phys_fault_addr;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 0f035d33b1..f9ac21d687 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -403,10 +403,10 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
MSTATUS_TW;
#if defined(TARGET_RISCV64)
/*
- * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
- mask |= MSTATUS_MTL | MSTATUS_MPV;
+ mask |= MSTATUS_MPV | MSTATUS_GVA;
#endif
mstatus = (mstatus & ~mask) | (val & mask);
@@ -432,7 +432,7 @@ static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
tlb_flush(env_cpu(env));
}
- val &= MSTATUS_MPV | MSTATUS_MTL;
+ val &= MSTATUS_MPV | MSTATUS_GVA;
env->mstatush = val;
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 06/13] target/riscv: Fix the interrupt cause code
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b5f4264525..9ab3ca4675 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -909,14 +909,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
+ /* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
- cause == IRQ_VS_EXT)
+ cause == IRQ_VS_EXT) {
cause = cause - 1;
- /* Trap to VS mode */
+ }
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 06/13] target/riscv: Fix the interrupt cause code
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b5f4264525..9ab3ca4675 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -909,14 +909,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
+ /* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
- cause == IRQ_VS_EXT)
+ cause == IRQ_VS_EXT) {
cause = cause - 1;
- /* Trap to VS mode */
+ }
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 16 ++++++----------
target/riscv/op_helper.c | 8 ++------
target/riscv/translate.c | 10 ----------
4 files changed, 9 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 43617e7c1f..fb6a3e9092 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -445,6 +445,7 @@
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HU 0x00000200
#define HSTATUS_GVA 0x00000040
+#define HSTATUS_SPVP 0x00000100
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9ab3ca4675..79166875a9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -922,9 +922,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
- get_field(env->hstatus, HSTATUS_SPV));
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
get_field(env->mstatus, SSTATUS_SPP));
env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env));
@@ -935,13 +933,11 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_set_force_hs_excep(env, 0);
} else {
/* Trap into HS mode */
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
- get_field(env->hstatus, HSTATUS_SPV));
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
- get_field(env->mstatus, SSTATUS_SPP));
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
- riscv_cpu_virt_enabled(env));
-
+ if (!riscv_cpu_two_stage_lookup(env)) {
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
+ riscv_cpu_virt_enabled(env));
+ }
+ riscv_cpu_set_two_stage_lookup(env, false);
htval = env->guest_phys_fault_addr;
}
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3d306c343c..4b64bfe7d2 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -97,12 +97,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
prev_priv = get_field(mstatus, MSTATUS_SPP);
prev_virt = get_field(hstatus, HSTATUS_SPV);
- hstatus = set_field(hstatus, HSTATUS_SPV,
- get_field(hstatus, HSTATUS_SP2V));
- mstatus = set_field(mstatus, MSTATUS_SPP,
- get_field(hstatus, HSTATUS_SP2P));
- hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
- hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
+ hstatus = set_field(hstatus, HSTATUS_SPV, 0);
+ mstatus = set_field(mstatus, MSTATUS_SPP, 0);
mstatus = set_field(mstatus, SSTATUS_SIE,
get_field(mstatus, SSTATUS_SPIE));
mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf3..f896412235 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -768,16 +768,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
- if (env->priv_ver == PRV_M &&
- get_field(env->mstatus, MSTATUS_MPRV) &&
- MSTATUS_MPV_ISSET(env)) {
- ctx->virt_enabled = true;
- } else if (env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env) &&
- get_field(env->hstatus, HSTATUS_SPRV) &&
- get_field(env->hstatus, HSTATUS_SPV)) {
- ctx->virt_enabled = true;
- }
} else {
ctx->virt_enabled = false;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 07/13] target/riscv: Update the Hypervisor trap return/entry
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 16 ++++++----------
target/riscv/op_helper.c | 8 ++------
target/riscv/translate.c | 10 ----------
4 files changed, 9 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 43617e7c1f..fb6a3e9092 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -445,6 +445,7 @@
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_HU 0x00000200
#define HSTATUS_GVA 0x00000040
+#define HSTATUS_SPVP 0x00000100
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 9ab3ca4675..79166875a9 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -922,9 +922,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
riscv_cpu_swap_hypervisor_regs(env);
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
- get_field(env->hstatus, HSTATUS_SPV));
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPVP,
get_field(env->mstatus, SSTATUS_SPP));
env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
riscv_cpu_virt_enabled(env));
@@ -935,13 +933,11 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_set_force_hs_excep(env, 0);
} else {
/* Trap into HS mode */
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2V,
- get_field(env->hstatus, HSTATUS_SPV));
- env->hstatus = set_field(env->hstatus, HSTATUS_SP2P,
- get_field(env->mstatus, SSTATUS_SPP));
- env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
- riscv_cpu_virt_enabled(env));
-
+ if (!riscv_cpu_two_stage_lookup(env)) {
+ env->hstatus = set_field(env->hstatus, HSTATUS_SPV,
+ riscv_cpu_virt_enabled(env));
+ }
+ riscv_cpu_set_two_stage_lookup(env, false);
htval = env->guest_phys_fault_addr;
}
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 3d306c343c..4b64bfe7d2 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -97,12 +97,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
prev_priv = get_field(mstatus, MSTATUS_SPP);
prev_virt = get_field(hstatus, HSTATUS_SPV);
- hstatus = set_field(hstatus, HSTATUS_SPV,
- get_field(hstatus, HSTATUS_SP2V));
- mstatus = set_field(mstatus, MSTATUS_SPP,
- get_field(hstatus, HSTATUS_SP2P));
- hstatus = set_field(hstatus, HSTATUS_SP2V, 0);
- hstatus = set_field(hstatus, HSTATUS_SP2P, 0);
+ hstatus = set_field(hstatus, HSTATUS_SPV, 0);
+ mstatus = set_field(mstatus, MSTATUS_SPP, 0);
mstatus = set_field(mstatus, SSTATUS_SIE,
get_field(mstatus, SSTATUS_SPIE));
mstatus = set_field(mstatus, SSTATUS_SPIE, 1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf3..f896412235 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -768,16 +768,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
#if !defined(CONFIG_USER_ONLY)
if (riscv_has_ext(env, RVH)) {
ctx->virt_enabled = riscv_cpu_virt_enabled(env);
- if (env->priv_ver == PRV_M &&
- get_field(env->mstatus, MSTATUS_MPRV) &&
- MSTATUS_MPV_ISSET(env)) {
- ctx->virt_enabled = true;
- } else if (env->priv == PRV_S &&
- !riscv_cpu_virt_enabled(env) &&
- get_field(env->hstatus, HSTATUS_SPRV) &&
- get_field(env->hstatus, HSTATUS_SPV)) {
- ctx->virt_enabled = true;
- }
} else {
ctx->virt_enabled = false;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fb6a3e9092..573d85da41 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -437,15 +437,17 @@
#endif
/* hstatus CSR bits */
-#define HSTATUS_SPRV 0x00000001
+#define HSTATUS_VSBE 0x00000020
+#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPV 0x00000080
-#define HSTATUS_SP2P 0x00000100
-#define HSTATUS_SP2V 0x00000200
+#define HSTATUS_SPVP 0x00000100
+#define HSTATUS_HU 0x00000200
+#define HSTATUS_VGEIN 0x0003F000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
-#define HSTATUS_HU 0x00000200
-#define HSTATUS_GVA 0x00000040
-#define HSTATUS_SPVP 0x00000100
+#if defined(TARGET_RISCV64)
+#define HSTATUS_VSXL 0x300000000
+#endif
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 08/13] target/riscv: Update the CSRs to the v0.6 Hyp extension
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index fb6a3e9092..573d85da41 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -437,15 +437,17 @@
#endif
/* hstatus CSR bits */
-#define HSTATUS_SPRV 0x00000001
+#define HSTATUS_VSBE 0x00000020
+#define HSTATUS_GVA 0x00000040
#define HSTATUS_SPV 0x00000080
-#define HSTATUS_SP2P 0x00000100
-#define HSTATUS_SP2V 0x00000200
+#define HSTATUS_SPVP 0x00000100
+#define HSTATUS_HU 0x00000200
+#define HSTATUS_VGEIN 0x0003F000
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
-#define HSTATUS_HU 0x00000200
-#define HSTATUS_GVA 0x00000040
-#define HSTATUS_SPVP 0x00000100
+#if defined(TARGET_RISCV64)
+#define HSTATUS_VSXL 0x300000000
+#endif
#define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 09/13] target/riscv: Only support a single VSXL length
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f9ac21d687..390ef781e4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -836,12 +836,21 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hstatus;
+#ifdef TARGET_RISCV64
+ /* We only support 64-bit VSXL */
+ *val = set_field(*val, HSTATUS_VSXL, 2);
+#endif
return 0;
}
static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
{
env->hstatus = val;
+#ifdef TARGET_RISCV64
+ if (get_field(val, HSTATUS_VSXL) != 2) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
+ }
+#endif
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 09/13] target/riscv: Only support a single VSXL length
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f9ac21d687..390ef781e4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -836,12 +836,21 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hstatus;
+#ifdef TARGET_RISCV64
+ /* We only support 64-bit VSXL */
+ *val = set_field(*val, HSTATUS_VSXL, 2);
+#endif
return 0;
}
static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
{
env->hstatus = val;
+#ifdef TARGET_RISCV64
+ if (get_field(val, HSTATUS_VSXL) != 2) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
+ }
+#endif
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 10/13] target/riscv: Only support little endian guests
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 390ef781e4..5e50683c58 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -840,6 +840,8 @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
#endif
+ /* We only support little endian */
+ *val = set_field(*val, HSTATUS_VSBE, 0);
return 0;
}
@@ -851,6 +853,9 @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
}
#endif
+ if (get_field(val, HSTATUS_VSBE) != 0) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+ }
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 10/13] target/riscv: Only support little endian guests
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 390ef781e4..5e50683c58 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -840,6 +840,8 @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
#endif
+ /* We only support little endian */
+ *val = set_field(*val, HSTATUS_VSBE, 0);
return 0;
}
@@ -851,6 +853,9 @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
}
#endif
+ if (get_field(val, HSTATUS_VSBE) != 0) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+ }
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 573d85da41..d88e2ea30d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -197,9 +197,12 @@
#define CSR_HIDELEG 0x603
#define CSR_HIE 0x604
#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
#define CSR_HTVAL 0x643
+#define CSR_HVIP 0x645
#define CSR_HIP 0x644
#define CSR_HTINST 0x64A
+#define CSR_HGEIP 0xE12
#define CSR_HGATP 0x680
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e50683c58..7dc50e6299 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -883,12 +883,25 @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret = rmw_mip(env, 0, ret_value, new_value,
+ write_mask & hip_writable_mask);
+
+ *ret_value &= hip_writable_mask;
+
+ return ret;
+}
+
static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask);
+ *ret_value &= hip_writable_mask;
+
return ret;
}
@@ -916,6 +929,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->htval;
@@ -939,6 +964,18 @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hgatp;
@@ -1341,11 +1378,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
[CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
+ [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
[CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
[CSR_HIE] = { hmode, read_hie, write_hie },
[CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
+ [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { hmode, read_htval, write_htval },
[CSR_HTINST] = { hmode, read_htinst, write_htinst },
+ [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
#if defined(TARGET_RISCV32)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 11/13] target/riscv: Support the v0.6 Hypervisor extension CRSs
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 573d85da41..d88e2ea30d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -197,9 +197,12 @@
#define CSR_HIDELEG 0x603
#define CSR_HIE 0x604
#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
#define CSR_HTVAL 0x643
+#define CSR_HVIP 0x645
#define CSR_HIP 0x644
#define CSR_HTINST 0x64A
+#define CSR_HGEIP 0xE12
#define CSR_HGATP 0x680
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e50683c58..7dc50e6299 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -883,12 +883,25 @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
+{
+ int ret = rmw_mip(env, 0, ret_value, new_value,
+ write_mask & hip_writable_mask);
+
+ *ret_value &= hip_writable_mask;
+
+ return ret;
+}
+
static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask);
+ *ret_value &= hip_writable_mask;
+
return ret;
}
@@ -916,6 +929,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->htval;
@@ -939,6 +964,18 @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
+static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
+{
+ qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
+ return 0;
+}
+
static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hgatp;
@@ -1341,11 +1378,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
[CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
+ [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
[CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
[CSR_HIE] = { hmode, read_hie, write_hie },
[CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
+ [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
[CSR_HTVAL] = { hmode, read_htval, write_htval },
[CSR_HTINST] = { hmode, read_htinst, write_htinst },
+ [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
#if defined(TARGET_RISCV32)
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 46 ++++++++++++++++++++--------------------
target/riscv/op_helper.c | 18 ++++++++++------
2 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7dc50e6299..197ce97e95 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -51,7 +51,7 @@ static int fs(CPURISCVState *env, int csrno)
return 0;
}
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
@@ -73,7 +73,7 @@ static int ctr(CPURISCVState *env, int csrno)
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
@@ -101,7 +101,7 @@ static int hmode(CPURISCVState *env, int csrno)
}
}
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
static int pmp(CPURISCVState *env, int csrno)
@@ -115,7 +115,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = riscv_cpu_get_fflags(env);
@@ -126,7 +126,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -138,7 +138,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = env->frm;
@@ -149,7 +149,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -161,7 +161,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -177,7 +177,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -291,7 +291,7 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->rdtime_fn() + delta;
@@ -304,7 +304,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = (env->rdtime_fn() + delta) >> 32;
@@ -570,7 +570,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->mcounteren;
return 0;
@@ -580,7 +580,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mcounteren = val;
return 0;
@@ -804,7 +804,7 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
}
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
*val = env->satp;
}
@@ -821,7 +821,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(env_cpu(env));
@@ -991,7 +991,7 @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@@ -1005,7 +1005,7 @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@@ -1020,7 +1020,7 @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->htimedelta >> 32;
@@ -1030,7 +1030,7 @@ static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
@@ -1228,18 +1228,18 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
if ((write_mask && read_only) ||
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* execute combined read/write operation if it exists */
@@ -1249,7 +1249,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
/* if no accessor exists then return failure */
if (!csr_ops[csrno].read) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* read old value */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 4b64bfe7d2..948d204793 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -43,8 +43,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
target_ulong csr)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, src, -1);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@@ -53,8 +55,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@@ -63,8 +67,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 12/13] target/riscv: Return the exception from invalid CSR accesses
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
When performing a CSR access let's return a negative exception value on
an error instead of -1. This will allow us to specify the exception in
future patches.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 46 ++++++++++++++++++++--------------------
target/riscv/op_helper.c | 18 ++++++++++------
2 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7dc50e6299..197ce97e95 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -51,7 +51,7 @@ static int fs(CPURISCVState *env, int csrno)
return 0;
}
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
@@ -73,7 +73,7 @@ static int ctr(CPURISCVState *env, int csrno)
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
return 0;
@@ -101,7 +101,7 @@ static int hmode(CPURISCVState *env, int csrno)
}
}
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
static int pmp(CPURISCVState *env, int csrno)
@@ -115,7 +115,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = riscv_cpu_get_fflags(env);
@@ -126,7 +126,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -138,7 +138,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = env->frm;
@@ -149,7 +149,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -161,7 +161,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
@@ -177,7 +177,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mstatus |= MSTATUS_FS;
#endif
@@ -291,7 +291,7 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->rdtime_fn() + delta;
@@ -304,7 +304,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = (env->rdtime_fn() + delta) >> 32;
@@ -570,7 +570,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->mcounteren;
return 0;
@@ -580,7 +580,7 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->mcounteren = val;
return 0;
@@ -804,7 +804,7 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
}
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
*val = env->satp;
}
@@ -821,7 +821,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
} else {
if((val ^ env->satp) & SATP_ASID) {
tlb_flush(env_cpu(env));
@@ -991,7 +991,7 @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@@ -1005,7 +1005,7 @@ static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#if defined(TARGET_RISCV32)
@@ -1020,7 +1020,7 @@ static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->htimedelta >> 32;
@@ -1030,7 +1030,7 @@ static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
@@ -1228,18 +1228,18 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
if ((write_mask && read_only) ||
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
#endif
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* execute combined read/write operation if it exists */
@@ -1249,7 +1249,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
/* if no accessor exists then return failure */
if (!csr_ops[csrno].read) {
- return -1;
+ return -RISCV_EXCP_ILLEGAL_INST;
}
/* read old value */
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 4b64bfe7d2..948d204793 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -43,8 +43,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
target_ulong csr)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, src, -1);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@@ -53,8 +55,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
@@ -63,8 +67,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+
+ if (ret < 0) {
+ riscv_raise_exception(env, -ret, GETPC());
}
return val;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-12 19:13 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, anup.patel, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 6 +++
target/riscv/helper.h | 1 +
target/riscv/csr.c | 64 ++++++++++++++++++++++++-
target/riscv/insn_trans/trans_rvh.inc.c | 2 +-
target/riscv/op_helper.c | 42 ++++++++++++++--
5 files changed, 109 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index d88e2ea30d..bd36062877 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -461,6 +461,11 @@
#define HSTATUS_WPRI HSTATUS64_WPRI
#endif
+#define HCOUNTEREN_CY (1 << 0)
+#define HCOUNTEREN_TM (1 << 1)
+#define HCOUNTEREN_IR (1 << 2)
+#define HCOUNTEREN_HPM3 (1 << 3)
+
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
@@ -553,6 +558,7 @@
#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
+#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
#define RISCV_EXCP_INT_FLAG 0x80000000
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c8029d83f9..4b690147fb 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -80,6 +80,7 @@ DEF_HELPER_1(tlb_flush, void, env)
/* Hypervisor functions */
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 197ce97e95..200001de74 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -75,6 +75,61 @@ static int ctr(CPURISCVState *env, int csrno)
/* The Counters extensions is not enabled */
return -RISCV_EXCP_ILLEGAL_INST;
}
+
+ if (riscv_cpu_virt_enabled(env)) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+#if defined(TARGET_RISCV32)
+ case CSR_CYCLEH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+#endif
+ }
+ }
#endif
return 0;
}
@@ -98,6 +153,8 @@ static int hmode(CPURISCVState *env, int csrno)
if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
env->priv == PRV_M) {
return 0;
+ } else {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
@@ -340,6 +397,7 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
+ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
@@ -1238,9 +1296,13 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
}
/* check predicate */
- if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
+ if (!csr_ops[csrno].predicate) {
return -RISCV_EXCP_ILLEGAL_INST;
}
+ ret = csr_ops[csrno].predicate(env, csrno);
+ if (ret < 0) {
+ return ret;
+ }
/* execute combined read/write operation if it exists */
if (csr_ops[csrno].op) {
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
index db650ae62a..881c9ef4d2 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -360,7 +360,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
- gen_helper_hyp_tlb_flush(cpu_env);
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
return true;
#endif
return false;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 948d204793..9b9ada45a9 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -94,6 +94,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+ if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_VTSR)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ }
+
mstatus = env->mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -176,7 +181,7 @@ void helper_wfi(CPURISCVState *env)
if ((env->priv == PRV_S &&
get_field(env->mstatus, MSTATUS_TW)) ||
riscv_cpu_virt_enabled(env)) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
@@ -191,6 +196,9 @@ void helper_tlb_flush(CPURISCVState *env)
(env->priv == PRV_S &&
get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_VTVM)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
tlb_flush(cs);
}
@@ -200,6 +208,10 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
+ if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ }
+
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
tlb_flush(cs);
@@ -209,6 +221,16 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
+{
+ if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
+ helper_hyp_tlb_flush(env);
+}
+
target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
target_ulong attrs, target_ulong memop)
{
@@ -251,7 +273,11 @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
return pte;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
return 0;
}
@@ -289,7 +315,11 @@ void helper_hyp_store(CPURISCVState *env, target_ulong address,
return;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
}
target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
@@ -319,7 +349,11 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
return pte;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread* [PATCH v3 13/13] target/riscv: Support the Virtual Instruction fault
@ 2020-08-12 19:13 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-12 19:13 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, anup.patel, alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 6 +++
target/riscv/helper.h | 1 +
target/riscv/csr.c | 64 ++++++++++++++++++++++++-
target/riscv/insn_trans/trans_rvh.inc.c | 2 +-
target/riscv/op_helper.c | 42 ++++++++++++++--
5 files changed, 109 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index d88e2ea30d..bd36062877 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -461,6 +461,11 @@
#define HSTATUS_WPRI HSTATUS64_WPRI
#endif
+#define HCOUNTEREN_CY (1 << 0)
+#define HCOUNTEREN_TM (1 << 1)
+#define HCOUNTEREN_IR (1 << 2)
+#define HCOUNTEREN_HPM3 (1 << 3)
+
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
@@ -553,6 +558,7 @@
#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
+#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
#define RISCV_EXCP_INT_FLAG 0x80000000
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c8029d83f9..4b690147fb 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -80,6 +80,7 @@ DEF_HELPER_1(tlb_flush, void, env)
/* Hypervisor functions */
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hyp_tlb_flush, void, env)
+DEF_HELPER_1(hyp_gvma_tlb_flush, void, env)
DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl)
DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl)
DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 197ce97e95..200001de74 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -75,6 +75,61 @@ static int ctr(CPURISCVState *env, int csrno)
/* The Counters extensions is not enabled */
return -RISCV_EXCP_ILLEGAL_INST;
}
+
+ if (riscv_cpu_virt_enabled(env)) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+#if defined(TARGET_RISCV32)
+ case CSR_CYCLEH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
+ get_field(env->mcounteren, HCOUNTEREN_CY)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
+ get_field(env->mcounteren, HCOUNTEREN_TM)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
+ get_field(env->mcounteren, HCOUNTEREN_IR)) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
+ get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
+ }
+ break;
+#endif
+ }
+ }
#endif
return 0;
}
@@ -98,6 +153,8 @@ static int hmode(CPURISCVState *env, int csrno)
if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
env->priv == PRV_M) {
return 0;
+ } else {
+ return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
}
@@ -340,6 +397,7 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
+ (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
@@ -1238,9 +1296,13 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
}
/* check predicate */
- if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
+ if (!csr_ops[csrno].predicate) {
return -RISCV_EXCP_ILLEGAL_INST;
}
+ ret = csr_ops[csrno].predicate(env, csrno);
+ if (ret < 0) {
+ return ret;
+ }
/* execute combined read/write operation if it exists */
if (csr_ops[csrno].op) {
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.inc.c
index db650ae62a..881c9ef4d2 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.inc.c
@@ -360,7 +360,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
REQUIRE_EXT(ctx, RVH);
#ifndef CONFIG_USER_ONLY
- gen_helper_hyp_tlb_flush(cpu_env);
+ gen_helper_hyp_gvma_tlb_flush(cpu_env);
return true;
#endif
return false;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 948d204793..9b9ada45a9 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -94,6 +94,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+ if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_VTSR)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ }
+
mstatus = env->mstatus;
if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
@@ -176,7 +181,7 @@ void helper_wfi(CPURISCVState *env)
if ((env->priv == PRV_S &&
get_field(env->mstatus, MSTATUS_TW)) ||
riscv_cpu_virt_enabled(env)) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
@@ -191,6 +196,9 @@ void helper_tlb_flush(CPURISCVState *env)
(env->priv == PRV_S &&
get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else if (riscv_has_ext(env, RVH) && riscv_cpu_virt_enabled(env) &&
+ get_field(env->hstatus, HSTATUS_VTVM)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
} else {
tlb_flush(cs);
}
@@ -200,6 +208,10 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
+ if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ }
+
if (env->priv == PRV_M ||
(env->priv == PRV_S && !riscv_cpu_virt_enabled(env))) {
tlb_flush(cs);
@@ -209,6 +221,16 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
+void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
+{
+ if (env->priv == PRV_S && !riscv_cpu_virt_enabled(env) &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
+ helper_hyp_tlb_flush(env);
+}
+
target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
target_ulong attrs, target_ulong memop)
{
@@ -251,7 +273,11 @@ target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address,
return pte;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
return 0;
}
@@ -289,7 +315,11 @@ void helper_hyp_store(CPURISCVState *env, target_ulong address,
return;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
}
target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
@@ -319,7 +349,11 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
return pte;
}
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ if (riscv_cpu_virt_enabled(env)) {
+ riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETPC());
+ } else {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
return 0;
}
--
2.27.0
^ permalink raw reply related [flat|nested] 32+ messages in thread
* Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
2020-08-12 19:13 ` Alistair Francis
@ 2020-08-13 2:26 ` LIU Zhiwei
-1 siblings, 0 replies; 32+ messages in thread
From: LIU Zhiwei @ 2020-08-13 2:26 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, anup.patel, palmer
On 2020/8/13 3:13, Alistair Francis wrote:
> This series updates the experimental QEMU RISC-V Hypervisor spec to the
> v0.6.1 draft implementation.
>
> THis includes support for the new 2-stage lookup instructions and the new
> CSRs.
>
> It also includes the new 0.6.1 support for the virtual instruction
> fault.
>
> This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
> Linux guests.
Hi Alistair,
I am reading Christoper Dall's article on ARM virtualization. As far as
I can see, Xvisor is type 1 hypervisor.
I want to try this patch set. Could you share the method? Thanks very much.
Best Regards,
Zhiwei
> v3:
> - Rebase on master
> v2:
> - Update to v0.6.1
>
>
>
> Alistair Francis (13):
> target/riscv: Allow setting a two-stage lookup in the virt status
> target/riscv: Allow generating hlv/hlvx/hsv instructions
> target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
> target/riscv: Don't allow guest to write to htinst
> target/riscv: Convert MSTATUS MTL to GVA
> target/riscv: Fix the interrupt cause code
> target/riscv: Update the Hypervisor trap return/entry
> target/riscv: Update the CSRs to the v0.6 Hyp extension
> target/riscv: Only support a single VSXL length
> target/riscv: Only support little endian guests
> target/riscv: Support the v0.6 Hypervisor extension CRSs
> target/riscv: Return the exception from invalid CSR accesses
> target/riscv: Support the Virtual Instruction fault
>
> target/riscv/cpu.h | 2 +
> target/riscv/cpu_bits.h | 25 +-
> target/riscv/helper.h | 4 +
> target/riscv/insn32-64.decode | 5 +
> target/riscv/insn32.decode | 11 +
> target/riscv/cpu_helper.c | 123 +++++----
> target/riscv/csr.c | 171 ++++++++++--
> target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
> target/riscv/op_helper.c | 176 +++++++++++-
> target/riscv/translate.c | 10 -
> 10 files changed, 761 insertions(+), 108 deletions(-)
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
@ 2020-08-13 2:26 ` LIU Zhiwei
0 siblings, 0 replies; 32+ messages in thread
From: LIU Zhiwei @ 2020-08-13 2:26 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: anup.patel, palmer, alistair23
On 2020/8/13 3:13, Alistair Francis wrote:
> This series updates the experimental QEMU RISC-V Hypervisor spec to the
> v0.6.1 draft implementation.
>
> THis includes support for the new 2-stage lookup instructions and the new
> CSRs.
>
> It also includes the new 0.6.1 support for the virtual instruction
> fault.
>
> This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
> Linux guests.
Hi Alistair,
I am reading Christoper Dall's article on ARM virtualization. As far as
I can see, Xvisor is type 1 hypervisor.
I want to try this patch set. Could you share the method? Thanks very much.
Best Regards,
Zhiwei
> v3:
> - Rebase on master
> v2:
> - Update to v0.6.1
>
>
>
> Alistair Francis (13):
> target/riscv: Allow setting a two-stage lookup in the virt status
> target/riscv: Allow generating hlv/hlvx/hsv instructions
> target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
> target/riscv: Don't allow guest to write to htinst
> target/riscv: Convert MSTATUS MTL to GVA
> target/riscv: Fix the interrupt cause code
> target/riscv: Update the Hypervisor trap return/entry
> target/riscv: Update the CSRs to the v0.6 Hyp extension
> target/riscv: Only support a single VSXL length
> target/riscv: Only support little endian guests
> target/riscv: Support the v0.6 Hypervisor extension CRSs
> target/riscv: Return the exception from invalid CSR accesses
> target/riscv: Support the Virtual Instruction fault
>
> target/riscv/cpu.h | 2 +
> target/riscv/cpu_bits.h | 25 +-
> target/riscv/helper.h | 4 +
> target/riscv/insn32-64.decode | 5 +
> target/riscv/insn32.decode | 11 +
> target/riscv/cpu_helper.c | 123 +++++----
> target/riscv/csr.c | 171 ++++++++++--
> target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
> target/riscv/op_helper.c | 176 +++++++++++-
> target/riscv/translate.c | 10 -
> 10 files changed, 761 insertions(+), 108 deletions(-)
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
2020-08-13 2:26 ` LIU Zhiwei
@ 2020-08-13 21:26 ` Alistair Francis
-1 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-13 21:26 UTC (permalink / raw)
To: LIU Zhiwei
Cc: open list:RISC-V, Palmer Dabbelt, Anup Patel, Alistair Francis,
qemu-devel@nongnu.org Developers
On Wed, Aug 12, 2020 at 7:26 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
>
> On 2020/8/13 3:13, Alistair Francis wrote:
> > This series updates the experimental QEMU RISC-V Hypervisor spec to the
> > v0.6.1 draft implementation.
> >
> > THis includes support for the new 2-stage lookup instructions and the new
> > CSRs.
> >
> > It also includes the new 0.6.1 support for the virtual instruction
> > fault.
> >
> > This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
> > Linux guests.
> Hi Alistair,
>
> I am reading Christoper Dall's article on ARM virtualization. As far as
> I can see, Xvisor is type 1 hypervisor.
Yep, it's a bare metal Hypervisor.
>
> I want to try this patch set. Could you share the method? Thanks very much.
There are some details in the origins submission, you can see them
here: https://patchew.org/QEMU/cover.1580518859.git.alistair.francis@wdc.com/
I'm also working on improving the support in meta-virtualisation to
help as well.
Thanks for helping test.
Alistair
>
> Best Regards,
> Zhiwei
> > v3:
> > - Rebase on master
> > v2:
> > - Update to v0.6.1
> >
> >
> >
> > Alistair Francis (13):
> > target/riscv: Allow setting a two-stage lookup in the virt status
> > target/riscv: Allow generating hlv/hlvx/hsv instructions
> > target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
> > target/riscv: Don't allow guest to write to htinst
> > target/riscv: Convert MSTATUS MTL to GVA
> > target/riscv: Fix the interrupt cause code
> > target/riscv: Update the Hypervisor trap return/entry
> > target/riscv: Update the CSRs to the v0.6 Hyp extension
> > target/riscv: Only support a single VSXL length
> > target/riscv: Only support little endian guests
> > target/riscv: Support the v0.6 Hypervisor extension CRSs
> > target/riscv: Return the exception from invalid CSR accesses
> > target/riscv: Support the Virtual Instruction fault
> >
> > target/riscv/cpu.h | 2 +
> > target/riscv/cpu_bits.h | 25 +-
> > target/riscv/helper.h | 4 +
> > target/riscv/insn32-64.decode | 5 +
> > target/riscv/insn32.decode | 11 +
> > target/riscv/cpu_helper.c | 123 +++++----
> > target/riscv/csr.c | 171 ++++++++++--
> > target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
> > target/riscv/op_helper.c | 176 +++++++++++-
> > target/riscv/translate.c | 10 -
> > 10 files changed, 761 insertions(+), 108 deletions(-)
> >
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH v3 00/13] RISC-V: Update the Hypervisor spec to v0.6.1
@ 2020-08-13 21:26 ` Alistair Francis
0 siblings, 0 replies; 32+ messages in thread
From: Alistair Francis @ 2020-08-13 21:26 UTC (permalink / raw)
To: LIU Zhiwei
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Anup Patel, Palmer Dabbelt
On Wed, Aug 12, 2020 at 7:26 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
>
>
> On 2020/8/13 3:13, Alistair Francis wrote:
> > This series updates the experimental QEMU RISC-V Hypervisor spec to the
> > v0.6.1 draft implementation.
> >
> > THis includes support for the new 2-stage lookup instructions and the new
> > CSRs.
> >
> > It also includes the new 0.6.1 support for the virtual instruction
> > fault.
> >
> > This was tested by running 32-bit and 64-bit Xvisor on QEMU and starting
> > Linux guests.
> Hi Alistair,
>
> I am reading Christoper Dall's article on ARM virtualization. As far as
> I can see, Xvisor is type 1 hypervisor.
Yep, it's a bare metal Hypervisor.
>
> I want to try this patch set. Could you share the method? Thanks very much.
There are some details in the origins submission, you can see them
here: https://patchew.org/QEMU/cover.1580518859.git.alistair.francis@wdc.com/
I'm also working on improving the support in meta-virtualisation to
help as well.
Thanks for helping test.
Alistair
>
> Best Regards,
> Zhiwei
> > v3:
> > - Rebase on master
> > v2:
> > - Update to v0.6.1
> >
> >
> >
> > Alistair Francis (13):
> > target/riscv: Allow setting a two-stage lookup in the virt status
> > target/riscv: Allow generating hlv/hlvx/hsv instructions
> > target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions
> > target/riscv: Don't allow guest to write to htinst
> > target/riscv: Convert MSTATUS MTL to GVA
> > target/riscv: Fix the interrupt cause code
> > target/riscv: Update the Hypervisor trap return/entry
> > target/riscv: Update the CSRs to the v0.6 Hyp extension
> > target/riscv: Only support a single VSXL length
> > target/riscv: Only support little endian guests
> > target/riscv: Support the v0.6 Hypervisor extension CRSs
> > target/riscv: Return the exception from invalid CSR accesses
> > target/riscv: Support the Virtual Instruction fault
> >
> > target/riscv/cpu.h | 2 +
> > target/riscv/cpu_bits.h | 25 +-
> > target/riscv/helper.h | 4 +
> > target/riscv/insn32-64.decode | 5 +
> > target/riscv/insn32.decode | 11 +
> > target/riscv/cpu_helper.c | 123 +++++----
> > target/riscv/csr.c | 171 ++++++++++--
> > target/riscv/insn_trans/trans_rvh.inc.c | 342 +++++++++++++++++++++++-
> > target/riscv/op_helper.c | 176 +++++++++++-
> > target/riscv/translate.c | 10 -
> > 10 files changed, 761 insertions(+), 108 deletions(-)
> >
>
^ permalink raw reply [flat|nested] 32+ messages in thread