* [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
@ 2020-07-09 15:23 Philippe Mathieu-Daudé
2020-07-09 15:38 ` Alistair Francis
2020-08-06 12:54 ` Peter Maydell
0 siblings, 2 replies; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-09 15:23 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Rob Herring, Igor Mitsyanko, Alistair Francis,
Philippe Mathieu-Daudé,
Jean-Christophe Dubois, qemu-arm, Randy Yates, Edgar E. Iglesias
The 'Cortex-A9MPCore internal peripheral' block can only be
used with Cortex A5 and A9 cores. As we don't model the A5
yet, simply check the machine cpu core is a Cortex A9. If
not return an error.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/cpu/a9mpcore.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index 642363d2f4..1724baf17c 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -15,6 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
+#include "cpu.h"
#define A9_GIC_NUM_PRIORITY_BITS 5
@@ -53,8 +54,18 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
Error *err = NULL;
int i;
bool has_el3;
+ CPUState *cpu0;
Object *cpuobj;
+ cpu0 = qemu_get_cpu(0);
+ cpuobj = OBJECT(cpu0);
+ if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
+ /* We might allow Cortex-A5 once we model it */
+ error_setg(errp,
+ "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU");
+ return;
+ }
+
scudev = DEVICE(&s->scu);
qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
@@ -73,7 +84,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
/* Make the GIC's TZ support match the CPUs. We assume that
* either all the CPUs have TZ, or none do.
*/
- cpuobj = OBJECT(qemu_get_cpu(0));
has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
object_property_get_bool(cpuobj, "has_el3", &error_abort);
qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
--
2.21.3
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
2020-07-09 15:23 [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores Philippe Mathieu-Daudé
@ 2020-07-09 15:38 ` Alistair Francis
2020-08-06 12:54 ` Peter Maydell
1 sibling, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2020-07-09 15:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Rob Herring, Igor Mitsyanko, Alistair Francis,
qemu-devel@nongnu.org Developers, Jean-Christophe Dubois,
qemu-arm, Randy Yates, Edgar E. Iglesias
On Thu, Jul 9, 2020 at 8:23 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The 'Cortex-A9MPCore internal peripheral' block can only be
> used with Cortex A5 and A9 cores. As we don't model the A5
> yet, simply check the machine cpu core is a Cortex A9. If
> not return an error.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/cpu/a9mpcore.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
> index 642363d2f4..1724baf17c 100644
> --- a/hw/cpu/a9mpcore.c
> +++ b/hw/cpu/a9mpcore.c
> @@ -15,6 +15,7 @@
> #include "hw/irq.h"
> #include "hw/qdev-properties.h"
> #include "hw/core/cpu.h"
> +#include "cpu.h"
>
> #define A9_GIC_NUM_PRIORITY_BITS 5
>
> @@ -53,8 +54,18 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
> Error *err = NULL;
> int i;
> bool has_el3;
> + CPUState *cpu0;
> Object *cpuobj;
>
> + cpu0 = qemu_get_cpu(0);
> + cpuobj = OBJECT(cpu0);
> + if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) {
> + /* We might allow Cortex-A5 once we model it */
> + error_setg(errp,
> + "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU");
> + return;
> + }
> +
> scudev = DEVICE(&s->scu);
> qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
> sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
> @@ -73,7 +84,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
> /* Make the GIC's TZ support match the CPUs. We assume that
> * either all the CPUs have TZ, or none do.
> */
> - cpuobj = OBJECT(qemu_get_cpu(0));
> has_el3 = object_property_find(cpuobj, "has_el3", NULL) &&
> object_property_get_bool(cpuobj, "has_el3", &error_abort);
> qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3);
> --
> 2.21.3
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
2020-07-09 15:23 [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores Philippe Mathieu-Daudé
2020-07-09 15:38 ` Alistair Francis
@ 2020-08-06 12:54 ` Peter Maydell
2020-08-06 13:00 ` Randy Yates
1 sibling, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2020-08-06 12:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Rob Herring, Igor Mitsyanko, Alistair Francis, QEMU Developers,
Jean-Christophe Dubois, qemu-arm, Randy Yates, Edgar E. Iglesias
On Thu, 9 Jul 2020 at 16:23, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> The 'Cortex-A9MPCore internal peripheral' block can only be
> used with Cortex A5 and A9 cores. As we don't model the A5
> yet, simply check the machine cpu core is a Cortex A9. If
> not return an error.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/cpu/a9mpcore.c | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
Applied to target-arm.next (for 5.2), thanks.
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
2020-08-06 12:54 ` Peter Maydell
@ 2020-08-06 13:00 ` Randy Yates
0 siblings, 0 replies; 4+ messages in thread
From: Randy Yates @ 2020-08-06 13:00 UTC (permalink / raw)
To: Peter Maydell, Philippe Mathieu-Daudé
Cc: Rob Herring, Igor Mitsyanko, Alistair Francis, QEMU Developers,
Jean-Christophe Dubois, qemu-arm, Randy Yates, Edgar E. Iglesias
Good! Thank you, Philippe.
--Randy
On 8/6/20 8:54 AM, Peter Maydell wrote:
> On Thu, 9 Jul 2020 at 16:23, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>> The 'Cortex-A9MPCore internal peripheral' block can only be
>> used with Cortex A5 and A9 cores. As we don't model the A5
>> yet, simply check the machine cpu core is a Cortex A9. If
>> not return an error.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> hw/cpu/a9mpcore.c | 12 +++++++++++-
>> 1 file changed, 11 insertions(+), 1 deletion(-)
> Applied to target-arm.next (for 5.2), thanks.
>
> -- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-08-06 13:02 UTC | newest]
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2020-07-09 15:23 [PATCH] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores Philippe Mathieu-Daudé
2020-07-09 15:38 ` Alistair Francis
2020-08-06 12:54 ` Peter Maydell
2020-08-06 13:00 ` Randy Yates
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