From: Alistair Francis <alistair23@gmail.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>, Bin Meng <bin.meng@windriver.com>, Alistair Francis <alistair.francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org> Subject: Re: [PATCH] hw/riscv: sifive_u: Correct the CLINT timebase frequency Date: Thu, 8 Jul 2021 14:47:54 +1000 [thread overview] Message-ID: <CAKmqyKNo=s0ipFjz1W6GKkDOhu3zJHVdJUnh_PY2jga0bNKA+g@mail.gmail.com> (raw) In-Reply-To: <20210706102616.1922469-1-bmeng.cn@gmail.com> On Tue, Jul 6, 2021 at 8:48 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > At present the CLINT timebase frequency is set to 10MHz on sifive_u, > but on the real hardware the timebase frequency is 1Mhz. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_u.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 273c86418c..e75ca38783 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -62,6 +62,9 @@ > > #include <libfdt.h> > > +/* CLINT timebase frequency */ > +#define CLINT_TIMEBASE_FREQ 1000000 > + > static const MemMapEntry sifive_u_memmap[] = { > [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, > [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, > @@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > > qemu_fdt_add_subnode(fdt, "/cpus"); > qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", > - SIFIVE_CLINT_TIMEBASE_FREQ); > + CLINT_TIMEBASE_FREQ); > qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); > qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); > > @@ -847,7 +850,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, > memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, > - SIFIVE_CLINT_TIMEBASE_FREQ, false); > + CLINT_TIMEBASE_FREQ, false); > > if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { > return; > -- > 2.25.1 > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Bin Meng <bmeng.cn@gmail.com> Cc: Alistair Francis <alistair.francis@wdc.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Bin Meng <bin.meng@windriver.com> Subject: Re: [PATCH] hw/riscv: sifive_u: Correct the CLINT timebase frequency Date: Thu, 8 Jul 2021 14:47:54 +1000 [thread overview] Message-ID: <CAKmqyKNo=s0ipFjz1W6GKkDOhu3zJHVdJUnh_PY2jga0bNKA+g@mail.gmail.com> (raw) In-Reply-To: <20210706102616.1922469-1-bmeng.cn@gmail.com> On Tue, Jul 6, 2021 at 8:48 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > At present the CLINT timebase frequency is set to 10MHz on sifive_u, > but on the real hardware the timebase frequency is 1Mhz. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_u.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 273c86418c..e75ca38783 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -62,6 +62,9 @@ > > #include <libfdt.h> > > +/* CLINT timebase frequency */ > +#define CLINT_TIMEBASE_FREQ 1000000 > + > static const MemMapEntry sifive_u_memmap[] = { > [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 }, > [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 }, > @@ -165,7 +168,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > > qemu_fdt_add_subnode(fdt, "/cpus"); > qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", > - SIFIVE_CLINT_TIMEBASE_FREQ); > + CLINT_TIMEBASE_FREQ); > qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); > qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); > > @@ -847,7 +850,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) > sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, > memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, > - SIFIVE_CLINT_TIMEBASE_FREQ, false); > + CLINT_TIMEBASE_FREQ, false); > > if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { > return; > -- > 2.25.1 > >
next prev parent reply other threads:[~2021-07-08 4:49 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-06 10:26 [PATCH] hw/riscv: sifive_u: Correct the CLINT timebase frequency Bin Meng 2021-07-08 4:47 ` Alistair Francis [this message] 2021-07-08 4:47 ` Alistair Francis 2021-07-09 3:50 ` Alistair Francis 2021-07-09 3:50 ` Alistair Francis
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