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From: Alistair Francis <alistair23@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/32] riscv-to-apply queue
Date: Fri, 19 Jun 2020 08:27:18 -0700	[thread overview]
Message-ID: <CAKmqyKO+YLQ+kYMsPsfBXPETAxKJJ1NE4PvhObZMy3DuFoUS8w@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA9VKbE89N3YkpN4VhcEHD92=fGb3W_-mgqd+yY0rc0=6g@mail.gmail.com>

On Fri, Jun 19, 2020 at 5:37 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Fri, 19 Jun 2020 at 07:34, Alistair Francis <alistair.francis@wdc.com> wrote:
> >
> > The following changes since commit eefe34ea4b82c2b47abe28af4cc7247d51553626:
> >
> >   Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200617a' into staging (2020-06-18 15:30:13 +0100)
> >
> > are available in the Git repository at:
> >
> >   git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200618-1
> >
> > for you to fetch changes up to fad6a8463510ff5e0fb31bb451a6c3218a45d179:
> >
> >   hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-18 23:09:16 -0700)
> >
> > ----------------------------------------------------------------
> > This is a range of patches for RISC-V.
> >
> > Some key points are:
> >  - Generalise the CPU init functions
> >  - Support the SiFive revB machine
> >  - Improvements to the Hypervisor implementation and error checking
> >  - Connect some OpenTitan devices
> >  - Changes to the sifive_u machine to support U-boot
> >
> > ----------------------------------------------------------------
>
> Hi; I'm afraid this fails "make check":
>
> MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}
> QTEST_QEMU_BINARY=riscv32-softmmu/qemu-system-riscv32 QTEST_QEM
> U_IMG=qemu-img tests/qtest/qom-test -m=quick -k --tap < /dev/null |
> ./scripts/tap-driver.pl --test-name="qom-test"
> PASS 1 qom-test /riscv32/qom/opentitan
> PASS 2 qom-test /riscv32/qom/spike
> PASS 3 qom-test /riscv32/qom/virt
> PASS 4 qom-test /riscv32/qom/none
> qemu-system-riscv32:
> /home/petmay01/linaro/qemu-for-merges/hw/core/qdev.c:438:
> qdev_assert_realized_properly: Assertion `dev->parent_bus ||
> !dc->bus_type' failed.
> Broken pipe
> /home/petmay01/linaro/qemu-for-merges/tests/qtest/libqtest.c:175:
> kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped)
>
> This is a recently introduced check that all devices created
> get realized; probably somebody's added a new device in this
> pullreq but forgot a realize call.

Argh! The final rebase introduced this. Sorry, I'll send a v2.

Alistair

>
> thanks
> -- PMM


  reply	other threads:[~2020-06-19 15:38 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-19  6:24 [PULL 00/32] riscv-to-apply queue Alistair Francis
2020-06-19  6:24 ` [PULL 01/32] riscv: Add helper to make NaN-boxing for FP register Alistair Francis
2020-06-19  6:24 ` [PULL 02/32] sifive_e: Support the revB machine Alistair Francis
2020-06-19  6:24 ` [PULL 03/32] riscv: Generalize CPU init routine for the base CPU Alistair Francis
2020-06-19  6:24 ` [PULL 04/32] riscv: Generalize CPU init routine for the gcsu CPU Alistair Francis
2020-06-19  6:24 ` [PULL 05/32] riscv: Generalize CPU init routine for the imacu CPU Alistair Francis
2020-06-19  6:24 ` [PULL 06/32] riscv: Keep the CPU init routine names consistent Alistair Francis
2020-06-19  6:24 ` [PULL 07/32] target/riscv: Set access as data_load when validating stage-2 PTEs Alistair Francis
2020-06-19  6:24 ` [PULL 08/32] target/riscv: Report errors validating 2nd-stage PTEs Alistair Francis
2020-06-19  6:24 ` [PULL 09/32] target/riscv: Move the hfence instructions to the rvh decode Alistair Francis
2020-06-19  6:24 ` [PULL 10/32] target/riscv: Implement checks for hfence Alistair Francis
2020-06-19  6:24 ` [PULL 11/32] riscv/opentitan: Fix the ROM size Alistair Francis
2020-06-19  6:24 ` [PULL 12/32] hw/char: Initial commit of Ibex UART Alistair Francis
2020-06-19  6:24 ` [PULL 13/32] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-06-19  6:25 ` [PULL 14/32] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-06-19  6:25 ` [PULL 15/32] riscv/opentitan: Connect the UART device Alistair Francis
2020-06-19  6:25 ` [PULL 16/32] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-06-19  6:25 ` [PULL 17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Alistair Francis
2020-06-19  6:25 ` [PULL 18/32] hw/riscv: opentitan: " Alistair Francis
2020-06-19  6:25 ` [PULL 19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Alistair Francis
2020-06-19  6:25 ` [PULL 20/32] hw/riscv: sifive_u: Generate device tree node for OTP Alistair Francis
2020-06-19  6:25 ` [PULL 21/32] hw/riscv: sifive_gpio: Clean up the codes Alistair Francis
2020-06-19  6:25 ` [PULL 22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property Alistair Francis
2020-06-19  6:25 ` [PULL 23/32] hw/riscv: sifive_u: Hook a GPIO controller Alistair Francis
2020-06-19  6:25 ` [PULL 24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Alistair Francis
2020-06-19  6:25 ` [PULL 25/32] hw/riscv: sifive_u: Add reset functionality Alistair Francis
2020-06-19  6:25 ` [PULL 26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Alistair Francis
2020-06-19  6:25 ` [PULL 27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Alistair Francis
2020-06-19  6:25 ` [PULL 28/32] target/riscv: Rename IBEX CPU init routine Alistair Francis
2020-06-19  6:25 ` [PULL 29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Alistair Francis
2020-06-19  6:25 ` [PULL 30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state Alistair Francis
2020-06-19  6:25 ` [PULL 31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries Alistair Francis
2020-06-19  6:25 ` [PULL 32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device Alistair Francis
2020-06-19  7:22 ` [PULL 00/32] riscv-to-apply queue no-reply
2020-06-19 12:37 ` Peter Maydell
2020-06-19 15:27   ` Alistair Francis [this message]
2021-06-08  0:29 Alistair Francis
2021-06-08 16:50 ` Peter Maydell
2023-02-07  7:09 Alistair Francis
2023-02-07 20:12 ` Peter Maydell

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