From: Peter Maydell <peter.maydell@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Alistair Francis <alistair23@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/32] riscv-to-apply queue
Date: Tue, 8 Jun 2021 17:50:57 +0100 [thread overview]
Message-ID: <CAFEAcA8PVz1V-Xucr5myBkbLuoZD9NA61_W3_Qs3jmC7+MCXwg@mail.gmail.com> (raw)
In-Reply-To: <20210608002947.1649775-1-alistair.francis@wdc.com>
On Tue, 8 Jun 2021 at 01:30, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca:
>
> Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 15:45:48 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1
>
> for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4:
>
> target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for QEMU 6.1
>
> - Update the PLIC and CLINT DT bindings
> - Improve documentation for RISC-V machines
> - Support direct kernel boot for microchip_pfsoc
> - Fix WFI exception behaviour
> - Improve CSR printing
> - Initial support for the experimental Bit Manip extension
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
next prev parent reply other threads:[~2021-06-08 16:52 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-08 0:29 [PULL 00/32] riscv-to-apply queue Alistair Francis
2021-06-08 0:29 ` [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper Alistair Francis
2021-06-08 0:29 ` [PULL 02/32] hw/riscv: virt: " Alistair Francis
2021-06-08 0:29 ` [PULL 03/32] hw/riscv: Support the official CLINT DT bindings Alistair Francis
2021-06-08 0:29 ` [PULL 04/32] hw/riscv: Support the official PLIC " Alistair Francis
2021-06-08 0:29 ` [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices Alistair Francis
2021-06-08 0:29 ` [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage Alistair Francis
2021-06-08 0:29 ` [PULL 07/32] hw/riscv: Use macros for BIOS image names Alistair Francis
2021-06-08 0:29 ` [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot Alistair Francis
2021-06-08 0:29 ` [PULL 09/32] target/riscv: fix wfi exception behavior Alistair Francis
2021-06-08 0:29 ` [PULL 10/32] docs/system: Move the RISC-V -bios information to removed Alistair Francis
2021-06-08 0:29 ` [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation Alistair Francis
2021-06-08 0:29 ` [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration Alistair Francis
2021-06-08 0:29 ` [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp Alistair Francis
2021-06-08 0:29 ` [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations Alistair Francis
2021-06-08 0:29 ` [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz Alistair Francis
2021-06-08 0:29 ` [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension Alistair Francis
2021-06-08 0:29 ` [PULL 17/32] target/riscv: rvb: count leading/trailing zeros Alistair Francis
2021-06-08 0:29 ` [PULL 18/32] target/riscv: rvb: count bits set Alistair Francis
2021-06-08 0:29 ` [PULL 19/32] target/riscv: rvb: logic-with-negate Alistair Francis
2021-06-08 0:29 ` [PULL 20/32] target/riscv: rvb: pack two words into one register Alistair Francis
2021-06-08 0:29 ` [PULL 21/32] target/riscv: rvb: min/max instructions Alistair Francis
2021-06-08 0:29 ` [PULL 22/32] target/riscv: rvb: sign-extend instructions Alistair Francis
2021-06-08 0:29 ` [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions Alistair Francis
2021-06-08 0:29 ` [PULL 24/32] target/riscv: rvb: single-bit instructions Alistair Francis
2021-06-08 0:29 ` [PULL 25/32] target/riscv: rvb: shift ones Alistair Francis
2021-06-08 0:29 ` [PULL 26/32] target/riscv: rvb: rotate (left/right) Alistair Francis
2021-06-08 0:29 ` [PULL 27/32] target/riscv: rvb: generalized reverse Alistair Francis
2021-06-08 0:29 ` [PULL 28/32] target/riscv: rvb: generalized or-combine Alistair Francis
2021-06-08 0:29 ` [PULL 29/32] target/riscv: rvb: address calculation Alistair Francis
2021-06-08 0:29 ` [PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend Alistair Francis
2021-06-08 0:29 ` [PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line Alistair Francis
2021-06-08 0:29 ` [PULL 32/32] target/riscv: rvb: add b-ext version cpu option Alistair Francis
2021-06-08 16:50 ` Peter Maydell [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-02-07 7:09 [PULL 00/32] riscv-to-apply queue Alistair Francis
2023-02-07 20:12 ` Peter Maydell
2020-06-19 6:24 Alistair Francis
2020-06-19 7:22 ` no-reply
2020-06-19 12:37 ` Peter Maydell
2020-06-19 15:27 ` Alistair Francis
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