* [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
@ 2021-05-16 20:53 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-16 20:53 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, qemu-trivial, Bin Meng, Laurent Vivier,
Philippe Mathieu-Daudé,
Palmer Dabbelt, Alistair Francis
Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7e879fb9ca5..0619b491a42 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -97,7 +97,9 @@ enum {
typedef struct CPURISCVState CPURISCVState;
+#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
+#endif
#define RV_VLEN_MAX 256
--
2.26.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
@ 2021-05-16 20:53 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-16 20:53 UTC (permalink / raw)
To: qemu-devel
Cc: Bin Meng, Alistair Francis, Laurent Vivier, qemu-riscv,
qemu-trivial, Palmer Dabbelt, Philippe Mathieu-Daudé
Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7e879fb9ca5..0619b491a42 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -97,7 +97,9 @@ enum {
typedef struct CPURISCVState CPURISCVState;
+#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
+#endif
#define RV_VLEN_MAX 256
--
2.26.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-05-16 20:53 ` Philippe Mathieu-Daudé
@ 2021-05-16 20:55 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-16 20:55 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers
Cc: open list:RISC-V TCG CPUs, QEMU Trivial, Bin Meng,
Laurent Vivier, Palmer Dabbelt, Alistair Francis
Oops this is v1, not v2.
On Sun, May 16, 2021 at 10:53 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
@ 2021-05-16 20:55 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 12+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-16 20:55 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers
Cc: Bin Meng, Alistair Francis, Laurent Vivier,
open list:RISC-V TCG CPUs, QEMU Trivial, Palmer Dabbelt
Oops this is v1, not v2.
On Sun, May 16, 2021 at 10:53 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-05-16 20:53 ` Philippe Mathieu-Daudé
@ 2021-05-16 23:14 ` Alistair Francis
-1 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2021-05-16 23:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: open list:RISC-V, QEMU Trivial, Bin Meng,
qemu-devel@nongnu.org Developers, Laurent Vivier, Palmer Dabbelt,
Alistair Francis
On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
@ 2021-05-16 23:14 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2021-05-16 23:14 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, QEMU Trivial,
Bin Meng, Laurent Vivier, Palmer Dabbelt, Alistair Francis
On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-05-16 20:53 ` Philippe Mathieu-Daudé
@ 2021-05-17 1:42 ` Bin Meng
-1 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-05-17 1:42 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: open list:RISC-V, QEMU Trivial, Bin Meng,
qemu-devel@nongnu.org Developers, Laurent Vivier, Palmer Dabbelt,
Alistair Francis
On Mon, May 17, 2021 at 4:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
@ 2021-05-17 1:42 ` Bin Meng
0 siblings, 0 replies; 12+ messages in thread
From: Bin Meng @ 2021-05-17 1:42 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, QEMU Trivial,
Bin Meng, Laurent Vivier, Palmer Dabbelt, Alistair Francis
On Mon, May 17, 2021 at 4:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-05-16 20:53 ` Philippe Mathieu-Daudé
@ 2021-05-18 6:33 ` Alistair Francis
-1 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2021-05-18 6:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: open list:RISC-V, QEMU Trivial, Bin Meng,
qemu-devel@nongnu.org Developers, Laurent Vivier, Palmer Dabbelt,
Alistair Francis
On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
@ 2021-05-18 6:33 ` Alistair Francis
0 siblings, 0 replies; 12+ messages in thread
From: Alistair Francis @ 2021-05-18 6:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, QEMU Trivial,
Bin Meng, Laurent Vivier, Palmer Dabbelt, Alistair Francis
On Mon, May 17, 2021 at 6:53 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
> --
> 2.26.3
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
2021-05-16 20:53 ` Philippe Mathieu-Daudé
@ 2021-06-05 18:59 ` Laurent Vivier
-1 siblings, 0 replies; 12+ messages in thread
From: Laurent Vivier @ 2021-06-05 18:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-trivial, Palmer Dabbelt, Alistair Francis, Bin Meng, qemu-riscv
Le 16/05/2021 à 22:53, Philippe Mathieu-Daudé a écrit :
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
>
Applied to my trivial-patches branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation
@ 2021-06-05 18:59 ` Laurent Vivier
0 siblings, 0 replies; 12+ messages in thread
From: Laurent Vivier @ 2021-06-05 18:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: qemu-riscv, qemu-trivial, Bin Meng, Palmer Dabbelt, Alistair Francis
Le 16/05/2021 à 22:53, Philippe Mathieu-Daudé a écrit :
> Physical Memory Protection is a system feature.
> Avoid polluting the user-mode emulation by its definitions.
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/riscv/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7e879fb9ca5..0619b491a42 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -97,7 +97,9 @@ enum {
>
> typedef struct CPURISCVState CPURISCVState;
>
> +#if !defined(CONFIG_USER_ONLY)
> #include "pmp.h"
> +#endif
>
> #define RV_VLEN_MAX 256
>
>
Applied to my trivial-patches branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-06-05 19:01 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
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2021-05-16 20:53 [PATCH v2] target/riscv: Do not include 'pmp.h' in user emulation Philippe Mathieu-Daudé
2021-05-16 20:53 ` Philippe Mathieu-Daudé
2021-05-16 20:55 ` Philippe Mathieu-Daudé
2021-05-16 20:55 ` Philippe Mathieu-Daudé
2021-05-16 23:14 ` Alistair Francis
2021-05-16 23:14 ` Alistair Francis
2021-05-17 1:42 ` Bin Meng
2021-05-17 1:42 ` Bin Meng
2021-05-18 6:33 ` Alistair Francis
2021-05-18 6:33 ` Alistair Francis
2021-06-05 18:59 ` Laurent Vivier
2021-06-05 18:59 ` Laurent Vivier
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