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* [PATCH v4] gdb: riscv: Add target description
@ 2021-01-06 20:41 ` Sylvain Pelissier
  0 siblings, 0 replies; 6+ messages in thread
From: Sylvain Pelissier @ 2021-01-06 20:41 UTC (permalink / raw)
  To: qemu-devel
  Cc: Sylvain Pelissier, open list:RISC-V TCG CPUs, Sagar Karandikar,
	Bastian Koppelmann, Bin Meng, Palmer Dabbelt, Alistair Francis

Target description is not currently implemented in RISC-V
architecture. Thus GDB won't set it properly when attached.
The patch implements the target description response.

Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 254cd83f8b..ed4971978b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static gchar *riscv_gdb_arch_name(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    if (riscv_cpu_is_32bit(env)) {
+        return g_strdup("riscv:rv32");
+    } else {
+        return g_strdup("riscv:rv64");
+    }
+}
+
 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 {
     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     /* For now, mark unmigratable: */
     cc->vmsd = &vmstate_riscv_cpu;
 #endif
+    cc->gdb_arch_name = riscv_gdb_arch_name;
 #ifdef CONFIG_TCG
     cc->tcg_initialize = riscv_translate_init;
     cc->tlb_fill = riscv_cpu_tlb_fill;
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH v4] gdb: riscv: Add target description
@ 2021-01-06 20:41 ` Sylvain Pelissier
  0 siblings, 0 replies; 6+ messages in thread
From: Sylvain Pelissier @ 2021-01-06 20:41 UTC (permalink / raw)
  To: qemu-devel
  Cc: Sylvain Pelissier, Bin Meng, Alistair Francis, Palmer Dabbelt,
	Alistair Francis, Sagar Karandikar, Bastian Koppelmann,
	open list:RISC-V TCG CPUs

Target description is not currently implemented in RISC-V
architecture. Thus GDB won't set it properly when attached.
The patch implements the target description response.

Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 254cd83f8b..ed4971978b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static gchar *riscv_gdb_arch_name(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    if (riscv_cpu_is_32bit(env)) {
+        return g_strdup("riscv:rv32");
+    } else {
+        return g_strdup("riscv:rv64");
+    }
+}
+
 static void riscv_cpu_class_init(ObjectClass *c, void *data)
 {
     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
     /* For now, mark unmigratable: */
     cc->vmsd = &vmstate_riscv_cpu;
 #endif
+    cc->gdb_arch_name = riscv_gdb_arch_name;
 #ifdef CONFIG_TCG
     cc->tcg_initialize = riscv_translate_init;
     cc->tlb_fill = riscv_cpu_tlb_fill;
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH v4] gdb: riscv: Add target description
  2021-01-06 20:41 ` Sylvain Pelissier
@ 2021-01-07  6:55   ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-07  6:55 UTC (permalink / raw)
  To: Sylvain Pelissier, qemu-devel
  Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
	Bin Meng, Alistair Francis, Palmer Dabbelt

On 1/6/21 9:41 PM, Sylvain Pelissier wrote:
> Target description is not currently implemented in RISC-V
> architecture. Thus GDB won't set it properly when attached.
> The patch implements the target description response.
> 
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v4] gdb: riscv: Add target description
@ 2021-01-07  6:55   ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-07  6:55 UTC (permalink / raw)
  To: Sylvain Pelissier, qemu-devel
  Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
	Bin Meng, Palmer Dabbelt, Alistair Francis

On 1/6/21 9:41 PM, Sylvain Pelissier wrote:
> Target description is not currently implemented in RISC-V
> architecture. Thus GDB won't set it properly when attached.
> The patch implements the target description response.
> 
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/cpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v4] gdb: riscv: Add target description
  2021-01-06 20:41 ` Sylvain Pelissier
@ 2021-01-07 17:12   ` Alistair Francis
  -1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2021-01-07 17:12 UTC (permalink / raw)
  To: Sylvain Pelissier
  Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
	Bin Meng, qemu-devel@nongnu.org Developers, Palmer Dabbelt,
	Alistair Francis

On Wed, Jan 6, 2021 at 12:42 PM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V
> architecture. Thus GDB won't set it properly when attached.
> The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Thanks for addressing all of the comments.

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +    CPURISCVState *env = &cpu->env;
> +
> +    if (riscv_cpu_is_32bit(env)) {
> +        return g_strdup("riscv:rv32");
> +    } else {
> +        return g_strdup("riscv:rv64");
> +    }
> +}
> +
>  static void riscv_cpu_class_init(ObjectClass *c, void *data)
>  {
>      RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
>      /* For now, mark unmigratable: */
>      cc->vmsd = &vmstate_riscv_cpu;
>  #endif
> +    cc->gdb_arch_name = riscv_gdb_arch_name;
>  #ifdef CONFIG_TCG
>      cc->tcg_initialize = riscv_translate_init;
>      cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
>
>


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH v4] gdb: riscv: Add target description
@ 2021-01-07 17:12   ` Alistair Francis
  0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2021-01-07 17:12 UTC (permalink / raw)
  To: Sylvain Pelissier
  Cc: qemu-devel@nongnu.org Developers, open list:RISC-V TCG CPUs,
	Sagar Karandikar, Bastian Koppelmann, Bin Meng, Palmer Dabbelt,
	Alistair Francis

On Wed, Jan 6, 2021 at 12:42 PM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V
> architecture. Thus GDB won't set it properly when attached.
> The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Thanks for addressing all of the comments.

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/cpu.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_END_OF_LIST(),
>  };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> +    RISCVCPU *cpu = RISCV_CPU(cs);
> +    CPURISCVState *env = &cpu->env;
> +
> +    if (riscv_cpu_is_32bit(env)) {
> +        return g_strdup("riscv:rv32");
> +    } else {
> +        return g_strdup("riscv:rv64");
> +    }
> +}
> +
>  static void riscv_cpu_class_init(ObjectClass *c, void *data)
>  {
>      RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
>      /* For now, mark unmigratable: */
>      cc->vmsd = &vmstate_riscv_cpu;
>  #endif
> +    cc->gdb_arch_name = riscv_gdb_arch_name;
>  #ifdef CONFIG_TCG
>      cc->tcg_initialize = riscv_translate_init;
>      cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
>
>


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-01-07 17:14 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-06 20:41 [PATCH v4] gdb: riscv: Add target description Sylvain Pelissier
2021-01-06 20:41 ` Sylvain Pelissier
2021-01-07  6:55 ` Philippe Mathieu-Daudé
2021-01-07  6:55   ` Philippe Mathieu-Daudé
2021-01-07 17:12 ` Alistair Francis
2021-01-07 17:12   ` Alistair Francis

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