* [PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses
@ 2022-04-19 9:08 ` frank.chang
0 siblings, 0 replies; 16+ messages in thread
From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw)
To: qemu-devel; +Cc: Frank Chang, qemu-riscv
From: Frank Chang <frank.chang@sifive.com>
This patchset makes ACLINT mtime to be writable as RISC-V privilege
spec defines that mtime is exposed as a memory-mapped machine-mode
read-write register. Also, mtimecmp and mtime should be 32/64-bit memory
accessible registers. ACLINT reset function is also added, which requires
mtime to be resetable if we need to support core power-gating feature in
the future.
This patchset is the updated verion of:
https://patchew.org/QEMU/20220126095448.2964-1-frank.chang@sifive.com/
Changelog:
v3:
* Forbid 8-byte write access to timecmp_hi and time_hi.
* Add ACLINT reset function.
v2:
* Support 32/64-bit mtimecmp/mtime memory accesses.
* Add .impl.[min|max]_access_size declaration.
Frank Chang (3):
hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT
hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V
ACLINT
hw/intc: Make RISC-V ACLINT mtime MMIO register writable
Jim Shu (1):
hw/intc: riscv_aclint: Add reset function of ACLINT devices
hw/intc/riscv_aclint.c | 144 ++++++++++++++++++++++++++-------
include/hw/intc/riscv_aclint.h | 1 +
target/riscv/cpu.h | 8 +-
target/riscv/cpu_helper.c | 4 +-
4 files changed, 121 insertions(+), 36 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses @ 2022-04-19 9:08 ` frank.chang 0 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-riscv, Frank Chang From: Frank Chang <frank.chang@sifive.com> This patchset makes ACLINT mtime to be writable as RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. Also, mtimecmp and mtime should be 32/64-bit memory accessible registers. ACLINT reset function is also added, which requires mtime to be resetable if we need to support core power-gating feature in the future. This patchset is the updated verion of: https://patchew.org/QEMU/20220126095448.2964-1-frank.chang@sifive.com/ Changelog: v3: * Forbid 8-byte write access to timecmp_hi and time_hi. * Add ACLINT reset function. v2: * Support 32/64-bit mtimecmp/mtime memory accesses. * Add .impl.[min|max]_access_size declaration. Frank Chang (3): hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT hw/intc: Make RISC-V ACLINT mtime MMIO register writable Jim Shu (1): hw/intc: riscv_aclint: Add reset function of ACLINT devices hw/intc/riscv_aclint.c | 144 ++++++++++++++++++++++++++------- include/hw/intc/riscv_aclint.h | 1 + target/riscv/cpu.h | 8 +- target/riscv/cpu_helper.c | 4 +- 4 files changed, 121 insertions(+), 36 deletions(-) -- 2.35.1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT 2022-04-19 9:08 ` frank.chang @ 2022-04-19 9:08 ` frank.chang -1 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Frank Chang, Anup Patel, Jim Shu, Alistair Francis, Bin Meng From: Frank Chang <frank.chang@sifive.com> If device's MemoryRegion doesn't have .impl.[min|max]_access_size declaration, the default access_size_min would be 1 byte and access_size_max would be 4 bytes (see: softmmu/memory.c). This will cause a 64-bit memory access to ACLINT to be splitted into two 32-bit memory accesses. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> --- hw/intc/riscv_aclint.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index e43b050e92..37e9ace801 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -208,6 +208,10 @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = { .valid = { .min_access_size = 4, .max_access_size = 8 + }, + .impl = { + .min_access_size = 4, + .max_access_size = 8, } }; -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT @ 2022-04-19 9:08 ` frank.chang 0 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Frank Chang, Alistair Francis, Jim Shu, Bin Meng, Anup Patel From: Frank Chang <frank.chang@sifive.com> If device's MemoryRegion doesn't have .impl.[min|max]_access_size declaration, the default access_size_min would be 1 byte and access_size_max would be 4 bytes (see: softmmu/memory.c). This will cause a 64-bit memory access to ACLINT to be splitted into two 32-bit memory accesses. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> --- hw/intc/riscv_aclint.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index e43b050e92..37e9ace801 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -208,6 +208,10 @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = { .valid = { .min_access_size = 4, .max_access_size = 8 + }, + .impl = { + .min_access_size = 4, + .max_access_size = 8, } }; -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/4] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT 2022-04-19 9:08 ` frank.chang @ 2022-04-19 9:08 ` frank.chang -1 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Frank Chang, Anup Patel, Jim Shu, Alistair Francis, Bin Meng From: Frank Chang <frank.chang@sifive.com> RISC-V privilege spec defines that: * In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part of the register. * For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are additionally supported and are atomic. It's possible to perform both 32/64-bit read/write accesses to both mtimecmp and mtime registers. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> --- hw/intc/riscv_aclint.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 37e9ace801..ad3c49706f 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -126,9 +126,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { - /* timecmp_lo */ + /* timecmp_lo for RV32/RV64 or timecmp for RV64 */ uint64_t timecmp = env->timecmp; - return timecmp & 0xFFFFFFFF; + return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp; } else if ((addr & 0x7) == 4) { /* timecmp_hi */ uint64_t timecmp = env->timecmp; @@ -139,8 +139,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, return 0; } } else if (addr == mtimer->time_base) { - /* time_lo */ - return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF; + /* time_lo for RV32/RV64 or timecmp for RV64 */ + uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); + return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; } else if (addr == mtimer->time_base + 4) { /* time_hi */ return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF; @@ -167,18 +168,29 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { - /* timecmp_lo */ - uint64_t timecmp_hi = env->timecmp >> 32; - riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - timecmp_hi << 32 | (value & 0xFFFFFFFF), - mtimer->timebase_freq); - return; + if (size == 4) { + /* timecmp_lo for RV32/RV64 */ + uint64_t timecmp_hi = env->timecmp >> 32; + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, + timecmp_hi << 32 | (value & 0xFFFFFFFF), + mtimer->timebase_freq); + } else { + /* timecmp for RV64 */ + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, + value, mtimer->timebase_freq); + } } else if ((addr & 0x7) == 4) { - /* timecmp_hi */ - uint64_t timecmp_lo = env->timecmp; - riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - value << 32 | (timecmp_lo & 0xFFFFFFFF), - mtimer->timebase_freq); + if (size == 4) { + /* timecmp_hi for RV32/RV64 */ + uint64_t timecmp_lo = env->timecmp; + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, + value << 32 | (timecmp_lo & 0xFFFFFFFF), + mtimer->timebase_freq); + } else { + qemu_log_mask(LOG_UNIMP, + "aclint-mtimer: invalid timecmp_hi write: %08x", + (uint32_t)addr); + } } else { qemu_log_mask(LOG_UNIMP, "aclint-mtimer: invalid timecmp write: %08x", -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/4] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT @ 2022-04-19 9:08 ` frank.chang 0 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Frank Chang, Alistair Francis, Jim Shu, Bin Meng, Anup Patel From: Frank Chang <frank.chang@sifive.com> RISC-V privilege spec defines that: * In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part of the register. * For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are additionally supported and are atomic. It's possible to perform both 32/64-bit read/write accesses to both mtimecmp and mtime registers. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> --- hw/intc/riscv_aclint.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 37e9ace801..ad3c49706f 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -126,9 +126,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { - /* timecmp_lo */ + /* timecmp_lo for RV32/RV64 or timecmp for RV64 */ uint64_t timecmp = env->timecmp; - return timecmp & 0xFFFFFFFF; + return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp; } else if ((addr & 0x7) == 4) { /* timecmp_hi */ uint64_t timecmp = env->timecmp; @@ -139,8 +139,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, return 0; } } else if (addr == mtimer->time_base) { - /* time_lo */ - return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF; + /* time_lo for RV32/RV64 or timecmp for RV64 */ + uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); + return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; } else if (addr == mtimer->time_base + 4) { /* time_hi */ return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF; @@ -167,18 +168,29 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { - /* timecmp_lo */ - uint64_t timecmp_hi = env->timecmp >> 32; - riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - timecmp_hi << 32 | (value & 0xFFFFFFFF), - mtimer->timebase_freq); - return; + if (size == 4) { + /* timecmp_lo for RV32/RV64 */ + uint64_t timecmp_hi = env->timecmp >> 32; + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, + timecmp_hi << 32 | (value & 0xFFFFFFFF), + mtimer->timebase_freq); + } else { + /* timecmp for RV64 */ + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, + value, mtimer->timebase_freq); + } } else if ((addr & 0x7) == 4) { - /* timecmp_hi */ - uint64_t timecmp_lo = env->timecmp; - riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - value << 32 | (timecmp_lo & 0xFFFFFFFF), - mtimer->timebase_freq); + if (size == 4) { + /* timecmp_hi for RV32/RV64 */ + uint64_t timecmp_lo = env->timecmp; + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, + value << 32 | (timecmp_lo & 0xFFFFFFFF), + mtimer->timebase_freq); + } else { + qemu_log_mask(LOG_UNIMP, + "aclint-mtimer: invalid timecmp_hi write: %08x", + (uint32_t)addr); + } } else { qemu_log_mask(LOG_UNIMP, "aclint-mtimer: invalid timecmp write: %08x", -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable 2022-04-19 9:08 ` frank.chang @ 2022-04-19 9:08 ` frank.chang -1 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: Anup Patel, qemu-riscv, Frank Chang, Bin Meng, Jim Shu, Palmer Dabbelt, Alistair Francis, LIU Zhiwei From: Frank Chang <frank.chang@sifive.com> RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. However, as QEMU uses host monotonic timer as timer source, this makes mtime to be read-only in RISC-V ACLINT. This patch makes mtime to be writable by recording the time delta value between the mtime value to be written and the timer value at the time mtime is written. Time delta value is then added back whenever the timer value is retrieved. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> --- hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++---------- include/hw/intc/riscv_aclint.h | 1 + target/riscv/cpu.h | 8 ++-- target/riscv/cpu_helper.c | 4 +- 4 files changed, 57 insertions(+), 27 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index ad3c49706f..ad7ccf96cd 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback { int num; } riscv_aclint_mtimer_callback; -static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) +static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), timebase_freq, NANOSECONDS_PER_SECOND); } +static uint64_t cpu_riscv_read_rtc(void *opaque) +{ + RISCVAclintMTimerState *mtimer = opaque; + return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta; +} + /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <= current timer value. @@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, RISCVCPU *cpu, int hartid, - uint64_t value, - uint32_t timebase_freq) + uint64_t value) { + uint32_t timebase_freq = mtimer->timebase_freq; uint64_t next; uint64_t diff; - uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); + uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); cpu->env.timecmp = value; if (cpu->env.timecmp <= rtc_r) { @@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, } } else if (addr == mtimer->time_base) { /* time_lo for RV32/RV64 or timecmp for RV64 */ - uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); + uint64_t rtc = cpu_riscv_read_rtc(mtimer); return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; } else if (addr == mtimer->time_base + 4) { /* time_hi */ - return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF; + return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; } qemu_log_mask(LOG_UNIMP, @@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { RISCVAclintMTimerState *mtimer = opaque; + int i; if (addr >= mtimer->timecmp_base && addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { @@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, /* timecmp_lo for RV32/RV64 */ uint64_t timecmp_hi = env->timecmp >> 32; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - timecmp_hi << 32 | (value & 0xFFFFFFFF), - mtimer->timebase_freq); + timecmp_hi << 32 | (value & 0xFFFFFFFF)); } else { /* timecmp for RV64 */ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - value, mtimer->timebase_freq); + value); } } else if ((addr & 0x7) == 4) { if (size == 4) { /* timecmp_hi for RV32/RV64 */ uint64_t timecmp_lo = env->timecmp; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - value << 32 | (timecmp_lo & 0xFFFFFFFF), - mtimer->timebase_freq); + value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { qemu_log_mask(LOG_UNIMP, "aclint-mtimer: invalid timecmp_hi write: %08x", @@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, (uint32_t)addr); } return; - } else if (addr == mtimer->time_base) { - /* time_lo */ - qemu_log_mask(LOG_UNIMP, - "aclint-mtimer: time_lo write not implemented"); - return; - } else if (addr == mtimer->time_base + 4) { - /* time_hi */ - qemu_log_mask(LOG_UNIMP, - "aclint-mtimer: time_hi write not implemented"); + } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) { + uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); + + if (addr == mtimer->time_base) { + if (size == 4) { + /* time_lo for RV32/RV64 */ + mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r; + } else { + /* time for RV64 */ + mtimer->time_delta = value - rtc_r; + } + } else { + if (size == 4) { + /* time_hi for RV32/RV64 */ + mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r; + } else { + qemu_log_mask(LOG_UNIMP, + "aclint-mtimer: invalid time_hi write: %08x", + (uint32_t)addr); + return; + } + } + + /* Check if timer interrupt is triggered for each hart. */ + for (i = 0; i < mtimer->num_harts; i++) { + CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); + CPURISCVState *env = cpu ? cpu->env_ptr : NULL; + if (!env) { + continue; + } + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), + i, env->timecmp); + } return; } @@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, continue; } if (provide_rdtime) { - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq); + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); } cb->s = RISCV_ACLINT_MTIMER(dev); diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 229bd08d25..26d4048687 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -31,6 +31,7 @@ typedef struct RISCVAclintMTimerState { /*< private >*/ SysBusDevice parent_obj; + uint64_t time_delta; /*< public >*/ MemoryRegion mmio; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 249fce4c3b..0cb7c2a05a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -286,8 +286,8 @@ struct CPUArchState { type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; /* machine specific rdtime callback */ - uint64_t (*rdtime_fn)(uint32_t); - uint32_t rdtime_fn_arg; + uint64_t (*rdtime_fn)(void *); + void *rdtime_fn_arg; /* machine specific AIA ireg read-modify-write callback */ #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ @@ -505,8 +505,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), - uint32_t arg); +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), + void *arg); void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, int (*rmw_fn)(void *arg, target_ulong reg, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b5bbe6fc39..51a3d96a66 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) return old; } -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), - uint32_t arg) +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), + void *arg) { env->rdtime_fn = fn; env->rdtime_fn_arg = arg; -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable @ 2022-04-19 9:08 ` frank.chang 0 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Frank Chang, Jim Shu, Palmer Dabbelt, Alistair Francis, Bin Meng, Anup Patel, LIU Zhiwei From: Frank Chang <frank.chang@sifive.com> RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. However, as QEMU uses host monotonic timer as timer source, this makes mtime to be read-only in RISC-V ACLINT. This patch makes mtime to be writable by recording the time delta value between the mtime value to be written and the timer value at the time mtime is written. Time delta value is then added back whenever the timer value is retrieved. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> --- hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++---------- include/hw/intc/riscv_aclint.h | 1 + target/riscv/cpu.h | 8 ++-- target/riscv/cpu_helper.c | 4 +- 4 files changed, 57 insertions(+), 27 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index ad3c49706f..ad7ccf96cd 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback { int num; } riscv_aclint_mtimer_callback; -static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) +static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), timebase_freq, NANOSECONDS_PER_SECOND); } +static uint64_t cpu_riscv_read_rtc(void *opaque) +{ + RISCVAclintMTimerState *mtimer = opaque; + return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta; +} + /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <= current timer value. @@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, RISCVCPU *cpu, int hartid, - uint64_t value, - uint32_t timebase_freq) + uint64_t value) { + uint32_t timebase_freq = mtimer->timebase_freq; uint64_t next; uint64_t diff; - uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); + uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); cpu->env.timecmp = value; if (cpu->env.timecmp <= rtc_r) { @@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, } } else if (addr == mtimer->time_base) { /* time_lo for RV32/RV64 or timecmp for RV64 */ - uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); + uint64_t rtc = cpu_riscv_read_rtc(mtimer); return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; } else if (addr == mtimer->time_base + 4) { /* time_hi */ - return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF; + return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; } qemu_log_mask(LOG_UNIMP, @@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { RISCVAclintMTimerState *mtimer = opaque; + int i; if (addr >= mtimer->timecmp_base && addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { @@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, /* timecmp_lo for RV32/RV64 */ uint64_t timecmp_hi = env->timecmp >> 32; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - timecmp_hi << 32 | (value & 0xFFFFFFFF), - mtimer->timebase_freq); + timecmp_hi << 32 | (value & 0xFFFFFFFF)); } else { /* timecmp for RV64 */ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - value, mtimer->timebase_freq); + value); } } else if ((addr & 0x7) == 4) { if (size == 4) { /* timecmp_hi for RV32/RV64 */ uint64_t timecmp_lo = env->timecmp; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, - value << 32 | (timecmp_lo & 0xFFFFFFFF), - mtimer->timebase_freq); + value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { qemu_log_mask(LOG_UNIMP, "aclint-mtimer: invalid timecmp_hi write: %08x", @@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, (uint32_t)addr); } return; - } else if (addr == mtimer->time_base) { - /* time_lo */ - qemu_log_mask(LOG_UNIMP, - "aclint-mtimer: time_lo write not implemented"); - return; - } else if (addr == mtimer->time_base + 4) { - /* time_hi */ - qemu_log_mask(LOG_UNIMP, - "aclint-mtimer: time_hi write not implemented"); + } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) { + uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); + + if (addr == mtimer->time_base) { + if (size == 4) { + /* time_lo for RV32/RV64 */ + mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r; + } else { + /* time for RV64 */ + mtimer->time_delta = value - rtc_r; + } + } else { + if (size == 4) { + /* time_hi for RV32/RV64 */ + mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r; + } else { + qemu_log_mask(LOG_UNIMP, + "aclint-mtimer: invalid time_hi write: %08x", + (uint32_t)addr); + return; + } + } + + /* Check if timer interrupt is triggered for each hart. */ + for (i = 0; i < mtimer->num_harts; i++) { + CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); + CPURISCVState *env = cpu ? cpu->env_ptr : NULL; + if (!env) { + continue; + } + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), + i, env->timecmp); + } return; } @@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, continue; } if (provide_rdtime) { - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq); + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); } cb->s = RISCV_ACLINT_MTIMER(dev); diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 229bd08d25..26d4048687 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -31,6 +31,7 @@ typedef struct RISCVAclintMTimerState { /*< private >*/ SysBusDevice parent_obj; + uint64_t time_delta; /*< public >*/ MemoryRegion mmio; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 249fce4c3b..0cb7c2a05a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -286,8 +286,8 @@ struct CPUArchState { type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; /* machine specific rdtime callback */ - uint64_t (*rdtime_fn)(uint32_t); - uint32_t rdtime_fn_arg; + uint64_t (*rdtime_fn)(void *); + void *rdtime_fn_arg; /* machine specific AIA ireg read-modify-write callback */ #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ @@ -505,8 +505,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), - uint32_t arg); +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), + void *arg); void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, int (*rmw_fn)(void *arg, target_ulong reg, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b5bbe6fc39..51a3d96a66 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) return old; } -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), - uint32_t arg) +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), + void *arg) { env->rdtime_fn = fn; env->rdtime_fn_arg = arg; -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable 2022-04-19 9:08 ` frank.chang @ 2022-04-20 7:42 ` Alistair Francis -1 siblings, 0 replies; 16+ messages in thread From: Alistair Francis @ 2022-04-20 7:42 UTC (permalink / raw) To: Frank Chang Cc: Anup Patel, open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers, Jim Shu, Palmer Dabbelt, Alistair Francis, LIU Zhiwei On Tue, Apr 19, 2022 at 7:10 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > RISC-V privilege spec defines that mtime is exposed as a memory-mapped > machine-mode read-write register. However, as QEMU uses host monotonic > timer as timer source, this makes mtime to be read-only in RISC-V > ACLINT. > > This patch makes mtime to be writable by recording the time delta value > between the mtime value to be written and the timer value at the time > mtime is written. Time delta value is then added back whenever the timer > value is retrieved. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> > --- > hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++---------- > include/hw/intc/riscv_aclint.h | 1 + > target/riscv/cpu.h | 8 ++-- > target/riscv/cpu_helper.c | 4 +- > 4 files changed, 57 insertions(+), 27 deletions(-) > > diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c > index ad3c49706f..ad7ccf96cd 100644 > --- a/hw/intc/riscv_aclint.c > +++ b/hw/intc/riscv_aclint.c > @@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback { > int num; > } riscv_aclint_mtimer_callback; > > -static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) > +static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) > { > return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), > timebase_freq, NANOSECONDS_PER_SECOND); > } > > +static uint64_t cpu_riscv_read_rtc(void *opaque) > +{ > + RISCVAclintMTimerState *mtimer = opaque; > + return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta; > +} > + > /* > * Called when timecmp is written to update the QEMU timer or immediately > * trigger timer interrupt if mtimecmp <= current timer value. > @@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) > static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, > RISCVCPU *cpu, > int hartid, > - uint64_t value, > - uint32_t timebase_freq) > + uint64_t value) > { > + uint32_t timebase_freq = mtimer->timebase_freq; > uint64_t next; > uint64_t diff; > > - uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); > + uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); > > cpu->env.timecmp = value; > if (cpu->env.timecmp <= rtc_r) { > @@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, > } > } else if (addr == mtimer->time_base) { > /* time_lo for RV32/RV64 or timecmp for RV64 */ > - uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); > + uint64_t rtc = cpu_riscv_read_rtc(mtimer); > return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; > } else if (addr == mtimer->time_base + 4) { > /* time_hi */ > - return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF; > + return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; > } > > qemu_log_mask(LOG_UNIMP, > @@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, > uint64_t value, unsigned size) > { > RISCVAclintMTimerState *mtimer = opaque; > + int i; > > if (addr >= mtimer->timecmp_base && > addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { > @@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, > /* timecmp_lo for RV32/RV64 */ > uint64_t timecmp_hi = env->timecmp >> 32; > riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, > - timecmp_hi << 32 | (value & 0xFFFFFFFF), > - mtimer->timebase_freq); > + timecmp_hi << 32 | (value & 0xFFFFFFFF)); > } else { > /* timecmp for RV64 */ > riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, > - value, mtimer->timebase_freq); > + value); > } > } else if ((addr & 0x7) == 4) { > if (size == 4) { > /* timecmp_hi for RV32/RV64 */ > uint64_t timecmp_lo = env->timecmp; > riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, > - value << 32 | (timecmp_lo & 0xFFFFFFFF), > - mtimer->timebase_freq); > + value << 32 | (timecmp_lo & 0xFFFFFFFF)); > } else { > qemu_log_mask(LOG_UNIMP, > "aclint-mtimer: invalid timecmp_hi write: %08x", > @@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, > (uint32_t)addr); > } > return; > - } else if (addr == mtimer->time_base) { > - /* time_lo */ > - qemu_log_mask(LOG_UNIMP, > - "aclint-mtimer: time_lo write not implemented"); > - return; > - } else if (addr == mtimer->time_base + 4) { > - /* time_hi */ > - qemu_log_mask(LOG_UNIMP, > - "aclint-mtimer: time_hi write not implemented"); > + } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) { > + uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); > + > + if (addr == mtimer->time_base) { > + if (size == 4) { > + /* time_lo for RV32/RV64 */ > + mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r; > + } else { > + /* time for RV64 */ > + mtimer->time_delta = value - rtc_r; > + } > + } else { > + if (size == 4) { > + /* time_hi for RV32/RV64 */ > + mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r; > + } else { > + qemu_log_mask(LOG_UNIMP, This should be a guest error instead Otherwise: Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > + "aclint-mtimer: invalid time_hi write: %08x", > + (uint32_t)addr); > + return; > + } > + } > + > + /* Check if timer interrupt is triggered for each hart. */ > + for (i = 0; i < mtimer->num_harts; i++) { > + CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); > + CPURISCVState *env = cpu ? cpu->env_ptr : NULL; > + if (!env) { > + continue; > + } > + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), > + i, env->timecmp); > + } > return; > } > > @@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, > continue; > } > if (provide_rdtime) { > - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq); > + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); > } > > cb->s = RISCV_ACLINT_MTIMER(dev); > diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h > index 229bd08d25..26d4048687 100644 > --- a/include/hw/intc/riscv_aclint.h > +++ b/include/hw/intc/riscv_aclint.h > @@ -31,6 +31,7 @@ > typedef struct RISCVAclintMTimerState { > /*< private >*/ > SysBusDevice parent_obj; > + uint64_t time_delta; > > /*< public >*/ > MemoryRegion mmio; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 249fce4c3b..0cb7c2a05a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -286,8 +286,8 @@ struct CPUArchState { > type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; > > /* machine specific rdtime callback */ > - uint64_t (*rdtime_fn)(uint32_t); > - uint32_t rdtime_fn_arg; > + uint64_t (*rdtime_fn)(void *); > + void *rdtime_fn_arg; > > /* machine specific AIA ireg read-modify-write callback */ > #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ > @@ -505,8 +505,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); > uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > - uint32_t arg); > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > + void *arg); > void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > int (*rmw_fn)(void *arg, > target_ulong reg, > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b5bbe6fc39..51a3d96a66 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) > return old; > } > > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > - uint32_t arg) > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > + void *arg) > { > env->rdtime_fn = fn; > env->rdtime_fn_arg = arg; > -- > 2.35.1 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable @ 2022-04-20 7:42 ` Alistair Francis 0 siblings, 0 replies; 16+ messages in thread From: Alistair Francis @ 2022-04-20 7:42 UTC (permalink / raw) To: Frank Chang Cc: qemu-devel@nongnu.org Developers, Anup Patel, open list:RISC-V, Bin Meng, Jim Shu, Palmer Dabbelt, Alistair Francis, LIU Zhiwei On Tue, Apr 19, 2022 at 7:10 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > RISC-V privilege spec defines that mtime is exposed as a memory-mapped > machine-mode read-write register. However, as QEMU uses host monotonic > timer as timer source, this makes mtime to be read-only in RISC-V > ACLINT. > > This patch makes mtime to be writable by recording the time delta value > between the mtime value to be written and the timer value at the time > mtime is written. Time delta value is then added back whenever the timer > value is retrieved. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Jim Shu <jim.shu@sifive.com> > --- > hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++---------- > include/hw/intc/riscv_aclint.h | 1 + > target/riscv/cpu.h | 8 ++-- > target/riscv/cpu_helper.c | 4 +- > 4 files changed, 57 insertions(+), 27 deletions(-) > > diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c > index ad3c49706f..ad7ccf96cd 100644 > --- a/hw/intc/riscv_aclint.c > +++ b/hw/intc/riscv_aclint.c > @@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback { > int num; > } riscv_aclint_mtimer_callback; > > -static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) > +static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) > { > return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), > timebase_freq, NANOSECONDS_PER_SECOND); > } > > +static uint64_t cpu_riscv_read_rtc(void *opaque) > +{ > + RISCVAclintMTimerState *mtimer = opaque; > + return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_delta; > +} > + > /* > * Called when timecmp is written to update the QEMU timer or immediately > * trigger timer interrupt if mtimecmp <= current timer value. > @@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) > static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtimer, > RISCVCPU *cpu, > int hartid, > - uint64_t value, > - uint32_t timebase_freq) > + uint64_t value) > { > + uint32_t timebase_freq = mtimer->timebase_freq; > uint64_t next; > uint64_t diff; > > - uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); > + uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); > > cpu->env.timecmp = value; > if (cpu->env.timecmp <= rtc_r) { > @@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr, > } > } else if (addr == mtimer->time_base) { > /* time_lo for RV32/RV64 or timecmp for RV64 */ > - uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); > + uint64_t rtc = cpu_riscv_read_rtc(mtimer); > return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; > } else if (addr == mtimer->time_base + 4) { > /* time_hi */ > - return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFFFFF; > + return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; > } > > qemu_log_mask(LOG_UNIMP, > @@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, > uint64_t value, unsigned size) > { > RISCVAclintMTimerState *mtimer = opaque; > + int i; > > if (addr >= mtimer->timecmp_base && > addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { > @@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, > /* timecmp_lo for RV32/RV64 */ > uint64_t timecmp_hi = env->timecmp >> 32; > riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, > - timecmp_hi << 32 | (value & 0xFFFFFFFF), > - mtimer->timebase_freq); > + timecmp_hi << 32 | (value & 0xFFFFFFFF)); > } else { > /* timecmp for RV64 */ > riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, > - value, mtimer->timebase_freq); > + value); > } > } else if ((addr & 0x7) == 4) { > if (size == 4) { > /* timecmp_hi for RV32/RV64 */ > uint64_t timecmp_lo = env->timecmp; > riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid, > - value << 32 | (timecmp_lo & 0xFFFFFFFF), > - mtimer->timebase_freq); > + value << 32 | (timecmp_lo & 0xFFFFFFFF)); > } else { > qemu_log_mask(LOG_UNIMP, > "aclint-mtimer: invalid timecmp_hi write: %08x", > @@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, > (uint32_t)addr); > } > return; > - } else if (addr == mtimer->time_base) { > - /* time_lo */ > - qemu_log_mask(LOG_UNIMP, > - "aclint-mtimer: time_lo write not implemented"); > - return; > - } else if (addr == mtimer->time_base + 4) { > - /* time_hi */ > - qemu_log_mask(LOG_UNIMP, > - "aclint-mtimer: time_hi write not implemented"); > + } else if (addr == mtimer->time_base || addr == mtimer->time_base + 4) { > + uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); > + > + if (addr == mtimer->time_base) { > + if (size == 4) { > + /* time_lo for RV32/RV64 */ > + mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) - rtc_r; > + } else { > + /* time for RV64 */ > + mtimer->time_delta = value - rtc_r; > + } > + } else { > + if (size == 4) { > + /* time_hi for RV32/RV64 */ > + mtimer->time_delta = (value << 32 | (rtc_r & 0xFFFFFFFF)) - rtc_r; > + } else { > + qemu_log_mask(LOG_UNIMP, This should be a guest error instead Otherwise: Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > + "aclint-mtimer: invalid time_hi write: %08x", > + (uint32_t)addr); > + return; > + } > + } > + > + /* Check if timer interrupt is triggered for each hart. */ > + for (i = 0; i < mtimer->num_harts; i++) { > + CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); > + CPURISCVState *env = cpu ? cpu->env_ptr : NULL; > + if (!env) { > + continue; > + } > + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), > + i, env->timecmp); > + } > return; > } > > @@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size, > continue; > } > if (provide_rdtime) { > - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq); > + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); > } > > cb->s = RISCV_ACLINT_MTIMER(dev); > diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h > index 229bd08d25..26d4048687 100644 > --- a/include/hw/intc/riscv_aclint.h > +++ b/include/hw/intc/riscv_aclint.h > @@ -31,6 +31,7 @@ > typedef struct RISCVAclintMTimerState { > /*< private >*/ > SysBusDevice parent_obj; > + uint64_t time_delta; > > /*< public >*/ > MemoryRegion mmio; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 249fce4c3b..0cb7c2a05a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -286,8 +286,8 @@ struct CPUArchState { > type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; > > /* machine specific rdtime callback */ > - uint64_t (*rdtime_fn)(uint32_t); > - uint32_t rdtime_fn_arg; > + uint64_t (*rdtime_fn)(void *); > + void *rdtime_fn_arg; > > /* machine specific AIA ireg read-modify-write callback */ > #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ > @@ -505,8 +505,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); > uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > - uint32_t arg); > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > + void *arg); > void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > int (*rmw_fn)(void *arg, > target_ulong reg, > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b5bbe6fc39..51a3d96a66 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) > return old; > } > > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), > - uint32_t arg) > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > + void *arg) > { > env->rdtime_fn = fn; > env->rdtime_fn_arg = arg; > -- > 2.35.1 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable 2022-04-20 7:42 ` Alistair Francis @ 2022-04-20 7:53 ` Frank Chang -1 siblings, 0 replies; 16+ messages in thread From: Frank Chang @ 2022-04-20 7:53 UTC (permalink / raw) To: Alistair Francis Cc: Anup Patel, open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers, Jim Shu, Palmer Dabbelt, Alistair Francis, LIU Zhiwei [-- Attachment #1: Type: text/plain, Size: 10462 bytes --] On Wed, Apr 20, 2022 at 3:42 PM Alistair Francis <alistair23@gmail.com> wrote: > On Tue, Apr 19, 2022 at 7:10 PM <frank.chang@sifive.com> wrote: > > > > From: Frank Chang <frank.chang@sifive.com> > > > > RISC-V privilege spec defines that mtime is exposed as a memory-mapped > > machine-mode read-write register. However, as QEMU uses host monotonic > > timer as timer source, this makes mtime to be read-only in RISC-V > > ACLINT. > > > > This patch makes mtime to be writable by recording the time delta value > > between the mtime value to be written and the timer value at the time > > mtime is written. Time delta value is then added back whenever the timer > > value is retrieved. > > > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > > Reviewed-by: Jim Shu <jim.shu@sifive.com> > > --- > > hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++---------- > > include/hw/intc/riscv_aclint.h | 1 + > > target/riscv/cpu.h | 8 ++-- > > target/riscv/cpu_helper.c | 4 +- > > 4 files changed, 57 insertions(+), 27 deletions(-) > > > > diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c > > index ad3c49706f..ad7ccf96cd 100644 > > --- a/hw/intc/riscv_aclint.c > > +++ b/hw/intc/riscv_aclint.c > > @@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback { > > int num; > > } riscv_aclint_mtimer_callback; > > > > -static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) > > +static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) > > { > > return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), > > timebase_freq, NANOSECONDS_PER_SECOND); > > } > > > > +static uint64_t cpu_riscv_read_rtc(void *opaque) > > +{ > > + RISCVAclintMTimerState *mtimer = opaque; > > + return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + > mtimer->time_delta; > > +} > > + > > /* > > * Called when timecmp is written to update the QEMU timer or > immediately > > * trigger timer interrupt if mtimecmp <= current timer value. > > @@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t > timebase_freq) > > static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState > *mtimer, > > RISCVCPU *cpu, > > int hartid, > > - uint64_t value, > > - uint32_t timebase_freq) > > + uint64_t value) > > { > > + uint32_t timebase_freq = mtimer->timebase_freq; > > uint64_t next; > > uint64_t diff; > > > > - uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); > > + uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); > > > > cpu->env.timecmp = value; > > if (cpu->env.timecmp <= rtc_r) { > > @@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void > *opaque, hwaddr addr, > > } > > } else if (addr == mtimer->time_base) { > > /* time_lo for RV32/RV64 or timecmp for RV64 */ > > - uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); > > + uint64_t rtc = cpu_riscv_read_rtc(mtimer); > > return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; > > } else if (addr == mtimer->time_base + 4) { > > /* time_hi */ > > - return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & > 0xFFFFFFFF; > > + return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; > > } > > > > qemu_log_mask(LOG_UNIMP, > > @@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, > hwaddr addr, > > uint64_t value, unsigned size) > > { > > RISCVAclintMTimerState *mtimer = opaque; > > + int i; > > > > if (addr >= mtimer->timecmp_base && > > addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { > > @@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void > *opaque, hwaddr addr, > > /* timecmp_lo for RV32/RV64 */ > > uint64_t timecmp_hi = env->timecmp >> 32; > > riscv_aclint_mtimer_write_timecmp(mtimer, > RISCV_CPU(cpu), hartid, > > - timecmp_hi << 32 | (value & 0xFFFFFFFF), > > - mtimer->timebase_freq); > > + timecmp_hi << 32 | (value & 0xFFFFFFFF)); > > } else { > > /* timecmp for RV64 */ > > riscv_aclint_mtimer_write_timecmp(mtimer, > RISCV_CPU(cpu), hartid, > > - value, > mtimer->timebase_freq); > > + value); > > } > > } else if ((addr & 0x7) == 4) { > > if (size == 4) { > > /* timecmp_hi for RV32/RV64 */ > > uint64_t timecmp_lo = env->timecmp; > > riscv_aclint_mtimer_write_timecmp(mtimer, > RISCV_CPU(cpu), hartid, > > - value << 32 | (timecmp_lo & 0xFFFFFFFF), > > - mtimer->timebase_freq); > > + value << 32 | (timecmp_lo & 0xFFFFFFFF)); > > } else { > > qemu_log_mask(LOG_UNIMP, > > "aclint-mtimer: invalid timecmp_hi write: > %08x", > > @@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void > *opaque, hwaddr addr, > > (uint32_t)addr); > > } > > return; > > - } else if (addr == mtimer->time_base) { > > - /* time_lo */ > > - qemu_log_mask(LOG_UNIMP, > > - "aclint-mtimer: time_lo write not implemented"); > > - return; > > - } else if (addr == mtimer->time_base + 4) { > > - /* time_hi */ > > - qemu_log_mask(LOG_UNIMP, > > - "aclint-mtimer: time_hi write not implemented"); > > + } else if (addr == mtimer->time_base || addr == mtimer->time_base + > 4) { > > + uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); > > + > > + if (addr == mtimer->time_base) { > > + if (size == 4) { > > + /* time_lo for RV32/RV64 */ > > + mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) > - rtc_r; > > + } else { > > + /* time for RV64 */ > > + mtimer->time_delta = value - rtc_r; > > + } > > + } else { > > + if (size == 4) { > > + /* time_hi for RV32/RV64 */ > > + mtimer->time_delta = (value << 32 | (rtc_r & > 0xFFFFFFFF)) - rtc_r; > > + } else { > > + qemu_log_mask(LOG_UNIMP, > > This should be a guest error instead > Thanks, I'll fix this in the next version patchset. Regards, Frank Chang > > Otherwise: > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > Alistair > > > + "aclint-mtimer: invalid time_hi write: > %08x", > > + (uint32_t)addr); > > + return; > > + } > > + } > > + > > + /* Check if timer interrupt is triggered for each hart. */ > > + for (i = 0; i < mtimer->num_harts; i++) { > > + CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); > > + CPURISCVState *env = cpu ? cpu->env_ptr : NULL; > > + if (!env) { > > + continue; > > + } > > + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), > > + i, env->timecmp); > > + } > > return; > > } > > > > @@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, > hwaddr size, > > continue; > > } > > if (provide_rdtime) { > > - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, > timebase_freq); > > + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); > > } > > > > cb->s = RISCV_ACLINT_MTIMER(dev); > > diff --git a/include/hw/intc/riscv_aclint.h > b/include/hw/intc/riscv_aclint.h > > index 229bd08d25..26d4048687 100644 > > --- a/include/hw/intc/riscv_aclint.h > > +++ b/include/hw/intc/riscv_aclint.h > > @@ -31,6 +31,7 @@ > > typedef struct RISCVAclintMTimerState { > > /*< private >*/ > > SysBusDevice parent_obj; > > + uint64_t time_delta; > > > > /*< public >*/ > > MemoryRegion mmio; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 249fce4c3b..0cb7c2a05a 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -286,8 +286,8 @@ struct CPUArchState { > > type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; > > > > /* machine specific rdtime callback */ > > - uint64_t (*rdtime_fn)(uint32_t); > > - uint32_t rdtime_fn_arg; > > + uint64_t (*rdtime_fn)(void *); > > + void *rdtime_fn_arg; > > > > /* machine specific AIA ireg read-modify-write callback */ > > #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ > > @@ -505,8 +505,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState > *env); > > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); > > uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t > value); > > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip > value */ > > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t > (*fn)(uint32_t), > > - uint32_t arg); > > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > > + void *arg); > > void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > > int (*rmw_fn)(void *arg, > > target_ulong reg, > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index b5bbe6fc39..51a3d96a66 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, > uint64_t mask, uint64_t value) > > return old; > > } > > > > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t > (*fn)(uint32_t), > > - uint32_t arg) > > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > > + void *arg) > > { > > env->rdtime_fn = fn; > > env->rdtime_fn_arg = arg; > > -- > > 2.35.1 > > > > > [-- Attachment #2: Type: text/html, Size: 13824 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable @ 2022-04-20 7:53 ` Frank Chang 0 siblings, 0 replies; 16+ messages in thread From: Frank Chang @ 2022-04-20 7:53 UTC (permalink / raw) To: Alistair Francis Cc: qemu-devel@nongnu.org Developers, Anup Patel, open list:RISC-V, Bin Meng, Jim Shu, Palmer Dabbelt, Alistair Francis, LIU Zhiwei [-- Attachment #1: Type: text/plain, Size: 10462 bytes --] On Wed, Apr 20, 2022 at 3:42 PM Alistair Francis <alistair23@gmail.com> wrote: > On Tue, Apr 19, 2022 at 7:10 PM <frank.chang@sifive.com> wrote: > > > > From: Frank Chang <frank.chang@sifive.com> > > > > RISC-V privilege spec defines that mtime is exposed as a memory-mapped > > machine-mode read-write register. However, as QEMU uses host monotonic > > timer as timer source, this makes mtime to be read-only in RISC-V > > ACLINT. > > > > This patch makes mtime to be writable by recording the time delta value > > between the mtime value to be written and the timer value at the time > > mtime is written. Time delta value is then added back whenever the timer > > value is retrieved. > > > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > > Reviewed-by: Jim Shu <jim.shu@sifive.com> > > --- > > hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++---------- > > include/hw/intc/riscv_aclint.h | 1 + > > target/riscv/cpu.h | 8 ++-- > > target/riscv/cpu_helper.c | 4 +- > > 4 files changed, 57 insertions(+), 27 deletions(-) > > > > diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c > > index ad3c49706f..ad7ccf96cd 100644 > > --- a/hw/intc/riscv_aclint.c > > +++ b/hw/intc/riscv_aclint.c > > @@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback { > > int num; > > } riscv_aclint_mtimer_callback; > > > > -static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) > > +static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) > > { > > return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), > > timebase_freq, NANOSECONDS_PER_SECOND); > > } > > > > +static uint64_t cpu_riscv_read_rtc(void *opaque) > > +{ > > + RISCVAclintMTimerState *mtimer = opaque; > > + return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + > mtimer->time_delta; > > +} > > + > > /* > > * Called when timecmp is written to update the QEMU timer or > immediately > > * trigger timer interrupt if mtimecmp <= current timer value. > > @@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t > timebase_freq) > > static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState > *mtimer, > > RISCVCPU *cpu, > > int hartid, > > - uint64_t value, > > - uint32_t timebase_freq) > > + uint64_t value) > > { > > + uint32_t timebase_freq = mtimer->timebase_freq; > > uint64_t next; > > uint64_t diff; > > > > - uint64_t rtc_r = cpu_riscv_read_rtc(timebase_freq); > > + uint64_t rtc_r = cpu_riscv_read_rtc(mtimer); > > > > cpu->env.timecmp = value; > > if (cpu->env.timecmp <= rtc_r) { > > @@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void > *opaque, hwaddr addr, > > } > > } else if (addr == mtimer->time_base) { > > /* time_lo for RV32/RV64 or timecmp for RV64 */ > > - uint64_t rtc = cpu_riscv_read_rtc(mtimer->timebase_freq); > > + uint64_t rtc = cpu_riscv_read_rtc(mtimer); > > return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; > > } else if (addr == mtimer->time_base + 4) { > > /* time_hi */ > > - return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & > 0xFFFFFFFF; > > + return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; > > } > > > > qemu_log_mask(LOG_UNIMP, > > @@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, > hwaddr addr, > > uint64_t value, unsigned size) > > { > > RISCVAclintMTimerState *mtimer = opaque; > > + int i; > > > > if (addr >= mtimer->timecmp_base && > > addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { > > @@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void > *opaque, hwaddr addr, > > /* timecmp_lo for RV32/RV64 */ > > uint64_t timecmp_hi = env->timecmp >> 32; > > riscv_aclint_mtimer_write_timecmp(mtimer, > RISCV_CPU(cpu), hartid, > > - timecmp_hi << 32 | (value & 0xFFFFFFFF), > > - mtimer->timebase_freq); > > + timecmp_hi << 32 | (value & 0xFFFFFFFF)); > > } else { > > /* timecmp for RV64 */ > > riscv_aclint_mtimer_write_timecmp(mtimer, > RISCV_CPU(cpu), hartid, > > - value, > mtimer->timebase_freq); > > + value); > > } > > } else if ((addr & 0x7) == 4) { > > if (size == 4) { > > /* timecmp_hi for RV32/RV64 */ > > uint64_t timecmp_lo = env->timecmp; > > riscv_aclint_mtimer_write_timecmp(mtimer, > RISCV_CPU(cpu), hartid, > > - value << 32 | (timecmp_lo & 0xFFFFFFFF), > > - mtimer->timebase_freq); > > + value << 32 | (timecmp_lo & 0xFFFFFFFF)); > > } else { > > qemu_log_mask(LOG_UNIMP, > > "aclint-mtimer: invalid timecmp_hi write: > %08x", > > @@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void > *opaque, hwaddr addr, > > (uint32_t)addr); > > } > > return; > > - } else if (addr == mtimer->time_base) { > > - /* time_lo */ > > - qemu_log_mask(LOG_UNIMP, > > - "aclint-mtimer: time_lo write not implemented"); > > - return; > > - } else if (addr == mtimer->time_base + 4) { > > - /* time_hi */ > > - qemu_log_mask(LOG_UNIMP, > > - "aclint-mtimer: time_hi write not implemented"); > > + } else if (addr == mtimer->time_base || addr == mtimer->time_base + > 4) { > > + uint64_t rtc_r = cpu_riscv_read_rtc_raw(mtimer->timebase_freq); > > + > > + if (addr == mtimer->time_base) { > > + if (size == 4) { > > + /* time_lo for RV32/RV64 */ > > + mtimer->time_delta = ((rtc_r & ~0xFFFFFFFFULL) | value) > - rtc_r; > > + } else { > > + /* time for RV64 */ > > + mtimer->time_delta = value - rtc_r; > > + } > > + } else { > > + if (size == 4) { > > + /* time_hi for RV32/RV64 */ > > + mtimer->time_delta = (value << 32 | (rtc_r & > 0xFFFFFFFF)) - rtc_r; > > + } else { > > + qemu_log_mask(LOG_UNIMP, > > This should be a guest error instead > Thanks, I'll fix this in the next version patchset. Regards, Frank Chang > > Otherwise: > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > Alistair > > > + "aclint-mtimer: invalid time_hi write: > %08x", > > + (uint32_t)addr); > > + return; > > + } > > + } > > + > > + /* Check if timer interrupt is triggered for each hart. */ > > + for (i = 0; i < mtimer->num_harts; i++) { > > + CPUState *cpu = qemu_get_cpu(mtimer->hartid_base + i); > > + CPURISCVState *env = cpu ? cpu->env_ptr : NULL; > > + if (!env) { > > + continue; > > + } > > + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), > > + i, env->timecmp); > > + } > > return; > > } > > > > @@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, > hwaddr size, > > continue; > > } > > if (provide_rdtime) { > > - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, > timebase_freq); > > + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); > > } > > > > cb->s = RISCV_ACLINT_MTIMER(dev); > > diff --git a/include/hw/intc/riscv_aclint.h > b/include/hw/intc/riscv_aclint.h > > index 229bd08d25..26d4048687 100644 > > --- a/include/hw/intc/riscv_aclint.h > > +++ b/include/hw/intc/riscv_aclint.h > > @@ -31,6 +31,7 @@ > > typedef struct RISCVAclintMTimerState { > > /*< private >*/ > > SysBusDevice parent_obj; > > + uint64_t time_delta; > > > > /*< public >*/ > > MemoryRegion mmio; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 249fce4c3b..0cb7c2a05a 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -286,8 +286,8 @@ struct CPUArchState { > > type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; > > > > /* machine specific rdtime callback */ > > - uint64_t (*rdtime_fn)(uint32_t); > > - uint32_t rdtime_fn_arg; > > + uint64_t (*rdtime_fn)(void *); > > + void *rdtime_fn_arg; > > > > /* machine specific AIA ireg read-modify-write callback */ > > #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ > > @@ -505,8 +505,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState > *env); > > int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); > > uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t > value); > > #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip > value */ > > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t > (*fn)(uint32_t), > > - uint32_t arg); > > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > > + void *arg); > > void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, > > int (*rmw_fn)(void *arg, > > target_ulong reg, > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index b5bbe6fc39..51a3d96a66 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, > uint64_t mask, uint64_t value) > > return old; > > } > > > > -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t > (*fn)(uint32_t), > > - uint32_t arg) > > +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), > > + void *arg) > > { > > env->rdtime_fn = fn; > > env->rdtime_fn_arg = arg; > > -- > > 2.35.1 > > > > > [-- Attachment #2: Type: text/html, Size: 13824 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices 2022-04-19 9:08 ` frank.chang @ 2022-04-19 9:08 ` frank.chang -1 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Frank Chang, Anup Patel, Jim Shu, Alistair Francis, Bin Meng From: Jim Shu <jim.shu@sifive.com> This commit implements reset function of all ACLINT devices. ACLINT device reset will clear MTIME and MSIP register to 0. Depend on RISC-V ACLINT spec v1.0-rc4: https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> --- hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index ad7ccf96cd..67a07bb5b9 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) } } +static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MTIMER device reset, the MTIME register is cleared to zero. + * - On MTIMER device reset, the MTIMECMP registers are in unknown state. + */ + RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj); + + /* + * Clear mtime register by writing to 0 it. + * Pending mtime interrupts will also be cleared at the same time. + */ + riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); +} + static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = riscv_aclint_mtimer_realize; device_class_set_props(dc, riscv_aclint_mtimer_properties); + ResettableClass *rc = RESETTABLE_CLASS(klass); + rc->phases.enter = riscv_aclint_mtimer_reset_enter; } static const TypeInfo riscv_aclint_mtimer_info = { @@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) } } +static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MSWI device reset, each MSIP register is cleared to zero. + * + * p.s. SSWI device reset does nothing since SETSIP register always reads 0. + */ + RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj); + int i; + + if (!swi->sswi) { + for (i = 0; i < swi->num_harts; i++) { + /* Clear MSIP registers by lowering software interrupts. */ + qemu_irq_lower(swi->soft_irqs[i]); + } + } +} + static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = riscv_aclint_swi_realize; device_class_set_props(dc, riscv_aclint_swi_properties); + ResettableClass *rc = RESETTABLE_CLASS(klass); + rc->phases.enter = riscv_aclint_swi_reset_enter; } static const TypeInfo riscv_aclint_swi_info = { -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices @ 2022-04-19 9:08 ` frank.chang 0 siblings, 0 replies; 16+ messages in thread From: frank.chang @ 2022-04-19 9:08 UTC (permalink / raw) To: qemu-devel Cc: qemu-riscv, Jim Shu, Frank Chang, Alistair Francis, Bin Meng, Anup Patel From: Jim Shu <jim.shu@sifive.com> This commit implements reset function of all ACLINT devices. ACLINT device reset will clear MTIME and MSIP register to 0. Depend on RISC-V ACLINT spec v1.0-rc4: https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> --- hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index ad7ccf96cd..67a07bb5b9 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) } } +static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MTIMER device reset, the MTIME register is cleared to zero. + * - On MTIMER device reset, the MTIMECMP registers are in unknown state. + */ + RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj); + + /* + * Clear mtime register by writing to 0 it. + * Pending mtime interrupts will also be cleared at the same time. + */ + riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); +} + static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = riscv_aclint_mtimer_realize; device_class_set_props(dc, riscv_aclint_mtimer_properties); + ResettableClass *rc = RESETTABLE_CLASS(klass); + rc->phases.enter = riscv_aclint_mtimer_reset_enter; } static const TypeInfo riscv_aclint_mtimer_info = { @@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) } } +static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MSWI device reset, each MSIP register is cleared to zero. + * + * p.s. SSWI device reset does nothing since SETSIP register always reads 0. + */ + RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj); + int i; + + if (!swi->sswi) { + for (i = 0; i < swi->num_harts; i++) { + /* Clear MSIP registers by lowering software interrupts. */ + qemu_irq_lower(swi->soft_irqs[i]); + } + } +} + static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = riscv_aclint_swi_realize; device_class_set_props(dc, riscv_aclint_swi_properties); + ResettableClass *rc = RESETTABLE_CLASS(klass); + rc->phases.enter = riscv_aclint_swi_reset_enter; } static const TypeInfo riscv_aclint_swi_info = { -- 2.35.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices 2022-04-19 9:08 ` frank.chang @ 2022-04-20 7:43 ` Alistair Francis -1 siblings, 0 replies; 16+ messages in thread From: Alistair Francis @ 2022-04-20 7:43 UTC (permalink / raw) To: Frank Chang Cc: open list:RISC-V, Anup Patel, qemu-devel@nongnu.org Developers, Jim Shu, Alistair Francis, Bin Meng On Tue, Apr 19, 2022 at 7:29 PM <frank.chang@sifive.com> wrote: > > From: Jim Shu <jim.shu@sifive.com> > > This commit implements reset function of all ACLINT devices. > ACLINT device reset will clear MTIME and MSIP register to 0. > > Depend on RISC-V ACLINT spec v1.0-rc4: > https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc > > Signed-off-by: Jim Shu <jim.shu@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c > index ad7ccf96cd..67a07bb5b9 100644 > --- a/hw/intc/riscv_aclint.c > +++ b/hw/intc/riscv_aclint.c > @@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) > } > } > > +static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) > +{ > + /* > + * According to RISC-V ACLINT spec: > + * - On MTIMER device reset, the MTIME register is cleared to zero. > + * - On MTIMER device reset, the MTIMECMP registers are in unknown state. > + */ > + RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj); > + > + /* > + * Clear mtime register by writing to 0 it. > + * Pending mtime interrupts will also be cleared at the same time. > + */ > + riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); > +} > + > static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > dc->realize = riscv_aclint_mtimer_realize; > device_class_set_props(dc, riscv_aclint_mtimer_properties); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + rc->phases.enter = riscv_aclint_mtimer_reset_enter; > } > > static const TypeInfo riscv_aclint_mtimer_info = { > @@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) > } > } > > +static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) > +{ > + /* > + * According to RISC-V ACLINT spec: > + * - On MSWI device reset, each MSIP register is cleared to zero. > + * > + * p.s. SSWI device reset does nothing since SETSIP register always reads 0. > + */ > + RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj); > + int i; > + > + if (!swi->sswi) { > + for (i = 0; i < swi->num_harts; i++) { > + /* Clear MSIP registers by lowering software interrupts. */ > + qemu_irq_lower(swi->soft_irqs[i]); > + } > + } > +} > + > static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > dc->realize = riscv_aclint_swi_realize; > device_class_set_props(dc, riscv_aclint_swi_properties); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + rc->phases.enter = riscv_aclint_swi_reset_enter; > } > > static const TypeInfo riscv_aclint_swi_info = { > -- > 2.35.1 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices @ 2022-04-20 7:43 ` Alistair Francis 0 siblings, 0 replies; 16+ messages in thread From: Alistair Francis @ 2022-04-20 7:43 UTC (permalink / raw) To: Frank Chang Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Anup Patel, Jim Shu, Alistair Francis, Bin Meng On Tue, Apr 19, 2022 at 7:29 PM <frank.chang@sifive.com> wrote: > > From: Jim Shu <jim.shu@sifive.com> > > This commit implements reset function of all ACLINT devices. > ACLINT device reset will clear MTIME and MSIP register to 0. > > Depend on RISC-V ACLINT spec v1.0-rc4: > https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc > > Signed-off-by: Jim Shu <jim.shu@sifive.com> > Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c > index ad7ccf96cd..67a07bb5b9 100644 > --- a/hw/intc/riscv_aclint.c > +++ b/hw/intc/riscv_aclint.c > @@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) > } > } > > +static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) > +{ > + /* > + * According to RISC-V ACLINT spec: > + * - On MTIMER device reset, the MTIME register is cleared to zero. > + * - On MTIMER device reset, the MTIMECMP registers are in unknown state. > + */ > + RISCVAclintMTimerState *mtimer = RISCV_ACLINT_MTIMER(obj); > + > + /* > + * Clear mtime register by writing to 0 it. > + * Pending mtime interrupts will also be cleared at the same time. > + */ > + riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); > +} > + > static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > dc->realize = riscv_aclint_mtimer_realize; > device_class_set_props(dc, riscv_aclint_mtimer_properties); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + rc->phases.enter = riscv_aclint_mtimer_reset_enter; > } > > static const TypeInfo riscv_aclint_mtimer_info = { > @@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) > } > } > > +static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) > +{ > + /* > + * According to RISC-V ACLINT spec: > + * - On MSWI device reset, each MSIP register is cleared to zero. > + * > + * p.s. SSWI device reset does nothing since SETSIP register always reads 0. > + */ > + RISCVAclintSwiState *swi = RISCV_ACLINT_SWI(obj); > + int i; > + > + if (!swi->sswi) { > + for (i = 0; i < swi->num_harts; i++) { > + /* Clear MSIP registers by lowering software interrupts. */ > + qemu_irq_lower(swi->soft_irqs[i]); > + } > + } > +} > + > static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc = DEVICE_CLASS(klass); > dc->realize = riscv_aclint_swi_realize; > device_class_set_props(dc, riscv_aclint_swi_properties); > + ResettableClass *rc = RESETTABLE_CLASS(klass); > + rc->phases.enter = riscv_aclint_swi_reset_enter; > } > > static const TypeInfo riscv_aclint_swi_info = { > -- > 2.35.1 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-04-20 7:57 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-19 9:08 [PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses frank.chang 2022-04-19 9:08 ` frank.chang 2022-04-19 9:08 ` [PATCH v3 1/4] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT frank.chang 2022-04-19 9:08 ` frank.chang 2022-04-19 9:08 ` [PATCH v3 2/4] hw/intc: Support 32/64-bit mtimecmp and mtime accesses " frank.chang 2022-04-19 9:08 ` frank.chang 2022-04-19 9:08 ` [PATCH v3 3/4] hw/intc: Make RISC-V ACLINT mtime MMIO register writable frank.chang 2022-04-19 9:08 ` frank.chang 2022-04-20 7:42 ` Alistair Francis 2022-04-20 7:42 ` Alistair Francis 2022-04-20 7:53 ` Frank Chang 2022-04-20 7:53 ` Frank Chang 2022-04-19 9:08 ` [PATCH v3 4/4] hw/intc: riscv_aclint: Add reset function of ACLINT devices frank.chang 2022-04-19 9:08 ` frank.chang 2022-04-20 7:43 ` Alistair Francis 2022-04-20 7:43 ` Alistair Francis
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.