* [Qemu-devel] [PATCH v2 1/5] timer: Initial commit of xlnx-pmu-iomod-pit device
2018-02-28 22:31 [Qemu-devel] [PATCH v2 0/5] Add and connect the PMU IOModule devices Alistair Francis
@ 2018-02-28 22:30 ` Alistair Francis
2018-03-01 18:21 ` Philippe Mathieu-Daudé
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 2/5] xlnx-zynqmp-pmu: Connect the PMU IOMOD PIT devices Alistair Francis
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2018-02-28 22:30 UTC (permalink / raw)
To: qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V2:
- Use UINT32_MAX and uint64_t in xlnx_iomod_pit_ctr_pr()
- Name frequency varaible frequency_hz
- Shorten R_MAX #define
include/hw/timer/xlnx-pmu-iomod-pit.h | 58 ++++++++
hw/timer/xlnx-pmu-iomod-pit.c | 241 ++++++++++++++++++++++++++++++++++
hw/timer/Makefile.objs | 2 +
3 files changed, 301 insertions(+)
create mode 100644 include/hw/timer/xlnx-pmu-iomod-pit.h
create mode 100644 hw/timer/xlnx-pmu-iomod-pit.c
diff --git a/include/hw/timer/xlnx-pmu-iomod-pit.h b/include/hw/timer/xlnx-pmu-iomod-pit.h
new file mode 100644
index 0000000000..75cac6bedd
--- /dev/null
+++ b/include/hw/timer/xlnx-pmu-iomod-pit.h
@@ -0,0 +1,58 @@
+/*
+ * QEMU model of Xilinx I/O Module PIT
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ptimer.h"
+
+#define TYPE_XLNX_ZYNQMP_IOMODULE_PIT "xlnx.pmu_iomodule_pit"
+
+#define XLNX_ZYNQMP_IOMODULE_PIT(obj) \
+ OBJECT_CHECK(XlnxPMUPIT, (obj), TYPE_XLNX_ZYNQMP_IOMODULE_PIT)
+
+#define XLNX_ZYNQMP_IOMOD_PIT_R_MAX (0x08 + 1)
+
+typedef struct XlnxPMUPIT {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ QEMUBH *bh;
+ ptimer_state *ptimer;
+
+ qemu_irq irq;
+ /* IRQ to pulse out when present timer hits zero */
+ qemu_irq hit_out;
+
+ /* Counter in Pre-Scalar(ps) Mode */
+ uint32_t ps_counter;
+ /* ps_mode irq-in to enable/disable pre-scalar */
+ bool ps_enable;
+ /* State var to remember hit_in level */
+ bool ps_level;
+
+ uint32_t frequency_hz;
+
+ uint32_t regs[XLNX_ZYNQMP_IOMOD_PIT_R_MAX];
+ RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_PIT_R_MAX];
+} XlnxPMUPIT;
diff --git a/hw/timer/xlnx-pmu-iomod-pit.c b/hw/timer/xlnx-pmu-iomod-pit.c
new file mode 100644
index 0000000000..a6bdc5211d
--- /dev/null
+++ b/hw/timer/xlnx-pmu-iomod-pit.c
@@ -0,0 +1,241 @@
+/*
+ * QEMU model of Xilinx I/O Module PIT
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "hw/register.h"
+#include "qemu/main-loop.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/timer/xlnx-pmu-iomod-pit.h"
+
+#ifndef XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG
+#define XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG 0
+#endif
+
+REG32(PIT_PRELOAD, 0x00)
+REG32(PIT_COUNTER, 0x04)
+REG32(PIT_CONTROL, 0x08)
+ FIELD(PIT_CONTROL, PRELOAD, 1, 1)
+ FIELD(PIT_CONTROL, EN, 0, 1)
+
+static uint64_t xlnx_iomod_pit_ctr_pr(RegisterInfo *reg, uint64_t val)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(reg->opaque);
+ uint64_t ret;
+
+ if (s->ps_enable) {
+ ret = s->ps_counter;
+ } else {
+ ret = ptimer_get_count(s->ptimer);
+ }
+
+ return ret & UINT32_MAX;
+}
+
+static void xlnx_iomod_pit_control_pw(RegisterInfo *reg, uint64_t val)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(reg->opaque);
+
+ ptimer_stop(s->ptimer);
+
+ if (val & R_PIT_CONTROL_EN_MASK) {
+ if (s->ps_enable) {
+ /* pre-scalar mode do-Nothing here */
+ s->ps_counter = s->regs[R_PIT_PRELOAD];
+ } else {
+ ptimer_set_limit(s->ptimer, s->regs[R_PIT_PRELOAD], 1);
+ ptimer_run(s->ptimer, !(val & R_PIT_CONTROL_PRELOAD_MASK));
+
+ }
+ }
+}
+
+static const RegisterAccessInfo xlnx_iomod_pit_regs_info[] = {
+ { .name = "PIT_PRELOAD", .addr = A_PIT_PRELOAD,
+ .ro = 0xffffffff,
+ },{ .name = "PIT_COUNTER", .addr = A_PIT_COUNTER,
+ .ro = 0xffffffff,
+ .post_read = xlnx_iomod_pit_ctr_pr,
+ },{ .name = "PIT_CONTROL", .addr = A_PIT_CONTROL,
+ .rsvd = 0xfffffffc,
+ .post_write = xlnx_iomod_pit_control_pw,
+ }
+};
+
+static void xlnx_iomod_pit_timer_hit(void *opaque)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
+
+ qemu_irq_pulse(s->irq);
+
+ /* hit_out to make another pit move it's counter in pre-scalar mode. */
+ qemu_irq_pulse(s->hit_out);
+}
+
+static void xlnx_iomod_pit_ps_config(void *opaque, int n, int level)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
+
+ s->ps_enable = level;
+}
+
+static void xlnx_iomod_pit_ps_hit_in(void *opaque, int n, int level)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
+
+ if (!ARRAY_FIELD_EX32(s->regs, PIT_CONTROL, EN)) {
+ /* PIT disabled */
+ return;
+ }
+
+ /* Count only on positive edge */
+ if (!s->ps_level && level) {
+ if (s->ps_counter) {
+ s->ps_counter--;
+ }
+ s->ps_level = level;
+ } else {
+ /* Not on positive edge */
+ s->ps_level = level;
+ return;
+ }
+
+ /* If timer expires, try to preload or stop */
+ if (s->ps_counter == 0) {
+ xlnx_iomod_pit_timer_hit(opaque);
+
+ /* Check for pit preload/one-shot mode */
+ if (ARRAY_FIELD_EX32(s->regs, PIT_CONTROL, PRELOAD)) {
+ /* Preload Mode, Reload the ps_counter */
+ s->ps_counter = s->regs[R_PIT_PRELOAD];
+ } else {
+ /* One-Shot mode, turn off the timer */
+ s->regs[R_PIT_CONTROL] &= ~R_PIT_CONTROL_PRELOAD_MASK;
+ }
+ }
+}
+
+static void xlnx_iomod_pit_reset(DeviceState *dev)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(dev);
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+
+ s->ps_level = false;
+}
+
+static const MemoryRegionOps xlnx_iomod_pit_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void xlnx_iomod_pit_realize(DeviceState *dev, Error **errp)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(dev);
+
+ s->bh = qemu_bh_new(xlnx_iomod_pit_timer_hit, s);
+ s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
+ ptimer_set_freq(s->ptimer, s->frequency_hz);
+
+ /* IRQ out to pulse when present timer expires/reloads */
+ qdev_init_gpio_out_named(dev, &s->hit_out, "ps_hit_out", 1);
+
+ /* IRQ in to enable pre-scalar mode. Routed from gpo1 */
+ qdev_init_gpio_in_named(dev, xlnx_iomod_pit_ps_config, "ps_config", 1);
+
+ /* hit_out of neighbouring PIT is received as hit_in */
+ qdev_init_gpio_in_named(dev, xlnx_iomod_pit_ps_hit_in, "ps_hit_in", 1);
+}
+
+static void xlnx_iomod_pit_init(Object *obj)
+{
+ XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
+ XLNX_ZYNQMP_IOMOD_PIT_R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), xlnx_iomod_pit_regs_info,
+ ARRAY_SIZE(xlnx_iomod_pit_regs_info),
+ s->regs_info, s->regs,
+ &xlnx_iomod_pit_ops,
+ XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG,
+ XLNX_ZYNQMP_IOMOD_PIT_R_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ 0x0,
+ ®_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static const VMStateDescription vmstate_xlnx_iomod_pit = {
+ .name = TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property xlnx_iomod_pit_properties[] = {
+ DEFINE_PROP_UINT32("frequency", XlnxPMUPIT, frequency_hz, 66000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xlnx_iomod_pit_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = xlnx_iomod_pit_reset;
+ dc->realize = xlnx_iomod_pit_realize;
+ dc->props = xlnx_iomod_pit_properties;
+ dc->vmsd = &vmstate_xlnx_iomod_pit;
+}
+
+static const TypeInfo xlnx_iomod_pit_info = {
+ .name = TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxPMUPIT),
+ .class_init = xlnx_iomod_pit_class_init,
+ .instance_init = xlnx_iomod_pit_init,
+};
+
+static void xlnx_iomod_pit_register_types(void)
+{
+ type_register_static(&xlnx_iomod_pit_info);
+}
+
+type_init(xlnx_iomod_pit_register_types)
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 8c19eac3b6..805c480cad 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -43,3 +43,5 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
common-obj-$(CONFIG_MSF2) += mss-timer.o
+
+common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-pit.o
--
2.14.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/5] timer: Initial commit of xlnx-pmu-iomod-pit device
2018-02-28 22:30 ` [Qemu-devel] [PATCH v2 1/5] timer: Initial commit of xlnx-pmu-iomod-pit device Alistair Francis
@ 2018-03-01 18:21 ` Philippe Mathieu-Daudé
2018-05-04 3:39 ` Alistair Francis
0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-01 18:21 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair23
On 02/28/2018 07:31 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V2:
> - Use UINT32_MAX and uint64_t in xlnx_iomod_pit_ctr_pr()
> - Name frequency varaible frequency_hz
> - Shorten R_MAX #define
>
> include/hw/timer/xlnx-pmu-iomod-pit.h | 58 ++++++++
> hw/timer/xlnx-pmu-iomod-pit.c | 241 ++++++++++++++++++++++++++++++++++
> hw/timer/Makefile.objs | 2 +
> 3 files changed, 301 insertions(+)
> create mode 100644 include/hw/timer/xlnx-pmu-iomod-pit.h
> create mode 100644 hw/timer/xlnx-pmu-iomod-pit.c
>
> diff --git a/include/hw/timer/xlnx-pmu-iomod-pit.h b/include/hw/timer/xlnx-pmu-iomod-pit.h
> new file mode 100644
> index 0000000000..75cac6bedd
> --- /dev/null
> +++ b/include/hw/timer/xlnx-pmu-iomod-pit.h
> @@ -0,0 +1,58 @@
> +/*
> + * QEMU model of Xilinx I/O Module PIT
> + *
> + * Copyright (c) 2013 Xilinx Inc
> + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/ptimer.h"
> +
> +#define TYPE_XLNX_ZYNQMP_IOMODULE_PIT "xlnx.pmu_iomodule_pit"
> +
> +#define XLNX_ZYNQMP_IOMODULE_PIT(obj) \
> + OBJECT_CHECK(XlnxPMUPIT, (obj), TYPE_XLNX_ZYNQMP_IOMODULE_PIT)
> +
> +#define XLNX_ZYNQMP_IOMOD_PIT_R_MAX (0x08 + 1)
0x04?
> +
> +typedef struct XlnxPMUPIT {
> + SysBusDevice parent_obj;
> + MemoryRegion iomem;
> +
> + QEMUBH *bh;
> + ptimer_state *ptimer;
> +
> + qemu_irq irq;
> + /* IRQ to pulse out when present timer hits zero */
> + qemu_irq hit_out;
> +
> + /* Counter in Pre-Scalar(ps) Mode */
> + uint32_t ps_counter;
> + /* ps_mode irq-in to enable/disable pre-scalar */
> + bool ps_enable;
> + /* State var to remember hit_in level */
> + bool ps_level;
> +
> + uint32_t frequency_hz;
> +
> + uint32_t regs[XLNX_ZYNQMP_IOMOD_PIT_R_MAX];
> + RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_PIT_R_MAX];
> +} XlnxPMUPIT;
> diff --git a/hw/timer/xlnx-pmu-iomod-pit.c b/hw/timer/xlnx-pmu-iomod-pit.c
> new file mode 100644
> index 0000000000..a6bdc5211d
> --- /dev/null
> +++ b/hw/timer/xlnx-pmu-iomod-pit.c
> @@ -0,0 +1,241 @@
> +/*
> + * QEMU model of Xilinx I/O Module PIT
> + *
> + * Copyright (c) 2013 Xilinx Inc
> + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/ptimer.h"
> +#include "hw/register.h"
> +#include "qemu/main-loop.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "hw/timer/xlnx-pmu-iomod-pit.h"
> +
> +#ifndef XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG
> +#define XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG 0
> +#endif
> +
> +REG32(PIT_PRELOAD, 0x00)
> +REG32(PIT_COUNTER, 0x04)
> +REG32(PIT_CONTROL, 0x08)
> + FIELD(PIT_CONTROL, PRELOAD, 1, 1)
> + FIELD(PIT_CONTROL, EN, 0, 1)
> +
> +static uint64_t xlnx_iomod_pit_ctr_pr(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(reg->opaque);
> + uint64_t ret;
> +
> + if (s->ps_enable) {
> + ret = s->ps_counter;
> + } else {
> + ret = ptimer_get_count(s->ptimer);
> + }
> +
> + return ret & UINT32_MAX;
> +}
> +
> +static void xlnx_iomod_pit_control_pw(RegisterInfo *reg, uint64_t val)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(reg->opaque);
> +
> + ptimer_stop(s->ptimer);
> +
> + if (val & R_PIT_CONTROL_EN_MASK) {
> + if (s->ps_enable) {
> + /* pre-scalar mode do-Nothing here */
> + s->ps_counter = s->regs[R_PIT_PRELOAD];
> + } else {
> + ptimer_set_limit(s->ptimer, s->regs[R_PIT_PRELOAD], 1);
> + ptimer_run(s->ptimer, !(val & R_PIT_CONTROL_PRELOAD_MASK));
> +
blank line
> + }
> + }
> +}
> +
> +static const RegisterAccessInfo xlnx_iomod_pit_regs_info[] = {
> + { .name = "PIT_PRELOAD", .addr = A_PIT_PRELOAD,
> + .ro = 0xffffffff,
Or UINT32_MAX
> + },{ .name = "PIT_COUNTER", .addr = A_PIT_COUNTER,
> + .ro = 0xffffffff,
> + .post_read = xlnx_iomod_pit_ctr_pr,
> + },{ .name = "PIT_CONTROL", .addr = A_PIT_CONTROL,
> + .rsvd = 0xfffffffc,
Or = ~(R_PIT_CONTROL_PRELOAD_MASK | R_PIT_CONTROL_EN_MASK),
and I always forgot this is mostly generated.
> + .post_write = xlnx_iomod_pit_control_pw,
> + }
> +};
> +
> +static void xlnx_iomod_pit_timer_hit(void *opaque)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
> +
> + qemu_irq_pulse(s->irq);
> +
> + /* hit_out to make another pit move it's counter in pre-scalar mode. */
> + qemu_irq_pulse(s->hit_out);
> +}
> +
> +static void xlnx_iomod_pit_ps_config(void *opaque, int n, int level)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
> +
> + s->ps_enable = level;
> +}
> +
> +static void xlnx_iomod_pit_ps_hit_in(void *opaque, int n, int level)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
> +
> + if (!ARRAY_FIELD_EX32(s->regs, PIT_CONTROL, EN)) {
> + /* PIT disabled */
> + return;
> + }
> +
> + /* Count only on positive edge */
> + if (!s->ps_level && level) {
> + if (s->ps_counter) {
> + s->ps_counter--;
> + }
> + s->ps_level = level;
> + } else {
> + /* Not on positive edge */
> + s->ps_level = level;
> + return;
> + }
Inverting this
if (C) {A} else {B return}
as
if (!C) {B return}
A
is a bit easier to read.
> +
> + /* If timer expires, try to preload or stop */
> + if (s->ps_counter == 0) {
> + xlnx_iomod_pit_timer_hit(opaque);
> +
> + /* Check for pit preload/one-shot mode */
> + if (ARRAY_FIELD_EX32(s->regs, PIT_CONTROL, PRELOAD)) {
> + /* Preload Mode, Reload the ps_counter */
> + s->ps_counter = s->regs[R_PIT_PRELOAD];
> + } else {
> + /* One-Shot mode, turn off the timer */
> + s->regs[R_PIT_CONTROL] &= ~R_PIT_CONTROL_PRELOAD_MASK;
> + }
> + }
Ditto, if (!s->ps_counter) return;
Anyway this is fine,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> +}
> +
> +static void xlnx_iomod_pit_reset(DeviceState *dev)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(dev);
> + unsigned int i;
> +
> + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
> + register_reset(&s->regs_info[i]);
> + }
> +
> + s->ps_level = false;
> +}
> +
> +static const MemoryRegionOps xlnx_iomod_pit_ops = {
> + .read = register_read_memory,
> + .write = register_write_memory,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
> +static void xlnx_iomod_pit_realize(DeviceState *dev, Error **errp)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(dev);
> +
> + s->bh = qemu_bh_new(xlnx_iomod_pit_timer_hit, s);
> + s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
> + ptimer_set_freq(s->ptimer, s->frequency_hz);
> +
> + /* IRQ out to pulse when present timer expires/reloads */
> + qdev_init_gpio_out_named(dev, &s->hit_out, "ps_hit_out", 1);
> +
> + /* IRQ in to enable pre-scalar mode. Routed from gpo1 */
> + qdev_init_gpio_in_named(dev, xlnx_iomod_pit_ps_config, "ps_config", 1);
> +
> + /* hit_out of neighbouring PIT is received as hit_in */
> + qdev_init_gpio_in_named(dev, xlnx_iomod_pit_ps_hit_in, "ps_hit_in", 1);
> +}
> +
> +static void xlnx_iomod_pit_init(Object *obj)
> +{
> + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + RegisterInfoArray *reg_array;
> +
> + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
> + XLNX_ZYNQMP_IOMOD_PIT_R_MAX * 4);
> + reg_array =
> + register_init_block32(DEVICE(obj), xlnx_iomod_pit_regs_info,
> + ARRAY_SIZE(xlnx_iomod_pit_regs_info),
> + s->regs_info, s->regs,
> + &xlnx_iomod_pit_ops,
> + XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG,
> + XLNX_ZYNQMP_IOMOD_PIT_R_MAX * 4);
> + memory_region_add_subregion(&s->iomem,
> + 0x0,
> + ®_array->mem);
> + sysbus_init_mmio(sbd, &s->iomem);
> + sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static const VMStateDescription vmstate_xlnx_iomod_pit = {
> + .name = TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> +static Property xlnx_iomod_pit_properties[] = {
> + DEFINE_PROP_UINT32("frequency", XlnxPMUPIT, frequency_hz, 66000000),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void xlnx_iomod_pit_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->reset = xlnx_iomod_pit_reset;
> + dc->realize = xlnx_iomod_pit_realize;
> + dc->props = xlnx_iomod_pit_properties;
> + dc->vmsd = &vmstate_xlnx_iomod_pit;
> +}
> +
> +static const TypeInfo xlnx_iomod_pit_info = {
> + .name = TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XlnxPMUPIT),
> + .class_init = xlnx_iomod_pit_class_init,
> + .instance_init = xlnx_iomod_pit_init,
> +};
> +
> +static void xlnx_iomod_pit_register_types(void)
> +{
> + type_register_static(&xlnx_iomod_pit_info);
> +}
> +
> +type_init(xlnx_iomod_pit_register_types)
> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> index 8c19eac3b6..805c480cad 100644
> --- a/hw/timer/Makefile.objs
> +++ b/hw/timer/Makefile.objs
> @@ -43,3 +43,5 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
> common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
> common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
> common-obj-$(CONFIG_MSF2) += mss-timer.o
> +
> +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-pit.o
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 1/5] timer: Initial commit of xlnx-pmu-iomod-pit device
2018-03-01 18:21 ` Philippe Mathieu-Daudé
@ 2018-05-04 3:39 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2018-05-04 3:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
Edgar Iglesias, Edgar Iglesias
On Thu, Mar 1, 2018 at 10:21 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> On 02/28/2018 07:31 PM, Alistair Francis wrote:
> > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> > ---
> > V2:
> > - Use UINT32_MAX and uint64_t in xlnx_iomod_pit_ctr_pr()
> > - Name frequency varaible frequency_hz
> > - Shorten R_MAX #define
> >
> > include/hw/timer/xlnx-pmu-iomod-pit.h | 58 ++++++++
> > hw/timer/xlnx-pmu-iomod-pit.c | 241
++++++++++++++++++++++++++++++++++
> > hw/timer/Makefile.objs | 2 +
> > 3 files changed, 301 insertions(+)
> > create mode 100644 include/hw/timer/xlnx-pmu-iomod-pit.h
> > create mode 100644 hw/timer/xlnx-pmu-iomod-pit.c
> >
> > diff --git a/include/hw/timer/xlnx-pmu-iomod-pit.h
b/include/hw/timer/xlnx-pmu-iomod-pit.h
> > new file mode 100644
> > index 0000000000..75cac6bedd
> > --- /dev/null
> > +++ b/include/hw/timer/xlnx-pmu-iomod-pit.h
> > @@ -0,0 +1,58 @@
> > +/*
> > + * QEMU model of Xilinx I/O Module PIT
> > + *
> > + * Copyright (c) 2013 Xilinx Inc
> > + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
obtaining a copy
> > + * of this software and associated documentation files (the
"Software"), to deal
> > + * in the Software without restriction, including without limitation
the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell
> > + * copies of the Software, and to permit persons to whom the Software
is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/ptimer.h"
> > +
> > +#define TYPE_XLNX_ZYNQMP_IOMODULE_PIT "xlnx.pmu_iomodule_pit"
> > +
> > +#define XLNX_ZYNQMP_IOMODULE_PIT(obj) \
> > + OBJECT_CHECK(XlnxPMUPIT, (obj), TYPE_XLNX_ZYNQMP_IOMODULE_PIT)
> > +
> > +#define XLNX_ZYNQMP_IOMOD_PIT_R_MAX (0x08 + 1)
> 0x04?
No, 0x08 is right.
> > +
> > +typedef struct XlnxPMUPIT {
> > + SysBusDevice parent_obj;
> > + MemoryRegion iomem;
> > +
> > + QEMUBH *bh;
> > + ptimer_state *ptimer;
> > +
> > + qemu_irq irq;
> > + /* IRQ to pulse out when present timer hits zero */
> > + qemu_irq hit_out;
> > +
> > + /* Counter in Pre-Scalar(ps) Mode */
> > + uint32_t ps_counter;
> > + /* ps_mode irq-in to enable/disable pre-scalar */
> > + bool ps_enable;
> > + /* State var to remember hit_in level */
> > + bool ps_level;
> > +
> > + uint32_t frequency_hz;
> > +
> > + uint32_t regs[XLNX_ZYNQMP_IOMOD_PIT_R_MAX];
> > + RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_PIT_R_MAX];
> > +} XlnxPMUPIT;
> > diff --git a/hw/timer/xlnx-pmu-iomod-pit.c
b/hw/timer/xlnx-pmu-iomod-pit.c
> > new file mode 100644
> > index 0000000000..a6bdc5211d
> > --- /dev/null
> > +++ b/hw/timer/xlnx-pmu-iomod-pit.c
> > @@ -0,0 +1,241 @@
> > +/*
> > + * QEMU model of Xilinx I/O Module PIT
> > + *
> > + * Copyright (c) 2013 Xilinx Inc
> > + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
obtaining a copy
> > + * of this software and associated documentation files (the
"Software"), to deal
> > + * in the Software without restriction, including without limitation
the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell
> > + * copies of the Software, and to permit persons to whom the Software
is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/sysbus.h"
> > +#include "hw/ptimer.h"
> > +#include "hw/register.h"
> > +#include "qemu/main-loop.h"
> > +#include "qemu/log.h"
> > +#include "qapi/error.h"
> > +#include "hw/timer/xlnx-pmu-iomod-pit.h"
> > +
> > +#ifndef XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG
> > +#define XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG 0
> > +#endif
> > +
> > +REG32(PIT_PRELOAD, 0x00)
> > +REG32(PIT_COUNTER, 0x04)
> > +REG32(PIT_CONTROL, 0x08)
> > + FIELD(PIT_CONTROL, PRELOAD, 1, 1)
> > + FIELD(PIT_CONTROL, EN, 0, 1)
> > +
> > +static uint64_t xlnx_iomod_pit_ctr_pr(RegisterInfo *reg, uint64_t val)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(reg->opaque);
> > + uint64_t ret;
> > +
> > + if (s->ps_enable) {
> > + ret = s->ps_counter;
> > + } else {
> > + ret = ptimer_get_count(s->ptimer);
> > + }
> > +
> > + return ret & UINT32_MAX;
> > +}
> > +
> > +static void xlnx_iomod_pit_control_pw(RegisterInfo *reg, uint64_t val)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(reg->opaque);
> > +
> > + ptimer_stop(s->ptimer);
> > +
> > + if (val & R_PIT_CONTROL_EN_MASK) {
> > + if (s->ps_enable) {
> > + /* pre-scalar mode do-Nothing here */
> > + s->ps_counter = s->regs[R_PIT_PRELOAD];
> > + } else {
> > + ptimer_set_limit(s->ptimer, s->regs[R_PIT_PRELOAD], 1);
> > + ptimer_run(s->ptimer, !(val & R_PIT_CONTROL_PRELOAD_MASK));
> > +
> blank line
Fixed.
> > + }
> > + }
> > +}
> > +
> > +static const RegisterAccessInfo xlnx_iomod_pit_regs_info[] = {
> > + { .name = "PIT_PRELOAD", .addr = A_PIT_PRELOAD,
> > + .ro = 0xffffffff,
> Or UINT32_MAX
Fixed.
> > + },{ .name = "PIT_COUNTER", .addr = A_PIT_COUNTER,
> > + .ro = 0xffffffff,
> > + .post_read = xlnx_iomod_pit_ctr_pr,
> > + },{ .name = "PIT_CONTROL", .addr = A_PIT_CONTROL,
> > + .rsvd = 0xfffffffc,
> Or = ~(R_PIT_CONTROL_PRELOAD_MASK | R_PIT_CONTROL_EN_MASK),
Fixed.
> and I always forgot this is mostly generated.
> > + .post_write = xlnx_iomod_pit_control_pw,
> > + }
> > +};
> > +
> > +static void xlnx_iomod_pit_timer_hit(void *opaque)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
> > +
> > + qemu_irq_pulse(s->irq);
> > +
> > + /* hit_out to make another pit move it's counter in pre-scalar
mode. */
> > + qemu_irq_pulse(s->hit_out);
> > +}
> > +
> > +static void xlnx_iomod_pit_ps_config(void *opaque, int n, int level)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
> > +
> > + s->ps_enable = level;
> > +}
> > +
> > +static void xlnx_iomod_pit_ps_hit_in(void *opaque, int n, int level)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(opaque);
> > +
> > + if (!ARRAY_FIELD_EX32(s->regs, PIT_CONTROL, EN)) {
> > + /* PIT disabled */
> > + return;
> > + }
> > +
> > + /* Count only on positive edge */
> > + if (!s->ps_level && level) {
> > + if (s->ps_counter) {
> > + s->ps_counter--;
> > + }
> > + s->ps_level = level;
> > + } else {
> > + /* Not on positive edge */
> > + s->ps_level = level;
> > + return;
> > + }
> Inverting this
> if (C) {A} else {B return}
> as
> if (!C) {B return}
> A
> is a bit easier to read.
Fixed.
> > +
> > + /* If timer expires, try to preload or stop */
> > + if (s->ps_counter == 0) {
> > + xlnx_iomod_pit_timer_hit(opaque);
> > +
> > + /* Check for pit preload/one-shot mode */
> > + if (ARRAY_FIELD_EX32(s->regs, PIT_CONTROL, PRELOAD)) {
> > + /* Preload Mode, Reload the ps_counter */
> > + s->ps_counter = s->regs[R_PIT_PRELOAD];
> > + } else {
> > + /* One-Shot mode, turn off the timer */
> > + s->regs[R_PIT_CONTROL] &= ~R_PIT_CONTROL_PRELOAD_MASK;
> > + }
> > + }
> Ditto, if (!s->ps_counter) return;
> Anyway this is fine,
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Thanks :)
Alistair
> > +}
> > +
> > +static void xlnx_iomod_pit_reset(DeviceState *dev)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(dev);
> > + unsigned int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
> > + register_reset(&s->regs_info[i]);
> > + }
> > +
> > + s->ps_level = false;
> > +}
> > +
> > +static const MemoryRegionOps xlnx_iomod_pit_ops = {
> > + .read = register_read_memory,
> > + .write = register_write_memory,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static void xlnx_iomod_pit_realize(DeviceState *dev, Error **errp)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(dev);
> > +
> > + s->bh = qemu_bh_new(xlnx_iomod_pit_timer_hit, s);
> > + s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
> > + ptimer_set_freq(s->ptimer, s->frequency_hz);
> > +
> > + /* IRQ out to pulse when present timer expires/reloads */
> > + qdev_init_gpio_out_named(dev, &s->hit_out, "ps_hit_out", 1);
> > +
> > + /* IRQ in to enable pre-scalar mode. Routed from gpo1 */
> > + qdev_init_gpio_in_named(dev, xlnx_iomod_pit_ps_config,
"ps_config", 1);
> > +
> > + /* hit_out of neighbouring PIT is received as hit_in */
> > + qdev_init_gpio_in_named(dev, xlnx_iomod_pit_ps_hit_in,
"ps_hit_in", 1);
> > +}
> > +
> > +static void xlnx_iomod_pit_init(Object *obj)
> > +{
> > + XlnxPMUPIT *s = XLNX_ZYNQMP_IOMODULE_PIT(obj);
> > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> > + RegisterInfoArray *reg_array;
> > +
> > + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
> > + XLNX_ZYNQMP_IOMOD_PIT_R_MAX * 4);
> > + reg_array =
> > + register_init_block32(DEVICE(obj), xlnx_iomod_pit_regs_info,
> > + ARRAY_SIZE(xlnx_iomod_pit_regs_info),
> > + s->regs_info, s->regs,
> > + &xlnx_iomod_pit_ops,
> > + XLNX_ZYNQMP_IOMODULE_PIT_ERR_DEBUG,
> > + XLNX_ZYNQMP_IOMOD_PIT_R_MAX * 4);
> > + memory_region_add_subregion(&s->iomem,
> > + 0x0,
> > + ®_array->mem);
> > + sysbus_init_mmio(sbd, &s->iomem);
> > + sysbus_init_irq(sbd, &s->irq);
> > +}
> > +
> > +static const VMStateDescription vmstate_xlnx_iomod_pit = {
> > + .name = TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_END_OF_LIST(),
> > + }
> > +};
> > +
> > +static Property xlnx_iomod_pit_properties[] = {
> > + DEFINE_PROP_UINT32("frequency", XlnxPMUPIT, frequency_hz,
66000000),
> > + DEFINE_PROP_END_OF_LIST(),
> > +};
> > +
> > +static void xlnx_iomod_pit_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->reset = xlnx_iomod_pit_reset;
> > + dc->realize = xlnx_iomod_pit_realize;
> > + dc->props = xlnx_iomod_pit_properties;
> > + dc->vmsd = &vmstate_xlnx_iomod_pit;
> > +}
> > +
> > +static const TypeInfo xlnx_iomod_pit_info = {
> > + .name = TYPE_XLNX_ZYNQMP_IOMODULE_PIT,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(XlnxPMUPIT),
> > + .class_init = xlnx_iomod_pit_class_init,
> > + .instance_init = xlnx_iomod_pit_init,
> > +};
> > +
> > +static void xlnx_iomod_pit_register_types(void)
> > +{
> > + type_register_static(&xlnx_iomod_pit_info);
> > +}
> > +
> > +type_init(xlnx_iomod_pit_register_types)
> > diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> > index 8c19eac3b6..805c480cad 100644
> > --- a/hw/timer/Makefile.objs
> > +++ b/hw/timer/Makefile.objs
> > @@ -43,3 +43,5 @@ common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
> > common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
> > common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o
> > common-obj-$(CONFIG_MSF2) += mss-timer.o
> > +
> > +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-pit.o
> >
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v2 2/5] xlnx-zynqmp-pmu: Connect the PMU IOMOD PIT devices
2018-02-28 22:31 [Qemu-devel] [PATCH v2 0/5] Add and connect the PMU IOModule devices Alistair Francis
2018-02-28 22:30 ` [Qemu-devel] [PATCH v2 1/5] timer: Initial commit of xlnx-pmu-iomod-pit device Alistair Francis
@ 2018-02-28 22:32 ` Alistair Francis
2018-03-01 18:22 ` Philippe Mathieu-Daudé
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 3/5] hw/gpio: Add the xlnx-pmu-iomod-gpo device Alistair Francis
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2018-02-28 22:32 UTC (permalink / raw)
To: qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/microblaze/xlnx-zynqmp-pmu.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
index 999a5657cf..35a2314ffb 100644
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
@@ -26,6 +26,7 @@
#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/intc/xlnx-pmu-iomod-intc.h"
+#include "hw/timer/xlnx-pmu-iomod-pit.h"
/* Define the PMU device */
@@ -40,6 +41,7 @@
#define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
+#define XLNX_ZYNQMP_PMU_NUM_PITS 4
static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
@@ -48,6 +50,13 @@ static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
19, 20, 21, 22,
};
+static const uint64_t pit_addr[XLNX_ZYNQMP_PMU_NUM_PITS] = {
+ 0xFFD40040, 0xFFD40050, 0xFFD40060, 0xFFD40070,
+};
+static const uint64_t pit_irq[XLNX_ZYNQMP_PMU_NUM_PITS] = {
+ 3, 4, 5, 6,
+};
+
typedef struct XlnxZynqMPPMUSoCState {
/*< private >*/
DeviceState parent_obj;
@@ -147,7 +156,9 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
+ XlnxPMUPIT *pit[XLNX_ZYNQMP_PMU_NUM_PITS];
qemu_irq irq[32];
+ qemu_irq tmp_irq;
int i;
/* Create the ROM */
@@ -186,6 +197,30 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
}
+ /* Create and connect the IOMOD PIT devices */
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_PITS; i++) {
+ pit[i] = g_new0(XlnxPMUPIT, 1);
+ object_initialize(pit[i], sizeof(XlnxPMUPIT), TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
+ qdev_set_parent_bus(DEVICE(pit[i]), sysbus_get_default());
+ }
+
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_PITS; i++) {
+ object_property_set_bool(OBJECT(pit[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(pit[i]), 0, pit_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(pit[i]), 0, irq[pit_irq[i]]);
+ }
+
+ /* PIT1 hits into PIT0 */
+ tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[0]), "ps_hit_in", 0);
+ qdev_connect_gpio_out_named(DEVICE(pit[1]), "ps_hit_out", 0, tmp_irq);
+
+ /* PIT3 hits into PIT2 */
+ tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_hit_in", 0);
+ qdev_connect_gpio_out_named(DEVICE(pit[3]), "ps_hit_out", 0, tmp_irq);
+
+ /* TODO: PIT0 and PIT2 "ps_config" GPIO goes to The GPO1 device. */
+
/* Load the kernel */
microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
machine->ram_size,
--
2.14.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/5] xlnx-zynqmp-pmu: Connect the PMU IOMOD PIT devices
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 2/5] xlnx-zynqmp-pmu: Connect the PMU IOMOD PIT devices Alistair Francis
@ 2018-03-01 18:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-01 18:22 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair23
On 02/28/2018 07:32 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>
> hw/microblaze/xlnx-zynqmp-pmu.c | 35 +++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
> index 999a5657cf..35a2314ffb 100644
> --- a/hw/microblaze/xlnx-zynqmp-pmu.c
> +++ b/hw/microblaze/xlnx-zynqmp-pmu.c
> @@ -26,6 +26,7 @@
>
> #include "hw/intc/xlnx-zynqmp-ipi.h"
> #include "hw/intc/xlnx-pmu-iomod-intc.h"
> +#include "hw/timer/xlnx-pmu-iomod-pit.h"
>
> /* Define the PMU device */
>
> @@ -40,6 +41,7 @@
> #define XLNX_ZYNQMP_PMU_INTC_ADDR 0xFFD40000
>
> #define XLNX_ZYNQMP_PMU_NUM_IPIS 4
> +#define XLNX_ZYNQMP_PMU_NUM_PITS 4
>
> static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
> 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
> @@ -48,6 +50,13 @@ static const uint64_t ipi_irq[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
> 19, 20, 21, 22,
> };
>
> +static const uint64_t pit_addr[XLNX_ZYNQMP_PMU_NUM_PITS] = {
> + 0xFFD40040, 0xFFD40050, 0xFFD40060, 0xFFD40070,
> +};
> +static const uint64_t pit_irq[XLNX_ZYNQMP_PMU_NUM_PITS] = {
> + 3, 4, 5, 6,
> +};
> +
> typedef struct XlnxZynqMPPMUSoCState {
> /*< private >*/
> DeviceState parent_obj;
> @@ -147,7 +156,9 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
> MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
> XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
> + XlnxPMUPIT *pit[XLNX_ZYNQMP_PMU_NUM_PITS];
> qemu_irq irq[32];
> + qemu_irq tmp_irq;
> int i;
>
> /* Create the ROM */
> @@ -186,6 +197,30 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
> }
>
> + /* Create and connect the IOMOD PIT devices */
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_PITS; i++) {
> + pit[i] = g_new0(XlnxPMUPIT, 1);
> + object_initialize(pit[i], sizeof(XlnxPMUPIT), TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
> + qdev_set_parent_bus(DEVICE(pit[i]), sysbus_get_default());
> + }
> +
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_PITS; i++) {
> + object_property_set_bool(OBJECT(pit[i]), true, "realized",
> + &error_abort);
> + sysbus_mmio_map(SYS_BUS_DEVICE(pit[i]), 0, pit_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(pit[i]), 0, irq[pit_irq[i]]);
> + }
> +
> + /* PIT1 hits into PIT0 */
> + tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[0]), "ps_hit_in", 0);
> + qdev_connect_gpio_out_named(DEVICE(pit[1]), "ps_hit_out", 0, tmp_irq);
> +
> + /* PIT3 hits into PIT2 */
> + tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_hit_in", 0);
> + qdev_connect_gpio_out_named(DEVICE(pit[3]), "ps_hit_out", 0, tmp_irq);
> +
> + /* TODO: PIT0 and PIT2 "ps_config" GPIO goes to The GPO1 device. */
> +
> /* Load the kernel */
> microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
> machine->ram_size,
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v2 3/5] hw/gpio: Add the xlnx-pmu-iomod-gpo device
2018-02-28 22:31 [Qemu-devel] [PATCH v2 0/5] Add and connect the PMU IOModule devices Alistair Francis
2018-02-28 22:30 ` [Qemu-devel] [PATCH v2 1/5] timer: Initial commit of xlnx-pmu-iomod-pit device Alistair Francis
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 2/5] xlnx-zynqmp-pmu: Connect the PMU IOMOD PIT devices Alistair Francis
@ 2018-02-28 22:32 ` Alistair Francis
2018-03-01 17:02 ` Philippe Mathieu-Daudé
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 4/5] hw/gpio: Add support for the xlnx-pmu-iomod-gpi device Alistair Francis
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices Alistair Francis
4 siblings, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2018-02-28 22:32 UTC (permalink / raw)
To: qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
include/hw/gpio/xlnx-pmu-iomod-gp.h | 52 +++++++++++++
hw/gpio/xlnx-pmu-iomod-gp.c | 150 ++++++++++++++++++++++++++++++++++++
hw/gpio/Makefile.objs | 2 +
3 files changed, 204 insertions(+)
create mode 100644 include/hw/gpio/xlnx-pmu-iomod-gp.h
create mode 100644 hw/gpio/xlnx-pmu-iomod-gp.c
diff --git a/include/hw/gpio/xlnx-pmu-iomod-gp.h b/include/hw/gpio/xlnx-pmu-iomod-gp.h
new file mode 100644
index 0000000000..0ee162829b
--- /dev/null
+++ b/include/hw/gpio/xlnx-pmu-iomod-gp.h
@@ -0,0 +1,52 @@
+/*
+ * QEMU model of Xilinx I/O Module GPO
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_XLNX_ZYNQMP_IOMOD_GPIO_H
+#define HW_XLNX_ZYNQMP_IOMOD_GPIO_H
+
+#include "qemu/osdep.h"
+
+#define TYPE_XLNX_ZYNQMP_IOMOD_GPIO "xlnx.pmu_iomodule_gpio"
+
+#define XLNX_ZYNQMP_IOMOD_GPIO(obj) \
+ OBJECT_CHECK(XlnxPMUIOGPIO, (obj), TYPE_XLNX_ZYNQMP_IOMOD_GPIO)
+
+#define XLNX_ZYNQMP_IOMOD_GPIO_R_MAX (0x00 + 1)
+
+typedef struct XlnxPMUIOGPIO {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+
+ uint32_t size;
+
+ /* GPO */
+ uint32_t init;
+ qemu_irq outputs[32];
+
+ uint32_t regs[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
+ RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
+} XlnxPMUIOGPIO;
+
+#endif /* HW_XLNX_ZYNQMP_IOMOD_GPIO_H */
diff --git a/hw/gpio/xlnx-pmu-iomod-gp.c b/hw/gpio/xlnx-pmu-iomod-gp.c
new file mode 100644
index 0000000000..0e45a89b44
--- /dev/null
+++ b/hw/gpio/xlnx-pmu-iomod-gp.c
@@ -0,0 +1,150 @@
+/*
+ * QEMU model of Xilinx I/O Module GPO
+ *
+ * Copyright (c) 2013 Xilinx Inc
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "qemu/log.h"
+#include "hw/gpio/xlnx-pmu-iomod-gp.h"
+
+#ifndef XLNX_ZYNQMP_IOMOD_GPIO_DEBUG
+#define XLNX_ZYNQMP_IOMOD_GPIO_DEBUG 0
+#endif
+
+REG32(GPO0, 0x00)
+
+static void xlnx_iomod_gpio_gpo0_prew(RegisterInfo *reg, uint64_t value)
+{
+ XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(reg->opaque);
+ unsigned int i;
+
+ for (i = 0; i < s->size; i++) {
+ bool flag = !!(value & (1 << i));
+ qemu_set_irq(s->outputs[i], flag);
+ }
+}
+
+static uint64_t xlnx_iomod_gpio_gpo0_postr(RegisterInfo *reg, uint64_t value)
+{
+ return 0;
+}
+
+static const RegisterAccessInfo xlnx_iomod_gpio_regs_info[] = {
+ { .name = "GPO0", .addr = A_GPO0,
+ .post_write = xlnx_iomod_gpio_gpo0_prew,
+ .post_read = xlnx_iomod_gpio_gpo0_postr,
+ }
+};
+
+static void xlnx_iomod_gpio_reset(DeviceState *dev)
+{
+ XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(dev);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
+ register_reset(&s->regs_info[i]);
+ }
+
+ xlnx_iomod_gpio_gpo0_prew(&s->regs_info[R_GPO0], s->init);
+}
+
+static const MemoryRegionOps xlnx_iomod_gpio_ops = {
+ .read = register_read_memory,
+ .write = register_write_memory,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void xlnx_iomod_gpio_realize(DeviceState *dev, Error **errp)
+{
+ XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(dev);
+
+ assert(s->size <= 32);
+ qdev_init_gpio_out(dev, s->outputs, s->size);
+}
+
+static void xlnx_iomod_gpio_init(Object *obj)
+{
+ XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ RegisterInfoArray *reg_array;
+
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
+ XLNX_ZYNQMP_IOMOD_GPIO_R_MAX * 4);
+ reg_array =
+ register_init_block32(DEVICE(obj), xlnx_iomod_gpio_regs_info,
+ ARRAY_SIZE(xlnx_iomod_gpio_regs_info),
+ s->regs_info, s->regs,
+ &xlnx_iomod_gpio_ops,
+ XLNX_ZYNQMP_IOMOD_GPIO_DEBUG,
+ XLNX_ZYNQMP_IOMOD_GPIO_R_MAX * 4);
+ memory_region_add_subregion(&s->iomem,
+ 0x0,
+ ®_array->mem);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_xlnx_iomod_gpio = {
+ .name = TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property xlnx_iomod_gpio_properties[] = {
+ DEFINE_PROP_UINT32("size", XlnxPMUIOGPIO, size, 0),
+ DEFINE_PROP_UINT32("gpo-init", XlnxPMUIOGPIO, init, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xlnx_iomod_gpio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->reset = xlnx_iomod_gpio_reset;
+ dc->realize = xlnx_iomod_gpio_realize;
+ dc->props = xlnx_iomod_gpio_properties;
+ dc->vmsd = &vmstate_xlnx_iomod_gpio;
+}
+
+static const TypeInfo xlnx_iomod_gpio_info = {
+ .name = TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XlnxPMUIOGPIO),
+ .class_init = xlnx_iomod_gpio_class_init,
+ .instance_init = xlnx_iomod_gpio_init,
+};
+
+static void xlnx_iomod_gpio_register_types(void)
+{
+ type_register_static(&xlnx_iomod_gpio_info);
+}
+
+type_init(xlnx_iomod_gpio_register_types)
diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
index fa0a72e6d0..4cefadee85 100644
--- a/hw/gpio/Makefile.objs
+++ b/hw/gpio/Makefile.objs
@@ -8,3 +8,5 @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
obj-$(CONFIG_OMAP) += omap_gpio.o
obj-$(CONFIG_IMX) += imx_gpio.o
obj-$(CONFIG_RASPI) += bcm2835_gpio.o
+
+obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-gp.o
--
2.14.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/5] hw/gpio: Add the xlnx-pmu-iomod-gpo device
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 3/5] hw/gpio: Add the xlnx-pmu-iomod-gpo device Alistair Francis
@ 2018-03-01 17:02 ` Philippe Mathieu-Daudé
2018-05-04 3:28 ` Alistair Francis
0 siblings, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-01 17:02 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair23
Hi Alistair,
On 02/28/2018 07:32 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> include/hw/gpio/xlnx-pmu-iomod-gp.h | 52 +++++++++++++
> hw/gpio/xlnx-pmu-iomod-gp.c | 150 ++++++++++++++++++++++++++++++++++++
> hw/gpio/Makefile.objs | 2 +
> 3 files changed, 204 insertions(+)
> create mode 100644 include/hw/gpio/xlnx-pmu-iomod-gp.h
> create mode 100644 hw/gpio/xlnx-pmu-iomod-gp.c
>
> diff --git a/include/hw/gpio/xlnx-pmu-iomod-gp.h b/include/hw/gpio/xlnx-pmu-iomod-gp.h
> new file mode 100644
> index 0000000000..0ee162829b
> --- /dev/null
> +++ b/include/hw/gpio/xlnx-pmu-iomod-gp.h
> @@ -0,0 +1,52 @@
> +/*
> + * QEMU model of Xilinx I/O Module GPO
> + *
> + * Copyright (c) 2013 Xilinx Inc
> + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_XLNX_ZYNQMP_IOMOD_GPIO_H
> +#define HW_XLNX_ZYNQMP_IOMOD_GPIO_H
Maybe HW_XLNX_IOMOD_GPIO_H is enough (removing ZYNQMP), or
HW_XLNX_PMU_IOMOD_GPIO_H is a better naming (using PMU).
(comment valid for the whole file).
> +
> +#include "qemu/osdep.h"
> +
> +#define TYPE_XLNX_ZYNQMP_IOMOD_GPIO "xlnx.pmu_iomodule_gpio"
> +
> +#define XLNX_ZYNQMP_IOMOD_GPIO(obj) \
> + OBJECT_CHECK(XlnxPMUIOGPIO, (obj), TYPE_XLNX_ZYNQMP_IOMOD_GPIO)
> +
> +#define XLNX_ZYNQMP_IOMOD_GPIO_R_MAX (0x00 + 1)
> +
> +typedef struct XlnxPMUIOGPIO {
> + SysBusDevice parent_obj;
> + MemoryRegion iomem;
> +
> + uint32_t size;
> +
> + /* GPO */
> + uint32_t init;
> + qemu_irq outputs[32];
Can you add a definition such XLNX_(PMU_)IOMOD_GPIO_COUNT?
> +
> + uint32_t regs[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
> + RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
> +} XlnxPMUIOGPIO;
> +
> +#endif /* HW_XLNX_ZYNQMP_IOMOD_GPIO_H */
> diff --git a/hw/gpio/xlnx-pmu-iomod-gp.c b/hw/gpio/xlnx-pmu-iomod-gp.c
> new file mode 100644
> index 0000000000..0e45a89b44
> --- /dev/null
> +++ b/hw/gpio/xlnx-pmu-iomod-gp.c
> @@ -0,0 +1,150 @@
> +/*
> + * QEMU model of Xilinx I/O Module GPO
> + *
> + * Copyright (c) 2013 Xilinx Inc
> + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/register.h"
> +#include "qemu/log.h"
> +#include "hw/gpio/xlnx-pmu-iomod-gp.h"
> +
> +#ifndef XLNX_ZYNQMP_IOMOD_GPIO_DEBUG
> +#define XLNX_ZYNQMP_IOMOD_GPIO_DEBUG 0
> +#endif
> +
> +REG32(GPO0, 0x00)
> +
> +static void xlnx_iomod_gpio_gpo0_prew(RegisterInfo *reg, uint64_t value)
> +{
> + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(reg->opaque);
> + unsigned int i;
> +
> + for (i = 0; i < s->size; i++) {
> + bool flag = !!(value & (1 << i));
> + qemu_set_irq(s->outputs[i], flag);
I thought this was available: qemu_set_irqs(s->outputs, value, s->size);
Maybe shorter:
qemu_set_irq(s->outputs[i], extract64(flag, i, 1);
> + }
> +}
> +
> +static uint64_t xlnx_iomod_gpio_gpo0_postr(RegisterInfo *reg, uint64_t value)
> +{
> + return 0;
> +}
> +
> +static const RegisterAccessInfo xlnx_iomod_gpio_regs_info[] = {
> + { .name = "GPO0", .addr = A_GPO0,
> + .post_write = xlnx_iomod_gpio_gpo0_prew,
> + .post_read = xlnx_iomod_gpio_gpo0_postr,
> + }
> +};
> +
> +static void xlnx_iomod_gpio_reset(DeviceState *dev)
> +{
> + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(dev);
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
> + register_reset(&s->regs_info[i]);
> + }
> +
> + xlnx_iomod_gpio_gpo0_prew(&s->regs_info[R_GPO0], s->init);
> +}
> +
> +static const MemoryRegionOps xlnx_iomod_gpio_ops = {
> + .read = register_read_memory,
> + .write = register_write_memory,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +
> +static void xlnx_iomod_gpio_realize(DeviceState *dev, Error **errp)
> +{
> + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(dev);
> +
> + assert(s->size <= 32);
XLNX_(PMU_)IOMOD_GPIO_COUNT?
> + qdev_init_gpio_out(dev, s->outputs, s->size);
> +}
> +
> +static void xlnx_iomod_gpio_init(Object *obj)
> +{
> + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(obj);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + RegisterInfoArray *reg_array;
> +
> + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
> + XLNX_ZYNQMP_IOMOD_GPIO_R_MAX * 4);
> + reg_array =
> + register_init_block32(DEVICE(obj), xlnx_iomod_gpio_regs_info,
> + ARRAY_SIZE(xlnx_iomod_gpio_regs_info),
> + s->regs_info, s->regs,
> + &xlnx_iomod_gpio_ops,
> + XLNX_ZYNQMP_IOMOD_GPIO_DEBUG,
> + XLNX_ZYNQMP_IOMOD_GPIO_R_MAX * 4);
> + memory_region_add_subregion(&s->iomem,
> + 0x0,
> + ®_array->mem);
> + sysbus_init_mmio(sbd, &s->iomem);
> +}
> +
> +static const VMStateDescription vmstate_xlnx_iomod_gpio = {
> + .name = TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_END_OF_LIST(),
> + }
> +};
> +
> +static Property xlnx_iomod_gpio_properties[] = {
> + DEFINE_PROP_UINT32("size", XlnxPMUIOGPIO, size, 0),
> + DEFINE_PROP_UINT32("gpo-init", XlnxPMUIOGPIO, init, 0),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void xlnx_iomod_gpio_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->reset = xlnx_iomod_gpio_reset;
> + dc->realize = xlnx_iomod_gpio_realize;
> + dc->props = xlnx_iomod_gpio_properties;
> + dc->vmsd = &vmstate_xlnx_iomod_gpio;
> +}
> +
> +static const TypeInfo xlnx_iomod_gpio_info = {
> + .name = TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XlnxPMUIOGPIO),
> + .class_init = xlnx_iomod_gpio_class_init,
> + .instance_init = xlnx_iomod_gpio_init,
> +};
> +
> +static void xlnx_iomod_gpio_register_types(void)
> +{
> + type_register_static(&xlnx_iomod_gpio_info);
> +}
> +
> +type_init(xlnx_iomod_gpio_register_types)
> diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
> index fa0a72e6d0..4cefadee85 100644
> --- a/hw/gpio/Makefile.objs
> +++ b/hw/gpio/Makefile.objs
> @@ -8,3 +8,5 @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
> obj-$(CONFIG_OMAP) += omap_gpio.o
> obj-$(CONFIG_IMX) += imx_gpio.o
> obj-$(CONFIG_RASPI) += bcm2835_gpio.o
> +
> +obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-gp.o
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 3/5] hw/gpio: Add the xlnx-pmu-iomod-gpo device
2018-03-01 17:02 ` Philippe Mathieu-Daudé
@ 2018-05-04 3:28 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2018-05-04 3:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
Edgar Iglesias, Edgar Iglesias
On Thu, Mar 1, 2018 at 9:02 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Alistair,
> On 02/28/2018 07:32 PM, Alistair Francis wrote:
> > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> > ---
> >
> > include/hw/gpio/xlnx-pmu-iomod-gp.h | 52 +++++++++++++
> > hw/gpio/xlnx-pmu-iomod-gp.c | 150
++++++++++++++++++++++++++++++++++++
> > hw/gpio/Makefile.objs | 2 +
> > 3 files changed, 204 insertions(+)
> > create mode 100644 include/hw/gpio/xlnx-pmu-iomod-gp.h
> > create mode 100644 hw/gpio/xlnx-pmu-iomod-gp.c
> >
> > diff --git a/include/hw/gpio/xlnx-pmu-iomod-gp.h
b/include/hw/gpio/xlnx-pmu-iomod-gp.h
> > new file mode 100644
> > index 0000000000..0ee162829b
> > --- /dev/null
> > +++ b/include/hw/gpio/xlnx-pmu-iomod-gp.h
> > @@ -0,0 +1,52 @@
> > +/*
> > + * QEMU model of Xilinx I/O Module GPO
> > + *
> > + * Copyright (c) 2013 Xilinx Inc
> > + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
obtaining a copy
> > + * of this software and associated documentation files (the
"Software"), to deal
> > + * in the Software without restriction, including without limitation
the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell
> > + * copies of the Software, and to permit persons to whom the Software
is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#ifndef HW_XLNX_ZYNQMP_IOMOD_GPIO_H
> > +#define HW_XLNX_ZYNQMP_IOMOD_GPIO_H
> Maybe HW_XLNX_IOMOD_GPIO_H is enough (removing ZYNQMP), or
> HW_XLNX_PMU_IOMOD_GPIO_H is a better naming (using PMU).
> (comment valid for the whole file).
That opens up a possibility of future conflicts. I think the ZynqMP should
stay in there.
> > +
> > +#include "qemu/osdep.h"
> > +
> > +#define TYPE_XLNX_ZYNQMP_IOMOD_GPIO "xlnx.pmu_iomodule_gpio"
> > +
> > +#define XLNX_ZYNQMP_IOMOD_GPIO(obj) \
> > + OBJECT_CHECK(XlnxPMUIOGPIO, (obj), TYPE_XLNX_ZYNQMP_IOMOD_GPIO)
> > +
> > +#define XLNX_ZYNQMP_IOMOD_GPIO_R_MAX (0x00 + 1)
> > +
> > +typedef struct XlnxPMUIOGPIO {
> > + SysBusDevice parent_obj;
> > + MemoryRegion iomem;
> > +
> > + uint32_t size;
> > +
> > + /* GPO */
> > + uint32_t init;
> > + qemu_irq outputs[32];
> Can you add a definition such XLNX_(PMU_)IOMOD_GPIO_COUNT?
Done.
> > +
> > + uint32_t regs[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
> > + RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
> > +} XlnxPMUIOGPIO;
> > +
> > +#endif /* HW_XLNX_ZYNQMP_IOMOD_GPIO_H */
> > diff --git a/hw/gpio/xlnx-pmu-iomod-gp.c b/hw/gpio/xlnx-pmu-iomod-gp.c
> > new file mode 100644
> > index 0000000000..0e45a89b44
> > --- /dev/null
> > +++ b/hw/gpio/xlnx-pmu-iomod-gp.c
> > @@ -0,0 +1,150 @@
> > +/*
> > + * QEMU model of Xilinx I/O Module GPO
> > + *
> > + * Copyright (c) 2013 Xilinx Inc
> > + * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
obtaining a copy
> > + * of this software and associated documentation files (the
"Software"), to deal
> > + * in the Software without restriction, including without limitation
the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell
> > + * copies of the Software, and to permit persons to whom the Software
is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/sysbus.h"
> > +#include "hw/register.h"
> > +#include "qemu/log.h"
> > +#include "hw/gpio/xlnx-pmu-iomod-gp.h"
> > +
> > +#ifndef XLNX_ZYNQMP_IOMOD_GPIO_DEBUG
> > +#define XLNX_ZYNQMP_IOMOD_GPIO_DEBUG 0
> > +#endif
> > +
> > +REG32(GPO0, 0x00)
> > +
> > +static void xlnx_iomod_gpio_gpo0_prew(RegisterInfo *reg, uint64_t
value)
> > +{
> > + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(reg->opaque);
> > + unsigned int i;
> > +
> > + for (i = 0; i < s->size; i++) {
> > + bool flag = !!(value & (1 << i));
> > + qemu_set_irq(s->outputs[i], flag);
> I thought this was available: qemu_set_irqs(s->outputs, value, s->size);
I don't see anything called that.
> Maybe shorter:
> qemu_set_irq(s->outputs[i], extract64(flag, i, 1);
I like the variable, it makes adding debug statements easier :)
Alistair
> > + }
> > +}
> > +
> > +static uint64_t xlnx_iomod_gpio_gpo0_postr(RegisterInfo *reg, uint64_t
value)
> > +{
> > + return 0;
> > +}
> > +
> > +static const RegisterAccessInfo xlnx_iomod_gpio_regs_info[] = {
> > + { .name = "GPO0", .addr = A_GPO0,
> > + .post_write = xlnx_iomod_gpio_gpo0_prew,
> > + .post_read = xlnx_iomod_gpio_gpo0_postr,
> > + }
> > +};
> > +
> > +static void xlnx_iomod_gpio_reset(DeviceState *dev)
> > +{
> > + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(dev);
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
> > + register_reset(&s->regs_info[i]);
> > + }
> > +
> > + xlnx_iomod_gpio_gpo0_prew(&s->regs_info[R_GPO0], s->init);
> > +}
> > +
> > +static const MemoryRegionOps xlnx_iomod_gpio_ops = {
> > + .read = register_read_memory,
> > + .write = register_write_memory,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4,
> > + },
> > +};
> > +
> > +static void xlnx_iomod_gpio_realize(DeviceState *dev, Error **errp)
> > +{
> > + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(dev);
> > +
> > + assert(s->size <= 32);
> XLNX_(PMU_)IOMOD_GPIO_COUNT?
> > + qdev_init_gpio_out(dev, s->outputs, s->size);
> > +}
> > +
> > +static void xlnx_iomod_gpio_init(Object *obj)
> > +{
> > + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(obj);
> > + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> > + RegisterInfoArray *reg_array;
> > +
> > + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
> > + XLNX_ZYNQMP_IOMOD_GPIO_R_MAX * 4);
> > + reg_array =
> > + register_init_block32(DEVICE(obj), xlnx_iomod_gpio_regs_info,
> > + ARRAY_SIZE(xlnx_iomod_gpio_regs_info),
> > + s->regs_info, s->regs,
> > + &xlnx_iomod_gpio_ops,
> > + XLNX_ZYNQMP_IOMOD_GPIO_DEBUG,
> > + XLNX_ZYNQMP_IOMOD_GPIO_R_MAX * 4);
> > + memory_region_add_subregion(&s->iomem,
> > + 0x0,
> > + ®_array->mem);
> > + sysbus_init_mmio(sbd, &s->iomem);
> > +}
> > +
> > +static const VMStateDescription vmstate_xlnx_iomod_gpio = {
> > + .name = TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
> > + .version_id = 1,
> > + .minimum_version_id = 1,
> > + .fields = (VMStateField[]) {
> > + VMSTATE_END_OF_LIST(),
> > + }
> > +};
> > +
> > +static Property xlnx_iomod_gpio_properties[] = {
> > + DEFINE_PROP_UINT32("size", XlnxPMUIOGPIO, size, 0),
> > + DEFINE_PROP_UINT32("gpo-init", XlnxPMUIOGPIO, init, 0),
> > + DEFINE_PROP_END_OF_LIST(),
> > +};
> > +
> > +static void xlnx_iomod_gpio_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->reset = xlnx_iomod_gpio_reset;
> > + dc->realize = xlnx_iomod_gpio_realize;
> > + dc->props = xlnx_iomod_gpio_properties;
> > + dc->vmsd = &vmstate_xlnx_iomod_gpio;
> > +}
> > +
> > +static const TypeInfo xlnx_iomod_gpio_info = {
> > + .name = TYPE_XLNX_ZYNQMP_IOMOD_GPIO,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(XlnxPMUIOGPIO),
> > + .class_init = xlnx_iomod_gpio_class_init,
> > + .instance_init = xlnx_iomod_gpio_init,
> > +};
> > +
> > +static void xlnx_iomod_gpio_register_types(void)
> > +{
> > + type_register_static(&xlnx_iomod_gpio_info);
> > +}
> > +
> > +type_init(xlnx_iomod_gpio_register_types)
> > diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs
> > index fa0a72e6d0..4cefadee85 100644
> > --- a/hw/gpio/Makefile.objs
> > +++ b/hw/gpio/Makefile.objs
> > @@ -8,3 +8,5 @@ common-obj-$(CONFIG_GPIO_KEY) += gpio_key.o
> > obj-$(CONFIG_OMAP) += omap_gpio.o
> > obj-$(CONFIG_IMX) += imx_gpio.o
> > obj-$(CONFIG_RASPI) += bcm2835_gpio.o
> > +
> > +obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-pmu-iomod-gp.o
> >
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v2 4/5] hw/gpio: Add support for the xlnx-pmu-iomod-gpi device
2018-02-28 22:31 [Qemu-devel] [PATCH v2 0/5] Add and connect the PMU IOModule devices Alistair Francis
` (2 preceding siblings ...)
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 3/5] hw/gpio: Add the xlnx-pmu-iomod-gpo device Alistair Francis
@ 2018-02-28 22:32 ` Alistair Francis
2018-03-01 17:12 ` Philippe Mathieu-Daudé
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices Alistair Francis
4 siblings, 1 reply; 15+ messages in thread
From: Alistair Francis @ 2018-02-28 22:32 UTC (permalink / raw)
To: qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair.francis, alistair23
Add support for setting the device and either input or output.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
include/hw/gpio/xlnx-pmu-iomod-gp.h | 7 ++++-
hw/gpio/xlnx-pmu-iomod-gp.c | 55 ++++++++++++++++++++++++++++++++++++-
2 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/include/hw/gpio/xlnx-pmu-iomod-gp.h b/include/hw/gpio/xlnx-pmu-iomod-gp.h
index 0ee162829b..d682693742 100644
--- a/include/hw/gpio/xlnx-pmu-iomod-gp.h
+++ b/include/hw/gpio/xlnx-pmu-iomod-gp.h
@@ -33,18 +33,23 @@
#define XLNX_ZYNQMP_IOMOD_GPIO(obj) \
OBJECT_CHECK(XlnxPMUIOGPIO, (obj), TYPE_XLNX_ZYNQMP_IOMOD_GPIO)
-#define XLNX_ZYNQMP_IOMOD_GPIO_R_MAX (0x00 + 1)
+#define XLNX_ZYNQMP_IOMOD_GPIO_R_MAX (0x20 + 1)
typedef struct XlnxPMUIOGPIO {
SysBusDevice parent_obj;
MemoryRegion iomem;
+ bool input;
uint32_t size;
/* GPO */
uint32_t init;
qemu_irq outputs[32];
+ /* GPI */
+ uint32_t ien;
+ qemu_irq parent_irq;
+
uint32_t regs[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
} XlnxPMUIOGPIO;
diff --git a/hw/gpio/xlnx-pmu-iomod-gp.c b/hw/gpio/xlnx-pmu-iomod-gp.c
index 0e45a89b44..467d844ae0 100644
--- a/hw/gpio/xlnx-pmu-iomod-gp.c
+++ b/hw/gpio/xlnx-pmu-iomod-gp.c
@@ -1,5 +1,5 @@
/*
- * QEMU model of Xilinx I/O Module GPO
+ * QEMU model of Xilinx I/O Module GPO and GPI
*
* Copyright (c) 2013 Xilinx Inc
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
@@ -34,12 +34,17 @@
#endif
REG32(GPO0, 0x00)
+REG32(GPI0, 0x20)
static void xlnx_iomod_gpio_gpo0_prew(RegisterInfo *reg, uint64_t value)
{
XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(reg->opaque);
unsigned int i;
+ if (s->input) {
+ return;
+ }
+
for (i = 0; i < s->size; i++) {
bool flag = !!(value & (1 << i));
qemu_set_irq(s->outputs[i], flag);
@@ -51,10 +56,50 @@ static uint64_t xlnx_iomod_gpio_gpo0_postr(RegisterInfo *reg, uint64_t value)
return 0;
}
+static void xlnx_iomod_gpio_irq_handler(void *opaque, int irq, int level)
+{
+ XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(opaque);
+ uint32_t old = s->regs[R_GPI0];
+
+ if (!s->input) {
+ return;
+ }
+
+ /* If enable is set for @irq pin, update @irq pin in GPI and
+ * trigger interrupt if transition is 0 -> 1.
+ */
+ if (s->ien & (1 << irq)) {
+ s->regs[R_GPI0] &= ~(1 << irq);
+ s->regs[R_GPI0] |= level << irq;
+ /* On input pin transition 0->1 trigger interrupt. */
+ if ((old != s->regs[R_GPI0]) && level) {
+ qemu_irq_pulse(s->parent_irq);
+ }
+ }
+}
+
+/* Called when someone writes into LOCAL GPIx_ENABLE */
+static void xlnx_iomod_gpio_ien_handler(void *opaque, int n, int level)
+{
+ XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(opaque);
+
+ if (!s->input) {
+ return;
+ }
+
+ s->ien = level;
+
+ /* Clear all GPIs that got disabled */
+ s->regs[R_GPI0] &= s->ien;
+}
+
static const RegisterAccessInfo xlnx_iomod_gpio_regs_info[] = {
{ .name = "GPO0", .addr = A_GPO0,
.post_write = xlnx_iomod_gpio_gpo0_prew,
.post_read = xlnx_iomod_gpio_gpo0_postr,
+ },{ .name = "GPI0", .addr = A_GPI0,
+ .rsvd = 0x300030,
+ .ro = 0xffcfffcf,
}
};
@@ -68,6 +113,9 @@ static void xlnx_iomod_gpio_reset(DeviceState *dev)
}
xlnx_iomod_gpio_gpo0_prew(&s->regs_info[R_GPO0], s->init);
+
+ /* Disable all interrupts initially. */
+ s->ien = 0;
}
static const MemoryRegionOps xlnx_iomod_gpio_ops = {
@@ -86,6 +134,9 @@ static void xlnx_iomod_gpio_realize(DeviceState *dev, Error **errp)
assert(s->size <= 32);
qdev_init_gpio_out(dev, s->outputs, s->size);
+
+ qdev_init_gpio_in_named(dev, xlnx_iomod_gpio_irq_handler, "GPI", 32);
+ qdev_init_gpio_in_named(dev, xlnx_iomod_gpio_ien_handler, "IEN", 32);
}
static void xlnx_iomod_gpio_init(Object *obj)
@@ -107,6 +158,7 @@ static void xlnx_iomod_gpio_init(Object *obj)
0x0,
®_array->mem);
sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->parent_irq);
}
static const VMStateDescription vmstate_xlnx_iomod_gpio = {
@@ -119,6 +171,7 @@ static const VMStateDescription vmstate_xlnx_iomod_gpio = {
};
static Property xlnx_iomod_gpio_properties[] = {
+ DEFINE_PROP_BOOL("input", XlnxPMUIOGPIO, input, false),
DEFINE_PROP_UINT32("size", XlnxPMUIOGPIO, size, 0),
DEFINE_PROP_UINT32("gpo-init", XlnxPMUIOGPIO, init, 0),
DEFINE_PROP_END_OF_LIST(),
--
2.14.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 4/5] hw/gpio: Add support for the xlnx-pmu-iomod-gpi device
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 4/5] hw/gpio: Add support for the xlnx-pmu-iomod-gpi device Alistair Francis
@ 2018-03-01 17:12 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-01 17:12 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair23
Hi Alistair,
On 02/28/2018 07:32 PM, Alistair Francis wrote:
> Add support for setting the device and either input or output.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> include/hw/gpio/xlnx-pmu-iomod-gp.h | 7 ++++-
> hw/gpio/xlnx-pmu-iomod-gp.c | 55 ++++++++++++++++++++++++++++++++++++-
> 2 files changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/gpio/xlnx-pmu-iomod-gp.h b/include/hw/gpio/xlnx-pmu-iomod-gp.h
> index 0ee162829b..d682693742 100644
> --- a/include/hw/gpio/xlnx-pmu-iomod-gp.h
> +++ b/include/hw/gpio/xlnx-pmu-iomod-gp.h
> @@ -33,18 +33,23 @@
> #define XLNX_ZYNQMP_IOMOD_GPIO(obj) \
> OBJECT_CHECK(XlnxPMUIOGPIO, (obj), TYPE_XLNX_ZYNQMP_IOMOD_GPIO)
>
> -#define XLNX_ZYNQMP_IOMOD_GPIO_R_MAX (0x00 + 1)
> +#define XLNX_ZYNQMP_IOMOD_GPIO_R_MAX (0x20 + 1)
>
> typedef struct XlnxPMUIOGPIO {
> SysBusDevice parent_obj;
> MemoryRegion iomem;
>
> + bool input;
Maybe rename as 'is_input'.
> uint32_t size;
>
> /* GPO */
> uint32_t init;
> qemu_irq outputs[32];
>
> + /* GPI */
> + uint32_t ien;
> + qemu_irq parent_irq;
> +
> uint32_t regs[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
> RegisterInfo regs_info[XLNX_ZYNQMP_IOMOD_GPIO_R_MAX];
> } XlnxPMUIOGPIO;
> diff --git a/hw/gpio/xlnx-pmu-iomod-gp.c b/hw/gpio/xlnx-pmu-iomod-gp.c
> index 0e45a89b44..467d844ae0 100644
> --- a/hw/gpio/xlnx-pmu-iomod-gp.c
> +++ b/hw/gpio/xlnx-pmu-iomod-gp.c
> @@ -1,5 +1,5 @@
> /*
> - * QEMU model of Xilinx I/O Module GPO
> + * QEMU model of Xilinx I/O Module GPO and GPI
> *
> * Copyright (c) 2013 Xilinx Inc
> * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> @@ -34,12 +34,17 @@
> #endif
>
> REG32(GPO0, 0x00)
> +REG32(GPI0, 0x20)
>
> static void xlnx_iomod_gpio_gpo0_prew(RegisterInfo *reg, uint64_t value)
> {
> XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(reg->opaque);
> unsigned int i;
>
> + if (s->input) {
Shouldn't we log something here? GUEST_ERROR probably.
> + return;
> + }
> +
> for (i = 0; i < s->size; i++) {
> bool flag = !!(value & (1 << i));
> qemu_set_irq(s->outputs[i], flag);
> @@ -51,10 +56,50 @@ static uint64_t xlnx_iomod_gpio_gpo0_postr(RegisterInfo *reg, uint64_t value)
> return 0;
> }
>
> +static void xlnx_iomod_gpio_irq_handler(void *opaque, int irq, int level)
> +{
> + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(opaque);
> + uint32_t old = s->regs[R_GPI0];
> +
> + if (!s->input) {
Ditto.
> + return;
> + }
> +
> + /* If enable is set for @irq pin, update @irq pin in GPI and
> + * trigger interrupt if transition is 0 -> 1.
> + */
> + if (s->ien & (1 << irq)) {
> + s->regs[R_GPI0] &= ~(1 << irq);
> + s->regs[R_GPI0] |= level << irq;
> + /* On input pin transition 0->1 trigger interrupt. */
> + if ((old != s->regs[R_GPI0]) && level) {
> + qemu_irq_pulse(s->parent_irq);
> + }
> + }
> +}
> +
> +/* Called when someone writes into LOCAL GPIx_ENABLE */
> +static void xlnx_iomod_gpio_ien_handler(void *opaque, int n, int level)
> +{
> + XlnxPMUIOGPIO *s = XLNX_ZYNQMP_IOMOD_GPIO(opaque);
> +
> + if (!s->input) {
Ditto.
> + return;
> + }
> +
> + s->ien = level;
> +
> + /* Clear all GPIs that got disabled */
> + s->regs[R_GPI0] &= s->ien;
> +}
> +
> static const RegisterAccessInfo xlnx_iomod_gpio_regs_info[] = {
> { .name = "GPO0", .addr = A_GPO0,
> .post_write = xlnx_iomod_gpio_gpo0_prew,
> .post_read = xlnx_iomod_gpio_gpo0_postr,
> + },{ .name = "GPI0", .addr = A_GPI0,
> + .rsvd = 0x300030,
> + .ro = 0xffcfffcf,
or
.ro = ~0x300030,
> }
> };
>
> @@ -68,6 +113,9 @@ static void xlnx_iomod_gpio_reset(DeviceState *dev)
> }
>
> xlnx_iomod_gpio_gpo0_prew(&s->regs_info[R_GPO0], s->init);
> +
> + /* Disable all interrupts initially. */
> + s->ien = 0;
> }
>
> static const MemoryRegionOps xlnx_iomod_gpio_ops = {
> @@ -86,6 +134,9 @@ static void xlnx_iomod_gpio_realize(DeviceState *dev, Error **errp)
>
> assert(s->size <= 32);
> qdev_init_gpio_out(dev, s->outputs, s->size);
> +
> + qdev_init_gpio_in_named(dev, xlnx_iomod_gpio_irq_handler, "GPI", 32);
> + qdev_init_gpio_in_named(dev, xlnx_iomod_gpio_ien_handler, "IEN", 32);
eventually 32 -> XLNX_(PMU_)IOMOD_GPIO_COUNT.
> }
>
> static void xlnx_iomod_gpio_init(Object *obj)
> @@ -107,6 +158,7 @@ static void xlnx_iomod_gpio_init(Object *obj)
> 0x0,
> ®_array->mem);
> sysbus_init_mmio(sbd, &s->iomem);
> + sysbus_init_irq(sbd, &s->parent_irq);
> }
>
> static const VMStateDescription vmstate_xlnx_iomod_gpio = {
> @@ -119,6 +171,7 @@ static const VMStateDescription vmstate_xlnx_iomod_gpio = {
> };
>
> static Property xlnx_iomod_gpio_properties[] = {
> + DEFINE_PROP_BOOL("input", XlnxPMUIOGPIO, input, false),
> DEFINE_PROP_UINT32("size", XlnxPMUIOGPIO, size, 0),
> DEFINE_PROP_UINT32("gpo-init", XlnxPMUIOGPIO, init, 0),
> DEFINE_PROP_END_OF_LIST(),
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices
2018-02-28 22:31 [Qemu-devel] [PATCH v2 0/5] Add and connect the PMU IOModule devices Alistair Francis
` (3 preceding siblings ...)
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 4/5] hw/gpio: Add support for the xlnx-pmu-iomod-gpi device Alistair Francis
@ 2018-02-28 22:32 ` Alistair Francis
2018-03-01 17:17 ` Philippe Mathieu-Daudé
2018-03-01 18:03 ` Philippe Mathieu-Daudé
4 siblings, 2 replies; 15+ messages in thread
From: Alistair Francis @ 2018-02-28 22:32 UTC (permalink / raw)
To: qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair.francis, alistair23
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
hw/microblaze/xlnx-zynqmp-pmu.c | 77 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 75 insertions(+), 2 deletions(-)
diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
index 35a2314ffb..fa5f0bfcf1 100644
--- a/hw/microblaze/xlnx-zynqmp-pmu.c
+++ b/hw/microblaze/xlnx-zynqmp-pmu.c
@@ -27,6 +27,7 @@
#include "hw/intc/xlnx-zynqmp-ipi.h"
#include "hw/intc/xlnx-pmu-iomod-intc.h"
#include "hw/timer/xlnx-pmu-iomod-pit.h"
+#include "hw/gpio/xlnx-pmu-iomod-gp.h"
/* Define the PMU device */
@@ -43,6 +44,9 @@
#define XLNX_ZYNQMP_PMU_NUM_IPIS 4
#define XLNX_ZYNQMP_PMU_NUM_PITS 4
+#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS 4
+#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS 4
+
static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
};
@@ -57,6 +61,17 @@ static const uint64_t pit_irq[XLNX_ZYNQMP_PMU_NUM_PITS] = {
3, 4, 5, 6,
};
+static const uint64_t iomod_gpi_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] = {
+ 0xFFD40020, 0xFFD40024, 0xFFD40028, 0xFFD4002C,
+};
+static const uint64_t iomod_gpi_irq[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] = {
+ 11, 12, 13, 14,
+};
+
+static const uint64_t iomod_gpo_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS] = {
+ 0xFFD40010, 0xFFD40014, 0xFFD40018, 0xFFD4001C,
+};
+
typedef struct XlnxZynqMPPMUSoCState {
/*< private >*/
DeviceState parent_obj;
@@ -156,6 +171,8 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
+ XlnxPMUIOGPIO *iomod_gpi[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS];
+ XlnxPMUIOGPIO *iomod_gpo[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS];
XlnxPMUPIT *pit[XLNX_ZYNQMP_PMU_NUM_PITS];
qemu_irq irq[32];
qemu_irq tmp_irq;
@@ -197,10 +214,60 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
}
+ /* Create and connect the IOMOD GPI device */
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
+ iomod_gpi[i] = g_new0(XlnxPMUIOGPIO, 1);
+ object_initialize(iomod_gpi[i], sizeof(XlnxPMUIOGPIO),
+ TYPE_XLNX_ZYNQMP_IOMOD_GPIO);
+ qdev_set_parent_bus(DEVICE(iomod_gpi[i]), sysbus_get_default());
+ }
+
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
+ object_property_set_bool(OBJECT(iomod_gpi[i]), true, "input",
+ &error_abort);
+ object_property_set_uint(OBJECT(iomod_gpi[i]), 0x20, "size",
+ &error_abort);
+ object_property_set_bool(OBJECT(iomod_gpi[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(iomod_gpi[i]), 0, iomod_gpi_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(iomod_gpi[i]), 0,
+ irq[iomod_gpi_irq[i]]);
+ /* The other GPIO lines connect to the ARM side of the SoC. When we
+ * have a way to model MicroBlaze QEMU and ARM QEMU together we can
+ * connect the GPIO lines.
+ */
+ }
+
+ /* Create and connect the IOMOD GPO device */
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS; i++) {
+ iomod_gpo[i] = g_new0(XlnxPMUIOGPIO, 1);
+ object_initialize(iomod_gpo[i], sizeof(XlnxPMUIOGPIO),
+ TYPE_XLNX_ZYNQMP_IOMOD_GPIO);
+ qdev_set_parent_bus(DEVICE(iomod_gpo[i]), sysbus_get_default());
+ }
+
+ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS; i++) {
+ object_property_set_bool(OBJECT(iomod_gpo[i]), false, "input",
+ &error_abort);
+ if (i) {
+ object_property_set_uint(OBJECT(iomod_gpo[i]), 0x20, "size",
+ &error_abort);
+ } else {
+ object_property_set_uint(OBJECT(iomod_gpo[i]), 0x09, "size",
+ &error_abort);
+ }
+ object_property_set_uint(OBJECT(iomod_gpo[i]), 0x00, "gpo-init",
+ &error_abort);
+ object_property_set_bool(OBJECT(iomod_gpo[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(iomod_gpo[i]), 0, iomod_gpo_addr[i]);
+ }
+
/* Create and connect the IOMOD PIT devices */
for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_PITS; i++) {
pit[i] = g_new0(XlnxPMUPIT, 1);
- object_initialize(pit[i], sizeof(XlnxPMUPIT), TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
+ object_initialize(pit[i], sizeof(XlnxPMUPIT),
+ TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
qdev_set_parent_bus(DEVICE(pit[i]), sysbus_get_default());
}
@@ -219,7 +286,13 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_hit_in", 0);
qdev_connect_gpio_out_named(DEVICE(pit[3]), "ps_hit_out", 0, tmp_irq);
- /* TODO: PIT0 and PIT2 "ps_config" GPIO goes to The GPO1 device. */
+ /* GP01 goes into PIT0 */
+ tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[0]), "ps_config", 0);
+ qdev_connect_gpio_out(DEVICE(iomod_gpo[1]), 2, tmp_irq);
+
+ /* GP01 goes into PIT2 */
+ tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_config", 0);
+ qdev_connect_gpio_out(DEVICE(iomod_gpo[1]), 6, tmp_irq);
/* Load the kernel */
microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
--
2.14.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices Alistair Francis
@ 2018-03-01 17:17 ` Philippe Mathieu-Daudé
2018-03-01 18:03 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-01 17:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair23
On 02/28/2018 07:32 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> hw/microblaze/xlnx-zynqmp-pmu.c | 77 +++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 75 insertions(+), 2 deletions(-)
>
> diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
> index 35a2314ffb..fa5f0bfcf1 100644
> --- a/hw/microblaze/xlnx-zynqmp-pmu.c
> +++ b/hw/microblaze/xlnx-zynqmp-pmu.c
> @@ -27,6 +27,7 @@
> #include "hw/intc/xlnx-zynqmp-ipi.h"
> #include "hw/intc/xlnx-pmu-iomod-intc.h"
> #include "hw/timer/xlnx-pmu-iomod-pit.h"
> +#include "hw/gpio/xlnx-pmu-iomod-gp.h"
>
> /* Define the PMU device */
>
> @@ -43,6 +44,9 @@
> #define XLNX_ZYNQMP_PMU_NUM_IPIS 4
> #define XLNX_ZYNQMP_PMU_NUM_PITS 4
>
> +#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS 4
> +#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS 4
> +
> static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
> 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
> };
> @@ -57,6 +61,17 @@ static const uint64_t pit_irq[XLNX_ZYNQMP_PMU_NUM_PITS] = {
> 3, 4, 5, 6,
> };
>
> +static const uint64_t iomod_gpi_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] = {
> + 0xFFD40020, 0xFFD40024, 0xFFD40028, 0xFFD4002C,
> +};
> +static const uint64_t iomod_gpi_irq[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] = {
> + 11, 12, 13, 14,
> +};
> +
> +static const uint64_t iomod_gpo_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS] = {
> + 0xFFD40010, 0xFFD40014, 0xFFD40018, 0xFFD4001C,
> +};
> +
> typedef struct XlnxZynqMPPMUSoCState {
> /*< private >*/
> DeviceState parent_obj;
> @@ -156,6 +171,8 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
> MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
> XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
> + XlnxPMUIOGPIO *iomod_gpi[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS];
> + XlnxPMUIOGPIO *iomod_gpo[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS];
> XlnxPMUPIT *pit[XLNX_ZYNQMP_PMU_NUM_PITS];
> qemu_irq irq[32];
> qemu_irq tmp_irq;
> @@ -197,10 +214,60 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
> }
>
> + /* Create and connect the IOMOD GPI device */
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
> + iomod_gpi[i] = g_new0(XlnxPMUIOGPIO, 1);
> + object_initialize(iomod_gpi[i], sizeof(XlnxPMUIOGPIO),
> + TYPE_XLNX_ZYNQMP_IOMOD_GPIO);
> + qdev_set_parent_bus(DEVICE(iomod_gpi[i]), sysbus_get_default());
> + }
> +
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
> + object_property_set_bool(OBJECT(iomod_gpi[i]), true, "input",
> + &error_abort);
> + object_property_set_uint(OBJECT(iomod_gpi[i]), 0x20, "size",
> + &error_abort);
> + object_property_set_bool(OBJECT(iomod_gpi[i]), true, "realized",
> + &error_abort);
> + sysbus_mmio_map(SYS_BUS_DEVICE(iomod_gpi[i]), 0, iomod_gpi_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(iomod_gpi[i]), 0,
> + irq[iomod_gpi_irq[i]]);
> + /* The other GPIO lines connect to the ARM side of the SoC. When we
> + * have a way to model MicroBlaze QEMU and ARM QEMU together we can
> + * connect the GPIO lines.
> + */
> + }
> +
> + /* Create and connect the IOMOD GPO device */
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS; i++) {
> + iomod_gpo[i] = g_new0(XlnxPMUIOGPIO, 1);
> + object_initialize(iomod_gpo[i], sizeof(XlnxPMUIOGPIO),
> + TYPE_XLNX_ZYNQMP_IOMOD_GPIO);
> + qdev_set_parent_bus(DEVICE(iomod_gpo[i]), sysbus_get_default());
> + }
> +
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS; i++) {
> + object_property_set_bool(OBJECT(iomod_gpo[i]), false, "input",
> + &error_abort);
> + if (i) {
> + object_property_set_uint(OBJECT(iomod_gpo[i]), 0x20, "size",
> + &error_abort);
> + } else {
> + object_property_set_uint(OBJECT(iomod_gpo[i]), 0x09, "size",
> + &error_abort);
> + }
> + object_property_set_uint(OBJECT(iomod_gpo[i]), 0x00, "gpo-init",
mis-indented :)
> + &error_abort);
> + object_property_set_bool(OBJECT(iomod_gpo[i]), true, "realized",
> + &error_abort);
> + sysbus_mmio_map(SYS_BUS_DEVICE(iomod_gpo[i]), 0, iomod_gpo_addr[i]);
> + }
> +
> /* Create and connect the IOMOD PIT devices */
> for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_PITS; i++) {
> pit[i] = g_new0(XlnxPMUPIT, 1);
> - object_initialize(pit[i], sizeof(XlnxPMUPIT), TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
> + object_initialize(pit[i], sizeof(XlnxPMUPIT),
> + TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
> qdev_set_parent_bus(DEVICE(pit[i]), sysbus_get_default());
> }
>
> @@ -219,7 +286,13 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_hit_in", 0);
> qdev_connect_gpio_out_named(DEVICE(pit[3]), "ps_hit_out", 0, tmp_irq);
>
> - /* TODO: PIT0 and PIT2 "ps_config" GPIO goes to The GPO1 device. */
> + /* GP01 goes into PIT0 */
> + tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[0]), "ps_config", 0);
> + qdev_connect_gpio_out(DEVICE(iomod_gpo[1]), 2, tmp_irq);
> +
> + /* GP01 goes into PIT2 */
> + tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_config", 0);
> + qdev_connect_gpio_out(DEVICE(iomod_gpo[1]), 6, tmp_irq);
>
> /* Load the kernel */
> microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices
2018-02-28 22:32 ` [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices Alistair Francis
2018-03-01 17:17 ` Philippe Mathieu-Daudé
@ 2018-03-01 18:03 ` Philippe Mathieu-Daudé
2018-05-04 3:54 ` Alistair Francis
1 sibling, 1 reply; 15+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-03-01 18:03 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, edgar.iglesias, edgar.iglesias; +Cc: alistair23
On 02/28/2018 07:32 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
>
> hw/microblaze/xlnx-zynqmp-pmu.c | 77 +++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 75 insertions(+), 2 deletions(-)
>
> diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c b/hw/microblaze/xlnx-zynqmp-pmu.c
> index 35a2314ffb..fa5f0bfcf1 100644
> --- a/hw/microblaze/xlnx-zynqmp-pmu.c
> +++ b/hw/microblaze/xlnx-zynqmp-pmu.c
> @@ -27,6 +27,7 @@
> #include "hw/intc/xlnx-zynqmp-ipi.h"
> #include "hw/intc/xlnx-pmu-iomod-intc.h"
> #include "hw/timer/xlnx-pmu-iomod-pit.h"
> +#include "hw/gpio/xlnx-pmu-iomod-gp.h"
>
> /* Define the PMU device */
>
> @@ -43,6 +44,9 @@
> #define XLNX_ZYNQMP_PMU_NUM_IPIS 4
> #define XLNX_ZYNQMP_PMU_NUM_PITS 4
>
> +#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS 4
> +#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS 4
> +
> static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
> 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
> };
> @@ -57,6 +61,17 @@ static const uint64_t pit_irq[XLNX_ZYNQMP_PMU_NUM_PITS] = {
> 3, 4, 5, 6,
> };
>
> +static const uint64_t iomod_gpi_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] = {
> + 0xFFD40020, 0xFFD40024, 0xFFD40028, 0xFFD4002C,
> +};
> +static const uint64_t iomod_gpi_irq[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] = {
> + 11, 12, 13, 14,
> +};
> +
> +static const uint64_t iomod_gpo_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS] = {
> + 0xFFD40010, 0xFFD40014, 0xFFD40018, 0xFFD4001C,
> +};
> +
> typedef struct XlnxZynqMPPMUSoCState {
> /*< private >*/
> DeviceState parent_obj;
> @@ -156,6 +171,8 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
> MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
> XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
> + XlnxPMUIOGPIO *iomod_gpi[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS];
> + XlnxPMUIOGPIO *iomod_gpo[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS];
> XlnxPMUPIT *pit[XLNX_ZYNQMP_PMU_NUM_PITS];
> qemu_irq irq[32];
> qemu_irq tmp_irq;
> @@ -197,10 +214,60 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
> }
>
> + /* Create and connect the IOMOD GPI device */
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
> + iomod_gpi[i] = g_new0(XlnxPMUIOGPIO, 1);
> + object_initialize(iomod_gpi[i], sizeof(XlnxPMUIOGPIO),
> + TYPE_XLNX_ZYNQMP_IOMOD_GPIO);
> + qdev_set_parent_bus(DEVICE(iomod_gpi[i]), sysbus_get_default());
> + }
> +
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
> + object_property_set_bool(OBJECT(iomod_gpi[i]), true, "input",
> + &error_abort);
> + object_property_set_uint(OBJECT(iomod_gpi[i]), 0x20, "size",
> + &error_abort);
I previously misread this, you are initializing the 4 GPIs as GPI0, it
may be cleaner to add an index property to select the correct GPI
RegisterAccessInfo, or add a 'reserved' bitmask property and use a
generic GPI.
In particular GPI3 is read-only.
> + object_property_set_bool(OBJECT(iomod_gpi[i]), true, "realized",
> + &error_abort);
> + sysbus_mmio_map(SYS_BUS_DEVICE(iomod_gpi[i]), 0, iomod_gpi_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(iomod_gpi[i]), 0,
> + irq[iomod_gpi_irq[i]]);
> + /* The other GPIO lines connect to the ARM side of the SoC. When we
> + * have a way to model MicroBlaze QEMU and ARM QEMU together we can
> + * connect the GPIO lines.
> + */
> + }
> +
> + /* Create and connect the IOMOD GPO device */
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS; i++) {
> + iomod_gpo[i] = g_new0(XlnxPMUIOGPIO, 1);
> + object_initialize(iomod_gpo[i], sizeof(XlnxPMUIOGPIO),
> + TYPE_XLNX_ZYNQMP_IOMOD_GPIO);
> + qdev_set_parent_bus(DEVICE(iomod_gpo[i]), sysbus_get_default());
> + }
> +
> + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS; i++) {
> + object_property_set_bool(OBJECT(iomod_gpo[i]), false, "input",
> + &error_abort);
> + if (i) {
> + object_property_set_uint(OBJECT(iomod_gpo[i]), 0x20, "size",
> + &error_abort);
> + } else {
> + object_property_set_uint(OBJECT(iomod_gpo[i]), 0x09, "size",
> + &error_abort);
> + }
> + object_property_set_uint(OBJECT(iomod_gpo[i]), 0x00, "gpo-init",
> + &error_abort);
Ditto, the 4 GPOs are initialized as GPO0 (and GPO3 is write-only, we
could use GUEST_ERROR reports).
> + object_property_set_bool(OBJECT(iomod_gpo[i]), true, "realized",
> + &error_abort);
> + sysbus_mmio_map(SYS_BUS_DEVICE(iomod_gpo[i]), 0, iomod_gpo_addr[i]);
> + }
> +
> /* Create and connect the IOMOD PIT devices */
> for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_PITS; i++) {
> pit[i] = g_new0(XlnxPMUPIT, 1);
> - object_initialize(pit[i], sizeof(XlnxPMUPIT), TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
> + object_initialize(pit[i], sizeof(XlnxPMUPIT),
> + TYPE_XLNX_ZYNQMP_IOMODULE_PIT);
> qdev_set_parent_bus(DEVICE(pit[i]), sysbus_get_default());
> }
>
> @@ -219,7 +286,13 @@ static void xlnx_zynqmp_pmu_init(MachineState *machine)
> tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_hit_in", 0);
> qdev_connect_gpio_out_named(DEVICE(pit[3]), "ps_hit_out", 0, tmp_irq);
>
> - /* TODO: PIT0 and PIT2 "ps_config" GPIO goes to The GPO1 device. */
> + /* GP01 goes into PIT0 */
> + tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[0]), "ps_config", 0);
> + qdev_connect_gpio_out(DEVICE(iomod_gpo[1]), 2, tmp_irq);
> +
> + /* GP01 goes into PIT2 */
> + tmp_irq = qdev_get_gpio_in_named(DEVICE(pit[2]), "ps_config", 0);
> + qdev_connect_gpio_out(DEVICE(iomod_gpo[1]), 6, tmp_irq);
>
> /* Load the kernel */
> microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR,
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [Qemu-devel] [PATCH v2 5/5] xlnx-zynqmp-pmu: Connect the IOMOD GPI/GPO devices
2018-03-01 18:03 ` Philippe Mathieu-Daudé
@ 2018-05-04 3:54 ` Alistair Francis
0 siblings, 0 replies; 15+ messages in thread
From: Alistair Francis @ 2018-05-04 3:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
Edgar Iglesias, Edgar Iglesias
On Thu, Mar 1, 2018 at 10:03 AM Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> On 02/28/2018 07:32 PM, Alistair Francis wrote:
> > Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> > ---
> >
> > hw/microblaze/xlnx-zynqmp-pmu.c | 77
+++++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 75 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/microblaze/xlnx-zynqmp-pmu.c
b/hw/microblaze/xlnx-zynqmp-pmu.c
> > index 35a2314ffb..fa5f0bfcf1 100644
> > --- a/hw/microblaze/xlnx-zynqmp-pmu.c
> > +++ b/hw/microblaze/xlnx-zynqmp-pmu.c
> > @@ -27,6 +27,7 @@
> > #include "hw/intc/xlnx-zynqmp-ipi.h"
> > #include "hw/intc/xlnx-pmu-iomod-intc.h"
> > #include "hw/timer/xlnx-pmu-iomod-pit.h"
> > +#include "hw/gpio/xlnx-pmu-iomod-gp.h"
> >
> > /* Define the PMU device */
> >
> > @@ -43,6 +44,9 @@
> > #define XLNX_ZYNQMP_PMU_NUM_IPIS 4
> > #define XLNX_ZYNQMP_PMU_NUM_PITS 4
> >
> > +#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS 4
> > +#define XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS 4
> > +
> > static const uint64_t ipi_addr[XLNX_ZYNQMP_PMU_NUM_IPIS] = {
> > 0xFF340000, 0xFF350000, 0xFF360000, 0xFF370000,
> > };
> > @@ -57,6 +61,17 @@ static const uint64_t
pit_irq[XLNX_ZYNQMP_PMU_NUM_PITS] = {
> > 3, 4, 5, 6,
> > };
> >
> > +static const uint64_t iomod_gpi_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] =
{
> > + 0xFFD40020, 0xFFD40024, 0xFFD40028, 0xFFD4002C,
> > +};
> > +static const uint64_t iomod_gpi_irq[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS] = {
> > + 11, 12, 13, 14,
> > +};
> > +
> > +static const uint64_t iomod_gpo_addr[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS] =
{
> > + 0xFFD40010, 0xFFD40014, 0xFFD40018, 0xFFD4001C,
> > +};
> > +
> > typedef struct XlnxZynqMPPMUSoCState {
> > /*< private >*/
> > DeviceState parent_obj;
> > @@ -156,6 +171,8 @@ static void xlnx_zynqmp_pmu_init(MachineState
*machine)
> > MemoryRegion *pmu_rom = g_new(MemoryRegion, 1);
> > MemoryRegion *pmu_ram = g_new(MemoryRegion, 1);
> > XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS];
> > + XlnxPMUIOGPIO *iomod_gpi[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS];
> > + XlnxPMUIOGPIO *iomod_gpo[XLNX_ZYNQMP_PMU_NUM_IOMOD_GPOS];
> > XlnxPMUPIT *pit[XLNX_ZYNQMP_PMU_NUM_PITS];
> > qemu_irq irq[32];
> > qemu_irq tmp_irq;
> > @@ -197,10 +214,60 @@ static void xlnx_zynqmp_pmu_init(MachineState
*machine)
> > sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]);
> > }
> >
> > + /* Create and connect the IOMOD GPI device */
> > + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
> > + iomod_gpi[i] = g_new0(XlnxPMUIOGPIO, 1);
> > + object_initialize(iomod_gpi[i], sizeof(XlnxPMUIOGPIO),
> > + TYPE_XLNX_ZYNQMP_IOMOD_GPIO);
> > + qdev_set_parent_bus(DEVICE(iomod_gpi[i]),
sysbus_get_default());
> > + }
> > +
> > + for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IOMOD_GPIS; i++) {
> > + object_property_set_bool(OBJECT(iomod_gpi[i]), true, "input",
> > + &error_abort);
> > + object_property_set_uint(OBJECT(iomod_gpi[i]), 0x20, "size",
> > + &error_abort);
> I previously misread this, you are initializing the 4 GPIs as GPI0, it
> may be cleaner to add an index property to select the correct GPI
> RegisterAccessInfo, or add a 'reserved' bitmask property and use a
> generic GPI.
> In particular GPI3 is read-only.
I'm not sure what you mean here.
Alistair
^ permalink raw reply [flat|nested] 15+ messages in thread