From: Alistair Francis <alistair23@gmail.com> To: Anup Patel <anup@brainfault.org> Cc: Peter Maydell <peter.maydell@linaro.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Anup Patel <anup.patel@wdc.com>, QEMU Developers <qemu-devel@nongnu.org>, Atish Patra <atish.patra@wdc.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: Re: [PATCH 0/4] AIA local interrupt CSR support Date: Fri, 11 Jun 2021 18:40:33 +1000 [thread overview] Message-ID: <CAKmqyKOHbVvM5haU-hVAUg_wB_h=Ap2rZzvutNyF7JMUvB80pw@mail.gmail.com> (raw) In-Reply-To: <CAAhSdy3KmvjR8hnMz2UXomA45FcEV9fmiCXRBFGMRQus5=c6Lg@mail.gmail.com> On Fri, Jun 11, 2021 at 4:48 PM Anup Patel <anup@brainfault.org> wrote: > > Hi Alistair, > > On Fri, May 14, 2021 at 8:03 PM Anup Patel <anup.patel@wdc.com> wrote: > > > > The advanced interrupt architecture (AIA) extends the per-HART local > > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > > and Advanced PLIC (wired interrupt controller). > > > > The latest AIA draft specification can be found here: > > http://jhauser.us/private/RISCV-AIA/riscv-interrupts-021.pdf > > > > This series adds initial AIA support in QEMU which includes emulating all > > AIA local CSR. To enable AIA in QEMU, we just need to pass "x-aia=true" > > paramenter in "-cpu" QEMU command-line. > > > > To test series, we require OpenSBI and Linux with AIA support which > > can be found in riscv_aia_v1 branch at: > > https://github.com/avpatel/opensbi.git > > https://github.com/avpatel/linux.git > > > > Anup Patel (4): > > target/riscv: Add defines for AIA local interrupt CSRs > > target/riscv: Add CPU feature for AIA CSRs > > target/riscv: Implement AIA local interrupt CSRs > > hw/riscv: virt: Use AIA INTC compatible string when available > > The ACLINT specification will be frozen soon (probably early next > month). The ACLINT QEMU support patches are also ready and don't > depend on the AIA QEMU support patches. > > Is it okay to target ACLINT support in QEMU first ? Yeah, go for it. Alistair > > I can rebase this series on ACLINT support patches and also include > more AIA emulation patches (APLIC and IMSIC) in the AIA series. > > Regards, > Anup > > > > > hw/riscv/virt.c | 11 +- > > target/riscv/cpu.c | 32 +- > > target/riscv/cpu.h | 56 +- > > target/riscv/cpu_bits.h | 128 +++++ > > target/riscv/cpu_helper.c | 245 ++++++++- > > target/riscv/csr.c | 1059 +++++++++++++++++++++++++++++++++++-- > > target/riscv/machine.c | 26 +- > > 7 files changed, 1454 insertions(+), 103 deletions(-) > > > > -- > > 2.25.1 > > >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Anup Patel <anup@brainfault.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, Peter Maydell <peter.maydell@linaro.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Anup Patel <anup.patel@wdc.com>, QEMU Developers <qemu-devel@nongnu.org>, Atish Patra <atish.patra@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: Re: [PATCH 0/4] AIA local interrupt CSR support Date: Fri, 11 Jun 2021 18:40:33 +1000 [thread overview] Message-ID: <CAKmqyKOHbVvM5haU-hVAUg_wB_h=Ap2rZzvutNyF7JMUvB80pw@mail.gmail.com> (raw) In-Reply-To: <CAAhSdy3KmvjR8hnMz2UXomA45FcEV9fmiCXRBFGMRQus5=c6Lg@mail.gmail.com> On Fri, Jun 11, 2021 at 4:48 PM Anup Patel <anup@brainfault.org> wrote: > > Hi Alistair, > > On Fri, May 14, 2021 at 8:03 PM Anup Patel <anup.patel@wdc.com> wrote: > > > > The advanced interrupt architecture (AIA) extends the per-HART local > > interrupt support. Along with this, it also adds IMSIC (MSI contrllor) > > and Advanced PLIC (wired interrupt controller). > > > > The latest AIA draft specification can be found here: > > http://jhauser.us/private/RISCV-AIA/riscv-interrupts-021.pdf > > > > This series adds initial AIA support in QEMU which includes emulating all > > AIA local CSR. To enable AIA in QEMU, we just need to pass "x-aia=true" > > paramenter in "-cpu" QEMU command-line. > > > > To test series, we require OpenSBI and Linux with AIA support which > > can be found in riscv_aia_v1 branch at: > > https://github.com/avpatel/opensbi.git > > https://github.com/avpatel/linux.git > > > > Anup Patel (4): > > target/riscv: Add defines for AIA local interrupt CSRs > > target/riscv: Add CPU feature for AIA CSRs > > target/riscv: Implement AIA local interrupt CSRs > > hw/riscv: virt: Use AIA INTC compatible string when available > > The ACLINT specification will be frozen soon (probably early next > month). The ACLINT QEMU support patches are also ready and don't > depend on the AIA QEMU support patches. > > Is it okay to target ACLINT support in QEMU first ? Yeah, go for it. Alistair > > I can rebase this series on ACLINT support patches and also include > more AIA emulation patches (APLIC and IMSIC) in the AIA series. > > Regards, > Anup > > > > > hw/riscv/virt.c | 11 +- > > target/riscv/cpu.c | 32 +- > > target/riscv/cpu.h | 56 +- > > target/riscv/cpu_bits.h | 128 +++++ > > target/riscv/cpu_helper.c | 245 ++++++++- > > target/riscv/csr.c | 1059 +++++++++++++++++++++++++++++++++++-- > > target/riscv/machine.c | 26 +- > > 7 files changed, 1454 insertions(+), 103 deletions(-) > > > > -- > > 2.25.1 > > >
next prev parent reply other threads:[~2021-06-11 8:42 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-14 14:32 [PATCH 0/4] AIA local interrupt CSR support Anup Patel 2021-05-14 14:32 ` Anup Patel 2021-05-14 14:32 ` [PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs Anup Patel 2021-05-14 14:32 ` Anup Patel 2021-06-10 22:26 ` Alistair Francis 2021-06-10 22:26 ` Alistair Francis 2021-05-14 14:32 ` [PATCH 2/4] target/riscv: Add CPU feature for AIA CSRs Anup Patel 2021-05-14 14:32 ` Anup Patel 2021-06-10 23:15 ` Alistair Francis 2021-06-10 23:15 ` Alistair Francis 2021-06-11 4:58 ` Anup Patel 2021-06-11 4:58 ` Anup Patel 2021-05-14 14:32 ` [PATCH 3/4] target/riscv: Implement AIA local interrupt CSRs Anup Patel 2021-05-14 14:32 ` Anup Patel 2021-06-10 23:19 ` Alistair Francis 2021-06-10 23:19 ` Alistair Francis 2021-06-11 5:04 ` Anup Patel 2021-06-11 5:04 ` Anup Patel 2021-06-11 8:45 ` Alistair Francis 2021-06-11 8:45 ` Alistair Francis 2021-06-11 14:04 ` Anup Patel 2021-06-11 14:04 ` Anup Patel 2021-06-15 8:11 ` Alistair Francis 2021-06-15 8:11 ` Alistair Francis 2021-06-15 12:48 ` Anup Patel 2021-06-15 12:48 ` Anup Patel 2021-05-14 14:32 ` [PATCH 4/4] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel 2021-05-14 14:32 ` Anup Patel 2021-06-10 23:20 ` Alistair Francis 2021-06-10 23:20 ` Alistair Francis 2021-06-11 6:47 ` [PATCH 0/4] AIA local interrupt CSR support Anup Patel 2021-06-11 6:47 ` Anup Patel 2021-06-11 8:40 ` Alistair Francis [this message] 2021-06-11 8:40 ` Alistair Francis
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