* [PATCH 0/3] Add support for Shakti SoC from IIT-M
@ 2021-03-14 8:39 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: Vijai Kumar K, qemu-devel
This series adds initial suppport for emulating shakti soc[1] running
on arty 100T.
Shakti SoC uses Shakti C class core[2] and Shakti Uart[3]
[1] https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
[2] https://gitlab.com/shaktiproject/cores/c-class/-/blob/master/README.md
[3] https://gitlab.com/shaktiproject/uncore/devices/-/tree/master/uart_v2
Vijai Kumar K (3):
riscv: Add initial support for Shakti C class
hw/char: Add Shakti UART emulation
hw/riscv: Connect Shakti UART to Shakti platform
MAINTAINERS | 9 +
default-configs/devices/riscv64-softmmu.mak | 1 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 204 ++++++++++++++++++++
hw/char/trace-events | 4 +
hw/riscv/Kconfig | 10 +
hw/riscv/meson.build | 1 +
hw/riscv/shakti_c.c | 185 ++++++++++++++++++
include/hw/char/shakti_uart.h | 74 +++++++
include/hw/riscv/shakti_c.h | 76 ++++++++
target/riscv/cpu.c | 9 +
target/riscv/cpu.h | 1 +
12 files changed, 575 insertions(+)
create mode 100644 hw/char/shakti_uart.c
create mode 100644 hw/riscv/shakti_c.c
create mode 100644 include/hw/char/shakti_uart.h
create mode 100644 include/hw/riscv/shakti_c.h
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/3] Add support for Shakti SoC from IIT-M
@ 2021-03-14 8:39 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: qemu-devel, Vijai Kumar K
This series adds initial suppport for emulating shakti soc[1] running
on arty 100T.
Shakti SoC uses Shakti C class core[2] and Shakti Uart[3]
[1] https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
[2] https://gitlab.com/shaktiproject/cores/c-class/-/blob/master/README.md
[3] https://gitlab.com/shaktiproject/uncore/devices/-/tree/master/uart_v2
Vijai Kumar K (3):
riscv: Add initial support for Shakti C class
hw/char: Add Shakti UART emulation
hw/riscv: Connect Shakti UART to Shakti platform
MAINTAINERS | 9 +
default-configs/devices/riscv64-softmmu.mak | 1 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 204 ++++++++++++++++++++
hw/char/trace-events | 4 +
hw/riscv/Kconfig | 10 +
hw/riscv/meson.build | 1 +
hw/riscv/shakti_c.c | 185 ++++++++++++++++++
include/hw/char/shakti_uart.h | 74 +++++++
include/hw/riscv/shakti_c.h | 76 ++++++++
target/riscv/cpu.c | 9 +
target/riscv/cpu.h | 1 +
12 files changed, 575 insertions(+)
create mode 100644 hw/char/shakti_uart.c
create mode 100644 hw/riscv/shakti_c.c
create mode 100644 include/hw/char/shakti_uart.h
create mode 100644 include/hw/riscv/shakti_c.h
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/3] riscv: Add initial support for Shakti C class
2021-03-14 8:39 ` Vijai Kumar K
@ 2021-03-14 8:39 ` Vijai Kumar K
-1 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: Vijai Kumar K, qemu-devel
C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Add support for emulating Shakti SoC based on C-class running on arty-100T
platform.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
---
MAINTAINERS | 7 +
default-configs/devices/riscv64-softmmu.mak | 1 +
hw/riscv/Kconfig | 10 ++
hw/riscv/meson.build | 1 +
hw/riscv/shakti_c.c | 178 ++++++++++++++++++++
include/hw/riscv/shakti_c.h | 74 ++++++++
target/riscv/cpu.c | 9 +
target/riscv/cpu.h | 1 +
8 files changed, 281 insertions(+)
create mode 100644 hw/riscv/shakti_c.c
create mode 100644 include/hw/riscv/shakti_c.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e9f0d591e..9f71c4cc3f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1380,6 +1380,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+Shakti C class SoC
+M: Vijai Kumar K <vijai@behindbytes.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/shakti_c.c
+F: include/hw/riscv/shakti_c.h
+
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
M: Bin Meng <bin.meng@windriver.com>
diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
index d5eec75f05..bc69301fa4 100644
--- a/default-configs/devices/riscv64-softmmu.mak
+++ b/default-configs/devices/riscv64-softmmu.mak
@@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
CONFIG_MICROCHIP_PFSOC=y
+CONFIG_SHAKTI_C=y
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index d139074b02..92a62b5ce9 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -19,6 +19,16 @@ config OPENTITAN
select IBEX
select UNIMP
+config SHAKTI
+ bool
+
+config SHAKTI_C
+ bool
+ select UNIMP
+ select SHAKTI
+ select SIFIVE_CLINT
+ select SIFIVE_PLIC
+
config RISCV_VIRT
bool
imply PCI_DEVICES
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 275c0f7eb7..a97454661c 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
new file mode 100644
index 0000000000..e96436a3bf
--- /dev/null
+++ b/hw/riscv/shakti_c.c
@@ -0,0 +1,178 @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/riscv/shakti_c.h"
+#include "qapi/error.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/intc/sifive_clint.h"
+#include "sysemu/sysemu.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "hw/riscv/boot.h"
+
+#define DEBUG_SHAKTI_C 0
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_SHAKTI_C) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_RISCV_SHAKTI_SOC, \
+ __func__, ##args); \
+ } \
+ } while (0)
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} shakti_c_memmap[] = {
+ [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
+ [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
+ [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
+ [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
+ [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
+ [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
+ [SHAKTI_C_DEBUG] = { 0x00000000, 0x00010 },
+ [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
+};
+
+static void shakti_c_machine_state_init(MachineState *mstate)
+{
+ ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ int i;
+
+ /* Initialize SoC */
+ object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
+ TYPE_RISCV_SHAKTI_SOC);
+ qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
+
+ /* register RAM */
+ memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
+ mstate->ram_size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ shakti_c_memmap[SHAKTI_C_RAM].base,
+ main_mem);
+
+ /* ROM reset vector */
+ uint32_t reset_vec[3];
+
+ reset_vec[0] = 0x080002b7; /* lui t0,0x08000 */
+ reset_vec[1] = 0x00429293; /* slli t0,t0,4 */
+ reset_vec[2] = 0x00028067; /* jr t0 */
+
+ /* copy in the reset vector in little_endian byte order */
+ for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
+ reset_vec[i] = cpu_to_le32(reset_vec[i]);
+ }
+ rom_add_blob_fixed_as("rom.reset", reset_vec, sizeof(reset_vec),
+ shakti_c_memmap[SHAKTI_C_ROM].base,
+ &address_space_memory);
+ riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
+ NULL);
+}
+
+static void shakti_c_machine_instance_init(Object *obj)
+{
+}
+
+static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(klass);
+ mc->desc = "RISC-V Board compatible with Shakti SDK";
+ mc->init = shakti_c_machine_state_init;
+ mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+}
+
+static const TypeInfo shakti_c_machine_type_info = {
+ .name = TYPE_RISCV_SHAKTI_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = shakti_c_machine_class_init,
+ .instance_init = shakti_c_machine_instance_init,
+ .instance_size = sizeof(ShaktiCMachineState),
+};
+
+static void shakti_c_machine_type_info_register(void)
+{
+ type_register_static(&shakti_c_machine_type_info);
+}
+type_init(shakti_c_machine_type_info_register)
+
+static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
+{
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
+ MemoryRegion *system_memory = get_system_memory();
+ sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
+ sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
+ (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
+ SHAKTI_C_PLIC_NUM_SOURCES,
+ SHAKTI_C_PLIC_NUM_PRIORITIES,
+ SHAKTI_C_PLIC_PRIORITY_BASE,
+ SHAKTI_C_PLIC_PENDING_BASE,
+ SHAKTI_C_PLIC_ENABLE_BASE,
+ SHAKTI_C_PLIC_ENABLE_STRIDE,
+ SHAKTI_C_PLIC_CONTEXT_BASE,
+ SHAKTI_C_PLIC_CONTEXT_STRIDE,
+ shakti_c_memmap[SHAKTI_C_PLIC].size);
+ sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
+ shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ /* ROM */
+ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
+ shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
+}
+
+static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = shakti_c_soc_state_realize;
+}
+
+static void shakti_c_soc_instance_init(Object *obj)
+{
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
+
+ object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+
+ /*
+ * CPU type is fixed and we are not supporting passing from commandline yet.
+ * So let it be in instance_init. When supported should use ms->cpu_type
+ * instead of TYPE_RISCV_CPU_SHAKTI_C
+ */
+ object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
+ TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
+ object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
+ &error_abort);
+}
+
+static const TypeInfo shakti_c_type_info = {
+ .name = TYPE_RISCV_SHAKTI_SOC,
+ .parent = TYPE_DEVICE,
+ .class_init = shakti_c_soc_class_init,
+ .instance_init = shakti_c_soc_instance_init,
+ .instance_size = sizeof(ShaktiCSoCState),
+};
+
+static void shakti_c_type_info_register(void)
+{
+ type_register_static(&shakti_c_type_info);
+}
+type_init(shakti_c_type_info_register)
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
new file mode 100644
index 0000000000..6c66a160f5
--- /dev/null
+++ b/include/hw/riscv/shakti_c.h
@@ -0,0 +1,74 @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SHAKTI_H
+#define HW_SHAKTI_H
+
+#include "hw/riscv/riscv_hart.h"
+#include "hw/boards.h"
+
+#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
+#define RISCV_SHAKTI_SOC(obj) \
+ OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
+
+typedef struct ShaktiCSoCState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ RISCVHartArrayState cpus;
+ DeviceState *plic;
+ MemoryRegion rom;
+
+} ShaktiCSoCState;
+
+#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
+#define RISCV_SHAKTI_MACHINE(obj) \
+ OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
+typedef struct ShaktiCMachineState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ ShaktiCSoCState soc;
+} ShaktiCMachineState;
+
+enum {
+ SHAKTI_C_ROM,
+ SHAKTI_C_RAM,
+ SHAKTI_C_UART,
+ SHAKTI_C_GPIO,
+ SHAKTI_C_PLIC,
+ SHAKTI_C_CLINT,
+ SHAKTI_C_DEBUG,
+ SHAKTI_C_I2C,
+};
+
+#define SHAKTI_C_PLIC_HART_CONFIG "MS"
+/* Including Interrupt ID 0 (no interrupt)*/
+#define SHAKTI_C_PLIC_NUM_SOURCES 28
+/* Excluding Priority 0 */
+#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
+#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
+#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
+#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
+#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
+#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
+#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
+
+#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2a990f6253..618d203aa0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -159,6 +159,14 @@ static void rv64_base_cpu_init(Object *obj)
set_misa(env, RV64);
}
+static void rv64_shakti_c_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_priv_version(env, PRIV_VERSION_1_10_0);
+ set_resetvec(env, DEFAULT_RSTVEC);
+}
+
static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -707,6 +715,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_shakti_c_cpu_init),
#endif
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0edb2826a2..ebbf15fb1c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -38,6 +38,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 1/3] riscv: Add initial support for Shakti C class
@ 2021-03-14 8:39 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: qemu-devel, Vijai Kumar K
C-Class is a member of the SHAKTI family of processors from Indian
Institute of Technology - Madras(IIT-M).
It is an extremely configurable and commercial-grade 5-stage in-order
core supporting the standard RV64GCSUN ISA extensions.
Add support for emulating Shakti SoC based on C-class running on arty-100T
platform.
https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
---
MAINTAINERS | 7 +
default-configs/devices/riscv64-softmmu.mak | 1 +
hw/riscv/Kconfig | 10 ++
hw/riscv/meson.build | 1 +
hw/riscv/shakti_c.c | 178 ++++++++++++++++++++
include/hw/riscv/shakti_c.h | 74 ++++++++
target/riscv/cpu.c | 9 +
target/riscv/cpu.h | 1 +
8 files changed, 281 insertions(+)
create mode 100644 hw/riscv/shakti_c.c
create mode 100644 include/hw/riscv/shakti_c.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8e9f0d591e..9f71c4cc3f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1380,6 +1380,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+Shakti C class SoC
+M: Vijai Kumar K <vijai@behindbytes.com>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: hw/riscv/shakti_c.c
+F: include/hw/riscv/shakti_c.h
+
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
M: Bin Meng <bin.meng@windriver.com>
diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
index d5eec75f05..bc69301fa4 100644
--- a/default-configs/devices/riscv64-softmmu.mak
+++ b/default-configs/devices/riscv64-softmmu.mak
@@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
CONFIG_SIFIVE_U=y
CONFIG_RISCV_VIRT=y
CONFIG_MICROCHIP_PFSOC=y
+CONFIG_SHAKTI_C=y
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index d139074b02..92a62b5ce9 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -19,6 +19,16 @@ config OPENTITAN
select IBEX
select UNIMP
+config SHAKTI
+ bool
+
+config SHAKTI_C
+ bool
+ select UNIMP
+ select SHAKTI
+ select SIFIVE_CLINT
+ select SIFIVE_PLIC
+
config RISCV_VIRT
bool
imply PCI_DEVICES
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index 275c0f7eb7..a97454661c 100644
--- a/hw/riscv/meson.build
+++ b/hw/riscv/meson.build
@@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
+riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
new file mode 100644
index 0000000000..e96436a3bf
--- /dev/null
+++ b/hw/riscv/shakti_c.c
@@ -0,0 +1,178 @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/boards.h"
+#include "hw/riscv/shakti_c.h"
+#include "qapi/error.h"
+#include "hw/intc/sifive_plic.h"
+#include "hw/intc/sifive_clint.h"
+#include "sysemu/sysemu.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "hw/riscv/boot.h"
+
+#define DEBUG_SHAKTI_C 0
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_SHAKTI_C) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_RISCV_SHAKTI_SOC, \
+ __func__, ##args); \
+ } \
+ } while (0)
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} shakti_c_memmap[] = {
+ [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
+ [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
+ [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
+ [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
+ [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
+ [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
+ [SHAKTI_C_DEBUG] = { 0x00000000, 0x00010 },
+ [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
+};
+
+static void shakti_c_machine_state_init(MachineState *mstate)
+{
+ ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ int i;
+
+ /* Initialize SoC */
+ object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
+ TYPE_RISCV_SHAKTI_SOC);
+ qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
+
+ /* register RAM */
+ memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
+ mstate->ram_size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ shakti_c_memmap[SHAKTI_C_RAM].base,
+ main_mem);
+
+ /* ROM reset vector */
+ uint32_t reset_vec[3];
+
+ reset_vec[0] = 0x080002b7; /* lui t0,0x08000 */
+ reset_vec[1] = 0x00429293; /* slli t0,t0,4 */
+ reset_vec[2] = 0x00028067; /* jr t0 */
+
+ /* copy in the reset vector in little_endian byte order */
+ for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
+ reset_vec[i] = cpu_to_le32(reset_vec[i]);
+ }
+ rom_add_blob_fixed_as("rom.reset", reset_vec, sizeof(reset_vec),
+ shakti_c_memmap[SHAKTI_C_ROM].base,
+ &address_space_memory);
+ riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
+ NULL);
+}
+
+static void shakti_c_machine_instance_init(Object *obj)
+{
+}
+
+static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(klass);
+ mc->desc = "RISC-V Board compatible with Shakti SDK";
+ mc->init = shakti_c_machine_state_init;
+ mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
+}
+
+static const TypeInfo shakti_c_machine_type_info = {
+ .name = TYPE_RISCV_SHAKTI_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = shakti_c_machine_class_init,
+ .instance_init = shakti_c_machine_instance_init,
+ .instance_size = sizeof(ShaktiCMachineState),
+};
+
+static void shakti_c_machine_type_info_register(void)
+{
+ type_register_static(&shakti_c_machine_type_info);
+}
+type_init(shakti_c_machine_type_info_register)
+
+static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
+{
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
+ MemoryRegion *system_memory = get_system_memory();
+ sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
+ sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
+ (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
+ SHAKTI_C_PLIC_NUM_SOURCES,
+ SHAKTI_C_PLIC_NUM_PRIORITIES,
+ SHAKTI_C_PLIC_PRIORITY_BASE,
+ SHAKTI_C_PLIC_PENDING_BASE,
+ SHAKTI_C_PLIC_ENABLE_BASE,
+ SHAKTI_C_PLIC_ENABLE_STRIDE,
+ SHAKTI_C_PLIC_CONTEXT_BASE,
+ SHAKTI_C_PLIC_CONTEXT_STRIDE,
+ shakti_c_memmap[SHAKTI_C_PLIC].size);
+ sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
+ shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
+ SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ /* ROM */
+ memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
+ shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
+}
+
+static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = shakti_c_soc_state_realize;
+}
+
+static void shakti_c_soc_instance_init(Object *obj)
+{
+ ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
+
+ object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+
+ /*
+ * CPU type is fixed and we are not supporting passing from commandline yet.
+ * So let it be in instance_init. When supported should use ms->cpu_type
+ * instead of TYPE_RISCV_CPU_SHAKTI_C
+ */
+ object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
+ TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
+ object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
+ &error_abort);
+}
+
+static const TypeInfo shakti_c_type_info = {
+ .name = TYPE_RISCV_SHAKTI_SOC,
+ .parent = TYPE_DEVICE,
+ .class_init = shakti_c_soc_class_init,
+ .instance_init = shakti_c_soc_instance_init,
+ .instance_size = sizeof(ShaktiCSoCState),
+};
+
+static void shakti_c_type_info_register(void)
+{
+ type_register_static(&shakti_c_type_info);
+}
+type_init(shakti_c_type_info_register)
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
new file mode 100644
index 0000000000..6c66a160f5
--- /dev/null
+++ b/include/hw/riscv/shakti_c.h
@@ -0,0 +1,74 @@
+/*
+ * Shakti C-class SoC emulation
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SHAKTI_H
+#define HW_SHAKTI_H
+
+#include "hw/riscv/riscv_hart.h"
+#include "hw/boards.h"
+
+#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
+#define RISCV_SHAKTI_SOC(obj) \
+ OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
+
+typedef struct ShaktiCSoCState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ RISCVHartArrayState cpus;
+ DeviceState *plic;
+ MemoryRegion rom;
+
+} ShaktiCSoCState;
+
+#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
+#define RISCV_SHAKTI_MACHINE(obj) \
+ OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
+typedef struct ShaktiCMachineState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ ShaktiCSoCState soc;
+} ShaktiCMachineState;
+
+enum {
+ SHAKTI_C_ROM,
+ SHAKTI_C_RAM,
+ SHAKTI_C_UART,
+ SHAKTI_C_GPIO,
+ SHAKTI_C_PLIC,
+ SHAKTI_C_CLINT,
+ SHAKTI_C_DEBUG,
+ SHAKTI_C_I2C,
+};
+
+#define SHAKTI_C_PLIC_HART_CONFIG "MS"
+/* Including Interrupt ID 0 (no interrupt)*/
+#define SHAKTI_C_PLIC_NUM_SOURCES 28
+/* Excluding Priority 0 */
+#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
+#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
+#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
+#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
+#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
+#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
+#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
+
+#endif
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2a990f6253..618d203aa0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -159,6 +159,14 @@ static void rv64_base_cpu_init(Object *obj)
set_misa(env, RV64);
}
+static void rv64_shakti_c_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_priv_version(env, PRIV_VERSION_1_10_0);
+ set_resetvec(env, DEFAULT_RSTVEC);
+}
+
static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -707,6 +715,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_shakti_c_cpu_init),
#endif
};
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0edb2826a2..ebbf15fb1c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -38,6 +38,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
+#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] hw/char: Add Shakti UART emulation
2021-03-14 8:39 ` Vijai Kumar K
@ 2021-03-14 8:39 ` Vijai Kumar K
-1 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: Vijai Kumar K, qemu-devel
This is the initial implementation of Shakti UART.
TX tested and works fine. RX is untested.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
---
MAINTAINERS | 2 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 204 ++++++++++++++++++++++++++++++++++
hw/char/trace-events | 4 +
include/hw/char/shakti_uart.h | 74 ++++++++++++
5 files changed, 285 insertions(+)
create mode 100644 hw/char/shakti_uart.c
create mode 100644 include/hw/char/shakti_uart.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9f71c4cc3f..be084865db 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1385,7 +1385,9 @@ M: Vijai Kumar K <vijai@behindbytes.com>
L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/shakti_c.c
+F: hw/char/shakti_uart.c
F: include/hw/riscv/shakti_c.h
+F: include/hw/char/shakti_uart.h
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
diff --git a/hw/char/meson.build b/hw/char/meson.build
index 7ba38dbd96..61c43d4b51 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -19,6 +19,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
+softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
new file mode 100644
index 0000000000..e1c72e8747
--- /dev/null
+++ b/hw/char/shakti_uart.c
@@ -0,0 +1,204 @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/shakti_uart.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "qemu/log.h"
+
+#define DEBUG_SHAKTI_UART 0
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_SHAKTI_UART) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_SHAKTI_UART, \
+ __func__, ##args); \
+ } \
+ } while (0)
+
+static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
+{
+ ShaktiUartState *s = opaque;
+ uint64_t retvalue = 0;
+
+ switch (addr) {
+ case SHAKTI_UART_BAUD:
+ return s->uart_baud;
+ break;
+ case SHAKTI_UART_RX:
+ retvalue = s->uart_rx;
+ qemu_chr_fe_accept_input(&s->chr);
+ s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+ return retvalue;
+ break;
+ case SHAKTI_UART_STATUS:
+ DPRINTF("uart_status: value = 0x%x)\n", s->uart_status);
+ return s->uart_status;
+ break;
+ case SHAKTI_UART_DELAY:
+ return s->uart_delay;
+ break;
+ case SHAKTI_UART_CONTROL:
+ return s->uart_control;
+ break;
+ case SHAKTI_UART_INT_EN:
+ return s->uart_interrupt;
+ break;
+ case SHAKTI_UART_IQ_CYCLES:
+ return s->uart_iq_cycles;
+ break;
+ case SHAKTI_UART_RX_THRES:
+ return s->uart_rx_threshold;
+ break;
+ default:
+ /* Also handles TX REG which is write only */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+
+ return 0;
+}
+
+static void shakti_uart_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ ShaktiUartState *s = opaque;
+ uint32_t value = data;
+ uint8_t ch;
+
+ switch (addr) {
+ case SHAKTI_UART_BAUD:
+ s->uart_baud = value;
+ break;
+ case SHAKTI_UART_TX:
+ ch = value;
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
+ s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
+ break;
+ case SHAKTI_UART_STATUS:
+ s->uart_status = value;
+ break;
+ case SHAKTI_UART_DELAY:
+ s->uart_delay = value;
+ break;
+ case SHAKTI_UART_CONTROL:
+ s->uart_control = value;
+ break;
+ case SHAKTI_UART_INT_EN:
+ s->uart_interrupt = value;
+ break;
+ case SHAKTI_UART_IQ_CYCLES:
+ s->uart_iq_cycles = value;
+ break;
+ case SHAKTI_UART_RX_THRES:
+ s->uart_rx_threshold = value;
+ break;
+ default:
+ /* Also handles TX REG which is write only */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps shakti_uart_ops = {
+ .read = shakti_uart_read,
+ .write = shakti_uart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {.min_access_size = 1, .max_access_size = 4},
+ .valid = {.min_access_size = 1, .max_access_size = 4},
+};
+
+static void shakti_uart_reset(DeviceState *dev)
+{
+ ShaktiUartState *s = SHAKTI_UART(dev);
+
+ s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
+ s->uart_tx = 0x0;
+ s->uart_rx = 0x0;
+ s->uart_status = 0x0000;
+ s->uart_delay = 0x0000;
+ s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
+ s->uart_interrupt = 0x0000;
+ s->uart_iq_cycles = 0x00;
+ s->uart_rx_threshold = 0x00;
+}
+
+static int shakti_uart_can_receive(void *opaque)
+{
+ return 1;
+}
+
+static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+ ShaktiUartState *s = opaque;
+
+ s->uart_rx = *buf;
+ s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+}
+
+static void shakti_uart_realize(DeviceState *dev, Error **errp)
+{
+ ShaktiUartState *sus = SHAKTI_UART(dev);
+ qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
+ shakti_uart_receive, NULL, NULL, sus, NULL, true);
+}
+
+static void shakti_uart_instance_init(Object *obj)
+{
+ ShaktiUartState *sus = SHAKTI_UART(obj);
+ memory_region_init_io(&sus->mmio,
+ obj,
+ &shakti_uart_ops,
+ sus,
+ TYPE_SHAKTI_UART,
+ 0x1000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
+}
+
+static Property shakti_uart_properties[] = {
+ DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void shakti_uart_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->reset = shakti_uart_reset;
+ dc->realize = shakti_uart_realize;
+ device_class_set_props(dc, shakti_uart_properties);
+}
+
+static const TypeInfo shakti_uart_info = {
+ .name = TYPE_SHAKTI_UART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ShaktiUartState),
+ .class_init = shakti_uart_class_init,
+ .instance_init = shakti_uart_instance_init,
+};
+
+static void shakti_uart_register_types(void)
+{
+ type_register_static(&shakti_uart_info);
+}
+type_init(shakti_uart_register_types)
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 81026f6612..54aeeb899c 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -80,6 +80,10 @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+# shakti_uart.c
+shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
+shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+
# exynos4210_uart.c
exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
new file mode 100644
index 0000000000..526c408233
--- /dev/null
+++ b/include/hw/char/shakti_uart.h
@@ -0,0 +1,74 @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_SHAKTI_UART_H
+#define HW_SHAKTI_UART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+
+#define SHAKTI_UART_BAUD 0x00
+#define SHAKTI_UART_TX 0x04
+#define SHAKTI_UART_RX 0x08
+#define SHAKTI_UART_STATUS 0x0C
+#define SHAKTI_UART_DELAY 0x10
+#define SHAKTI_UART_CONTROL 0x14
+#define SHAKTI_UART_INT_EN 0x18
+#define SHAKTI_UART_IQ_CYCLES 0x1C
+#define SHAKTI_UART_RX_THRES 0x20
+
+#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0)
+#define SHAKTI_UART_STATUS_TX_FULL (1 << 1)
+#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
+#define SHAKTI_UART_STATUS_RX_FULL (1 << 3)
+/* 9600 8N1 is the default setting */
+/* Reg value = (50000000 Hz)/(16 * 9600)*/
+#define SHAKTI_UART_BAUD_DEFAULT 0x0145
+#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
+
+#define TYPE_SHAKTI_UART "shakti-uart"
+#define SHAKTI_UART(obj) \
+ OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t uart_baud;
+ uint32_t uart_tx;
+ uint32_t uart_rx;
+ uint32_t uart_status;
+ uint32_t uart_delay;
+ uint32_t uart_control;
+ uint32_t uart_interrupt;
+ uint32_t uart_iq_cycles;
+ uint32_t uart_rx_threshold;
+
+ CharBackend chr;
+} ShaktiUartState;
+
+#endif /* HW_SHAKTI_UART_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] hw/char: Add Shakti UART emulation
@ 2021-03-14 8:39 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: qemu-devel, Vijai Kumar K
This is the initial implementation of Shakti UART.
TX tested and works fine. RX is untested.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
---
MAINTAINERS | 2 +
hw/char/meson.build | 1 +
hw/char/shakti_uart.c | 204 ++++++++++++++++++++++++++++++++++
hw/char/trace-events | 4 +
include/hw/char/shakti_uart.h | 74 ++++++++++++
5 files changed, 285 insertions(+)
create mode 100644 hw/char/shakti_uart.c
create mode 100644 include/hw/char/shakti_uart.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 9f71c4cc3f..be084865db 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1385,7 +1385,9 @@ M: Vijai Kumar K <vijai@behindbytes.com>
L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/shakti_c.c
+F: hw/char/shakti_uart.c
F: include/hw/riscv/shakti_c.h
+F: include/hw/char/shakti_uart.h
SiFive Machines
M: Alistair Francis <Alistair.Francis@wdc.com>
diff --git a/hw/char/meson.build b/hw/char/meson.build
index 7ba38dbd96..61c43d4b51 100644
--- a/hw/char/meson.build
+++ b/hw/char/meson.build
@@ -19,6 +19,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
+softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
new file mode 100644
index 0000000000..e1c72e8747
--- /dev/null
+++ b/hw/char/shakti_uart.c
@@ -0,0 +1,204 @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/char/shakti_uart.h"
+#include "hw/qdev-properties.h"
+#include "hw/qdev-properties-system.h"
+#include "qemu/log.h"
+
+#define DEBUG_SHAKTI_UART 0
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_SHAKTI_UART) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_SHAKTI_UART, \
+ __func__, ##args); \
+ } \
+ } while (0)
+
+static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
+{
+ ShaktiUartState *s = opaque;
+ uint64_t retvalue = 0;
+
+ switch (addr) {
+ case SHAKTI_UART_BAUD:
+ return s->uart_baud;
+ break;
+ case SHAKTI_UART_RX:
+ retvalue = s->uart_rx;
+ qemu_chr_fe_accept_input(&s->chr);
+ s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+ return retvalue;
+ break;
+ case SHAKTI_UART_STATUS:
+ DPRINTF("uart_status: value = 0x%x)\n", s->uart_status);
+ return s->uart_status;
+ break;
+ case SHAKTI_UART_DELAY:
+ return s->uart_delay;
+ break;
+ case SHAKTI_UART_CONTROL:
+ return s->uart_control;
+ break;
+ case SHAKTI_UART_INT_EN:
+ return s->uart_interrupt;
+ break;
+ case SHAKTI_UART_IQ_CYCLES:
+ return s->uart_iq_cycles;
+ break;
+ case SHAKTI_UART_RX_THRES:
+ return s->uart_rx_threshold;
+ break;
+ default:
+ /* Also handles TX REG which is write only */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+
+ return 0;
+}
+
+static void shakti_uart_write(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size)
+{
+ ShaktiUartState *s = opaque;
+ uint32_t value = data;
+ uint8_t ch;
+
+ switch (addr) {
+ case SHAKTI_UART_BAUD:
+ s->uart_baud = value;
+ break;
+ case SHAKTI_UART_TX:
+ ch = value;
+ qemu_chr_fe_write_all(&s->chr, &ch, 1);
+ s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
+ break;
+ case SHAKTI_UART_STATUS:
+ s->uart_status = value;
+ break;
+ case SHAKTI_UART_DELAY:
+ s->uart_delay = value;
+ break;
+ case SHAKTI_UART_CONTROL:
+ s->uart_control = value;
+ break;
+ case SHAKTI_UART_INT_EN:
+ s->uart_interrupt = value;
+ break;
+ case SHAKTI_UART_IQ_CYCLES:
+ s->uart_iq_cycles = value;
+ break;
+ case SHAKTI_UART_RX_THRES:
+ s->uart_rx_threshold = value;
+ break;
+ default:
+ /* Also handles TX REG which is write only */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
+ }
+}
+
+static const MemoryRegionOps shakti_uart_ops = {
+ .read = shakti_uart_read,
+ .write = shakti_uart_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {.min_access_size = 1, .max_access_size = 4},
+ .valid = {.min_access_size = 1, .max_access_size = 4},
+};
+
+static void shakti_uart_reset(DeviceState *dev)
+{
+ ShaktiUartState *s = SHAKTI_UART(dev);
+
+ s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
+ s->uart_tx = 0x0;
+ s->uart_rx = 0x0;
+ s->uart_status = 0x0000;
+ s->uart_delay = 0x0000;
+ s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
+ s->uart_interrupt = 0x0000;
+ s->uart_iq_cycles = 0x00;
+ s->uart_rx_threshold = 0x00;
+}
+
+static int shakti_uart_can_receive(void *opaque)
+{
+ return 1;
+}
+
+static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
+{
+ ShaktiUartState *s = opaque;
+
+ s->uart_rx = *buf;
+ s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
+}
+
+static void shakti_uart_realize(DeviceState *dev, Error **errp)
+{
+ ShaktiUartState *sus = SHAKTI_UART(dev);
+ qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
+ shakti_uart_receive, NULL, NULL, sus, NULL, true);
+}
+
+static void shakti_uart_instance_init(Object *obj)
+{
+ ShaktiUartState *sus = SHAKTI_UART(obj);
+ memory_region_init_io(&sus->mmio,
+ obj,
+ &shakti_uart_ops,
+ sus,
+ TYPE_SHAKTI_UART,
+ 0x1000);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
+}
+
+static Property shakti_uart_properties[] = {
+ DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void shakti_uart_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->reset = shakti_uart_reset;
+ dc->realize = shakti_uart_realize;
+ device_class_set_props(dc, shakti_uart_properties);
+}
+
+static const TypeInfo shakti_uart_info = {
+ .name = TYPE_SHAKTI_UART,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(ShaktiUartState),
+ .class_init = shakti_uart_class_init,
+ .instance_init = shakti_uart_instance_init,
+};
+
+static void shakti_uart_register_types(void)
+{
+ type_register_static(&shakti_uart_info);
+}
+type_init(shakti_uart_register_types)
diff --git a/hw/char/trace-events b/hw/char/trace-events
index 81026f6612..54aeeb899c 100644
--- a/hw/char/trace-events
+++ b/hw/char/trace-events
@@ -80,6 +80,10 @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+# shakti_uart.c
+shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
+shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
+
# exynos4210_uart.c
exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
new file mode 100644
index 0000000000..526c408233
--- /dev/null
+++ b/include/hw/char/shakti_uart.h
@@ -0,0 +1,74 @@
+/*
+ * SHAKTI UART
+ *
+ * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_SHAKTI_UART_H
+#define HW_SHAKTI_UART_H
+
+#include "hw/sysbus.h"
+#include "chardev/char-fe.h"
+
+#define SHAKTI_UART_BAUD 0x00
+#define SHAKTI_UART_TX 0x04
+#define SHAKTI_UART_RX 0x08
+#define SHAKTI_UART_STATUS 0x0C
+#define SHAKTI_UART_DELAY 0x10
+#define SHAKTI_UART_CONTROL 0x14
+#define SHAKTI_UART_INT_EN 0x18
+#define SHAKTI_UART_IQ_CYCLES 0x1C
+#define SHAKTI_UART_RX_THRES 0x20
+
+#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0)
+#define SHAKTI_UART_STATUS_TX_FULL (1 << 1)
+#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
+#define SHAKTI_UART_STATUS_RX_FULL (1 << 3)
+/* 9600 8N1 is the default setting */
+/* Reg value = (50000000 Hz)/(16 * 9600)*/
+#define SHAKTI_UART_BAUD_DEFAULT 0x0145
+#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
+
+#define TYPE_SHAKTI_UART "shakti-uart"
+#define SHAKTI_UART(obj) \
+ OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
+
+typedef struct {
+ /* <private> */
+ SysBusDevice parent_obj;
+
+ /* <public> */
+ MemoryRegion mmio;
+
+ uint32_t uart_baud;
+ uint32_t uart_tx;
+ uint32_t uart_rx;
+ uint32_t uart_status;
+ uint32_t uart_delay;
+ uint32_t uart_control;
+ uint32_t uart_interrupt;
+ uint32_t uart_iq_cycles;
+ uint32_t uart_rx_threshold;
+
+ CharBackend chr;
+} ShaktiUartState;
+
+#endif /* HW_SHAKTI_UART_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
2021-03-14 8:39 ` Vijai Kumar K
@ 2021-03-14 8:39 ` Vijai Kumar K
-1 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: Vijai Kumar K, qemu-devel
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
---
hw/riscv/shakti_c.c | 7 +++++++
include/hw/riscv/shakti_c.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index e96436a3bf..07cc42a380 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -133,6 +133,12 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
+ shakti_c_memmap[SHAKTI_C_UART].base);
/* ROM */
memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
@@ -151,6 +157,7 @@ static void shakti_c_soc_instance_init(Object *obj)
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+ object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
/*
* CPU type is fixed and we are not supporting passing from commandline yet.
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index 6c66a160f5..3abb080d3c 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/boards.h"
+#include "hw/char/shakti_uart.h"
#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
#define RISCV_SHAKTI_SOC(obj) \
@@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
+ ShaktiUartState uart;
MemoryRegion rom;
} ShaktiCSoCState;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
@ 2021-03-14 8:39 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-14 8:39 UTC (permalink / raw)
To: qemu-riscv; +Cc: qemu-devel, Vijai Kumar K
Connect one shakti uart to the shakti_c machine.
Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
---
hw/riscv/shakti_c.c | 7 +++++++
include/hw/riscv/shakti_c.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index e96436a3bf..07cc42a380 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -133,6 +133,12 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
SIFIVE_CLINT_TIMEBASE_FREQ, false);
+ qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
+ if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
+ shakti_c_memmap[SHAKTI_C_UART].base);
/* ROM */
memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
@@ -151,6 +157,7 @@ static void shakti_c_soc_instance_init(Object *obj)
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
+ object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
/*
* CPU type is fixed and we are not supporting passing from commandline yet.
diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
index 6c66a160f5..3abb080d3c 100644
--- a/include/hw/riscv/shakti_c.h
+++ b/include/hw/riscv/shakti_c.h
@@ -21,6 +21,7 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/boards.h"
+#include "hw/char/shakti_uart.h"
#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
#define RISCV_SHAKTI_SOC(obj) \
@@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *plic;
+ ShaktiUartState uart;
MemoryRegion rom;
} ShaktiCSoCState;
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] riscv: Add initial support for Shakti C class
2021-03-14 8:39 ` Vijai Kumar K
(?)
@ 2021-03-19 13:39 ` Alistair Francis
2021-03-20 9:46 ` Vijai Kumar K
-1 siblings, 1 reply; 14+ messages in thread
From: Alistair Francis @ 2021-03-19 13:39 UTC (permalink / raw)
To: Vijai Kumar K; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Sun, Mar 14, 2021 at 5:10 AM Vijai Kumar K <vijai@behindbytes.com> wrote:
>
> C-Class is a member of the SHAKTI family of processors from Indian
> Institute of Technology - Madras(IIT-M).
> It is an extremely configurable and commercial-grade 5-stage in-order
> core supporting the standard RV64GCSUN ISA extensions.
>
> Add support for emulating Shakti SoC based on C-class running on arty-100T
> platform.
>
> https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
>
> Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
> ---
> MAINTAINERS | 7 +
> default-configs/devices/riscv64-softmmu.mak | 1 +
> hw/riscv/Kconfig | 10 ++
> hw/riscv/meson.build | 1 +
> hw/riscv/shakti_c.c | 178 ++++++++++++++++++++
> include/hw/riscv/shakti_c.h | 74 ++++++++
> target/riscv/cpu.c | 9 +
> target/riscv/cpu.h | 1 +
> 8 files changed, 281 insertions(+)
> create mode 100644 hw/riscv/shakti_c.c
> create mode 100644 include/hw/riscv/shakti_c.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8e9f0d591e..9f71c4cc3f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1380,6 +1380,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
> F: include/hw/misc/mchp_pfsoc_ioscb.h
> F: include/hw/misc/mchp_pfsoc_sysreg.h
>
> +Shakti C class SoC
> +M: Vijai Kumar K <vijai@behindbytes.com>
> +L: qemu-riscv@nongnu.org
> +S: Supported
> +F: hw/riscv/shakti_c.c
> +F: include/hw/riscv/shakti_c.h
> +
> SiFive Machines
> M: Alistair Francis <Alistair.Francis@wdc.com>
> M: Bin Meng <bin.meng@windriver.com>
> diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
> index d5eec75f05..bc69301fa4 100644
> --- a/default-configs/devices/riscv64-softmmu.mak
> +++ b/default-configs/devices/riscv64-softmmu.mak
> @@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
> CONFIG_SIFIVE_U=y
> CONFIG_RISCV_VIRT=y
> CONFIG_MICROCHIP_PFSOC=y
> +CONFIG_SHAKTI_C=y
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index d139074b02..92a62b5ce9 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -19,6 +19,16 @@ config OPENTITAN
> select IBEX
> select UNIMP
>
> +config SHAKTI
> + bool
> +
> +config SHAKTI_C
> + bool
> + select UNIMP
> + select SHAKTI
> + select SIFIVE_CLINT
> + select SIFIVE_PLIC
> +
> config RISCV_VIRT
> bool
> imply PCI_DEVICES
> diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> index 275c0f7eb7..a97454661c 100644
> --- a/hw/riscv/meson.build
> +++ b/hw/riscv/meson.build
> @@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c'))
> riscv_ss.add(files('riscv_hart.c'))
> riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
> riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> +riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
> riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> new file mode 100644
> index 0000000000..e96436a3bf
> --- /dev/null
> +++ b/hw/riscv/shakti_c.c
> @@ -0,0 +1,178 @@
> +/*
> + * Shakti C-class SoC emulation
> + *
> + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/boards.h"
> +#include "hw/riscv/shakti_c.h"
> +#include "qapi/error.h"
> +#include "hw/intc/sifive_plic.h"
> +#include "hw/intc/sifive_clint.h"
> +#include "sysemu/sysemu.h"
> +#include "hw/qdev-properties.h"
> +#include "exec/address-spaces.h"
> +#include "hw/riscv/boot.h"
> +
> +#define DEBUG_SHAKTI_C 0
> +#define DPRINTF(fmt, args...) \
> + do { \
> + if (DEBUG_SHAKTI_C) { \
> + fprintf(stderr, "[%s]%s: " fmt , TYPE_RISCV_SHAKTI_SOC, \
> + __func__, ##args); \
> + } \
> + } while (0)
This doesn't seem to be used, can you remove it?
> +
> +static const struct MemmapEntry {
> + hwaddr base;
> + hwaddr size;
> +} shakti_c_memmap[] = {
> + [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
> + [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
> + [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
> + [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
> + [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
> + [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
> + [SHAKTI_C_DEBUG] = { 0x00000000, 0x00010 },
> + [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
> +};
> +
> +static void shakti_c_machine_state_init(MachineState *mstate)
> +{
> + ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
> + MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> + int i;
> +
> + /* Initialize SoC */
> + object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
> + TYPE_RISCV_SHAKTI_SOC);
> + qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
> +
> + /* register RAM */
> + memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
> + mstate->ram_size, &error_fatal);
> + memory_region_add_subregion(system_memory,
> + shakti_c_memmap[SHAKTI_C_RAM].base,
> + main_mem);
> +
> + /* ROM reset vector */
> + uint32_t reset_vec[3];
> +
> + reset_vec[0] = 0x080002b7; /* lui t0,0x08000 */
> + reset_vec[1] = 0x00429293; /* slli t0,t0,4 */
> + reset_vec[2] = 0x00028067; /* jr t0 */
Is there a reason you can't use riscv_setup_rom_reset_vec()?
> +
> + /* copy in the reset vector in little_endian byte order */
> + for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
> + reset_vec[i] = cpu_to_le32(reset_vec[i]);
> + }
> + rom_add_blob_fixed_as("rom.reset", reset_vec, sizeof(reset_vec),
> + shakti_c_memmap[SHAKTI_C_ROM].base,
> + &address_space_memory);
> + riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
> + NULL);
> +}
> +
> +static void shakti_c_machine_instance_init(Object *obj)
> +{
> +}
> +
> +static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
> +{
> + MachineClass *mc = MACHINE_CLASS(klass);
> + mc->desc = "RISC-V Board compatible with Shakti SDK";
> + mc->init = shakti_c_machine_state_init;
> + mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
> +}
> +
> +static const TypeInfo shakti_c_machine_type_info = {
> + .name = TYPE_RISCV_SHAKTI_MACHINE,
> + .parent = TYPE_MACHINE,
> + .class_init = shakti_c_machine_class_init,
> + .instance_init = shakti_c_machine_instance_init,
> + .instance_size = sizeof(ShaktiCMachineState),
> +};
> +
> +static void shakti_c_machine_type_info_register(void)
> +{
> + type_register_static(&shakti_c_machine_type_info);
> +}
> +type_init(shakti_c_machine_type_info_register)
> +
> +static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
> +{
> + ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
> + MemoryRegion *system_memory = get_system_memory();
Can you add a newline here.
> + sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
and here
> + sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
> + (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
> + SHAKTI_C_PLIC_NUM_SOURCES,
> + SHAKTI_C_PLIC_NUM_PRIORITIES,
> + SHAKTI_C_PLIC_PRIORITY_BASE,
> + SHAKTI_C_PLIC_PENDING_BASE,
> + SHAKTI_C_PLIC_ENABLE_BASE,
> + SHAKTI_C_PLIC_ENABLE_STRIDE,
> + SHAKTI_C_PLIC_CONTEXT_BASE,
> + SHAKTI_C_PLIC_CONTEXT_STRIDE,
> + shakti_c_memmap[SHAKTI_C_PLIC].size);
and here
> + sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
> + shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
> + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> + SIFIVE_CLINT_TIMEBASE_FREQ, false);
and here
> + /* ROM */
> + memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
> + shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
> + memory_region_add_subregion(system_memory,
> + shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
> +}
> +
> +static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + dc->realize = shakti_c_soc_state_realize;
> +}
> +
> +static void shakti_c_soc_instance_init(Object *obj)
> +{
> + ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
> +
> + object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
> +
> + /*
> + * CPU type is fixed and we are not supporting passing from commandline yet.
> + * So let it be in instance_init. When supported should use ms->cpu_type
> + * instead of TYPE_RISCV_CPU_SHAKTI_C
> + */
You need to return an error then if the user tries to change the
number or type of CPU instead of ignoring it.
> + object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
> + TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
> + object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
> + &error_abort);
> +}
> +
> +static const TypeInfo shakti_c_type_info = {
> + .name = TYPE_RISCV_SHAKTI_SOC,
> + .parent = TYPE_DEVICE,
> + .class_init = shakti_c_soc_class_init,
> + .instance_init = shakti_c_soc_instance_init,
> + .instance_size = sizeof(ShaktiCSoCState),
> +};
> +
> +static void shakti_c_type_info_register(void)
> +{
> + type_register_static(&shakti_c_type_info);
> +}
> +type_init(shakti_c_type_info_register)
> diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
> new file mode 100644
> index 0000000000..6c66a160f5
> --- /dev/null
> +++ b/include/hw/riscv/shakti_c.h
> @@ -0,0 +1,74 @@
> +/*
> + * Shakti C-class SoC emulation
> + *
> + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef HW_SHAKTI_H
> +#define HW_SHAKTI_H
> +
> +#include "hw/riscv/riscv_hart.h"
> +#include "hw/boards.h"
> +
> +#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
> +#define RISCV_SHAKTI_SOC(obj) \
> + OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
> +
> +typedef struct ShaktiCSoCState {
> + /*< private >*/
> + DeviceState parent_obj;
> +
> + /*< public >*/
> + RISCVHartArrayState cpus;
> + DeviceState *plic;
> + MemoryRegion rom;
> +
> +} ShaktiCSoCState;
> +
> +#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
> +#define RISCV_SHAKTI_MACHINE(obj) \
> + OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
> +typedef struct ShaktiCMachineState {
> + /*< private >*/
> + MachineState parent_obj;
> +
> + /*< public >*/
> + ShaktiCSoCState soc;
> +} ShaktiCMachineState;
> +
> +enum {
> + SHAKTI_C_ROM,
> + SHAKTI_C_RAM,
> + SHAKTI_C_UART,
> + SHAKTI_C_GPIO,
> + SHAKTI_C_PLIC,
> + SHAKTI_C_CLINT,
> + SHAKTI_C_DEBUG,
> + SHAKTI_C_I2C,
> +};
> +
> +#define SHAKTI_C_PLIC_HART_CONFIG "MS"
> +/* Including Interrupt ID 0 (no interrupt)*/
> +#define SHAKTI_C_PLIC_NUM_SOURCES 28
> +/* Excluding Priority 0 */
> +#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
> +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
> +#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
> +#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
> +#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
> +#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
> +#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
> +
> +#endif
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2a990f6253..618d203aa0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -159,6 +159,14 @@ static void rv64_base_cpu_init(Object *obj)
> set_misa(env, RV64);
> }
>
> +static void rv64_shakti_c_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
Don't use RVXLEN, this is a 64-bit CPU right?
This is also exactly the same as the rv64_sifive_u_cpu_init() can we
just use an existing CPU instead of adding a new one?
> + set_priv_version(env, PRIV_VERSION_1_10_0);
> + set_resetvec(env, DEFAULT_RSTVEC);
> +}
> +
> static void rv64_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -707,6 +715,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_shakti_c_cpu_init),
> #endif
> };
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0edb2826a2..ebbf15fb1c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -38,6 +38,7 @@
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
Can you add the CPU in a separate patch?
Alistair
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> --
> 2.25.1
>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] hw/char: Add Shakti UART emulation
2021-03-14 8:39 ` Vijai Kumar K
(?)
@ 2021-03-19 13:44 ` Alistair Francis
2021-03-20 9:41 ` Vijai Kumar K
-1 siblings, 1 reply; 14+ messages in thread
From: Alistair Francis @ 2021-03-19 13:44 UTC (permalink / raw)
To: Vijai Kumar K; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Sun, Mar 14, 2021 at 5:14 AM Vijai Kumar K <vijai@behindbytes.com> wrote:
>
> This is the initial implementation of Shakti UART.
>
> TX tested and works fine. RX is untested.
>
> Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
> ---
> MAINTAINERS | 2 +
> hw/char/meson.build | 1 +
> hw/char/shakti_uart.c | 204 ++++++++++++++++++++++++++++++++++
> hw/char/trace-events | 4 +
> include/hw/char/shakti_uart.h | 74 ++++++++++++
> 5 files changed, 285 insertions(+)
> create mode 100644 hw/char/shakti_uart.c
> create mode 100644 include/hw/char/shakti_uart.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9f71c4cc3f..be084865db 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1385,7 +1385,9 @@ M: Vijai Kumar K <vijai@behindbytes.com>
> L: qemu-riscv@nongnu.org
> S: Supported
> F: hw/riscv/shakti_c.c
> +F: hw/char/shakti_uart.c
> F: include/hw/riscv/shakti_c.h
> +F: include/hw/char/shakti_uart.h
>
> SiFive Machines
> M: Alistair Francis <Alistair.Francis@wdc.com>
> diff --git a/hw/char/meson.build b/hw/char/meson.build
> index 7ba38dbd96..61c43d4b51 100644
> --- a/hw/char/meson.build
> +++ b/hw/char/meson.build
> @@ -19,6 +19,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
> softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
> softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
> softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
> +softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
> softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
> softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
> softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
> diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
> new file mode 100644
> index 0000000000..e1c72e8747
> --- /dev/null
> +++ b/hw/char/shakti_uart.c
> @@ -0,0 +1,204 @@
> +/*
> + * SHAKTI UART
> + *
> + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/char/shakti_uart.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/qdev-properties-system.h"
> +#include "qemu/log.h"
> +
> +#define DEBUG_SHAKTI_UART 0
> +#define DPRINTF(fmt, args...) \
> + do { \
> + if (DEBUG_SHAKTI_UART) { \
> + fprintf(stderr, "[%s]%s: " fmt , TYPE_SHAKTI_UART, \
> + __func__, ##args); \
> + } \
> + } while (0)
Can you use the trace infrastructure instead?
https://gitlab.com/qemu-project/qemu/-/blob/master/docs/devel/tracing.rst
> +
> +static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
> +{
> + ShaktiUartState *s = opaque;
> + uint64_t retvalue = 0;
> +
> + switch (addr) {
> + case SHAKTI_UART_BAUD:
> + return s->uart_baud;
> + break;
You don't need a return and a break.
Also if you return in each one you don't need the retvalue variable.
> + case SHAKTI_UART_RX:
> + retvalue = s->uart_rx;
> + qemu_chr_fe_accept_input(&s->chr);
> + s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
> + return retvalue;
> + break;
> + case SHAKTI_UART_STATUS:
> + DPRINTF("uart_status: value = 0x%x)\n", s->uart_status);
> + return s->uart_status;
> + break;
> + case SHAKTI_UART_DELAY:
> + return s->uart_delay;
> + break;
> + case SHAKTI_UART_CONTROL:
> + return s->uart_control;
> + break;
> + case SHAKTI_UART_INT_EN:
> + return s->uart_interrupt;
> + break;
> + case SHAKTI_UART_IQ_CYCLES:
> + return s->uart_iq_cycles;
> + break;
> + case SHAKTI_UART_RX_THRES:
> + return s->uart_rx_threshold;
> + break;
> + default:
> + /* Also handles TX REG which is write only */
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
Maybe add a seperate log for TX then?
Alistair
> + }
> +
> + return 0;
> +}
> +
> +static void shakti_uart_write(void *opaque, hwaddr addr,
> + uint64_t data, unsigned size)
> +{
> + ShaktiUartState *s = opaque;
> + uint32_t value = data;
> + uint8_t ch;
> +
> + switch (addr) {
> + case SHAKTI_UART_BAUD:
> + s->uart_baud = value;
> + break;
> + case SHAKTI_UART_TX:
> + ch = value;
> + qemu_chr_fe_write_all(&s->chr, &ch, 1);
> + s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
> + break;
> + case SHAKTI_UART_STATUS:
> + s->uart_status = value;
> + break;
> + case SHAKTI_UART_DELAY:
> + s->uart_delay = value;
> + break;
> + case SHAKTI_UART_CONTROL:
> + s->uart_control = value;
> + break;
> + case SHAKTI_UART_INT_EN:
> + s->uart_interrupt = value;
> + break;
> + case SHAKTI_UART_IQ_CYCLES:
> + s->uart_iq_cycles = value;
> + break;
> + case SHAKTI_UART_RX_THRES:
> + s->uart_rx_threshold = value;
> + break;
> + default:
> + /* Also handles TX REG which is write only */
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
> + }
> +}
> +
> +static const MemoryRegionOps shakti_uart_ops = {
> + .read = shakti_uart_read,
> + .write = shakti_uart_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .impl = {.min_access_size = 1, .max_access_size = 4},
> + .valid = {.min_access_size = 1, .max_access_size = 4},
> +};
> +
> +static void shakti_uart_reset(DeviceState *dev)
> +{
> + ShaktiUartState *s = SHAKTI_UART(dev);
> +
> + s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
> + s->uart_tx = 0x0;
> + s->uart_rx = 0x0;
> + s->uart_status = 0x0000;
> + s->uart_delay = 0x0000;
> + s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
> + s->uart_interrupt = 0x0000;
> + s->uart_iq_cycles = 0x00;
> + s->uart_rx_threshold = 0x00;
> +}
> +
> +static int shakti_uart_can_receive(void *opaque)
> +{
> + return 1;
> +}
> +
> +static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
> +{
> + ShaktiUartState *s = opaque;
> +
> + s->uart_rx = *buf;
> + s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
> +}
> +
> +static void shakti_uart_realize(DeviceState *dev, Error **errp)
> +{
> + ShaktiUartState *sus = SHAKTI_UART(dev);
> + qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
> + shakti_uart_receive, NULL, NULL, sus, NULL, true);
> +}
> +
> +static void shakti_uart_instance_init(Object *obj)
> +{
> + ShaktiUartState *sus = SHAKTI_UART(obj);
> + memory_region_init_io(&sus->mmio,
> + obj,
> + &shakti_uart_ops,
> + sus,
> + TYPE_SHAKTI_UART,
> + 0x1000);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
> +}
> +
> +static Property shakti_uart_properties[] = {
> + DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void shakti_uart_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + dc->reset = shakti_uart_reset;
> + dc->realize = shakti_uart_realize;
> + device_class_set_props(dc, shakti_uart_properties);
> +}
> +
> +static const TypeInfo shakti_uart_info = {
> + .name = TYPE_SHAKTI_UART,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(ShaktiUartState),
> + .class_init = shakti_uart_class_init,
> + .instance_init = shakti_uart_instance_init,
> +};
> +
> +static void shakti_uart_register_types(void)
> +{
> + type_register_static(&shakti_uart_info);
> +}
> +type_init(shakti_uart_register_types)
> diff --git a/hw/char/trace-events b/hw/char/trace-events
> index 81026f6612..54aeeb899c 100644
> --- a/hw/char/trace-events
> +++ b/hw/char/trace-events
> @@ -80,6 +80,10 @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
> nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
> nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
>
> +# shakti_uart.c
> +shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
> +shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
> +
> # exynos4210_uart.c
> exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
> exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
> diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
> new file mode 100644
> index 0000000000..526c408233
> --- /dev/null
> +++ b/include/hw/char/shakti_uart.h
> @@ -0,0 +1,74 @@
> +/*
> + * SHAKTI UART
> + *
> + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_SHAKTI_UART_H
> +#define HW_SHAKTI_UART_H
> +
> +#include "hw/sysbus.h"
> +#include "chardev/char-fe.h"
> +
> +#define SHAKTI_UART_BAUD 0x00
> +#define SHAKTI_UART_TX 0x04
> +#define SHAKTI_UART_RX 0x08
> +#define SHAKTI_UART_STATUS 0x0C
> +#define SHAKTI_UART_DELAY 0x10
> +#define SHAKTI_UART_CONTROL 0x14
> +#define SHAKTI_UART_INT_EN 0x18
> +#define SHAKTI_UART_IQ_CYCLES 0x1C
> +#define SHAKTI_UART_RX_THRES 0x20
> +
> +#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0)
> +#define SHAKTI_UART_STATUS_TX_FULL (1 << 1)
> +#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
> +#define SHAKTI_UART_STATUS_RX_FULL (1 << 3)
> +/* 9600 8N1 is the default setting */
> +/* Reg value = (50000000 Hz)/(16 * 9600)*/
> +#define SHAKTI_UART_BAUD_DEFAULT 0x0145
> +#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
> +
> +#define TYPE_SHAKTI_UART "shakti-uart"
> +#define SHAKTI_UART(obj) \
> + OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
> +
> +typedef struct {
> + /* <private> */
> + SysBusDevice parent_obj;
> +
> + /* <public> */
> + MemoryRegion mmio;
> +
> + uint32_t uart_baud;
> + uint32_t uart_tx;
> + uint32_t uart_rx;
> + uint32_t uart_status;
> + uint32_t uart_delay;
> + uint32_t uart_control;
> + uint32_t uart_interrupt;
> + uint32_t uart_iq_cycles;
> + uint32_t uart_rx_threshold;
> +
> + CharBackend chr;
> +} ShaktiUartState;
> +
> +#endif /* HW_SHAKTI_UART_H */
> --
> 2.25.1
>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
2021-03-14 8:39 ` Vijai Kumar K
(?)
@ 2021-03-19 13:47 ` Alistair Francis
2021-03-20 9:38 ` Vijai Kumar K
-1 siblings, 1 reply; 14+ messages in thread
From: Alistair Francis @ 2021-03-19 13:47 UTC (permalink / raw)
To: Vijai Kumar K; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
On Sun, Mar 14, 2021 at 5:11 AM Vijai Kumar K <vijai@behindbytes.com> wrote:
>
> Connect one shakti uart to the shakti_c machine.
>
> Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
> ---
> hw/riscv/shakti_c.c | 7 +++++++
> include/hw/riscv/shakti_c.h | 2 ++
> 2 files changed, 9 insertions(+)
>
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index e96436a3bf..07cc42a380 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -133,6 +133,12 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
> shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> SIFIVE_CLINT_TIMEBASE_FREQ, false);
> + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
> + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
> + return;
> + }
> + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
> + shakti_c_memmap[SHAKTI_C_UART].base);
Are there no interrupts?
Alistair
> /* ROM */
> memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
> shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
> @@ -151,6 +157,7 @@ static void shakti_c_soc_instance_init(Object *obj)
> ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
>
> object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
> + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
>
> /*
> * CPU type is fixed and we are not supporting passing from commandline yet.
> diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
> index 6c66a160f5..3abb080d3c 100644
> --- a/include/hw/riscv/shakti_c.h
> +++ b/include/hw/riscv/shakti_c.h
> @@ -21,6 +21,7 @@
>
> #include "hw/riscv/riscv_hart.h"
> #include "hw/boards.h"
> +#include "hw/char/shakti_uart.h"
>
> #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
> #define RISCV_SHAKTI_SOC(obj) \
> @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
> /*< public >*/
> RISCVHartArrayState cpus;
> DeviceState *plic;
> + ShaktiUartState uart;
> MemoryRegion rom;
>
> } ShaktiCSoCState;
> --
> 2.25.1
>
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform
2021-03-19 13:47 ` Alistair Francis
@ 2021-03-20 9:38 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-20 9:38 UTC (permalink / raw)
To: Alistair Francis; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
---- On Fri, 19 Mar 2021 19:17:58 +0530 Alistair Francis <alistair23@gmail.com> wrote ----
> On Sun, Mar 14, 2021 at 5:11 AM Vijai Kumar K <vijai@behindbytes.com> wrote:
> >
> > Connect one shakti uart to the shakti_c machine.
> >
> > Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
> > ---
> > hw/riscv/shakti_c.c | 7 +++++++
> > include/hw/riscv/shakti_c.h | 2 ++
> > 2 files changed, 9 insertions(+)
> >
> > diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> > index e96436a3bf..07cc42a380 100644
> > --- a/hw/riscv/shakti_c.c
> > +++ b/hw/riscv/shakti_c.c
> > @@ -133,6 +133,12 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
> > shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
> > SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> > SIFIVE_CLINT_TIMEBASE_FREQ, false);
> > + qdev_prop_set_chr(DEVICE(&(sss->uart)), "chardev", serial_hd(0));
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&sss->uart), errp)) {
> > + return;
> > + }
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&sss->uart), 0,
> > + shakti_c_memmap[SHAKTI_C_UART].base);
>
> Are there no interrupts?
>
> Alistair
Not in the initial implementation. Interrupt support was added to the UART IP meanwhile. I did not test it.
Will come as a separate patch later.
Thanks,
Vijai Kumar K
>
> > /* ROM */
> > memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
> > shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
> > @@ -151,6 +157,7 @@ static void shakti_c_soc_instance_init(Object *obj)
> > ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
> >
> > object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
> > + object_initialize_child(obj, "uart", &sss->uart, TYPE_SHAKTI_UART);
> >
> > /*
> > * CPU type is fixed and we are not supporting passing from commandline yet.
> > diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
> > index 6c66a160f5..3abb080d3c 100644
> > --- a/include/hw/riscv/shakti_c.h
> > +++ b/include/hw/riscv/shakti_c.h
> > @@ -21,6 +21,7 @@
> >
> > #include "hw/riscv/riscv_hart.h"
> > #include "hw/boards.h"
> > +#include "hw/char/shakti_uart.h"
> >
> > #define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
> > #define RISCV_SHAKTI_SOC(obj) \
> > @@ -33,6 +34,7 @@ typedef struct ShaktiCSoCState {
> > /*< public >*/
> > RISCVHartArrayState cpus;
> > DeviceState *plic;
> > + ShaktiUartState uart;
> > MemoryRegion rom;
> >
> > } ShaktiCSoCState;
> > --
> > 2.25.1
> >
> >
> >
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] hw/char: Add Shakti UART emulation
2021-03-19 13:44 ` Alistair Francis
@ 2021-03-20 9:41 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-20 9:41 UTC (permalink / raw)
To: Alistair Francis; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
---- On Fri, 19 Mar 2021 19:14:31 +0530 Alistair Francis <alistair23@gmail.com> wrote ----
> On Sun, Mar 14, 2021 at 5:14 AM Vijai Kumar K <vijai@behindbytes.com> wrote:
> >
> > This is the initial implementation of Shakti UART.
> >
> > TX tested and works fine. RX is untested.
> >
> > Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
> > ---
> > MAINTAINERS | 2 +
> > hw/char/meson.build | 1 +
> > hw/char/shakti_uart.c | 204 ++++++++++++++++++++++++++++++++++
> > hw/char/trace-events | 4 +
> > include/hw/char/shakti_uart.h | 74 ++++++++++++
> > 5 files changed, 285 insertions(+)
> > create mode 100644 hw/char/shakti_uart.c
> > create mode 100644 include/hw/char/shakti_uart.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 9f71c4cc3f..be084865db 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1385,7 +1385,9 @@ M: Vijai Kumar K <vijai@behindbytes.com>
> > L: qemu-riscv@nongnu.org
> > S: Supported
> > F: hw/riscv/shakti_c.c
> > +F: hw/char/shakti_uart.c
> > F: include/hw/riscv/shakti_c.h
> > +F: include/hw/char/shakti_uart.h
> >
> > SiFive Machines
> > M: Alistair Francis <Alistair.Francis@wdc.com>
> > diff --git a/hw/char/meson.build b/hw/char/meson.build
> > index 7ba38dbd96..61c43d4b51 100644
> > --- a/hw/char/meson.build
> > +++ b/hw/char/meson.build
> > @@ -19,6 +19,7 @@ softmmu_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c'))
> > softmmu_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c'))
> > softmmu_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c'))
> > softmmu_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c'))
> > +softmmu_ss.add(when: 'CONFIG_SHAKTI', if_true: files('shakti_uart.c'))
> > softmmu_ss.add(when: 'CONFIG_VIRTIO_SERIAL', if_true: files('virtio-console.c'))
> > softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen_console.c'))
> > softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_uartlite.c'))
> > diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c
> > new file mode 100644
> > index 0000000000..e1c72e8747
> > --- /dev/null
> > +++ b/hw/char/shakti_uart.c
> > @@ -0,0 +1,204 @@
> > +/*
> > + * SHAKTI UART
> > + *
> > + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a copy
> > + * of this software and associated documentation files (the "Software"), to deal
> > + * in the Software without restriction, including without limitation the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/char/shakti_uart.h"
> > +#include "hw/qdev-properties.h"
> > +#include "hw/qdev-properties-system.h"
> > +#include "qemu/log.h"
> > +
> > +#define DEBUG_SHAKTI_UART 0
> > +#define DPRINTF(fmt, args...) \
> > + do { \
> > + if (DEBUG_SHAKTI_UART) { \
> > + fprintf(stderr, "[%s]%s: " fmt , TYPE_SHAKTI_UART, \
> > + __func__, ##args); \
> > + } \
> > + } while (0)
>
> Can you use the trace infrastructure instead?
>
> https://gitlab.com/qemu-project/qemu/-/blob/master/docs/devel/tracing.rst
I felt the tracing infra was a bit difficult to work with in this scenario, hence the DPRINTF.
This is not needed anymore. I will drop the DPRINTF logs.
>
>
> > +
> > +static uint64_t shakti_uart_read(void *opaque, hwaddr addr, unsigned size)
> > +{
> > + ShaktiUartState *s = opaque;
> > + uint64_t retvalue = 0;
> > +
> > + switch (addr) {
> > + case SHAKTI_UART_BAUD:
> > + return s->uart_baud;
> > + break;
>
> You don't need a return and a break.
>
> Also if you return in each one you don't need the retvalue variable.
Yes. Will drop it.
>
> > + case SHAKTI_UART_RX:
> > + retvalue = s->uart_rx;
> > + qemu_chr_fe_accept_input(&s->chr);
> > + s->uart_status &= ~SHAKTI_UART_STATUS_RX_NOT_EMPTY;
> > + return retvalue;
> > + break;
> > + case SHAKTI_UART_STATUS:
> > + DPRINTF("uart_status: value = 0x%x)\n", s->uart_status);
> > + return s->uart_status;
> > + break;
> > + case SHAKTI_UART_DELAY:
> > + return s->uart_delay;
> > + break;
> > + case SHAKTI_UART_CONTROL:
> > + return s->uart_control;
> > + break;
> > + case SHAKTI_UART_INT_EN:
> > + return s->uart_interrupt;
> > + break;
> > + case SHAKTI_UART_IQ_CYCLES:
> > + return s->uart_iq_cycles;
> > + break;
> > + case SHAKTI_UART_RX_THRES:
> > + return s->uart_rx_threshold;
> > + break;
> > + default:
> > + /* Also handles TX REG which is write only */
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
>
> Maybe add a seperate log for TX then?
>
> Alistair
I believe this is sufficient. Anyway we are going to throw the same log.
Thanks,
Vijai Kumar K
>
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void shakti_uart_write(void *opaque, hwaddr addr,
> > + uint64_t data, unsigned size)
> > +{
> > + ShaktiUartState *s = opaque;
> > + uint32_t value = data;
> > + uint8_t ch;
> > +
> > + switch (addr) {
> > + case SHAKTI_UART_BAUD:
> > + s->uart_baud = value;
> > + break;
> > + case SHAKTI_UART_TX:
> > + ch = value;
> > + qemu_chr_fe_write_all(&s->chr, &ch, 1);
> > + s->uart_status &= ~SHAKTI_UART_STATUS_TX_FULL;
> > + break;
> > + case SHAKTI_UART_STATUS:
> > + s->uart_status = value;
> > + break;
> > + case SHAKTI_UART_DELAY:
> > + s->uart_delay = value;
> > + break;
> > + case SHAKTI_UART_CONTROL:
> > + s->uart_control = value;
> > + break;
> > + case SHAKTI_UART_INT_EN:
> > + s->uart_interrupt = value;
> > + break;
> > + case SHAKTI_UART_IQ_CYCLES:
> > + s->uart_iq_cycles = value;
> > + break;
> > + case SHAKTI_UART_RX_THRES:
> > + s->uart_rx_threshold = value;
> > + break;
> > + default:
> > + /* Also handles TX REG which is write only */
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
> > + }
> > +}
> > +
> > +static const MemoryRegionOps shakti_uart_ops = {
> > + .read = shakti_uart_read,
> > + .write = shakti_uart_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > + .impl = {.min_access_size = 1, .max_access_size = 4},
> > + .valid = {.min_access_size = 1, .max_access_size = 4},
> > +};
> > +
> > +static void shakti_uart_reset(DeviceState *dev)
> > +{
> > + ShaktiUartState *s = SHAKTI_UART(dev);
> > +
> > + s->uart_baud = SHAKTI_UART_BAUD_DEFAULT;
> > + s->uart_tx = 0x0;
> > + s->uart_rx = 0x0;
> > + s->uart_status = 0x0000;
> > + s->uart_delay = 0x0000;
> > + s->uart_control = SHAKTI_UART_CONTROL_DEFAULT;
> > + s->uart_interrupt = 0x0000;
> > + s->uart_iq_cycles = 0x00;
> > + s->uart_rx_threshold = 0x00;
> > +}
> > +
> > +static int shakti_uart_can_receive(void *opaque)
> > +{
> > + return 1;
> > +}
> > +
> > +static void shakti_uart_receive(void *opaque, const uint8_t *buf, int size)
> > +{
> > + ShaktiUartState *s = opaque;
> > +
> > + s->uart_rx = *buf;
> > + s->uart_status |= SHAKTI_UART_STATUS_RX_NOT_EMPTY;
> > +}
> > +
> > +static void shakti_uart_realize(DeviceState *dev, Error **errp)
> > +{
> > + ShaktiUartState *sus = SHAKTI_UART(dev);
> > + qemu_chr_fe_set_handlers(&sus->chr, shakti_uart_can_receive,
> > + shakti_uart_receive, NULL, NULL, sus, NULL, true);
> > +}
> > +
> > +static void shakti_uart_instance_init(Object *obj)
> > +{
> > + ShaktiUartState *sus = SHAKTI_UART(obj);
> > + memory_region_init_io(&sus->mmio,
> > + obj,
> > + &shakti_uart_ops,
> > + sus,
> > + TYPE_SHAKTI_UART,
> > + 0x1000);
> > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &sus->mmio);
> > +}
> > +
> > +static Property shakti_uart_properties[] = {
> > + DEFINE_PROP_CHR("chardev", ShaktiUartState, chr),
> > + DEFINE_PROP_END_OF_LIST(),
> > +};
> > +
> > +static void shakti_uart_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + dc->reset = shakti_uart_reset;
> > + dc->realize = shakti_uart_realize;
> > + device_class_set_props(dc, shakti_uart_properties);
> > +}
> > +
> > +static const TypeInfo shakti_uart_info = {
> > + .name = TYPE_SHAKTI_UART,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(ShaktiUartState),
> > + .class_init = shakti_uart_class_init,
> > + .instance_init = shakti_uart_instance_init,
> > +};
> > +
> > +static void shakti_uart_register_types(void)
> > +{
> > + type_register_static(&shakti_uart_info);
> > +}
> > +type_init(shakti_uart_register_types)
> > diff --git a/hw/char/trace-events b/hw/char/trace-events
> > index 81026f6612..54aeeb899c 100644
> > --- a/hw/char/trace-events
> > +++ b/hw/char/trace-events
> > @@ -80,6 +80,10 @@ cmsdk_apb_uart_set_params(int speed) "CMSDK APB UART: params set to %d 8N1"
> > nrf51_uart_read(uint64_t addr, uint64_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
> > nrf51_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
> >
> > +# shakti_uart.c
> > +shakti_uart_read(uint64_t addr, uint16_t r, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx16 " size %u"
> > +shakti_uart_write(uint64_t addr, uint64_t value, unsigned int size) "addr 0x%" PRIx64 " value 0x%" PRIx64 " size %u"
> > +
> > # exynos4210_uart.c
> > exynos_uart_dmabusy(uint32_t channel) "UART%d: DMA busy (Rx buffer empty)"
> > exynos_uart_dmaready(uint32_t channel) "UART%d: DMA ready"
> > diff --git a/include/hw/char/shakti_uart.h b/include/hw/char/shakti_uart.h
> > new file mode 100644
> > index 0000000000..526c408233
> > --- /dev/null
> > +++ b/include/hw/char/shakti_uart.h
> > @@ -0,0 +1,74 @@
> > +/*
> > + * SHAKTI UART
> > + *
> > + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person obtaining a copy
> > + * of this software and associated documentation files (the "Software"), to deal
> > + * in the Software without restriction, including without limitation the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#ifndef HW_SHAKTI_UART_H
> > +#define HW_SHAKTI_UART_H
> > +
> > +#include "hw/sysbus.h"
> > +#include "chardev/char-fe.h"
> > +
> > +#define SHAKTI_UART_BAUD 0x00
> > +#define SHAKTI_UART_TX 0x04
> > +#define SHAKTI_UART_RX 0x08
> > +#define SHAKTI_UART_STATUS 0x0C
> > +#define SHAKTI_UART_DELAY 0x10
> > +#define SHAKTI_UART_CONTROL 0x14
> > +#define SHAKTI_UART_INT_EN 0x18
> > +#define SHAKTI_UART_IQ_CYCLES 0x1C
> > +#define SHAKTI_UART_RX_THRES 0x20
> > +
> > +#define SHAKTI_UART_STATUS_TX_EMPTY (1 << 0)
> > +#define SHAKTI_UART_STATUS_TX_FULL (1 << 1)
> > +#define SHAKTI_UART_STATUS_RX_NOT_EMPTY (1 << 2)
> > +#define SHAKTI_UART_STATUS_RX_FULL (1 << 3)
> > +/* 9600 8N1 is the default setting */
> > +/* Reg value = (50000000 Hz)/(16 * 9600)*/
> > +#define SHAKTI_UART_BAUD_DEFAULT 0x0145
> > +#define SHAKTI_UART_CONTROL_DEFAULT 0x0100
> > +
> > +#define TYPE_SHAKTI_UART "shakti-uart"
> > +#define SHAKTI_UART(obj) \
> > + OBJECT_CHECK(ShaktiUartState, (obj), TYPE_SHAKTI_UART)
> > +
> > +typedef struct {
> > + /* <private> */
> > + SysBusDevice parent_obj;
> > +
> > + /* <public> */
> > + MemoryRegion mmio;
> > +
> > + uint32_t uart_baud;
> > + uint32_t uart_tx;
> > + uint32_t uart_rx;
> > + uint32_t uart_status;
> > + uint32_t uart_delay;
> > + uint32_t uart_control;
> > + uint32_t uart_interrupt;
> > + uint32_t uart_iq_cycles;
> > + uint32_t uart_rx_threshold;
> > +
> > + CharBackend chr;
> > +} ShaktiUartState;
> > +
> > +#endif /* HW_SHAKTI_UART_H */
> > --
> > 2.25.1
> >
> >
> >
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] riscv: Add initial support for Shakti C class
2021-03-19 13:39 ` Alistair Francis
@ 2021-03-20 9:46 ` Vijai Kumar K
0 siblings, 0 replies; 14+ messages in thread
From: Vijai Kumar K @ 2021-03-20 9:46 UTC (permalink / raw)
To: Alistair Francis; +Cc: open list:RISC-V, qemu-devel@nongnu.org Developers
---- On Fri, 19 Mar 2021 19:09:17 +0530 Alistair Francis <alistair23@gmail.com> wrote ----
> On Sun, Mar 14, 2021 at 5:10 AM Vijai Kumar K <vijai@behindbytes.com> wrote:
> >
> > C-Class is a member of the SHAKTI family of processors from Indian
> > Institute of Technology - Madras(IIT-M).
> > It is an extremely configurable and commercial-grade 5-stage in-order
> > core supporting the standard RV64GCSUN ISA extensions.
> >
> > Add support for emulating Shakti SoC based on C-class running on arty-100T
> > platform.
> >
> > https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/README.rst
> >
> > Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
> > ---
> > MAINTAINERS | 7 +
> > default-configs/devices/riscv64-softmmu.mak | 1 +
> > hw/riscv/Kconfig | 10 ++
> > hw/riscv/meson.build | 1 +
> > hw/riscv/shakti_c.c | 178 ++++++++++++++++++++
> > include/hw/riscv/shakti_c.h | 74 ++++++++
> > target/riscv/cpu.c | 9 +
> > target/riscv/cpu.h | 1 +
> > 8 files changed, 281 insertions(+)
> > create mode 100644 hw/riscv/shakti_c.c
> > create mode 100644 include/hw/riscv/shakti_c.h
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 8e9f0d591e..9f71c4cc3f 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1380,6 +1380,13 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
> > F: include/hw/misc/mchp_pfsoc_ioscb.h
> > F: include/hw/misc/mchp_pfsoc_sysreg.h
> >
> > +Shakti C class SoC
> > +M: Vijai Kumar K <vijai@behindbytes.com>
> > +L: qemu-riscv@nongnu.org
> > +S: Supported
> > +F: hw/riscv/shakti_c.c
> > +F: include/hw/riscv/shakti_c.h
> > +
> > SiFive Machines
> > M: Alistair Francis <Alistair.Francis@wdc.com>
> > M: Bin Meng <bin.meng@windriver.com>
> > diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/devices/riscv64-softmmu.mak
> > index d5eec75f05..bc69301fa4 100644
> > --- a/default-configs/devices/riscv64-softmmu.mak
> > +++ b/default-configs/devices/riscv64-softmmu.mak
> > @@ -13,3 +13,4 @@ CONFIG_SIFIVE_E=y
> > CONFIG_SIFIVE_U=y
> > CONFIG_RISCV_VIRT=y
> > CONFIG_MICROCHIP_PFSOC=y
> > +CONFIG_SHAKTI_C=y
> > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> > index d139074b02..92a62b5ce9 100644
> > --- a/hw/riscv/Kconfig
> > +++ b/hw/riscv/Kconfig
> > @@ -19,6 +19,16 @@ config OPENTITAN
> > select IBEX
> > select UNIMP
> >
> > +config SHAKTI
> > + bool
> > +
> > +config SHAKTI_C
> > + bool
> > + select UNIMP
> > + select SHAKTI
> > + select SIFIVE_CLINT
> > + select SIFIVE_PLIC
> > +
> > config RISCV_VIRT
> > bool
> > imply PCI_DEVICES
> > diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
> > index 275c0f7eb7..a97454661c 100644
> > --- a/hw/riscv/meson.build
> > +++ b/hw/riscv/meson.build
> > @@ -4,6 +4,7 @@ riscv_ss.add(files('numa.c'))
> > riscv_ss.add(files('riscv_hart.c'))
> > riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
> > riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))
> > +riscv_ss.add(when: 'CONFIG_SHAKTI_C', if_true: files('shakti_c.c'))
> > riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
> > riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
> > riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
> > diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> > new file mode 100644
> > index 0000000000..e96436a3bf
> > --- /dev/null
> > +++ b/hw/riscv/shakti_c.c
> > @@ -0,0 +1,178 @@
> > +/*
> > + * Shakti C-class SoC emulation
> > + *
> > + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2 or later, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along with
> > + * this program. If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "hw/boards.h"
> > +#include "hw/riscv/shakti_c.h"
> > +#include "qapi/error.h"
> > +#include "hw/intc/sifive_plic.h"
> > +#include "hw/intc/sifive_clint.h"
> > +#include "sysemu/sysemu.h"
> > +#include "hw/qdev-properties.h"
> > +#include "exec/address-spaces.h"
> > +#include "hw/riscv/boot.h"
> > +
> > +#define DEBUG_SHAKTI_C 0
> > +#define DPRINTF(fmt, args...) \
> > + do { \
> > + if (DEBUG_SHAKTI_C) { \
> > + fprintf(stderr, "[%s]%s: " fmt , TYPE_RISCV_SHAKTI_SOC, \
> > + __func__, ##args); \
> > + } \
> > + } while (0)
>
> This doesn't seem to be used, can you remove it?
>
Sure. Will drop it in V2.
> > +
> > +static const struct MemmapEntry {
> > + hwaddr base;
> > + hwaddr size;
> > +} shakti_c_memmap[] = {
> > + [SHAKTI_C_ROM] = { 0x00001000, 0x2000 },
> > + [SHAKTI_C_RAM] = { 0x80000000, 0x0 },
> > + [SHAKTI_C_UART] = { 0x00011300, 0x00040 },
> > + [SHAKTI_C_GPIO] = { 0x020d0000, 0x00100 },
> > + [SHAKTI_C_PLIC] = { 0x0c000000, 0x20000 },
> > + [SHAKTI_C_CLINT] = { 0x02000000, 0xc0000 },
> > + [SHAKTI_C_DEBUG] = { 0x00000000, 0x00010 },
> > + [SHAKTI_C_I2C] = { 0x20c00000, 0x00100 },
> > +};
> > +
> > +static void shakti_c_machine_state_init(MachineState *mstate)
> > +{
> > + ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
> > + MemoryRegion *system_memory = get_system_memory();
> > + MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> > + int i;
> > +
> > + /* Initialize SoC */
> > + object_initialize_child(OBJECT(mstate), "soc", &sms->soc,
> > + TYPE_RISCV_SHAKTI_SOC);
> > + qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
> > +
> > + /* register RAM */
> > + memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
> > + mstate->ram_size, &error_fatal);
> > + memory_region_add_subregion(system_memory,
> > + shakti_c_memmap[SHAKTI_C_RAM].base,
> > + main_mem);
> > +
> > + /* ROM reset vector */
> > + uint32_t reset_vec[3];
> > +
> > + reset_vec[0] = 0x080002b7; /* lui t0,0x08000 */
> > + reset_vec[1] = 0x00429293; /* slli t0,t0,4 */
> > + reset_vec[2] = 0x00028067; /* jr t0 */
>
> Is there a reason you can't use riscv_setup_rom_reset_vec()?
I did a quick try and seems I can. Thanks for the pointer. I will use that API.
>
> > +
> > + /* copy in the reset vector in little_endian byte order */
> > + for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
> > + reset_vec[i] = cpu_to_le32(reset_vec[i]);
> > + }
> > + rom_add_blob_fixed_as("rom.reset", reset_vec, sizeof(reset_vec),
> > + shakti_c_memmap[SHAKTI_C_ROM].base,
> > + &address_space_memory);
> > + riscv_load_firmware(mstate->firmware, shakti_c_memmap[SHAKTI_C_RAM].base,
> > + NULL);
> > +}
> > +
> > +static void shakti_c_machine_instance_init(Object *obj)
> > +{
> > +}
> > +
> > +static void shakti_c_machine_class_init(ObjectClass *klass, void *data)
> > +{
> > + MachineClass *mc = MACHINE_CLASS(klass);
> > + mc->desc = "RISC-V Board compatible with Shakti SDK";
> > + mc->init = shakti_c_machine_state_init;
> > + mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
> > +}
> > +
> > +static const TypeInfo shakti_c_machine_type_info = {
> > + .name = TYPE_RISCV_SHAKTI_MACHINE,
> > + .parent = TYPE_MACHINE,
> > + .class_init = shakti_c_machine_class_init,
> > + .instance_init = shakti_c_machine_instance_init,
> > + .instance_size = sizeof(ShaktiCMachineState),
> > +};
> > +
> > +static void shakti_c_machine_type_info_register(void)
> > +{
> > + type_register_static(&shakti_c_machine_type_info);
> > +}
> > +type_init(shakti_c_machine_type_info_register)
> > +
> > +static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
> > +{
> > + ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
> > + MemoryRegion *system_memory = get_system_memory();
>
> Can you add a newline here.
Will fix the formatting.
>
> > + sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
>
> and here
>
> > + sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
> > + (char *)SHAKTI_C_PLIC_HART_CONFIG, 0,
> > + SHAKTI_C_PLIC_NUM_SOURCES,
> > + SHAKTI_C_PLIC_NUM_PRIORITIES,
> > + SHAKTI_C_PLIC_PRIORITY_BASE,
> > + SHAKTI_C_PLIC_PENDING_BASE,
> > + SHAKTI_C_PLIC_ENABLE_BASE,
> > + SHAKTI_C_PLIC_ENABLE_STRIDE,
> > + SHAKTI_C_PLIC_CONTEXT_BASE,
> > + SHAKTI_C_PLIC_CONTEXT_STRIDE,
> > + shakti_c_memmap[SHAKTI_C_PLIC].size);
>
> and here
>
> > + sifive_clint_create(shakti_c_memmap[SHAKTI_C_CLINT].base,
> > + shakti_c_memmap[SHAKTI_C_CLINT].size, 0, 1,
> > + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
> > + SIFIVE_CLINT_TIMEBASE_FREQ, false);
>
> and here
>
> > + /* ROM */
> > + memory_region_init_rom(&sss->rom, OBJECT(dev), "riscv.shakti.c.rom",
> > + shakti_c_memmap[SHAKTI_C_ROM].size, &error_fatal);
> > + memory_region_add_subregion(system_memory,
> > + shakti_c_memmap[SHAKTI_C_ROM].base, &sss->rom);
> > +}
> > +
> > +static void shakti_c_soc_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + dc->realize = shakti_c_soc_state_realize;
> > +}
> > +
> > +static void shakti_c_soc_instance_init(Object *obj)
> > +{
> > + ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(obj);
> > +
> > + object_initialize_child(obj, "cpus", &sss->cpus, TYPE_RISCV_HART_ARRAY);
> > +
> > + /*
> > + * CPU type is fixed and we are not supporting passing from commandline yet.
> > + * So let it be in instance_init. When supported should use ms->cpu_type
> > + * instead of TYPE_RISCV_CPU_SHAKTI_C
> > + */
>
> You need to return an error then if the user tries to change the
> number or type of CPU instead of ignoring it.
Sure. Will handle it.
>
> > + object_property_set_str(OBJECT(&sss->cpus), "cpu-type",
> > + TYPE_RISCV_CPU_SHAKTI_C, &error_abort);
> > + object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1,
> > + &error_abort);
> > +}
> > +
> > +static const TypeInfo shakti_c_type_info = {
> > + .name = TYPE_RISCV_SHAKTI_SOC,
> > + .parent = TYPE_DEVICE,
> > + .class_init = shakti_c_soc_class_init,
> > + .instance_init = shakti_c_soc_instance_init,
> > + .instance_size = sizeof(ShaktiCSoCState),
> > +};
> > +
> > +static void shakti_c_type_info_register(void)
> > +{
> > + type_register_static(&shakti_c_type_info);
> > +}
> > +type_init(shakti_c_type_info_register)
> > diff --git a/include/hw/riscv/shakti_c.h b/include/hw/riscv/shakti_c.h
> > new file mode 100644
> > index 0000000000..6c66a160f5
> > --- /dev/null
> > +++ b/include/hw/riscv/shakti_c.h
> > @@ -0,0 +1,74 @@
> > +/*
> > + * Shakti C-class SoC emulation
> > + *
> > + * Copyright (c) 2021 Vijai Kumar K <vijai@behindbytes.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2 or later, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along with
> > + * this program. If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#ifndef HW_SHAKTI_H
> > +#define HW_SHAKTI_H
> > +
> > +#include "hw/riscv/riscv_hart.h"
> > +#include "hw/boards.h"
> > +
> > +#define TYPE_RISCV_SHAKTI_SOC "riscv.shakti.cclass.soc"
> > +#define RISCV_SHAKTI_SOC(obj) \
> > + OBJECT_CHECK(ShaktiCSoCState, (obj), TYPE_RISCV_SHAKTI_SOC)
> > +
> > +typedef struct ShaktiCSoCState {
> > + /*< private >*/
> > + DeviceState parent_obj;
> > +
> > + /*< public >*/
> > + RISCVHartArrayState cpus;
> > + DeviceState *plic;
> > + MemoryRegion rom;
> > +
> > +} ShaktiCSoCState;
> > +
> > +#define TYPE_RISCV_SHAKTI_MACHINE MACHINE_TYPE_NAME("shakti_c")
> > +#define RISCV_SHAKTI_MACHINE(obj) \
> > + OBJECT_CHECK(ShaktiCMachineState, (obj), TYPE_RISCV_SHAKTI_MACHINE)
> > +typedef struct ShaktiCMachineState {
> > + /*< private >*/
> > + MachineState parent_obj;
> > +
> > + /*< public >*/
> > + ShaktiCSoCState soc;
> > +} ShaktiCMachineState;
> > +
> > +enum {
> > + SHAKTI_C_ROM,
> > + SHAKTI_C_RAM,
> > + SHAKTI_C_UART,
> > + SHAKTI_C_GPIO,
> > + SHAKTI_C_PLIC,
> > + SHAKTI_C_CLINT,
> > + SHAKTI_C_DEBUG,
> > + SHAKTI_C_I2C,
> > +};
> > +
> > +#define SHAKTI_C_PLIC_HART_CONFIG "MS"
> > +/* Including Interrupt ID 0 (no interrupt)*/
> > +#define SHAKTI_C_PLIC_NUM_SOURCES 28
> > +/* Excluding Priority 0 */
> > +#define SHAKTI_C_PLIC_NUM_PRIORITIES 2
> > +#define SHAKTI_C_PLIC_PRIORITY_BASE 0x04
> > +#define SHAKTI_C_PLIC_PENDING_BASE 0x1000
> > +#define SHAKTI_C_PLIC_ENABLE_BASE 0x2000
> > +#define SHAKTI_C_PLIC_ENABLE_STRIDE 0x80
> > +#define SHAKTI_C_PLIC_CONTEXT_BASE 0x200000
> > +#define SHAKTI_C_PLIC_CONTEXT_STRIDE 0x1000
> > +
> > +#endif
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 2a990f6253..618d203aa0 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -159,6 +159,14 @@ static void rv64_base_cpu_init(Object *obj)
> > set_misa(env, RV64);
> > }
> >
> > +static void rv64_shakti_c_cpu_init(Object *obj)
> > +{
> > + CPURISCVState *env = &RISCV_CPU(obj)->env;
> > + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>
> Don't use RVXLEN, this is a 64-bit CPU right?
>
> This is also exactly the same as the rv64_sifive_u_cpu_init() can we
> just use an existing CPU instead of adding a new one?
Will reuse the sifive_u_cpu_init()
>
> > + set_priv_version(env, PRIV_VERSION_1_10_0);
> > + set_resetvec(env, DEFAULT_RSTVEC);
> > +}
> > +
> > static void rv64_sifive_u_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > @@ -707,6 +715,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
> > + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_shakti_c_cpu_init),
> > #endif
> > };
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 0edb2826a2..ebbf15fb1c 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -38,6 +38,7 @@
> > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> > +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
>
> Can you add the CPU in a separate patch?
>
> Alistair
I guess I can. Let me check.
Thanks,
Vijai Kumar K
>
> > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> > #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> > --
> > 2.25.1
> >
> >
> >
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-03-20 9:50 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-14 8:39 [PATCH 0/3] Add support for Shakti SoC from IIT-M Vijai Kumar K
2021-03-14 8:39 ` Vijai Kumar K
2021-03-14 8:39 ` [PATCH 1/3] riscv: Add initial support for Shakti C class Vijai Kumar K
2021-03-14 8:39 ` Vijai Kumar K
2021-03-19 13:39 ` Alistair Francis
2021-03-20 9:46 ` Vijai Kumar K
2021-03-14 8:39 ` [PATCH 2/3] hw/char: Add Shakti UART emulation Vijai Kumar K
2021-03-14 8:39 ` Vijai Kumar K
2021-03-19 13:44 ` Alistair Francis
2021-03-20 9:41 ` Vijai Kumar K
2021-03-14 8:39 ` [PATCH 3/3] hw/riscv: Connect Shakti UART to Shakti platform Vijai Kumar K
2021-03-14 8:39 ` Vijai Kumar K
2021-03-19 13:47 ` Alistair Francis
2021-03-20 9:38 ` Vijai Kumar K
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