* [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support
@ 2020-06-08 14:17 Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
` (15 more replies)
0 siblings, 16 replies; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
This series updates the 'sifive_u' machine support:
- Add GPIO controller support
- Support reboot functionality via GPIO pin#10
- Change SiFive E/U series CPU reset vector to 0x1004
- Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new
"msel" machine property
- Add a dummy DDR memory controller device
The series also does some clean-ups to the existing codes.
With this series, QEMU can boot U-Boot SPL built for SiFive FU540
all the way up to loading U-Boot proper from MMC:
$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
Trying to boot from MMC1
Unhandled exception: Load access fault
EPC: 0000000008009be6 TVAL: 0000000010050014
The last big gap for the 'sifive_u' machine is the QSPI modeling.
Bin Meng (15):
hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc*
functions
hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc*
functions
hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
hw/riscv: sifive_u: Generate device tree node for OTP
hw/riscv: sifive_gpio: Clean up the codes
hw/riscv: sifive_gpio: Add a new 'ngpio' property
hw/riscv: sifive_u: Hook a GPIO controller
hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
hw/riscv: sifive_u: Add reset functionality
hw/riscv: sifive_u: Rename serial property get/set functions to a
generic name
hw/riscv: sifive_u: Add a new property msel for MSEL pin state
hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
hw/riscv: sifive_u: Support different boot source per MSEL pin state
hw/riscv: sifive_u: Sort the SoC memmap table entries
hw/riscv: sifive_u: Add a dummy DDR memory controller device
hw/riscv/opentitan.c | 29 ++++----
hw/riscv/sifive_e.c | 32 +++++----
hw/riscv/sifive_gpio.c | 45 +++++++-----
hw/riscv/sifive_u.c | 158 ++++++++++++++++++++++++++++++++++-------
include/hw/riscv/sifive_gpio.h | 8 ++-
include/hw/riscv/sifive_u.h | 27 +++++++
target/riscv/cpu.c | 4 +-
7 files changed, 223 insertions(+), 80 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:05 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
` (14 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
This was done in the virt & sifive_u codes, but sifive_e codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_e.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 472a989..8fab152 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -75,7 +75,7 @@ static const struct MemmapEntry {
[SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
};
-static void riscv_sifive_e_init(MachineState *machine)
+static void sifive_e_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -124,7 +124,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "RISC-V Board compatible with SiFive E SDK";
- mc->init = riscv_sifive_e_init;
+ mc->init = sifive_e_machine_init;
mc->max_cpus = 1;
mc->default_cpu_type = SIFIVE_E_CPU;
}
@@ -144,7 +144,7 @@ static void sifive_e_machine_init_register_types(void)
type_init(sifive_e_machine_init_register_types)
-static void riscv_sifive_e_soc_init(Object *obj)
+static void sifive_e_soc_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
SiFiveESoCState *s = RISCV_E_SOC(obj);
@@ -159,7 +159,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
TYPE_SIFIVE_GPIO);
}
-static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
+static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
const struct MemmapEntry *memmap = sifive_e_memmap;
@@ -243,26 +243,26 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
&s->xip_mem);
}
-static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
+static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->realize = riscv_sifive_e_soc_realize;
+ dc->realize = sifive_e_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
}
-static const TypeInfo riscv_sifive_e_soc_type_info = {
+static const TypeInfo sifive_e_soc_type_info = {
.name = TYPE_RISCV_E_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(SiFiveESoCState),
- .instance_init = riscv_sifive_e_soc_init,
- .class_init = riscv_sifive_e_soc_class_init,
+ .instance_init = sifive_e_soc_init,
+ .class_init = sifive_e_soc_class_init,
};
-static void riscv_sifive_e_soc_register_types(void)
+static void sifive_e_soc_register_types(void)
{
- type_register_static(&riscv_sifive_e_soc_type_info);
+ type_register_static(&sifive_e_soc_type_info);
}
-type_init(riscv_sifive_e_soc_register_types)
+type_init(sifive_e_soc_register_types)
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:06 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
` (13 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
This was done in the virt & sifive_u codes, but opentitan codes were
missed. Remove the riscv_ prefix of the machine* and soc* functions.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/opentitan.c | 29 ++++++++++++++---------------
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index b4fb836..0907a42 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -51,7 +51,7 @@ static const struct MemmapEntry {
[IBEX_PADCTRL] = { 0x40160000, 0x10000 }
};
-static void riscv_opentitan_init(MachineState *machine)
+static void opentitan_board_init(MachineState *machine)
{
const struct MemmapEntry *memmap = ibex_memmap;
OpenTitanState *s = g_new0(OpenTitanState, 1);
@@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine)
memory_region_add_subregion(sys_mem,
memmap[IBEX_RAM].base, main_mem);
-
if (machine->firmware) {
riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
}
@@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine)
}
}
-static void riscv_opentitan_machine_init(MachineClass *mc)
+static void opentitan_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Board compatible with OpenTitan";
- mc->init = riscv_opentitan_init;
+ mc->init = opentitan_board_init;
mc->max_cpus = 1;
mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
}
-DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
+DEFINE_MACHINE("opentitan", opentitan_machine_init)
-static void riscv_lowrisc_ibex_soc_init(Object *obj)
+static void lowrisc_ibex_soc_init(Object *obj)
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
@@ -99,7 +98,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
&error_abort, NULL);
}
-static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
+static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
{
const struct MemmapEntry *memmap = ibex_memmap;
MachineState *ms = MACHINE(qdev_get_machine());
@@ -159,26 +158,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
}
-static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
+static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- dc->realize = riscv_lowrisc_ibex_soc_realize;
+ dc->realize = lowrisc_ibex_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
}
-static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
+static const TypeInfo lowrisc_ibex_soc_type_info = {
.name = TYPE_RISCV_IBEX_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(LowRISCIbexSoCState),
- .instance_init = riscv_lowrisc_ibex_soc_init,
- .class_init = riscv_lowrisc_ibex_soc_class_init,
+ .instance_init = lowrisc_ibex_soc_init,
+ .class_init = lowrisc_ibex_soc_class_init,
};
-static void riscv_lowrisc_ibex_soc_register_types(void)
+static void lowrisc_ibex_soc_register_types(void)
{
- type_register_static(&riscv_lowrisc_ibex_soc_type_info);
+ type_register_static(&lowrisc_ibex_soc_type_info);
}
-type_init(riscv_lowrisc_ibex_soc_register_types)
+type_init(lowrisc_ibex_soc_register_types)
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:07 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
` (12 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
There is no need to retrieve all PLIC IRQ information in order to
just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
what is done for other peripherals.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f9fef2b..cf7f833 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -528,7 +528,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
- qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
@@ -612,10 +611,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
- for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
- plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
- }
-
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem), nd);
@@ -629,7 +624,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
- plic_gpios[SIFIVE_U_GEM_IRQ]);
+ qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (2 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:08 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
` (11 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
based on device tree information. Let's generate the device tree
node for OTP.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index cf7f833..8dc6842 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -207,6 +207,17 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/otp@%lx",
+ (long)memmap[SIFIVE_U_OTP].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_OTP].base,
+ 0x0, memmap[SIFIVE_U_OTP].size);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "sifive,fu540-c000-otp");
+ g_free(nodename);
+
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
(long)memmap[SIFIVE_U_PRCI].base);
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (3 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:13 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
` (10 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Do various minor clean-ups to the exisiting codes for:
- coding convention conformance
- remove unnecessary blank lines
- spell SiFive correctly
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_gpio.c | 13 +++++--------
include/hw/riscv/sifive_gpio.h | 7 ++++---
2 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 5c7c596..c9cffa2 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -1,5 +1,5 @@
/*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
*
* Copyright 2019 AdaCore
*
@@ -20,7 +20,6 @@
static void update_output_irq(SIFIVEGPIOState *s)
{
-
uint32_t pending;
uint32_t pin;
@@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
}
static void sifive_gpio_write(void *opaque, hwaddr offset,
- uint64_t value, unsigned int size)
+ uint64_t value, unsigned int size)
{
SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
@@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev)
s->out_xor = 0;
s->in = 0;
s->in_mask = 0;
-
}
static const VMStateDescription vmstate_sifive_gpio = {
@@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio = {
VMSTATE_UINT32(iof_en, SIFIVEGPIOState),
VMSTATE_UINT32(iof_sel, SIFIVEGPIOState),
VMSTATE_UINT32(out_xor, SIFIVEGPIOState),
- VMSTATE_UINT32(in, SIFIVEGPIOState),
- VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
+ VMSTATE_UINT32(in, SIFIVEGPIOState),
+ VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
VMSTATE_END_OF_LIST()
}
};
@@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj)
TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
-
for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
}
@@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_sifive_gpio;
dc->reset = sifive_gpio_reset;
- dc->desc = "sifive GPIO";
+ dc->desc = "SiFive GPIO";
}
static const TypeInfo sifive_gpio_info = {
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
index fce03d6..ad915b2 100644
--- a/include/hw/riscv/sifive_gpio.h
+++ b/include/hw/riscv/sifive_gpio.h
@@ -1,5 +1,5 @@
/*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
*
* Copyright 2019 AdaCore
*
@@ -10,10 +10,12 @@
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*/
+
#ifndef SIFIVE_GPIO_H
#define SIFIVE_GPIO_H
#include "hw/sysbus.h"
+
#define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
#define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
@@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState {
uint32_t out_xor;
uint32_t in;
uint32_t in_mask;
-
} SIFIVEGPIOState;
-#endif
+#endif /* SIFIVE_GPIO_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (4 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:16 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
` (9 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Add a new property to represent the number of GPIO pins supported
by the GPIO controller.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_gpio.c | 30 +++++++++++++++++++-----------
include/hw/riscv/sifive_gpio.h | 3 +++
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index c9cffa2..0d0fd2b 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -14,6 +14,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "hw/irq.h"
+#include "hw/qdev-properties.h"
#include "hw/riscv/sifive_gpio.h"
#include "migration/vmstate.h"
#include "trace.h"
@@ -28,7 +29,7 @@ static void update_output_irq(SIFIVEGPIOState *s)
pending |= s->rise_ip & s->rise_ie;
pending |= s->fall_ip & s->fall_ie;
- for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
+ for (int i = 0; i < s->ngpio; i++) {
pin = 1 << i;
qemu_set_irq(s->irq[i], (pending & pin) != 0);
trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);
@@ -41,7 +42,7 @@ static void update_state(SIFIVEGPIOState *s)
bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,
rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;
- for (i = 0; i < SIFIVE_GPIO_PINS; i++) {
+ for (i = 0; i < s->ngpio; i++) {
prev_ival = extract32(s->value, i, 1);
in = extract32(s->in, i, 1);
@@ -346,27 +347,35 @@ static const VMStateDescription vmstate_sifive_gpio = {
}
};
-static void sifive_gpio_init(Object *obj)
+static Property sifive_gpio_properties[] = {
+ DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_gpio_realize(DeviceState *dev, Error **errp)
{
- SIFIVEGPIOState *s = SIFIVE_GPIO(obj);
+ SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
- memory_region_init_io(&s->mmio, obj, &gpio_ops, s,
+ memory_region_init_io(&s->mmio, OBJECT(dev), &gpio_ops, s,
TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
- sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
- for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
- sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
+
+ for (int i = 0; i < s->ngpio; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
}
- qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS);
- qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS);
+ qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio);
+ qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio);
}
static void sifive_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ device_class_set_props(dc, sifive_gpio_properties);
dc->vmsd = &vmstate_sifive_gpio;
+ dc->realize = sifive_gpio_realize;
dc->reset = sifive_gpio_reset;
dc->desc = "SiFive GPIO";
}
@@ -375,7 +384,6 @@ static const TypeInfo sifive_gpio_info = {
.name = TYPE_SIFIVE_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SIFIVEGPIOState),
- .instance_init = sifive_gpio_init,
.class_init = sifive_gpio_class_init
};
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
index ad915b2..cf12fcf 100644
--- a/include/hw/riscv/sifive_gpio.h
+++ b/include/hw/riscv/sifive_gpio.h
@@ -68,6 +68,9 @@ typedef struct SIFIVEGPIOState {
uint32_t out_xor;
uint32_t in;
uint32_t in_mask;
+
+ /* config */
+ uint32_t ngpio;
} SIFIVEGPIOState;
#endif /* SIFIVE_GPIO_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (5 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:26 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
` (8 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines.
This hooks the exsiting SiFive GPIO model to the SoC, and adds its
device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
include/hw/riscv/sifive_u.h | 19 +++++++++++++++++++
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 8dc6842..881949b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -11,8 +11,9 @@
* 1) CLINT (Core Level Interruptor)
* 2) PLIC (Platform Level Interrupt Controller)
* 3) PRCI (Power, Reset, Clock, Interrupt)
- * 4) OTP (One-Time Programmable) memory with stored serial number
- * 5) GEM (Gigabit Ethernet Controller) and management block
+ * 4) GPIO (General Purpose Input/Output Controller)
+ * 5) OTP (One-Time Programmable) memory with stored serial number
+ * 6) GEM (Gigabit Ethernet Controller) and management block
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -75,6 +76,7 @@ static const struct MemmapEntry {
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
[SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
@@ -268,6 +270,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/gpio@%lx",
+ (long)memmap[SIFIVE_U_GPIO].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
+ qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_GPIO].base,
+ 0x0, memmap[SIFIVE_U_GPIO].size);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
+ SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
+ SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
+ SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
+ SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
+ SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
+ g_free(nodename);
+
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
(long)memmap[SIFIVE_U_GEM].base);
@@ -525,6 +549,8 @@ static void sifive_u_soc_instance_init(Object *obj)
sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
TYPE_SIFIVE_U_PRCI);
+ sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
+ TYPE_SIFIVE_GPIO);
sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
TYPE_SIFIVE_U_OTP);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
@@ -618,6 +644,20 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
+ object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+
+ /* Pass all GPIOs to the SOC layer so they are available to the board */
+ qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
+
+ /* Connect GPIO interrupts to the PLIC */
+ for (i = 0; i < 16; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ SIFIVE_U_GPIO_IRQ0 + i));
+ }
+
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 16c297e..dcf7f3b 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -22,6 +22,7 @@
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
+#include "hw/riscv/sifive_gpio.h"
#include "hw/riscv/sifive_u_prci.h"
#include "hw/riscv/sifive_u_otp.h"
@@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState {
RISCVHartArrayState u_cpus;
DeviceState *plic;
SiFiveUPRCIState prci;
+ SIFIVEGPIOState gpio;
SiFiveUOTPState otp;
CadenceGEMState gem;
@@ -73,6 +75,7 @@ enum {
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
SIFIVE_U_UART1,
+ SIFIVE_U_GPIO,
SIFIVE_U_OTP,
SIFIVE_U_FLASH0,
SIFIVE_U_DRAM,
@@ -83,6 +86,22 @@ enum {
enum {
SIFIVE_U_UART0_IRQ = 4,
SIFIVE_U_UART1_IRQ = 5,
+ SIFIVE_U_GPIO_IRQ0 = 7,
+ SIFIVE_U_GPIO_IRQ1 = 8,
+ SIFIVE_U_GPIO_IRQ2 = 9,
+ SIFIVE_U_GPIO_IRQ3 = 10,
+ SIFIVE_U_GPIO_IRQ4 = 11,
+ SIFIVE_U_GPIO_IRQ5 = 12,
+ SIFIVE_U_GPIO_IRQ6 = 13,
+ SIFIVE_U_GPIO_IRQ7 = 14,
+ SIFIVE_U_GPIO_IRQ8 = 15,
+ SIFIVE_U_GPIO_IRQ9 = 16,
+ SIFIVE_U_GPIO_IRQ10 = 17,
+ SIFIVE_U_GPIO_IRQ11 = 18,
+ SIFIVE_U_GPIO_IRQ12 = 19,
+ SIFIVE_U_GPIO_IRQ13 = 20,
+ SIFIVE_U_GPIO_IRQ14 = 21,
+ SIFIVE_U_GPIO_IRQ15 = 22,
SIFIVE_U_GEM_IRQ = 0x35
};
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (6 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:28 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
` (7 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
At present the GPIO output IRQs are triggered each time any GPIO
register is written. However this is not correct. We should only
trigger the output IRQ when the pin is configured as output enable.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_gpio.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 0d0fd2b..aac6b44 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s)
actual_value = pull;
}
- qemu_set_irq(s->output[i], actual_value);
+ if (output_en) {
+ qemu_set_irq(s->output[i], actual_value);
+ }
/* Input value */
ival = input_en && actual_value;
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (7 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:35 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
` (6 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. Let's set up the GPIO pin#10 and insert a
"gpio-restart" device tree node so that reboot is now functional
with QEMU 'sifive_u' machine.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 881949b..ef51874 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -37,6 +37,7 @@
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "hw/boards.h"
+#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
@@ -53,6 +54,7 @@
#include "net/eth.h"
#include "sysemu/arch_init.h"
#include "sysemu/device_tree.h"
+#include "sysemu/runstate.h"
#include "sysemu/sysemu.h"
#include "exec/address-spaces.h"
@@ -96,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
uint32_t *cells;
char *nodename;
char ethclk_names[] = "pclk\0hclk";
- uint32_t plic_phandle, prci_phandle, phandle = 1;
+ uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
@@ -270,9 +272,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
(long)memmap[SIFIVE_U_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
@@ -292,6 +296,12 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
g_free(nodename);
+ nodename = g_strdup_printf("/gpio-restart");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
+ g_free(nodename);
+
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
(long)memmap[SIFIVE_U_GEM].base);
@@ -352,6 +362,14 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
+static void sifive_u_machine_reset(void *opaque, int n, int level)
+{
+ /* gpio pin active low triggers reset */
+ if (!level) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ }
+}
+
static void sifive_u_machine_init(MachineState *machine)
{
const struct MemmapEntry *memmap = sifive_u_memmap;
@@ -383,6 +401,10 @@ static void sifive_u_machine_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
flash0);
+ /* register gpio-restart */
+ qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
+ qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
+
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (8 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:39 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
` (5 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
In prepration to add more properties to this machine, rename the
existing serial property get/set functions to a generic name.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ef51874..07e2ba0 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -481,14 +481,16 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
s->start_in_flash = value;
}
-static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
{
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
}
-static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
{
visit_type_uint32(v, name, (uint32_t *)opaque, errp);
}
@@ -507,8 +509,8 @@ static void sifive_u_machine_instance_init(Object *obj)
s->serial = OTP_SERIAL;
object_property_add(obj, "serial", "uint32",
- sifive_u_machine_get_serial,
- sifive_u_machine_set_serial, NULL, &s->serial);
+ sifive_u_machine_get_uint32_prop,
+ sifive_u_machine_set_uint32_prop, NULL, &s->serial);
object_property_set_description(obj, "serial", "Board serial number");
}
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (9 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 16:41 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
` (4 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
On SiFive FU540 SoC, the value stored at physical address 0x1000
stores the MSEL pin state that is used to control the next boot
location that ROM codes jump to.
Add a new property msel to sifive_u machine for this.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 7 +++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 07e2ba0..aaa5adb 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -507,6 +507,13 @@ static void sifive_u_machine_instance_init(Object *obj)
"Set on to tell QEMU's ROM to jump to "
"flash. Otherwise QEMU will jump to DRAM");
+ s->msel = 0;
+ object_property_add(obj, "msel", "uint32",
+ sifive_u_machine_get_uint32_prop,
+ sifive_u_machine_set_uint32_prop, NULL, &s->msel);
+ object_property_set_description(obj, "msel",
+ "Mode Select (MSEL[3:0]) pin state");
+
s->serial = OTP_SERIAL;
object_property_add(obj, "serial", "uint32",
sifive_u_machine_get_uint32_prop,
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index dcf7f3b..d82cfe0 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -63,6 +63,7 @@ typedef struct SiFiveUState {
int fdt_size;
bool start_in_flash;
+ uint32_t msel;
uint32_t serial;
} SiFiveUState;
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (10 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 19:02 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
` (3 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Per the SiFive manual, all E/U series CPU cores' reset vector is
at 0x1004. Update our codes to match the hardware.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_e.c | 8 +++++---
hw/riscv/sifive_u.c | 6 +++---
target/riscv/cpu.c | 4 ++--
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 8fab152..f05cabd 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -98,9 +98,11 @@ static void sifive_e_machine_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2] = {
- 0x204002b7, /* 0x1000: lui t0,0x20400 */
- 0x00028067, /* 0x1004: jr t0 */
+ uint32_t reset_vec[4] = {
+ 0x00000000,
+ 0x204002b7, /* 0x1004: lui t0,0x20400 */
+ 0x00028067, /* 0x1008: jr t0 */
+ 0x00000000,
};
/* copy in the reset vector in little_endian byte order */
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index aaa5adb..0a86ffc 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -433,18 +433,18 @@ static void sifive_u_machine_init(MachineState *machine)
/* reset vector */
uint32_t reset_vec[8] = {
+ 0x00000000,
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
+ 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32)
0x0182a283, /* lw t0, 24(t0) */
#elif defined(TARGET_RISCV64)
- 0x0182b283, /* ld t0, 24(t0) */
+ 0x0182e283, /* lwu t0, 24(t0) */
#endif
0x00028067, /* jr t0 */
0x00000000,
start_addr, /* start: .dword */
- 0x00000000,
/* dtb: */
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5060534..1944ad6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -139,7 +139,7 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
+ set_resetvec(env, 0x1004);
}
static void rvnn_imacu_nommu_cpu_init(Object *obj)
@@ -147,7 +147,7 @@ static void rvnn_imacu_nommu_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
+ set_resetvec(env, 0x1004);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (11 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
` (2 subsequent siblings)
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
SiFive FU540 SoC supports booting from several sources, which are
controlled using the Mode Select (MSEL[3:0]) pins on the chip.
Typically, the boot process runs through several stages before it
begins execution of user-provided programs.
The SoC supports booting from memory-mapped QSPI flash, which is
how start_in_flash property is used for at present. This matches
MSEL = 1 configuration (QSPI0).
Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL).
It's not necessary for QEMU to implement the full ZSBL ROM codes,
because we know ZSBL downloads the next stage program into the L2
LIM at address 0x8000000 and executes from there. We can bypass
the whole ZSBL execution and use "-bios" to load the next stage
program directly if MSEL indicates a ZSBL booting flow.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 39 +++++++++++++++++++++++++++++++--------
include/hw/riscv/sifive_u.h | 6 ++++++
2 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0a86ffc..f64aa52 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -408,8 +408,34 @@ static void sifive_u_machine_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
- riscv_find_and_load_firmware(machine, BIOS_FILENAME,
- memmap[SIFIVE_U_DRAM].base, NULL);
+ if (s->start_in_flash) {
+ /*
+ * If start_in_flash property is given, assign s->msel to a value
+ * that representing booting from QSPI0 memory-mapped flash.
+ *
+ * This also means that when both start_in_flash and msel properties
+ * are given, start_in_flash takes the precedence over msel.
+ *
+ * Note this is to keep backward compatibility not to break existing
+ * users that use start_in_flash property.
+ */
+ s->msel = MSEL_MEMMAP_QSPI0_FLASH;
+ }
+
+ switch (s->msel) {
+ case MSEL_MEMMAP_QSPI0_FLASH:
+ start_addr = memmap[SIFIVE_U_FLASH0].base;
+ break;
+ case MSEL_L2LIM_QSPI0_FLASH:
+ case MSEL_L2LIM_QSPI2_SD:
+ start_addr = memmap[SIFIVE_U_L2LIM].base;
+ break;
+ default:
+ start_addr = memmap[SIFIVE_U_DRAM].base;
+ break;
+ }
+
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
@@ -427,13 +453,9 @@ static void sifive_u_machine_init(MachineState *machine)
}
}
- if (s->start_in_flash) {
- start_addr = memmap[SIFIVE_U_FLASH0].base;
- }
-
/* reset vector */
uint32_t reset_vec[8] = {
- 0x00000000,
+ s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
@@ -505,7 +527,8 @@ static void sifive_u_machine_instance_init(Object *obj)
sifive_u_machine_set_start_in_flash);
object_property_set_description(obj, "start-in-flash",
"Set on to tell QEMU's ROM to jump to "
- "flash. Otherwise QEMU will jump to DRAM");
+ "flash. Otherwise QEMU will jump to DRAM "
+ "or L2LIM depending on the msel value");
s->msel = 0;
object_property_add(obj, "msel", "uint32",
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index d82cfe0..5d80f91 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -111,6 +111,12 @@ enum {
SIFIVE_U_RTCCLK_FREQ = 1000000
};
+enum {
+ MSEL_MEMMAP_QSPI0_FLASH = 1,
+ MSEL_L2LIM_QSPI0_FLASH = 6,
+ MSEL_L2LIM_QSPI2_SD = 11
+};
+
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
#define SIFIVE_U_COMPUTE_CPU_COUNT 4
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (12 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-15 19:31 ` Alistair Francis
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Move the flash and DRAM to the end of the SoC memmap table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f64aa52..c94ff6f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -80,10 +80,10 @@ static const struct MemmapEntry {
[SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
[SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
` (13 preceding siblings ...)
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
@ 2020-06-08 14:17 ` Bin Meng
2020-06-15 19:20 ` Alistair Francis
2020-06-15 19:31 ` Alistair Francis
15 siblings, 1 reply; 48+ messages in thread
From: Bin Meng @ 2020-06-08 14:17 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
It is enough to simply map the SiFive FU540 DDR memory controller
into the MMIO space using create_unimplemented_device(), to make
the upstream U-Boot v2020.07 DDR memory initialization codes happy.
Note we do not generate device tree fragment for the DDR memory
controller. Since the controller data in device tree consumes a
very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the
U-Boot source), and it is only needed by U-Boot SPL but not any
operating system, we choose not to generate the fragment here.
This also means when testing with U-Boot SPL, the device tree has
to come from U-Boot SPL itself, but not the one generated by QEMU
on the fly. The memory has to be set to 8GiB to match the real
HiFive Unleashed board when invoking QEMU (-m 8G).
With this commit, QEMU can boot U-Boot SPL built for SiFive FU540
all the way up to loading U-Boot proper from MMC:
$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
Trying to boot from MMC1
Unhandled exception: Load access fault
EPC: 0000000008009be6 TVAL: 0000000010050014
The above exception is expected because QSPI is unsupported yet.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 4 ++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index c94ff6f..7923df4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -82,6 +82,7 @@ static const struct MemmapEntry {
[SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
[SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
[SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
[SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
};
@@ -733,6 +734,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+
+ create_unimplemented_device("riscv.sifive.u.dmc",
+ memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
}
static Property sifive_u_soc_props[] = {
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 5d80f91..3e33646 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -78,6 +78,7 @@ enum {
SIFIVE_U_UART1,
SIFIVE_U_GPIO,
SIFIVE_U_OTP,
+ SIFIVE_U_DMC,
SIFIVE_U_FLASH0,
SIFIVE_U_DRAM,
SIFIVE_U_GEM,
--
2.7.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
@ 2020-06-15 16:05 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:05 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:20 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This was done in the virt & sifive_u codes, but sifive_e codes were
> missed. Remove the riscv_ prefix of the machine* and soc* functions.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_e.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 472a989..8fab152 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -75,7 +75,7 @@ static const struct MemmapEntry {
> [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
> };
>
> -static void riscv_sifive_e_init(MachineState *machine)
> +static void sifive_e_machine_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
>
> @@ -124,7 +124,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> MachineClass *mc = MACHINE_CLASS(oc);
>
> mc->desc = "RISC-V Board compatible with SiFive E SDK";
> - mc->init = riscv_sifive_e_init;
> + mc->init = sifive_e_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = SIFIVE_E_CPU;
> }
> @@ -144,7 +144,7 @@ static void sifive_e_machine_init_register_types(void)
>
> type_init(sifive_e_machine_init_register_types)
>
> -static void riscv_sifive_e_soc_init(Object *obj)
> +static void sifive_e_soc_init(Object *obj)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> SiFiveESoCState *s = RISCV_E_SOC(obj);
> @@ -159,7 +159,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
> TYPE_SIFIVE_GPIO);
> }
>
> -static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> +static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> const struct MemmapEntry *memmap = sifive_e_memmap;
> @@ -243,26 +243,26 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> &s->xip_mem);
> }
>
> -static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
> +static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - dc->realize = riscv_sifive_e_soc_realize;
> + dc->realize = sifive_e_soc_realize;
> /* Reason: Uses serial_hds in realize function, thus can't be used twice */
> dc->user_creatable = false;
> }
>
> -static const TypeInfo riscv_sifive_e_soc_type_info = {
> +static const TypeInfo sifive_e_soc_type_info = {
> .name = TYPE_RISCV_E_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(SiFiveESoCState),
> - .instance_init = riscv_sifive_e_soc_init,
> - .class_init = riscv_sifive_e_soc_class_init,
> + .instance_init = sifive_e_soc_init,
> + .class_init = sifive_e_soc_class_init,
> };
>
> -static void riscv_sifive_e_soc_register_types(void)
> +static void sifive_e_soc_register_types(void)
> {
> - type_register_static(&riscv_sifive_e_soc_type_info);
> + type_register_static(&sifive_e_soc_type_info);
> }
>
> -type_init(riscv_sifive_e_soc_register_types)
> +type_init(sifive_e_soc_register_types)
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
@ 2020-06-15 16:05 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:05 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:20 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This was done in the virt & sifive_u codes, but sifive_e codes were
> missed. Remove the riscv_ prefix of the machine* and soc* functions.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_e.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 472a989..8fab152 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -75,7 +75,7 @@ static const struct MemmapEntry {
> [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 }
> };
>
> -static void riscv_sifive_e_init(MachineState *machine)
> +static void sifive_e_machine_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
>
> @@ -124,7 +124,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
> MachineClass *mc = MACHINE_CLASS(oc);
>
> mc->desc = "RISC-V Board compatible with SiFive E SDK";
> - mc->init = riscv_sifive_e_init;
> + mc->init = sifive_e_machine_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = SIFIVE_E_CPU;
> }
> @@ -144,7 +144,7 @@ static void sifive_e_machine_init_register_types(void)
>
> type_init(sifive_e_machine_init_register_types)
>
> -static void riscv_sifive_e_soc_init(Object *obj)
> +static void sifive_e_soc_init(Object *obj)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> SiFiveESoCState *s = RISCV_E_SOC(obj);
> @@ -159,7 +159,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
> TYPE_SIFIVE_GPIO);
> }
>
> -static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> +static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
> {
> MachineState *ms = MACHINE(qdev_get_machine());
> const struct MemmapEntry *memmap = sifive_e_memmap;
> @@ -243,26 +243,26 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> &s->xip_mem);
> }
>
> -static void riscv_sifive_e_soc_class_init(ObjectClass *oc, void *data)
> +static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - dc->realize = riscv_sifive_e_soc_realize;
> + dc->realize = sifive_e_soc_realize;
> /* Reason: Uses serial_hds in realize function, thus can't be used twice */
> dc->user_creatable = false;
> }
>
> -static const TypeInfo riscv_sifive_e_soc_type_info = {
> +static const TypeInfo sifive_e_soc_type_info = {
> .name = TYPE_RISCV_E_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(SiFiveESoCState),
> - .instance_init = riscv_sifive_e_soc_init,
> - .class_init = riscv_sifive_e_soc_class_init,
> + .instance_init = sifive_e_soc_init,
> + .class_init = sifive_e_soc_class_init,
> };
>
> -static void riscv_sifive_e_soc_register_types(void)
> +static void sifive_e_soc_register_types(void)
> {
> - type_register_static(&riscv_sifive_e_soc_type_info);
> + type_register_static(&sifive_e_soc_type_info);
> }
>
> -type_init(riscv_sifive_e_soc_register_types)
> +type_init(sifive_e_soc_register_types)
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
@ 2020-06-15 16:06 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:06 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This was done in the virt & sifive_u codes, but opentitan codes were
> missed. Remove the riscv_ prefix of the machine* and soc* functions.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/opentitan.c | 29 ++++++++++++++---------------
> 1 file changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index b4fb836..0907a42 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -51,7 +51,7 @@ static const struct MemmapEntry {
> [IBEX_PADCTRL] = { 0x40160000, 0x10000 }
> };
>
> -static void riscv_opentitan_init(MachineState *machine)
> +static void opentitan_board_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = ibex_memmap;
> OpenTitanState *s = g_new0(OpenTitanState, 1);
> @@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine)
> memory_region_add_subregion(sys_mem,
> memmap[IBEX_RAM].base, main_mem);
>
> -
> if (machine->firmware) {
> riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
> }
> @@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine)
> }
> }
>
> -static void riscv_opentitan_machine_init(MachineClass *mc)
> +static void opentitan_machine_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Board compatible with OpenTitan";
> - mc->init = riscv_opentitan_init;
> + mc->init = opentitan_board_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> }
>
> -DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
> +DEFINE_MACHINE("opentitan", opentitan_machine_init)
>
> -static void riscv_lowrisc_ibex_soc_init(Object *obj)
> +static void lowrisc_ibex_soc_init(Object *obj)
> {
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
>
> @@ -99,7 +98,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
> &error_abort, NULL);
> }
>
> -static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> +static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> const struct MemmapEntry *memmap = ibex_memmap;
> MachineState *ms = MACHINE(qdev_get_machine());
> @@ -159,26 +158,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
> }
>
> -static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> +static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - dc->realize = riscv_lowrisc_ibex_soc_realize;
> + dc->realize = lowrisc_ibex_soc_realize;
> /* Reason: Uses serial_hds in realize function, thus can't be used twice */
> dc->user_creatable = false;
> }
>
> -static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
> +static const TypeInfo lowrisc_ibex_soc_type_info = {
> .name = TYPE_RISCV_IBEX_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(LowRISCIbexSoCState),
> - .instance_init = riscv_lowrisc_ibex_soc_init,
> - .class_init = riscv_lowrisc_ibex_soc_class_init,
> + .instance_init = lowrisc_ibex_soc_init,
> + .class_init = lowrisc_ibex_soc_class_init,
> };
>
> -static void riscv_lowrisc_ibex_soc_register_types(void)
> +static void lowrisc_ibex_soc_register_types(void)
> {
> - type_register_static(&riscv_lowrisc_ibex_soc_type_info);
> + type_register_static(&lowrisc_ibex_soc_type_info);
> }
>
> -type_init(riscv_lowrisc_ibex_soc_register_types)
> +type_init(lowrisc_ibex_soc_register_types)
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
@ 2020-06-15 16:06 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:06 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This was done in the virt & sifive_u codes, but opentitan codes were
> missed. Remove the riscv_ prefix of the machine* and soc* functions.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/opentitan.c | 29 ++++++++++++++---------------
> 1 file changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index b4fb836..0907a42 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -51,7 +51,7 @@ static const struct MemmapEntry {
> [IBEX_PADCTRL] = { 0x40160000, 0x10000 }
> };
>
> -static void riscv_opentitan_init(MachineState *machine)
> +static void opentitan_board_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = ibex_memmap;
> OpenTitanState *s = g_new0(OpenTitanState, 1);
> @@ -70,7 +70,6 @@ static void riscv_opentitan_init(MachineState *machine)
> memory_region_add_subregion(sys_mem,
> memmap[IBEX_RAM].base, main_mem);
>
> -
> if (machine->firmware) {
> riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
> }
> @@ -80,17 +79,17 @@ static void riscv_opentitan_init(MachineState *machine)
> }
> }
>
> -static void riscv_opentitan_machine_init(MachineClass *mc)
> +static void opentitan_machine_init(MachineClass *mc)
> {
> mc->desc = "RISC-V Board compatible with OpenTitan";
> - mc->init = riscv_opentitan_init;
> + mc->init = opentitan_board_init;
> mc->max_cpus = 1;
> mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> }
>
> -DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
> +DEFINE_MACHINE("opentitan", opentitan_machine_init)
>
> -static void riscv_lowrisc_ibex_soc_init(Object *obj)
> +static void lowrisc_ibex_soc_init(Object *obj)
> {
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
>
> @@ -99,7 +98,7 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
> &error_abort, NULL);
> }
>
> -static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> +static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> const struct MemmapEntry *memmap = ibex_memmap;
> MachineState *ms = MACHINE(qdev_get_machine());
> @@ -159,26 +158,26 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
> }
>
> -static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> +static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> - dc->realize = riscv_lowrisc_ibex_soc_realize;
> + dc->realize = lowrisc_ibex_soc_realize;
> /* Reason: Uses serial_hds in realize function, thus can't be used twice */
> dc->user_creatable = false;
> }
>
> -static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
> +static const TypeInfo lowrisc_ibex_soc_type_info = {
> .name = TYPE_RISCV_IBEX_SOC,
> .parent = TYPE_DEVICE,
> .instance_size = sizeof(LowRISCIbexSoCState),
> - .instance_init = riscv_lowrisc_ibex_soc_init,
> - .class_init = riscv_lowrisc_ibex_soc_class_init,
> + .instance_init = lowrisc_ibex_soc_init,
> + .class_init = lowrisc_ibex_soc_class_init,
> };
>
> -static void riscv_lowrisc_ibex_soc_register_types(void)
> +static void lowrisc_ibex_soc_register_types(void)
> {
> - type_register_static(&riscv_lowrisc_ibex_soc_type_info);
> + type_register_static(&lowrisc_ibex_soc_type_info);
> }
>
> -type_init(riscv_lowrisc_ibex_soc_register_types)
> +type_init(lowrisc_ibex_soc_register_types)
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
@ 2020-06-15 16:07 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:07 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:19 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to retrieve all PLIC IRQ information in order to
> just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
> what is done for other peripherals.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f9fef2b..cf7f833 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -528,7 +528,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> - qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
> char *plic_hart_config;
> size_t plic_hart_config_len;
> int i;
> @@ -612,10 +611,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
>
> - for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
> - plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
> - }
> -
> if (nd->used) {
> qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
> qdev_set_nic_properties(DEVICE(&s->gem), nd);
> @@ -629,7 +624,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> }
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
> - plic_gpios[SIFIVE_U_GEM_IRQ]);
> + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
>
> create_unimplemented_device("riscv.sifive.u.gem-mgmt",
> memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
@ 2020-06-15 16:07 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:07 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:19 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> There is no need to retrieve all PLIC IRQ information in order to
> just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
> what is done for other peripherals.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f9fef2b..cf7f833 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -528,7 +528,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> - qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
> char *plic_hart_config;
> size_t plic_hart_config_len;
> int i;
> @@ -612,10 +611,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
>
> - for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
> - plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
> - }
> -
> if (nd->used) {
> qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
> qdev_set_nic_properties(DEVICE(&s->gem), nd);
> @@ -629,7 +624,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> }
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
> - plic_gpios[SIFIVE_U_GEM_IRQ]);
> + qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
>
> create_unimplemented_device("riscv.sifive.u.gem-mgmt",
> memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
@ 2020-06-15 16:08 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:08 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:21 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
> based on device tree information. Let's generate the device tree
> node for OTP.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index cf7f833..8dc6842 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -207,6 +207,17 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/otp@%lx",
> + (long)memmap[SIFIVE_U_OTP].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_OTP].base,
> + 0x0, memmap[SIFIVE_U_OTP].size);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible",
> + "sifive,fu540-c000-otp");
> + g_free(nodename);
> +
> prci_phandle = phandle++;
> nodename = g_strdup_printf("/soc/clock-controller@%lx",
> (long)memmap[SIFIVE_U_PRCI].base);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP
@ 2020-06-15 16:08 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:08 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:21 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
> based on device tree information. Let's generate the device tree
> node for OTP.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index cf7f833..8dc6842 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -207,6 +207,17 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/otp@%lx",
> + (long)memmap[SIFIVE_U_OTP].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_OTP].base,
> + 0x0, memmap[SIFIVE_U_OTP].size);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible",
> + "sifive,fu540-c000-otp");
> + g_free(nodename);
> +
> prci_phandle = phandle++;
> nodename = g_strdup_printf("/soc/clock-controller@%lx",
> (long)memmap[SIFIVE_U_PRCI].base);
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
@ 2020-06-15 16:13 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:13 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:22 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Do various minor clean-ups to the exisiting codes for:
>
> - coding convention conformance
> - remove unnecessary blank lines
> - spell SiFive correctly
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_gpio.c | 13 +++++--------
> include/hw/riscv/sifive_gpio.h | 7 ++++---
> 2 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index 5c7c596..c9cffa2 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -1,5 +1,5 @@
> /*
> - * sifive System-on-Chip general purpose input/output register definition
> + * SiFive System-on-Chip general purpose input/output register definition
> *
> * Copyright 2019 AdaCore
> *
> @@ -20,7 +20,6 @@
>
> static void update_output_irq(SIFIVEGPIOState *s)
> {
> -
> uint32_t pending;
> uint32_t pin;
>
> @@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
> }
>
> static void sifive_gpio_write(void *opaque, hwaddr offset,
> - uint64_t value, unsigned int size)
> + uint64_t value, unsigned int size)
> {
> SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
>
> @@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev)
> s->out_xor = 0;
> s->in = 0;
> s->in_mask = 0;
> -
> }
>
> static const VMStateDescription vmstate_sifive_gpio = {
> @@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio = {
> VMSTATE_UINT32(iof_en, SIFIVEGPIOState),
> VMSTATE_UINT32(iof_sel, SIFIVEGPIOState),
> VMSTATE_UINT32(out_xor, SIFIVEGPIOState),
> - VMSTATE_UINT32(in, SIFIVEGPIOState),
> - VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
> + VMSTATE_UINT32(in, SIFIVEGPIOState),
> + VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
> VMSTATE_END_OF_LIST()
> }
> };
> @@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj)
> TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
>
> -
> for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
> }
> @@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data)
>
> dc->vmsd = &vmstate_sifive_gpio;
> dc->reset = sifive_gpio_reset;
> - dc->desc = "sifive GPIO";
> + dc->desc = "SiFive GPIO";
> }
>
> static const TypeInfo sifive_gpio_info = {
> diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
> index fce03d6..ad915b2 100644
> --- a/include/hw/riscv/sifive_gpio.h
> +++ b/include/hw/riscv/sifive_gpio.h
> @@ -1,5 +1,5 @@
> /*
> - * sifive System-on-Chip general purpose input/output register definition
> + * SiFive System-on-Chip general purpose input/output register definition
> *
> * Copyright 2019 AdaCore
> *
> @@ -10,10 +10,12 @@
> * This code is licensed under the GPL version 2 or later. See
> * the COPYING file in the top-level directory.
> */
> +
> #ifndef SIFIVE_GPIO_H
> #define SIFIVE_GPIO_H
>
> #include "hw/sysbus.h"
> +
> #define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
> #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
>
> @@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState {
> uint32_t out_xor;
> uint32_t in;
> uint32_t in_mask;
> -
> } SIFIVEGPIOState;
>
> -#endif
> +#endif /* SIFIVE_GPIO_H */
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes
@ 2020-06-15 16:13 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:13 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:22 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Do various minor clean-ups to the exisiting codes for:
>
> - coding convention conformance
> - remove unnecessary blank lines
> - spell SiFive correctly
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_gpio.c | 13 +++++--------
> include/hw/riscv/sifive_gpio.h | 7 ++++---
> 2 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index 5c7c596..c9cffa2 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -1,5 +1,5 @@
> /*
> - * sifive System-on-Chip general purpose input/output register definition
> + * SiFive System-on-Chip general purpose input/output register definition
> *
> * Copyright 2019 AdaCore
> *
> @@ -20,7 +20,6 @@
>
> static void update_output_irq(SIFIVEGPIOState *s)
> {
> -
> uint32_t pending;
> uint32_t pin;
>
> @@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
> }
>
> static void sifive_gpio_write(void *opaque, hwaddr offset,
> - uint64_t value, unsigned int size)
> + uint64_t value, unsigned int size)
> {
> SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
>
> @@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev)
> s->out_xor = 0;
> s->in = 0;
> s->in_mask = 0;
> -
> }
>
> static const VMStateDescription vmstate_sifive_gpio = {
> @@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio = {
> VMSTATE_UINT32(iof_en, SIFIVEGPIOState),
> VMSTATE_UINT32(iof_sel, SIFIVEGPIOState),
> VMSTATE_UINT32(out_xor, SIFIVEGPIOState),
> - VMSTATE_UINT32(in, SIFIVEGPIOState),
> - VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
> + VMSTATE_UINT32(in, SIFIVEGPIOState),
> + VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
> VMSTATE_END_OF_LIST()
> }
> };
> @@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj)
> TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
> sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
>
> -
> for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
> sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
> }
> @@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data)
>
> dc->vmsd = &vmstate_sifive_gpio;
> dc->reset = sifive_gpio_reset;
> - dc->desc = "sifive GPIO";
> + dc->desc = "SiFive GPIO";
> }
>
> static const TypeInfo sifive_gpio_info = {
> diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
> index fce03d6..ad915b2 100644
> --- a/include/hw/riscv/sifive_gpio.h
> +++ b/include/hw/riscv/sifive_gpio.h
> @@ -1,5 +1,5 @@
> /*
> - * sifive System-on-Chip general purpose input/output register definition
> + * SiFive System-on-Chip general purpose input/output register definition
> *
> * Copyright 2019 AdaCore
> *
> @@ -10,10 +10,12 @@
> * This code is licensed under the GPL version 2 or later. See
> * the COPYING file in the top-level directory.
> */
> +
> #ifndef SIFIVE_GPIO_H
> #define SIFIVE_GPIO_H
>
> #include "hw/sysbus.h"
> +
> #define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
> #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
>
> @@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState {
> uint32_t out_xor;
> uint32_t in;
> uint32_t in_mask;
> -
> } SIFIVEGPIOState;
>
> -#endif
> +#endif /* SIFIVE_GPIO_H */
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
@ 2020-06-15 16:16 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:16 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:22 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Add a new property to represent the number of GPIO pins supported
> by the GPIO controller.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_gpio.c | 30 +++++++++++++++++++-----------
> include/hw/riscv/sifive_gpio.h | 3 +++
> 2 files changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index c9cffa2..0d0fd2b 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -14,6 +14,7 @@
> #include "qemu/osdep.h"
> #include "qemu/log.h"
> #include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> #include "hw/riscv/sifive_gpio.h"
> #include "migration/vmstate.h"
> #include "trace.h"
> @@ -28,7 +29,7 @@ static void update_output_irq(SIFIVEGPIOState *s)
> pending |= s->rise_ip & s->rise_ie;
> pending |= s->fall_ip & s->fall_ie;
>
> - for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
> + for (int i = 0; i < s->ngpio; i++) {
> pin = 1 << i;
> qemu_set_irq(s->irq[i], (pending & pin) != 0);
> trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);
> @@ -41,7 +42,7 @@ static void update_state(SIFIVEGPIOState *s)
> bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,
> rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;
>
> - for (i = 0; i < SIFIVE_GPIO_PINS; i++) {
> + for (i = 0; i < s->ngpio; i++) {
>
> prev_ival = extract32(s->value, i, 1);
> in = extract32(s->in, i, 1);
> @@ -346,27 +347,35 @@ static const VMStateDescription vmstate_sifive_gpio = {
> }
> };
>
> -static void sifive_gpio_init(Object *obj)
> +static Property sifive_gpio_properties[] = {
> + DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void sifive_gpio_realize(DeviceState *dev, Error **errp)
> {
> - SIFIVEGPIOState *s = SIFIVE_GPIO(obj);
> + SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
>
> - memory_region_init_io(&s->mmio, obj, &gpio_ops, s,
> + memory_region_init_io(&s->mmio, OBJECT(dev), &gpio_ops, s,
> TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
> - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
>
> - for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
> - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
> +
> + for (int i = 0; i < s->ngpio; i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
> }
>
> - qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS);
> - qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS);
> + qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio);
> + qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio);
> }
>
> static void sifive_gpio_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> + device_class_set_props(dc, sifive_gpio_properties);
> dc->vmsd = &vmstate_sifive_gpio;
> + dc->realize = sifive_gpio_realize;
> dc->reset = sifive_gpio_reset;
> dc->desc = "SiFive GPIO";
> }
> @@ -375,7 +384,6 @@ static const TypeInfo sifive_gpio_info = {
> .name = TYPE_SIFIVE_GPIO,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(SIFIVEGPIOState),
> - .instance_init = sifive_gpio_init,
> .class_init = sifive_gpio_class_init
> };
>
> diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
> index ad915b2..cf12fcf 100644
> --- a/include/hw/riscv/sifive_gpio.h
> +++ b/include/hw/riscv/sifive_gpio.h
> @@ -68,6 +68,9 @@ typedef struct SIFIVEGPIOState {
> uint32_t out_xor;
> uint32_t in;
> uint32_t in_mask;
> +
> + /* config */
> + uint32_t ngpio;
> } SIFIVEGPIOState;
>
> #endif /* SIFIVE_GPIO_H */
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property
@ 2020-06-15 16:16 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:16 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:22 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Add a new property to represent the number of GPIO pins supported
> by the GPIO controller.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_gpio.c | 30 +++++++++++++++++++-----------
> include/hw/riscv/sifive_gpio.h | 3 +++
> 2 files changed, 22 insertions(+), 11 deletions(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index c9cffa2..0d0fd2b 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -14,6 +14,7 @@
> #include "qemu/osdep.h"
> #include "qemu/log.h"
> #include "hw/irq.h"
> +#include "hw/qdev-properties.h"
> #include "hw/riscv/sifive_gpio.h"
> #include "migration/vmstate.h"
> #include "trace.h"
> @@ -28,7 +29,7 @@ static void update_output_irq(SIFIVEGPIOState *s)
> pending |= s->rise_ip & s->rise_ie;
> pending |= s->fall_ip & s->fall_ie;
>
> - for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
> + for (int i = 0; i < s->ngpio; i++) {
> pin = 1 << i;
> qemu_set_irq(s->irq[i], (pending & pin) != 0);
> trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);
> @@ -41,7 +42,7 @@ static void update_state(SIFIVEGPIOState *s)
> bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,
> rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;
>
> - for (i = 0; i < SIFIVE_GPIO_PINS; i++) {
> + for (i = 0; i < s->ngpio; i++) {
>
> prev_ival = extract32(s->value, i, 1);
> in = extract32(s->in, i, 1);
> @@ -346,27 +347,35 @@ static const VMStateDescription vmstate_sifive_gpio = {
> }
> };
>
> -static void sifive_gpio_init(Object *obj)
> +static Property sifive_gpio_properties[] = {
> + DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void sifive_gpio_realize(DeviceState *dev, Error **errp)
> {
> - SIFIVEGPIOState *s = SIFIVE_GPIO(obj);
> + SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
>
> - memory_region_init_io(&s->mmio, obj, &gpio_ops, s,
> + memory_region_init_io(&s->mmio, OBJECT(dev), &gpio_ops, s,
> TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
> - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
>
> - for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
> - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
> +
> + for (int i = 0; i < s->ngpio; i++) {
> + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
> }
>
> - qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS);
> - qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS);
> + qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio);
> + qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio);
> }
>
> static void sifive_gpio_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> + device_class_set_props(dc, sifive_gpio_properties);
> dc->vmsd = &vmstate_sifive_gpio;
> + dc->realize = sifive_gpio_realize;
> dc->reset = sifive_gpio_reset;
> dc->desc = "SiFive GPIO";
> }
> @@ -375,7 +384,6 @@ static const TypeInfo sifive_gpio_info = {
> .name = TYPE_SIFIVE_GPIO,
> .parent = TYPE_SYS_BUS_DEVICE,
> .instance_size = sizeof(SIFIVEGPIOState),
> - .instance_init = sifive_gpio_init,
> .class_init = sifive_gpio_class_init
> };
>
> diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
> index ad915b2..cf12fcf 100644
> --- a/include/hw/riscv/sifive_gpio.h
> +++ b/include/hw/riscv/sifive_gpio.h
> @@ -68,6 +68,9 @@ typedef struct SIFIVEGPIOState {
> uint32_t out_xor;
> uint32_t in;
> uint32_t in_mask;
> +
> + /* config */
> + uint32_t ngpio;
> } SIFIVEGPIOState;
>
> #endif /* SIFIVE_GPIO_H */
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
@ 2020-06-15 16:26 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:26 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:24 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines.
> This hooks the exsiting SiFive GPIO model to the SoC, and adds its
> device tree data as well.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
> include/hw/riscv/sifive_u.h | 19 +++++++++++++++++++
> 2 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 8dc6842..881949b 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -11,8 +11,9 @@
> * 1) CLINT (Core Level Interruptor)
> * 2) PLIC (Platform Level Interrupt Controller)
> * 3) PRCI (Power, Reset, Clock, Interrupt)
> - * 4) OTP (One-Time Programmable) memory with stored serial number
> - * 5) GEM (Gigabit Ethernet Controller) and management block
> + * 4) GPIO (General Purpose Input/Output Controller)
> + * 5) OTP (One-Time Programmable) memory with stored serial number
> + * 6) GEM (Gigabit Ethernet Controller) and management block
> *
> * This board currently generates devicetree dynamically that indicates at least
> * two harts and up to five harts.
> @@ -75,6 +76,7 @@ static const struct MemmapEntry {
> [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
> [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
> [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> + [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> @@ -268,6 +270,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/gpio@%lx",
> + (long)memmap[SIFIVE_U_GPIO].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
> + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
> + qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
> + qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_GPIO].base,
> + 0x0, memmap[SIFIVE_U_GPIO].size);
> + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
> + SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
> + SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
> + SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
> + SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
> + SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
> + g_free(nodename);
> +
> phy_phandle = phandle++;
> nodename = g_strdup_printf("/soc/ethernet@%lx",
> (long)memmap[SIFIVE_U_GEM].base);
> @@ -525,6 +549,8 @@ static void sifive_u_soc_instance_init(Object *obj)
>
> sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
> TYPE_SIFIVE_U_PRCI);
> + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
> + TYPE_SIFIVE_GPIO);
> sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
> TYPE_SIFIVE_U_OTP);
> sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
> @@ -618,6 +644,20 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
>
> + qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
> + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
> +
> + /* Pass all GPIOs to the SOC layer so they are available to the board */
> + qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
> +
> + /* Connect GPIO interrupts to the PLIC */
> + for (i = 0; i < 16; i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
> + qdev_get_gpio_in(DEVICE(s->plic),
> + SIFIVE_U_GPIO_IRQ0 + i));
> + }
> +
> qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
> object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 16c297e..dcf7f3b 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -22,6 +22,7 @@
> #include "hw/net/cadence_gem.h"
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_cpu.h"
> +#include "hw/riscv/sifive_gpio.h"
> #include "hw/riscv/sifive_u_prci.h"
> #include "hw/riscv/sifive_u_otp.h"
>
> @@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState {
> RISCVHartArrayState u_cpus;
> DeviceState *plic;
> SiFiveUPRCIState prci;
> + SIFIVEGPIOState gpio;
> SiFiveUOTPState otp;
> CadenceGEMState gem;
>
> @@ -73,6 +75,7 @@ enum {
> SIFIVE_U_PRCI,
> SIFIVE_U_UART0,
> SIFIVE_U_UART1,
> + SIFIVE_U_GPIO,
> SIFIVE_U_OTP,
> SIFIVE_U_FLASH0,
> SIFIVE_U_DRAM,
> @@ -83,6 +86,22 @@ enum {
> enum {
> SIFIVE_U_UART0_IRQ = 4,
> SIFIVE_U_UART1_IRQ = 5,
> + SIFIVE_U_GPIO_IRQ0 = 7,
> + SIFIVE_U_GPIO_IRQ1 = 8,
> + SIFIVE_U_GPIO_IRQ2 = 9,
> + SIFIVE_U_GPIO_IRQ3 = 10,
> + SIFIVE_U_GPIO_IRQ4 = 11,
> + SIFIVE_U_GPIO_IRQ5 = 12,
> + SIFIVE_U_GPIO_IRQ6 = 13,
> + SIFIVE_U_GPIO_IRQ7 = 14,
> + SIFIVE_U_GPIO_IRQ8 = 15,
> + SIFIVE_U_GPIO_IRQ9 = 16,
> + SIFIVE_U_GPIO_IRQ10 = 17,
> + SIFIVE_U_GPIO_IRQ11 = 18,
> + SIFIVE_U_GPIO_IRQ12 = 19,
> + SIFIVE_U_GPIO_IRQ13 = 20,
> + SIFIVE_U_GPIO_IRQ14 = 21,
> + SIFIVE_U_GPIO_IRQ15 = 22,
> SIFIVE_U_GEM_IRQ = 0x35
> };
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller
@ 2020-06-15 16:26 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:26 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:24 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines.
> This hooks the exsiting SiFive GPIO model to the SoC, and adds its
> device tree data as well.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++++++++++++++++++--
> include/hw/riscv/sifive_u.h | 19 +++++++++++++++++++
> 2 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 8dc6842..881949b 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -11,8 +11,9 @@
> * 1) CLINT (Core Level Interruptor)
> * 2) PLIC (Platform Level Interrupt Controller)
> * 3) PRCI (Power, Reset, Clock, Interrupt)
> - * 4) OTP (One-Time Programmable) memory with stored serial number
> - * 5) GEM (Gigabit Ethernet Controller) and management block
> + * 4) GPIO (General Purpose Input/Output Controller)
> + * 5) OTP (One-Time Programmable) memory with stored serial number
> + * 6) GEM (Gigabit Ethernet Controller) and management block
> *
> * This board currently generates devicetree dynamically that indicates at least
> * two harts and up to five harts.
> @@ -75,6 +76,7 @@ static const struct MemmapEntry {
> [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
> [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
> [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> + [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> @@ -268,6 +270,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> + nodename = g_strdup_printf("/soc/gpio@%lx",
> + (long)memmap[SIFIVE_U_GPIO].base);
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> + prci_phandle, PRCI_CLK_TLCLK);
> + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
> + qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
> + qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
> + qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
> + qemu_fdt_setprop_cells(fdt, nodename, "reg",
> + 0x0, memmap[SIFIVE_U_GPIO].base,
> + 0x0, memmap[SIFIVE_U_GPIO].size);
> + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
> + SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
> + SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
> + SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
> + SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
> + SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
> + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
> + g_free(nodename);
> +
> phy_phandle = phandle++;
> nodename = g_strdup_printf("/soc/ethernet@%lx",
> (long)memmap[SIFIVE_U_GEM].base);
> @@ -525,6 +549,8 @@ static void sifive_u_soc_instance_init(Object *obj)
>
> sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci),
> TYPE_SIFIVE_U_PRCI);
> + sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
> + TYPE_SIFIVE_GPIO);
> sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
> TYPE_SIFIVE_U_OTP);
> sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
> @@ -618,6 +644,20 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
> object_property_set_bool(OBJECT(&s->prci), true, "realized", &err);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
>
> + qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
> + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
> +
> + /* Pass all GPIOs to the SOC layer so they are available to the board */
> + qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
> +
> + /* Connect GPIO interrupts to the PLIC */
> + for (i = 0; i < 16; i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
> + qdev_get_gpio_in(DEVICE(s->plic),
> + SIFIVE_U_GPIO_IRQ0 + i));
> + }
> +
> qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
> object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 16c297e..dcf7f3b 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -22,6 +22,7 @@
> #include "hw/net/cadence_gem.h"
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_cpu.h"
> +#include "hw/riscv/sifive_gpio.h"
> #include "hw/riscv/sifive_u_prci.h"
> #include "hw/riscv/sifive_u_otp.h"
>
> @@ -40,6 +41,7 @@ typedef struct SiFiveUSoCState {
> RISCVHartArrayState u_cpus;
> DeviceState *plic;
> SiFiveUPRCIState prci;
> + SIFIVEGPIOState gpio;
> SiFiveUOTPState otp;
> CadenceGEMState gem;
>
> @@ -73,6 +75,7 @@ enum {
> SIFIVE_U_PRCI,
> SIFIVE_U_UART0,
> SIFIVE_U_UART1,
> + SIFIVE_U_GPIO,
> SIFIVE_U_OTP,
> SIFIVE_U_FLASH0,
> SIFIVE_U_DRAM,
> @@ -83,6 +86,22 @@ enum {
> enum {
> SIFIVE_U_UART0_IRQ = 4,
> SIFIVE_U_UART1_IRQ = 5,
> + SIFIVE_U_GPIO_IRQ0 = 7,
> + SIFIVE_U_GPIO_IRQ1 = 8,
> + SIFIVE_U_GPIO_IRQ2 = 9,
> + SIFIVE_U_GPIO_IRQ3 = 10,
> + SIFIVE_U_GPIO_IRQ4 = 11,
> + SIFIVE_U_GPIO_IRQ5 = 12,
> + SIFIVE_U_GPIO_IRQ6 = 13,
> + SIFIVE_U_GPIO_IRQ7 = 14,
> + SIFIVE_U_GPIO_IRQ8 = 15,
> + SIFIVE_U_GPIO_IRQ9 = 16,
> + SIFIVE_U_GPIO_IRQ10 = 17,
> + SIFIVE_U_GPIO_IRQ11 = 18,
> + SIFIVE_U_GPIO_IRQ12 = 19,
> + SIFIVE_U_GPIO_IRQ13 = 20,
> + SIFIVE_U_GPIO_IRQ14 = 21,
> + SIFIVE_U_GPIO_IRQ15 = 22,
> SIFIVE_U_GEM_IRQ = 0x35
> };
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
@ 2020-06-15 16:28 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:28 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:24 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the GPIO output IRQs are triggered each time any GPIO
> register is written. However this is not correct. We should only
> trigger the output IRQ when the pin is configured as output enable.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_gpio.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index 0d0fd2b..aac6b44 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s)
> actual_value = pull;
> }
>
> - qemu_set_irq(s->output[i], actual_value);
> + if (output_en) {
> + qemu_set_irq(s->output[i], actual_value);
> + }
>
> /* Input value */
> ival = input_en && actual_value;
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
@ 2020-06-15 16:28 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:28 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:24 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the GPIO output IRQs are triggered each time any GPIO
> register is written. However this is not correct. We should only
> trigger the output IRQ when the pin is configured as output enable.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_gpio.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
> index 0d0fd2b..aac6b44 100644
> --- a/hw/riscv/sifive_gpio.c
> +++ b/hw/riscv/sifive_gpio.c
> @@ -76,7 +76,9 @@ static void update_state(SIFIVEGPIOState *s)
> actual_value = pull;
> }
>
> - qemu_set_irq(s->output[i], actual_value);
> + if (output_en) {
> + qemu_set_irq(s->output[i], actual_value);
> + }
>
> /* Input value */
> ival = input_en && actual_value;
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
@ 2020-06-15 16:35 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:35 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:23 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The HiFive Unleashed board wires GPIO pin#10 to the input of the
> system reset signal. Let's set up the GPIO pin#10 and insert a
> "gpio-restart" device tree node so that reboot is now functional
> with QEMU 'sifive_u' machine.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 881949b..ef51874 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -37,6 +37,7 @@
> #include "qapi/error.h"
> #include "qapi/visitor.h"
> #include "hw/boards.h"
> +#include "hw/irq.h"
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> #include "hw/char/serial.h"
> @@ -53,6 +54,7 @@
> #include "net/eth.h"
> #include "sysemu/arch_init.h"
> #include "sysemu/device_tree.h"
> +#include "sysemu/runstate.h"
> #include "sysemu/sysemu.h"
> #include "exec/address-spaces.h"
>
> @@ -96,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> uint32_t *cells;
> char *nodename;
> char ethclk_names[] = "pclk\0hclk";
> - uint32_t plic_phandle, prci_phandle, phandle = 1;
> + uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
> uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
>
> fdt = s->fdt = create_device_tree(&s->fdt_size);
> @@ -270,9 +272,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> + gpio_phandle = phandle++;
> nodename = g_strdup_printf("/soc/gpio@%lx",
> (long)memmap[SIFIVE_U_GPIO].base);
> qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> prci_phandle, PRCI_CLK_TLCLK);
> qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
> @@ -292,6 +296,12 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
> g_free(nodename);
>
> + nodename = g_strdup_printf("/gpio-restart");
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
> + g_free(nodename);
> +
> phy_phandle = phandle++;
> nodename = g_strdup_printf("/soc/ethernet@%lx",
> (long)memmap[SIFIVE_U_GEM].base);
> @@ -352,6 +362,14 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
> }
>
> +static void sifive_u_machine_reset(void *opaque, int n, int level)
> +{
> + /* gpio pin active low triggers reset */
> + if (!level) {
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + }
> +}
> +
> static void sifive_u_machine_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_u_memmap;
> @@ -383,6 +401,10 @@ static void sifive_u_machine_init(MachineState *machine)
> memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
> flash0);
>
> + /* register gpio-restart */
> + qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
> + qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
> +
> /* create device tree */
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality
@ 2020-06-15 16:35 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:35 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:23 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The HiFive Unleashed board wires GPIO pin#10 to the input of the
> system reset signal. Let's set up the GPIO pin#10 and insert a
> "gpio-restart" device tree node so that reboot is now functional
> with QEMU 'sifive_u' machine.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 24 +++++++++++++++++++++++-
> 1 file changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 881949b..ef51874 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -37,6 +37,7 @@
> #include "qapi/error.h"
> #include "qapi/visitor.h"
> #include "hw/boards.h"
> +#include "hw/irq.h"
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> #include "hw/char/serial.h"
> @@ -53,6 +54,7 @@
> #include "net/eth.h"
> #include "sysemu/arch_init.h"
> #include "sysemu/device_tree.h"
> +#include "sysemu/runstate.h"
> #include "sysemu/sysemu.h"
> #include "exec/address-spaces.h"
>
> @@ -96,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> uint32_t *cells;
> char *nodename;
> char ethclk_names[] = "pclk\0hclk";
> - uint32_t plic_phandle, prci_phandle, phandle = 1;
> + uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
> uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
>
> fdt = s->fdt = create_device_tree(&s->fdt_size);
> @@ -270,9 +272,11 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(cells);
> g_free(nodename);
>
> + gpio_phandle = phandle++;
> nodename = g_strdup_printf("/soc/gpio@%lx",
> (long)memmap[SIFIVE_U_GPIO].base);
> qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
> qemu_fdt_setprop_cells(fdt, nodename, "clocks",
> prci_phandle, PRCI_CLK_TLCLK);
> qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
> @@ -292,6 +296,12 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
> g_free(nodename);
>
> + nodename = g_strdup_printf("/gpio-restart");
> + qemu_fdt_add_subnode(fdt, nodename);
> + qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
> + qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
> + g_free(nodename);
> +
> phy_phandle = phandle++;
> nodename = g_strdup_printf("/soc/ethernet@%lx",
> (long)memmap[SIFIVE_U_GEM].base);
> @@ -352,6 +362,14 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
> g_free(nodename);
> }
>
> +static void sifive_u_machine_reset(void *opaque, int n, int level)
> +{
> + /* gpio pin active low triggers reset */
> + if (!level) {
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + }
> +}
> +
> static void sifive_u_machine_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_u_memmap;
> @@ -383,6 +401,10 @@ static void sifive_u_machine_init(MachineState *machine)
> memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
> flash0);
>
> + /* register gpio-restart */
> + qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
> + qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
> +
> /* create device tree */
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
@ 2020-06-15 16:39 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:39 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:21 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> In prepration to add more properties to this machine, rename the
> existing serial property get/set functions to a generic name.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index ef51874..07e2ba0 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -481,14 +481,16 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
> s->start_in_flash = value;
> }
>
> -static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> +static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
> + const char *name, void *opaque,
> + Error **errp)
> {
> visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> }
>
> -static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> +static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
> + const char *name, void *opaque,
> + Error **errp)
> {
> visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> }
> @@ -507,8 +509,8 @@ static void sifive_u_machine_instance_init(Object *obj)
>
> s->serial = OTP_SERIAL;
> object_property_add(obj, "serial", "uint32",
> - sifive_u_machine_get_serial,
> - sifive_u_machine_set_serial, NULL, &s->serial);
> + sifive_u_machine_get_uint32_prop,
> + sifive_u_machine_set_uint32_prop, NULL, &s->serial);
> object_property_set_description(obj, "serial", "Board serial number");
> }
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
@ 2020-06-15 16:39 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:39 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:21 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> In prepration to add more properties to this machine, rename the
> existing serial property get/set functions to a generic name.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index ef51874..07e2ba0 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -481,14 +481,16 @@ static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error *
> s->start_in_flash = value;
> }
>
> -static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> +static void sifive_u_machine_get_uint32_prop(Object *obj, Visitor *v,
> + const char *name, void *opaque,
> + Error **errp)
> {
> visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> }
>
> -static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const char *name,
> - void *opaque, Error **errp)
> +static void sifive_u_machine_set_uint32_prop(Object *obj, Visitor *v,
> + const char *name, void *opaque,
> + Error **errp)
> {
> visit_type_uint32(v, name, (uint32_t *)opaque, errp);
> }
> @@ -507,8 +509,8 @@ static void sifive_u_machine_instance_init(Object *obj)
>
> s->serial = OTP_SERIAL;
> object_property_add(obj, "serial", "uint32",
> - sifive_u_machine_get_serial,
> - sifive_u_machine_set_serial, NULL, &s->serial);
> + sifive_u_machine_get_uint32_prop,
> + sifive_u_machine_set_uint32_prop, NULL, &s->serial);
> object_property_set_description(obj, "serial", "Board serial number");
> }
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
@ 2020-06-15 16:41 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:41 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:27 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> On SiFive FU540 SoC, the value stored at physical address 0x1000
> stores the MSEL pin state that is used to control the next boot
> location that ROM codes jump to.
>
> Add a new property msel to sifive_u machine for this.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 7 +++++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 07e2ba0..aaa5adb 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -507,6 +507,13 @@ static void sifive_u_machine_instance_init(Object *obj)
> "Set on to tell QEMU's ROM to jump to "
> "flash. Otherwise QEMU will jump to DRAM");
>
> + s->msel = 0;
> + object_property_add(obj, "msel", "uint32",
> + sifive_u_machine_get_uint32_prop,
> + sifive_u_machine_set_uint32_prop, NULL, &s->msel);
> + object_property_set_description(obj, "msel",
> + "Mode Select (MSEL[3:0]) pin state");
> +
> s->serial = OTP_SERIAL;
> object_property_add(obj, "serial", "uint32",
> sifive_u_machine_get_uint32_prop,
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index dcf7f3b..d82cfe0 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -63,6 +63,7 @@ typedef struct SiFiveUState {
> int fdt_size;
>
> bool start_in_flash;
> + uint32_t msel;
> uint32_t serial;
> } SiFiveUState;
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
@ 2020-06-15 16:41 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 16:41 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:27 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> On SiFive FU540 SoC, the value stored at physical address 0x1000
> stores the MSEL pin state that is used to control the next boot
> location that ROM codes jump to.
>
> Add a new property msel to sifive_u machine for this.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 7 +++++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 07e2ba0..aaa5adb 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -507,6 +507,13 @@ static void sifive_u_machine_instance_init(Object *obj)
> "Set on to tell QEMU's ROM to jump to "
> "flash. Otherwise QEMU will jump to DRAM");
>
> + s->msel = 0;
> + object_property_add(obj, "msel", "uint32",
> + sifive_u_machine_get_uint32_prop,
> + sifive_u_machine_set_uint32_prop, NULL, &s->msel);
> + object_property_set_description(obj, "msel",
> + "Mode Select (MSEL[3:0]) pin state");
> +
> s->serial = OTP_SERIAL;
> object_property_add(obj, "serial", "uint32",
> sifive_u_machine_get_uint32_prop,
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index dcf7f3b..d82cfe0 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -63,6 +63,7 @@ typedef struct SiFiveUState {
> int fdt_size;
>
> bool start_in_flash;
> + uint32_t msel;
> uint32_t serial;
> } SiFiveUState;
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
@ 2020-06-15 19:02 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:02 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:27 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Per the SiFive manual, all E/U series CPU cores' reset vector is
> at 0x1004. Update our codes to match the hardware.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/sifive_e.c | 8 +++++---
> hw/riscv/sifive_u.c | 6 +++---
> target/riscv/cpu.c | 4 ++--
> 3 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 8fab152..f05cabd 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -98,9 +98,11 @@ static void sifive_e_machine_init(MachineState *machine)
> memmap[SIFIVE_E_DTIM].base, main_mem);
>
> /* Mask ROM reset vector */
> - uint32_t reset_vec[2] = {
> - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> - 0x00028067, /* 0x1004: jr t0 */
> + uint32_t reset_vec[4] = {
> + 0x00000000,
> + 0x204002b7, /* 0x1004: lui t0,0x20400 */
> + 0x00028067, /* 0x1008: jr t0 */
> + 0x00000000,
> };
>
> /* copy in the reset vector in little_endian byte order */
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index aaa5adb..0a86ffc 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -433,18 +433,18 @@ static void sifive_u_machine_init(MachineState *machine)
>
> /* reset vector */
> uint32_t reset_vec[8] = {
> + 0x00000000,
> 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
> - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
> + 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
> 0xf1402573, /* csrr a0, mhartid */
> #if defined(TARGET_RISCV32)
> 0x0182a283, /* lw t0, 24(t0) */
> #elif defined(TARGET_RISCV64)
> - 0x0182b283, /* ld t0, 24(t0) */
> + 0x0182e283, /* lwu t0, 24(t0) */
> #endif
> 0x00028067, /* jr t0 */
> 0x00000000,
> start_addr, /* start: .dword */
> - 0x00000000,
> /* dtb: */
> };
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5060534..1944ad6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -139,7 +139,7 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> + set_resetvec(env, 0x1004);
> }
>
> static void rvnn_imacu_nommu_cpu_init(Object *obj)
> @@ -147,7 +147,7 @@ static void rvnn_imacu_nommu_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> + set_resetvec(env, 0x1004);
I know the Ibex CPU does the same thing, but I'm a little worried about this.
At this rate we will have multiple generic (rvx_im*_cpu_init()) CPUs
that don't have generic reset vectors. It might be best to rename the
functions to match the actual CPUs in this case.
Alistair
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
@ 2020-06-15 19:02 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:02 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:27 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Per the SiFive manual, all E/U series CPU cores' reset vector is
> at 0x1004. Update our codes to match the hardware.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/sifive_e.c | 8 +++++---
> hw/riscv/sifive_u.c | 6 +++---
> target/riscv/cpu.c | 4 ++--
> 3 files changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 8fab152..f05cabd 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -98,9 +98,11 @@ static void sifive_e_machine_init(MachineState *machine)
> memmap[SIFIVE_E_DTIM].base, main_mem);
>
> /* Mask ROM reset vector */
> - uint32_t reset_vec[2] = {
> - 0x204002b7, /* 0x1000: lui t0,0x20400 */
> - 0x00028067, /* 0x1004: jr t0 */
> + uint32_t reset_vec[4] = {
> + 0x00000000,
> + 0x204002b7, /* 0x1004: lui t0,0x20400 */
> + 0x00028067, /* 0x1008: jr t0 */
> + 0x00000000,
> };
>
> /* copy in the reset vector in little_endian byte order */
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index aaa5adb..0a86ffc 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -433,18 +433,18 @@ static void sifive_u_machine_init(MachineState *machine)
>
> /* reset vector */
> uint32_t reset_vec[8] = {
> + 0x00000000,
> 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
> - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
> + 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
> 0xf1402573, /* csrr a0, mhartid */
> #if defined(TARGET_RISCV32)
> 0x0182a283, /* lw t0, 24(t0) */
> #elif defined(TARGET_RISCV64)
> - 0x0182b283, /* ld t0, 24(t0) */
> + 0x0182e283, /* lwu t0, 24(t0) */
> #endif
> 0x00028067, /* jr t0 */
> 0x00000000,
> start_addr, /* start: .dword */
> - 0x00000000,
> /* dtb: */
> };
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5060534..1944ad6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -139,7 +139,7 @@ static void rvnn_gcsu_priv1_10_0_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> + set_resetvec(env, 0x1004);
> }
>
> static void rvnn_imacu_nommu_cpu_init(Object *obj)
> @@ -147,7 +147,7 @@ static void rvnn_imacu_nommu_cpu_init(Object *obj)
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> + set_resetvec(env, 0x1004);
I know the Ibex CPU does the same thing, but I'm a little worried about this.
At this rate we will have multiple generic (rvx_im*_cpu_init()) CPUs
that don't have generic reset vectors. It might be best to rename the
functions to match the actual CPUs in this case.
Alistair
> qdev_prop_set_bit(DEVICE(obj), "mmu", false);
> }
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
@ 2020-06-15 19:04 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:04 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:28 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> SiFive FU540 SoC supports booting from several sources, which are
> controlled using the Mode Select (MSEL[3:0]) pins on the chip.
> Typically, the boot process runs through several stages before it
> begins execution of user-provided programs.
>
> The SoC supports booting from memory-mapped QSPI flash, which is
> how start_in_flash property is used for at present. This matches
> MSEL = 1 configuration (QSPI0).
>
> Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL).
> It's not necessary for QEMU to implement the full ZSBL ROM codes,
> because we know ZSBL downloads the next stage program into the L2
> LIM at address 0x8000000 and executes from there. We can bypass
> the whole ZSBL execution and use "-bios" to load the next stage
> program directly if MSEL indicates a ZSBL booting flow.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 39 +++++++++++++++++++++++++++++++--------
> include/hw/riscv/sifive_u.h | 6 ++++++
> 2 files changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0a86ffc..f64aa52 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -408,8 +408,34 @@ static void sifive_u_machine_init(MachineState *machine)
> /* create device tree */
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> - riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> - memmap[SIFIVE_U_DRAM].base, NULL);
> + if (s->start_in_flash) {
> + /*
> + * If start_in_flash property is given, assign s->msel to a value
> + * that representing booting from QSPI0 memory-mapped flash.
> + *
> + * This also means that when both start_in_flash and msel properties
> + * are given, start_in_flash takes the precedence over msel.
> + *
> + * Note this is to keep backward compatibility not to break existing
> + * users that use start_in_flash property.
> + */
> + s->msel = MSEL_MEMMAP_QSPI0_FLASH;
> + }
> +
> + switch (s->msel) {
> + case MSEL_MEMMAP_QSPI0_FLASH:
> + start_addr = memmap[SIFIVE_U_FLASH0].base;
> + break;
> + case MSEL_L2LIM_QSPI0_FLASH:
> + case MSEL_L2LIM_QSPI2_SD:
> + start_addr = memmap[SIFIVE_U_L2LIM].base;
> + break;
> + default:
> + start_addr = memmap[SIFIVE_U_DRAM].base;
> + break;
> + }
> +
> + riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> @@ -427,13 +453,9 @@ static void sifive_u_machine_init(MachineState *machine)
> }
> }
>
> - if (s->start_in_flash) {
> - start_addr = memmap[SIFIVE_U_FLASH0].base;
> - }
> -
> /* reset vector */
> uint32_t reset_vec[8] = {
> - 0x00000000,
> + s->msel, /* MSEL pin state */
> 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
> 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
> 0xf1402573, /* csrr a0, mhartid */
> @@ -505,7 +527,8 @@ static void sifive_u_machine_instance_init(Object *obj)
> sifive_u_machine_set_start_in_flash);
> object_property_set_description(obj, "start-in-flash",
> "Set on to tell QEMU's ROM to jump to "
> - "flash. Otherwise QEMU will jump to DRAM");
> + "flash. Otherwise QEMU will jump to DRAM "
> + "or L2LIM depending on the msel value");
>
> s->msel = 0;
> object_property_add(obj, "msel", "uint32",
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index d82cfe0..5d80f91 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -111,6 +111,12 @@ enum {
> SIFIVE_U_RTCCLK_FREQ = 1000000
> };
>
> +enum {
> + MSEL_MEMMAP_QSPI0_FLASH = 1,
> + MSEL_L2LIM_QSPI0_FLASH = 6,
> + MSEL_L2LIM_QSPI2_SD = 11
> +};
> +
> #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
> #define SIFIVE_U_COMPUTE_CPU_COUNT 4
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state
@ 2020-06-15 19:04 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:04 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:28 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> SiFive FU540 SoC supports booting from several sources, which are
> controlled using the Mode Select (MSEL[3:0]) pins on the chip.
> Typically, the boot process runs through several stages before it
> begins execution of user-provided programs.
>
> The SoC supports booting from memory-mapped QSPI flash, which is
> how start_in_flash property is used for at present. This matches
> MSEL = 1 configuration (QSPI0).
>
> Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL).
> It's not necessary for QEMU to implement the full ZSBL ROM codes,
> because we know ZSBL downloads the next stage program into the L2
> LIM at address 0x8000000 and executes from there. We can bypass
> the whole ZSBL execution and use "-bios" to load the next stage
> program directly if MSEL indicates a ZSBL booting flow.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 39 +++++++++++++++++++++++++++++++--------
> include/hw/riscv/sifive_u.h | 6 ++++++
> 2 files changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 0a86ffc..f64aa52 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -408,8 +408,34 @@ static void sifive_u_machine_init(MachineState *machine)
> /* create device tree */
> create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
>
> - riscv_find_and_load_firmware(machine, BIOS_FILENAME,
> - memmap[SIFIVE_U_DRAM].base, NULL);
> + if (s->start_in_flash) {
> + /*
> + * If start_in_flash property is given, assign s->msel to a value
> + * that representing booting from QSPI0 memory-mapped flash.
> + *
> + * This also means that when both start_in_flash and msel properties
> + * are given, start_in_flash takes the precedence over msel.
> + *
> + * Note this is to keep backward compatibility not to break existing
> + * users that use start_in_flash property.
> + */
> + s->msel = MSEL_MEMMAP_QSPI0_FLASH;
> + }
> +
> + switch (s->msel) {
> + case MSEL_MEMMAP_QSPI0_FLASH:
> + start_addr = memmap[SIFIVE_U_FLASH0].base;
> + break;
> + case MSEL_L2LIM_QSPI0_FLASH:
> + case MSEL_L2LIM_QSPI2_SD:
> + start_addr = memmap[SIFIVE_U_L2LIM].base;
> + break;
> + default:
> + start_addr = memmap[SIFIVE_U_DRAM].base;
> + break;
> + }
> +
> + riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
>
> if (machine->kernel_filename) {
> uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
> @@ -427,13 +453,9 @@ static void sifive_u_machine_init(MachineState *machine)
> }
> }
>
> - if (s->start_in_flash) {
> - start_addr = memmap[SIFIVE_U_FLASH0].base;
> - }
> -
> /* reset vector */
> uint32_t reset_vec[8] = {
> - 0x00000000,
> + s->msel, /* MSEL pin state */
> 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
> 0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
> 0xf1402573, /* csrr a0, mhartid */
> @@ -505,7 +527,8 @@ static void sifive_u_machine_instance_init(Object *obj)
> sifive_u_machine_set_start_in_flash);
> object_property_set_description(obj, "start-in-flash",
> "Set on to tell QEMU's ROM to jump to "
> - "flash. Otherwise QEMU will jump to DRAM");
> + "flash. Otherwise QEMU will jump to DRAM "
> + "or L2LIM depending on the msel value");
>
> s->msel = 0;
> object_property_add(obj, "msel", "uint32",
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index d82cfe0..5d80f91 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -111,6 +111,12 @@ enum {
> SIFIVE_U_RTCCLK_FREQ = 1000000
> };
>
> +enum {
> + MSEL_MEMMAP_QSPI0_FLASH = 1,
> + MSEL_L2LIM_QSPI0_FLASH = 6,
> + MSEL_L2LIM_QSPI2_SD = 11
> +};
> +
> #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
> #define SIFIVE_U_COMPUTE_CPU_COUNT 4
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
@ 2020-06-15 19:04 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:04 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Move the flash and DRAM to the end of the SoC memmap table.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f64aa52..c94ff6f 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -80,10 +80,10 @@ static const struct MemmapEntry {
> [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> - [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> - [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> + [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> };
>
> #define OTP_SERIAL 1
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries
@ 2020-06-15 19:04 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:04 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:26 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Move the flash and DRAM to the end of the SoC memmap table.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index f64aa52..c94ff6f 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -80,10 +80,10 @@ static const struct MemmapEntry {
> [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
> [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> - [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> - [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> + [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> };
>
> #define OTP_SERIAL 1
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
@ 2020-06-15 19:20 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:20 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:29 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> It is enough to simply map the SiFive FU540 DDR memory controller
> into the MMIO space using create_unimplemented_device(), to make
> the upstream U-Boot v2020.07 DDR memory initialization codes happy.
>
> Note we do not generate device tree fragment for the DDR memory
> controller. Since the controller data in device tree consumes a
> very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the
> U-Boot source), and it is only needed by U-Boot SPL but not any
> operating system, we choose not to generate the fragment here.
> This also means when testing with U-Boot SPL, the device tree has
> to come from U-Boot SPL itself, but not the one generated by QEMU
> on the fly. The memory has to be set to 8GiB to match the real
> HiFive Unleashed board when invoking QEMU (-m 8G).
>
> With this commit, QEMU can boot U-Boot SPL built for SiFive FU540
> all the way up to loading U-Boot proper from MMC:
>
> $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
>
> U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
> Trying to boot from MMC1
> Unhandled exception: Load access fault
> EPC: 0000000008009be6 TVAL: 0000000010050014
>
> The above exception is expected because QSPI is unsupported yet.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> hw/riscv/sifive_u.c | 4 ++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index c94ff6f..7923df4 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -82,6 +82,7 @@ static const struct MemmapEntry {
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
> [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -733,6 +734,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
> create_unimplemented_device("riscv.sifive.u.gem-mgmt",
> memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> +
> + create_unimplemented_device("riscv.sifive.u.dmc",
> + memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
> }
>
> static Property sifive_u_soc_props[] = {
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 5d80f91..3e33646 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -78,6 +78,7 @@ enum {
> SIFIVE_U_UART1,
> SIFIVE_U_GPIO,
> SIFIVE_U_OTP,
> + SIFIVE_U_DMC,
> SIFIVE_U_FLASH0,
> SIFIVE_U_DRAM,
> SIFIVE_U_GEM,
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device
@ 2020-06-15 19:20 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:20 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:29 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> It is enough to simply map the SiFive FU540 DDR memory controller
> into the MMIO space using create_unimplemented_device(), to make
> the upstream U-Boot v2020.07 DDR memory initialization codes happy.
>
> Note we do not generate device tree fragment for the DDR memory
> controller. Since the controller data in device tree consumes a
> very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the
> U-Boot source), and it is only needed by U-Boot SPL but not any
> operating system, we choose not to generate the fragment here.
> This also means when testing with U-Boot SPL, the device tree has
> to come from U-Boot SPL itself, but not the one generated by QEMU
> on the fly. The memory has to be set to 8GiB to match the real
> HiFive Unleashed board when invoking QEMU (-m 8G).
>
> With this commit, QEMU can boot U-Boot SPL built for SiFive FU540
> all the way up to loading U-Boot proper from MMC:
>
> $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
>
> U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
> Trying to boot from MMC1
> Unhandled exception: Load access fault
> EPC: 0000000008009be6 TVAL: 0000000010050014
>
> The above exception is expected because QSPI is unsupported yet.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> hw/riscv/sifive_u.c | 4 ++++
> include/hw/riscv/sifive_u.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index c94ff6f..7923df4 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -82,6 +82,7 @@ static const struct MemmapEntry {
> [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
> [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
> [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
> + [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
> [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
> [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
> };
> @@ -733,6 +734,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
> create_unimplemented_device("riscv.sifive.u.gem-mgmt",
> memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> +
> + create_unimplemented_device("riscv.sifive.u.dmc",
> + memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
> }
>
> static Property sifive_u_soc_props[] = {
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 5d80f91..3e33646 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -78,6 +78,7 @@ enum {
> SIFIVE_U_UART1,
> SIFIVE_U_GPIO,
> SIFIVE_U_OTP,
> + SIFIVE_U_DMC,
> SIFIVE_U_FLASH0,
> SIFIVE_U_DRAM,
> SIFIVE_U_GEM,
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
@ 2020-06-15 19:31 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
` (14 subsequent siblings)
15 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:31 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Mon, Jun 8, 2020 at 7:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This series updates the 'sifive_u' machine support:
>
> - Add GPIO controller support
> - Support reboot functionality via GPIO pin#10
> - Change SiFive E/U series CPU reset vector to 0x1004
> - Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new
> "msel" machine property
> - Add a dummy DDR memory controller device
>
> The series also does some clean-ups to the existing codes.
>
> With this series, QEMU can boot U-Boot SPL built for SiFive FU540
> all the way up to loading U-Boot proper from MMC:
>
> $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
>
> U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
> Trying to boot from MMC1
> Unhandled exception: Load access fault
> EPC: 0000000008009be6 TVAL: 0000000010050014
>
> The last big gap for the 'sifive_u' machine is the QSPI modeling.
>
>
> Bin Meng (15):
> hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc*
> functions
> hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc*
> functions
> hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
> hw/riscv: sifive_u: Generate device tree node for OTP
> hw/riscv: sifive_gpio: Clean up the codes
> hw/riscv: sifive_gpio: Add a new 'ngpio' property
> hw/riscv: sifive_u: Hook a GPIO controller
> hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
> hw/riscv: sifive_u: Add reset functionality
> hw/riscv: sifive_u: Rename serial property get/set functions to a
> generic name
> hw/riscv: sifive_u: Add a new property msel for MSEL pin state
> hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
> hw/riscv: sifive_u: Support different boot source per MSEL pin state
> hw/riscv: sifive_u: Sort the SoC memmap table entries
> hw/riscv: sifive_u: Add a dummy DDR memory controller device
I have applied patches 1 to 11 to the RISC-V branch.
Alistair
>
> hw/riscv/opentitan.c | 29 ++++----
> hw/riscv/sifive_e.c | 32 +++++----
> hw/riscv/sifive_gpio.c | 45 +++++++-----
> hw/riscv/sifive_u.c | 158 ++++++++++++++++++++++++++++++++++-------
> include/hw/riscv/sifive_gpio.h | 8 ++-
> include/hw/riscv/sifive_u.h | 27 +++++++
> target/riscv/cpu.c | 4 +-
> 7 files changed, 223 insertions(+), 80 deletions(-)
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support
@ 2020-06-15 19:31 ` Alistair Francis
0 siblings, 0 replies; 48+ messages in thread
From: Alistair Francis @ 2020-06-15 19:31 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel@nongnu.org Developers,
open list:RISC-V, Bin Meng
On Mon, Jun 8, 2020 at 7:18 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This series updates the 'sifive_u' machine support:
>
> - Add GPIO controller support
> - Support reboot functionality via GPIO pin#10
> - Change SiFive E/U series CPU reset vector to 0x1004
> - Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new
> "msel" machine property
> - Add a dummy DDR memory controller device
>
> The series also does some clean-ups to the existing codes.
>
> With this series, QEMU can boot U-Boot SPL built for SiFive FU540
> all the way up to loading U-Boot proper from MMC:
>
> $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
>
> U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
> Trying to boot from MMC1
> Unhandled exception: Load access fault
> EPC: 0000000008009be6 TVAL: 0000000010050014
>
> The last big gap for the 'sifive_u' machine is the QSPI modeling.
>
>
> Bin Meng (15):
> hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc*
> functions
> hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc*
> functions
> hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
> hw/riscv: sifive_u: Generate device tree node for OTP
> hw/riscv: sifive_gpio: Clean up the codes
> hw/riscv: sifive_gpio: Add a new 'ngpio' property
> hw/riscv: sifive_u: Hook a GPIO controller
> hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
> hw/riscv: sifive_u: Add reset functionality
> hw/riscv: sifive_u: Rename serial property get/set functions to a
> generic name
> hw/riscv: sifive_u: Add a new property msel for MSEL pin state
> hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
> hw/riscv: sifive_u: Support different boot source per MSEL pin state
> hw/riscv: sifive_u: Sort the SoC memmap table entries
> hw/riscv: sifive_u: Add a dummy DDR memory controller device
I have applied patches 1 to 11 to the RISC-V branch.
Alistair
>
> hw/riscv/opentitan.c | 29 ++++----
> hw/riscv/sifive_e.c | 32 +++++----
> hw/riscv/sifive_gpio.c | 45 +++++++-----
> hw/riscv/sifive_u.c | 158 ++++++++++++++++++++++++++++++++++-------
> include/hw/riscv/sifive_gpio.h | 8 ++-
> include/hw/riscv/sifive_u.h | 27 +++++++
> target/riscv/cpu.c | 4 +-
> 7 files changed, 223 insertions(+), 80 deletions(-)
>
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2020-06-15 19:43 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
2020-06-15 16:05 ` Alistair Francis
2020-06-15 16:05 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
2020-06-15 16:06 ` Alistair Francis
2020-06-15 16:06 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
2020-06-15 16:07 ` Alistair Francis
2020-06-15 16:07 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
2020-06-15 16:08 ` Alistair Francis
2020-06-15 16:08 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
2020-06-15 16:13 ` Alistair Francis
2020-06-15 16:13 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
2020-06-15 16:16 ` Alistair Francis
2020-06-15 16:16 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
2020-06-15 16:26 ` Alistair Francis
2020-06-15 16:26 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
2020-06-15 16:28 ` Alistair Francis
2020-06-15 16:28 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
2020-06-15 16:35 ` Alistair Francis
2020-06-15 16:35 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
2020-06-15 16:39 ` Alistair Francis
2020-06-15 16:39 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
2020-06-15 16:41 ` Alistair Francis
2020-06-15 16:41 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-15 19:02 ` Alistair Francis
2020-06-15 19:02 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-15 19:20 ` Alistair Francis
2020-06-15 19:20 ` Alistair Francis
2020-06-15 19:31 ` [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Alistair Francis
2020-06-15 19:31 ` Alistair Francis
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