* [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3
@ 2019-01-14 23:57 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
Alistair Francis (1):
RISC-V: Add priv_ver to DisasContext
Michael Clark (5):
RISC-V: Implement mstatus.TSR/TW/TVM
RISC-V: Use riscv prefix consistently on cpu helpers
RISC-V: Add misa to DisasContext
RISC-V: Add misa.MAFD checks to translate
RISC-V: Add misa runtime write support
Richard Henderson (2):
RISC-V: Split out mstatus_fs from tb_flags
RISC-V: Mark mstatus.fs dirty
linux-user/riscv/signal.c | 4 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 31 ++--
target/riscv/cpu_bits.h | 11 ++
target/riscv/cpu_helper.c | 10 +-
target/riscv/csr.c | 91 +++++++++---
target/riscv/fpu_helper.c | 6 +-
target/riscv/op_helper.c | 47 ++++--
target/riscv/translate.c | 292 ++++++++++++++++++++++++++++++++------
9 files changed, 388 insertions(+), 106 deletions(-)
--
2.19.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3
@ 2019-01-14 23:57 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
Alistair Francis (1):
RISC-V: Add priv_ver to DisasContext
Michael Clark (5):
RISC-V: Implement mstatus.TSR/TW/TVM
RISC-V: Use riscv prefix consistently on cpu helpers
RISC-V: Add misa to DisasContext
RISC-V: Add misa.MAFD checks to translate
RISC-V: Add misa runtime write support
Richard Henderson (2):
RISC-V: Split out mstatus_fs from tb_flags
RISC-V: Mark mstatus.fs dirty
linux-user/riscv/signal.c | 4 +-
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 31 ++--
target/riscv/cpu_bits.h | 11 ++
target/riscv/cpu_helper.c | 10 +-
target/riscv/csr.c | 91 +++++++++---
target/riscv/fpu_helper.c | 6 +-
target/riscv/op_helper.c | 47 ++++--
target/riscv/translate.c | 292 ++++++++++++++++++++++++++++++++------
9 files changed, 388 insertions(+), 106 deletions(-)
--
2.19.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 1/8] RISC-V: Split out mstatus_fs from tb_flags
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:57 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Richard Henderson <richard.henderson@linaro.org>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 743f02c8b9..681341f5d5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -275,8 +275,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
-#define TB_FLAGS_FP_ENABLE MSTATUS_FS
+#define TB_FLAGS_MMU_MASK 3
+#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@@ -284,7 +284,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
#ifdef CONFIG_USER_ONLY
- *flags = TB_FLAGS_FP_ENABLE;
+ *flags = TB_FLAGS_MSTATUS_FS;
#else
*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 312bf298b3..3d07d651b6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -44,7 +44,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
uint32_t opcode;
- uint32_t flags;
+ uint32_t mstatus_fs;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
@@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
{
TCGv t0 = NULL;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
goto do_illegal;
}
@@ -1818,8 +1818,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->pc_succ_insn = ctx->base.pc_first;
- ctx->flags = ctx->base.tb->flags;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
+ ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->frm = -1; /* unknown rounding mode */
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 1/8] RISC-V: Split out mstatus_fs from tb_flags
@ 2019-01-14 23:57 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Richard Henderson <richard.henderson@linaro.org>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 6 +++---
target/riscv/translate.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 743f02c8b9..681341f5d5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -275,8 +275,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
-#define TB_FLAGS_FP_ENABLE MSTATUS_FS
+#define TB_FLAGS_MMU_MASK 3
+#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
@@ -284,7 +284,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
#ifdef CONFIG_USER_ONLY
- *flags = TB_FLAGS_FP_ENABLE;
+ *flags = TB_FLAGS_MSTATUS_FS;
#else
*flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 312bf298b3..3d07d651b6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -44,7 +44,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
uint32_t opcode;
- uint32_t flags;
+ uint32_t mstatus_fs;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
@@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
{
TCGv t0;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
gen_exception_illegal(ctx);
return;
}
@@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
{
TCGv t0 = NULL;
- if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
+ if (ctx->mstatus_fs == 0) {
goto do_illegal;
}
@@ -1818,8 +1818,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->pc_succ_insn = ctx->base.pc_first;
- ctx->flags = ctx->base.tb->flags;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
+ ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->frm = -1; /* unknown rounding mode */
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 2/8] RISC-V: Mark mstatus.fs dirty
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:57 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Richard Henderson <richard.henderson@linaro.org>
Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html
Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Co-authored-by: Michael Clark <mjc@sifive.com>
---
target/riscv/csr.c | 12 ------------
target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e7e7d16b8..5714147689 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -317,18 +317,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
- /* Note: this is a workaround for an issue where mstatus.FS
- does not report dirty after floating point operations
- that modify floating point state. This workaround is
- technically compliant with the RISC-V Privileged
- specification as it is legal to return only off, or dirty.
- at the expense of extra floating point save/restore. */
-
- /* FP is always dirty or off */
- if (mstatus & MSTATUS_FS) {
- mstatus |= MSTATUS_FS;
- }
-
int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3d07d651b6..0581b3c1f7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,6 +651,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(dat);
}
+#ifndef CONFIG_USER_ONLY
+/* The states of mstatus_fs are:
+ * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+ * We will have already diagnosed disabled state,
+ * and need to turn initial/clean into dirty.
+ */
+static void mark_fs_dirty(DisasContext *ctx)
+{
+ TCGv tmp;
+ if (ctx->mstatus_fs == MSTATUS_FS) {
+ return;
+ }
+ /* Remember the state change for the rest of the TB. */
+ ctx->mstatus_fs = MSTATUS_FS;
+
+ tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_temp_free(tmp);
+}
+#else
+static inline void mark_fs_dirty(DisasContext *ctx) { }
+#endif
+
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
@@ -679,6 +704,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
break;
}
tcg_temp_free(t0);
+
+ mark_fs_dirty(ctx);
}
static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
@@ -944,6 +971,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
int rs1, int rs2, int rm)
{
TCGv t0 = NULL;
+ bool fp_output = true;
if (ctx->mstatus_fs == 0) {
goto do_illegal;
@@ -1006,6 +1034,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_W_S:
@@ -1035,6 +1064,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_S_W:
@@ -1085,6 +1115,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FMV_S_X:
@@ -1177,6 +1208,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_W_D:
@@ -1206,6 +1238,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_D_W:
@@ -1254,6 +1287,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
default:
goto do_illegal;
}
+ fp_output = false;
break;
#if defined(TARGET_RISCV64)
@@ -1271,7 +1305,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(t0);
}
gen_exception_illegal(ctx);
- break;
+ return;
+ }
+
+ if (fp_output) {
+ mark_fs_dirty(ctx);
}
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 2/8] RISC-V: Mark mstatus.fs dirty
@ 2019-01-14 23:57 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:57 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Richard Henderson <richard.henderson@linaro.org>
Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.
[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html
Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Co-authored-by: Richard Henderson <richard.henderson@linaro.org>
Co-authored-by: Michael Clark <mjc@sifive.com>
---
target/riscv/csr.c | 12 ------------
target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 39 insertions(+), 13 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5e7e7d16b8..5714147689 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -317,18 +317,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
mstatus = (mstatus & ~mask) | (val & mask);
- /* Note: this is a workaround for an issue where mstatus.FS
- does not report dirty after floating point operations
- that modify floating point state. This workaround is
- technically compliant with the RISC-V Privileged
- specification as it is legal to return only off, or dirty.
- at the expense of extra floating point save/restore. */
-
- /* FP is always dirty or off */
- if (mstatus & MSTATUS_FS) {
- mstatus |= MSTATUS_FS;
- }
-
int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
mstatus = set_field(mstatus, MSTATUS_SD, dirty);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3d07d651b6..0581b3c1f7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -651,6 +651,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
tcg_temp_free(dat);
}
+#ifndef CONFIG_USER_ONLY
+/* The states of mstatus_fs are:
+ * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
+ * We will have already diagnosed disabled state,
+ * and need to turn initial/clean into dirty.
+ */
+static void mark_fs_dirty(DisasContext *ctx)
+{
+ TCGv tmp;
+ if (ctx->mstatus_fs == MSTATUS_FS) {
+ return;
+ }
+ /* Remember the state change for the rest of the TB. */
+ ctx->mstatus_fs = MSTATUS_FS;
+
+ tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+ tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
+ tcg_temp_free(tmp);
+}
+#else
+static inline void mark_fs_dirty(DisasContext *ctx) { }
+#endif
+
static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
int rs1, target_long imm)
{
@@ -679,6 +704,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
break;
}
tcg_temp_free(t0);
+
+ mark_fs_dirty(ctx);
}
static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
@@ -944,6 +971,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
int rs1, int rs2, int rm)
{
TCGv t0 = NULL;
+ bool fp_output = true;
if (ctx->mstatus_fs == 0) {
goto do_illegal;
@@ -1006,6 +1034,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_W_S:
@@ -1035,6 +1064,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_S_W:
@@ -1085,6 +1115,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FMV_S_X:
@@ -1177,6 +1208,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_W_D:
@@ -1206,6 +1238,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
gen_set_gpr(rd, t0);
tcg_temp_free(t0);
+ fp_output = false;
break;
case OPC_RISC_FCVT_D_W:
@@ -1254,6 +1287,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
default:
goto do_illegal;
}
+ fp_output = false;
break;
#if defined(TARGET_RISCV64)
@@ -1271,7 +1305,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(t0);
}
gen_exception_illegal(ctx);
- break;
+ return;
+ }
+
+ if (fp_output) {
+ mark_fs_dirty(ctx);
}
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 3/8] RISC-V: Implement mstatus.TSR/TW/TVM
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:58 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Matthew Suozzo <msuozzo@google.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Co-authored-by: Matthew Suozzo <msuozzo@google.com>
Co-authored-by: Michael Clark <mjc@sifive.com>
---
target/riscv/csr.c | 17 +++++++++++++----
target/riscv/op_helper.c | 25 +++++++++++++++++++++----
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5714147689..390d3a9a56 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -305,7 +305,8 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
- MSTATUS_MPP | MSTATUS_MXR;
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+ MSTATUS_TW;
}
/* silenty discard mstatus.mpp writes for unsupported modes */
@@ -642,7 +643,11 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
*val = 0;
} else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- *val = env->satp;
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
+ } else {
+ *val = env->satp;
+ }
} else {
*val = env->sptbr;
}
@@ -663,8 +668,12 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
validate_vm(env, get_field(val, SATP_MODE)) &&
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
- tlb_flush(CPU(riscv_env_get_cpu(env)));
- env->satp = val;
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
+ } else {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ env->satp = val;
+ }
}
return 0;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 81bd1a77ea..77c79ba36e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -82,6 +82,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
+ if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TSR)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_SPP);
mstatus = set_field(mstatus,
@@ -125,16 +130,28 @@ void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
- cs->halted = 1;
- cs->exception_index = EXCP_HLT;
- cpu_loop_exit(cs);
+ if (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TW)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ cs->halted = 1;
+ cs->exception_index = EXCP_HLT;
+ cpu_loop_exit(cs);
+ }
}
void helper_tlb_flush(CPURISCVState *env)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- tlb_flush(cs);
+ if (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ tlb_flush(cs);
+ }
}
#endif /* !CONFIG_USER_ONLY */
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 3/8] RISC-V: Implement mstatus.TSR/TW/TVM
@ 2019-01-14 23:58 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Matthew Suozzo <msuozzo@google.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Co-authored-by: Matthew Suozzo <msuozzo@google.com>
Co-authored-by: Michael Clark <mjc@sifive.com>
---
target/riscv/csr.c | 17 +++++++++++++----
target/riscv/op_helper.c | 25 +++++++++++++++++++++----
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5714147689..390d3a9a56 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -305,7 +305,8 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
- MSTATUS_MPP | MSTATUS_MXR;
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+ MSTATUS_TW;
}
/* silenty discard mstatus.mpp writes for unsupported modes */
@@ -642,7 +643,11 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
*val = 0;
} else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- *val = env->satp;
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
+ } else {
+ *val = env->satp;
+ }
} else {
*val = env->sptbr;
}
@@ -663,8 +668,12 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
validate_vm(env, get_field(val, SATP_MODE)) &&
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
- tlb_flush(CPU(riscv_env_get_cpu(env)));
- env->satp = val;
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
+ } else {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ env->satp = val;
+ }
}
return 0;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 81bd1a77ea..77c79ba36e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -82,6 +82,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
+ if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TSR)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_SPP);
mstatus = set_field(mstatus,
@@ -125,16 +130,28 @@ void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
- cs->halted = 1;
- cs->exception_index = EXCP_HLT;
- cpu_loop_exit(cs);
+ if (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TW)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ cs->halted = 1;
+ cs->exception_index = EXCP_HLT;
+ cpu_loop_exit(cs);
+ }
}
void helper_tlb_flush(CPURISCVState *env)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- tlb_flush(cs);
+ if (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ tlb_flush(cs);
+ }
}
#endif /* !CONFIG_USER_ONLY */
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:58 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
linux-user/riscv/signal.c | 4 ++--
target/riscv/cpu.h | 21 ++++++++++-----------
target/riscv/cpu_helper.c | 10 +++++-----
target/riscv/csr.c | 8 ++++----
target/riscv/fpu_helper.c | 6 +++---
target/riscv/op_helper.c | 28 ++++++++++++++--------------
6 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index f598d41891..83ecc6f799 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
__put_user(env->fpr[i], &sc->fpr[i]);
}
- uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
+ uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
__put_user(fcsr, &sc->fcsr);
}
@@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
uint32_t fcsr;
__get_user(fcsr, &sc->fcsr);
- csr_write_helper(env, fcsr, CSR_FCSR);
+ riscv_csr_write(env, CSR_FCSR, fcsr);
}
static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 681341f5d5..a97435bd7b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
-#define cpu_signal_handler cpu_riscv_signal_handler
+#define cpu_signal_handler riscv_cpu_signal_handler
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index
@@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
#endif
-void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
+void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void);
-RISCVCPU *cpu_riscv_init(const char *cpu_model);
-int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
-void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
- uint32_t exception, uintptr_t pc);
+int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
+void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
+ uint32_t exception, uintptr_t pc);
-target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
-void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
+target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
+void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
@@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
-static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
- int csrno)
+static inline void riscv_csr_write(CPURISCVState *env, int csrno,
+ target_ulong val)
{
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
}
-static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
+static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{
target_ulong val = 0;
riscv_csrrw(env, csrno, &val, 0, 0);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f257050f12..f49e98ed59 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
return old;
}
-void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
+void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
g_assert_not_reached();
@@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
- do_raise_exception_err(env, cs->exception_index, retaddr);
+ riscv_raise_exception(env, cs->exception_index, retaddr);
}
/* called by qemu's softmmu to fill the qemu tlb */
@@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
if (ret == TRANSLATE_FAIL) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- do_raise_exception_err(env, cs->exception_index, retaddr);
+ riscv_raise_exception(env, cs->exception_index, retaddr);
}
}
@@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- riscv_set_mode(env, PRV_S);
+ riscv_cpu_set_mode(env, PRV_S);
} else {
/* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
env->pc = env->mtvec;
@@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
- riscv_set_mode(env, PRV_M);
+ riscv_cpu_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 390d3a9a56..e2bd374f09 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
return -1;
}
#endif
- *val = cpu_riscv_get_fflags(env);
+ *val = riscv_cpu_get_fflags(env);
return 0;
}
@@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
}
env->mstatus |= MSTATUS_FS;
#endif
- cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
+ riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return 0;
}
@@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
return -1;
}
#endif
- *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
+ *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
return 0;
}
@@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
- cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
+ riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 01b45ca0ae..b4f818a646 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -22,7 +22,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
+target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
{
int soft = get_float_exception_flags(&env->fp_status);
target_ulong hard = 0;
@@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
return hard;
}
-void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
+void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
{
int soft = 0;
@@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
softrm = float_round_ties_away;
break;
default:
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
set_float_rounding_mode(softrm, &env->fp_status);
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 77c79ba36e..b7dc18a41e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -25,7 +25,7 @@
#include "exec/helper-proto.h"
/* Exceptions processing helpers */
-void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
+void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
@@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
void helper_raise_exception(CPURISCVState *env, uint32_t exception)
{
- do_raise_exception_err(env, exception, 0);
+ riscv_raise_exception(env, exception, 0);
}
target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
@@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_S)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->sepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
- do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TSR)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong mstatus = env->mstatus;
@@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
- riscv_set_mode(env, prev_priv);
+ riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
return retpc;
@@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_M)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->mepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
- do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
target_ulong mstatus = env->mstatus;
@@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
- riscv_set_mode(env, prev_priv);
+ riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
return retpc;
@@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TW)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
@@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TVM)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
@ 2019-01-14 23:58 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
linux-user/riscv/signal.c | 4 ++--
target/riscv/cpu.h | 21 ++++++++++-----------
target/riscv/cpu_helper.c | 10 +++++-----
target/riscv/csr.c | 8 ++++----
target/riscv/fpu_helper.c | 6 +++---
target/riscv/op_helper.c | 28 ++++++++++++++--------------
6 files changed, 38 insertions(+), 39 deletions(-)
diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
index f598d41891..83ecc6f799 100644
--- a/linux-user/riscv/signal.c
+++ b/linux-user/riscv/signal.c
@@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
__put_user(env->fpr[i], &sc->fpr[i]);
}
- uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
+ uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
__put_user(fcsr, &sc->fcsr);
}
@@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
uint32_t fcsr;
__get_user(fcsr, &sc->fcsr);
- csr_write_helper(env, fcsr, CSR_FCSR);
+ riscv_csr_write(env, CSR_FCSR, fcsr);
}
static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 681341f5d5..a97435bd7b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
-#define cpu_signal_handler cpu_riscv_signal_handler
+#define cpu_signal_handler riscv_cpu_signal_handler
#define cpu_list riscv_cpu_list
#define cpu_mmu_index riscv_cpu_mmu_index
@@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
#endif
-void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
+void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
void riscv_translate_init(void);
-RISCVCPU *cpu_riscv_init(const char *cpu_model);
-int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
-void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
- uint32_t exception, uintptr_t pc);
+int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
+void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
+ uint32_t exception, uintptr_t pc);
-target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
-void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
+target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
+void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
#define TB_FLAGS_MMU_MASK 3
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
@@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
-static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
- int csrno)
+static inline void riscv_csr_write(CPURISCVState *env, int csrno,
+ target_ulong val)
{
riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
}
-static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
+static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
{
target_ulong val = 0;
riscv_csrrw(env, csrno, &val, 0, 0);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f257050f12..f49e98ed59 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
return old;
}
-void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
+void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
g_assert_not_reached();
@@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
g_assert_not_reached();
}
env->badaddr = addr;
- do_raise_exception_err(env, cs->exception_index, retaddr);
+ riscv_raise_exception(env, cs->exception_index, retaddr);
}
/* called by qemu's softmmu to fill the qemu tlb */
@@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
if (ret == TRANSLATE_FAIL) {
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
- do_raise_exception_err(env, cs->exception_index, retaddr);
+ riscv_raise_exception(env, cs->exception_index, retaddr);
}
}
@@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
- riscv_set_mode(env, PRV_S);
+ riscv_cpu_set_mode(env, PRV_S);
} else {
/* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
env->pc = env->mtvec;
@@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
- riscv_set_mode(env, PRV_M);
+ riscv_cpu_set_mode(env, PRV_M);
}
/* TODO yield load reservation */
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 390d3a9a56..e2bd374f09 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
return -1;
}
#endif
- *val = cpu_riscv_get_fflags(env);
+ *val = riscv_cpu_get_fflags(env);
return 0;
}
@@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
}
env->mstatus |= MSTATUS_FS;
#endif
- cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
+ riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return 0;
}
@@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
return -1;
}
#endif
- *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
+ *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
return 0;
}
@@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
env->mstatus |= MSTATUS_FS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
- cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
+ riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 01b45ca0ae..b4f818a646 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -22,7 +22,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
+target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
{
int soft = get_float_exception_flags(&env->fp_status);
target_ulong hard = 0;
@@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
return hard;
}
-void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
+void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
{
int soft = 0;
@@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
softrm = float_round_ties_away;
break;
default:
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
set_float_rounding_mode(softrm, &env->fp_status);
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 77c79ba36e..b7dc18a41e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -25,7 +25,7 @@
#include "exec/helper-proto.h"
/* Exceptions processing helpers */
-void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
+void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
@@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
void helper_raise_exception(CPURISCVState *env, uint32_t exception)
{
- do_raise_exception_err(env, exception, 0);
+ riscv_raise_exception(env, exception, 0);
}
target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
@@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
{
target_ulong val = 0;
if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
return val;
}
@@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_S)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->sepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
- do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TSR)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong mstatus = env->mstatus;
@@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
- riscv_set_mode(env, prev_priv);
+ riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
return retpc;
@@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
{
if (!(env->priv >= PRV_M)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->mepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
- do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
target_ulong mstatus = env->mstatus;
@@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
- riscv_set_mode(env, prev_priv);
+ riscv_cpu_set_mode(env, prev_priv);
env->mstatus = mstatus;
return retpc;
@@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TW)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
@@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
if (env->priv == PRV_S &&
env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TVM)) {
- do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
tlb_flush(cs);
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:58 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0581b3c1f7..833adf1d6f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -43,6 +43,7 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
+ target_ulong priv_ver;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mem_idx;
@@ -1330,7 +1331,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
#ifndef CONFIG_USER_ONLY
/* Extract funct7 value and check whether it matches SFENCE.VMA */
if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
- if (env->priv_ver == PRIV_VERSION_1_10_0) {
+ if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
/* sfence.vma */
/* TODO: handle ASID specific fences */
gen_helper_tlb_flush(cpu_env);
@@ -1384,7 +1385,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_helper_wfi(cpu_env);
break;
case 0x104: /* SFENCE.VM */
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+ if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
gen_helper_tlb_flush(cpu_env);
} else {
gen_exception_illegal(ctx);
@@ -1851,13 +1852,15 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
}
}
-static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ CPURISCVState *env = cpu->env_ptr;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
+ ctx->priv_ver = env->priv_ver;
ctx->frm = -1; /* unknown rounding mode */
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
@ 2019-01-14 23:58 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0581b3c1f7..833adf1d6f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -43,6 +43,7 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
+ target_ulong priv_ver;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mem_idx;
@@ -1330,7 +1331,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
#ifndef CONFIG_USER_ONLY
/* Extract funct7 value and check whether it matches SFENCE.VMA */
if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
- if (env->priv_ver == PRIV_VERSION_1_10_0) {
+ if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
/* sfence.vma */
/* TODO: handle ASID specific fences */
gen_helper_tlb_flush(cpu_env);
@@ -1384,7 +1385,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_helper_wfi(cpu_env);
break;
case 0x104: /* SFENCE.VM */
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+ if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
gen_helper_tlb_flush(cpu_env);
} else {
gen_exception_illegal(ctx);
@@ -1851,13 +1852,15 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
}
}
-static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ CPURISCVState *env = cpu->env_ptr;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
+ ctx->priv_ver = env->priv_ver;
ctx->frm = -1; /* unknown rounding mode */
}
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 6/8] RISC-V: Add misa to DisasContext
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:58 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Emilio G. Cota <cota@braap.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 75 +++++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 35 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 833adf1d6f..7ebea308b4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -46,6 +46,7 @@ typedef struct DisasContext {
target_ulong priv_ver;
uint32_t opcode;
uint32_t mstatus_fs;
+ uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
@@ -75,6 +76,11 @@ static const int tcg_memop_lookup[8] = {
#define CASE_OP_32_64(X) case X
#endif
+static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+{
+ return ctx->misa & ext;
+}
+
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
@@ -506,14 +512,13 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(source1);
}
-static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
- target_ulong imm)
+static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
- if (!riscv_has_ext(env, RVC)) {
+ if (!has_ext(ctx, RVC)) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@@ -527,8 +532,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
+static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+ target_long imm)
{
/* no chaining with JALR */
TCGLabel *misaligned = NULL;
@@ -540,7 +545,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
- if (!riscv_has_ext(env, RVC)) {
+ if (!has_ext(ctx, RVC)) {
misaligned = gen_new_label();
tcg_gen_andi_tl(t0, cpu_pc, 0x2);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
@@ -565,8 +570,8 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_temp_free(t0);
}
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rs1, int rs2, target_long bimm)
+static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+ target_long bimm)
{
TCGLabel *l = gen_new_label();
TCGv source1, source2;
@@ -603,7 +608,7 @@ static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(l); /* branch taken */
- if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
+ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
@@ -1314,8 +1319,8 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
}
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
+static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+ int csr)
{
TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
source1 = tcg_temp_new();
@@ -1361,7 +1366,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_exception_illegal(ctx);
break;
case 0x102: /* SRET */
- if (riscv_has_ext(env, RVS)) {
+ if (has_ext(ctx, RVS)) {
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
@@ -1506,7 +1511,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
-static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64C1(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
@@ -1526,7 +1531,7 @@ static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
GET_C_IMM(ctx->opcode));
#else
/* C.JAL(RV32) -> jal x1, offset[11:1] */
- gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode));
+ gen_jal(ctx, 1, GET_C_J_IMM(ctx->opcode));
#endif
break;
case 2:
@@ -1605,22 +1610,22 @@ static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
break;
case 5:
/* C.J -> jal x0, offset[11:1]*/
- gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode));
+ gen_jal(ctx, 0, GET_C_J_IMM(ctx->opcode));
break;
case 6:
/* C.BEQZ -> beq rs1', x0, offset[8:1]*/
rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
+ gen_branch(ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
break;
case 7:
/* C.BNEZ -> bne rs1', x0, offset[8:1]*/
rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
+ gen_branch(ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
break;
}
}
-static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64C2(DisasContext *ctx)
{
uint8_t rd, rs2;
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -1654,7 +1659,7 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
if (extract32(ctx->opcode, 12, 1) == 0) {
if (rs2 == 0) {
/* C.JR -> jalr x0, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0);
+ gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0);
} else {
/* C.MV -> add rd, x0, rs2 */
gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
@@ -1662,11 +1667,11 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
} else {
if (rd == 0) {
/* C.EBREAK -> ebreak*/
- gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1);
+ gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1);
} else {
if (rs2 == 0) {
/* C.JALR -> jalr x1, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0);
+ gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0);
} else {
/* C.ADD -> add rd, rd, rs2 */
gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
@@ -1698,7 +1703,7 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
}
}
-static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64C(DisasContext *ctx)
{
uint8_t op = extract32(ctx->opcode, 0, 2);
@@ -1707,15 +1712,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
decode_RV32_64C0(ctx);
break;
case 1:
- decode_RV32_64C1(env, ctx);
+ decode_RV32_64C1(ctx);
break;
case 2:
- decode_RV32_64C2(env, ctx);
+ decode_RV32_64C2(ctx);
break;
}
}
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64G(DisasContext *ctx)
{
int rs1;
int rs2;
@@ -1750,13 +1755,13 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
break;
case OPC_RISC_JAL:
imm = GET_JAL_IMM(ctx->opcode);
- gen_jal(env, ctx, rd, imm);
+ gen_jal(ctx, rd, imm);
break;
case OPC_RISC_JALR:
- gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
+ gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
break;
case OPC_RISC_BRANCH:
- gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
+ gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
GET_B_IMM(ctx->opcode));
break;
case OPC_RISC_LOAD:
@@ -1827,7 +1832,7 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
break;
case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
+ gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
break;
default:
@@ -1836,19 +1841,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
}
-static void decode_opc(CPURISCVState *env, DisasContext *ctx)
+static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
- if (!riscv_has_ext(env, RVC)) {
+ if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(env, ctx);
+ decode_RV32_64C(ctx);
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(env, ctx);
+ decode_RV32_64G(ctx);
}
}
@@ -1861,6 +1866,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
+ ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
}
@@ -1891,14 +1897,13 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
return true;
}
-
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu->env_ptr;
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
- decode_opc(env, ctx);
+ decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 6/8] RISC-V: Add misa to DisasContext
@ 2019-01-14 23:58 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Emilio G. Cota <cota@braap.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 75 +++++++++++++++++++++-------------------
1 file changed, 40 insertions(+), 35 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 833adf1d6f..7ebea308b4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -46,6 +46,7 @@ typedef struct DisasContext {
target_ulong priv_ver;
uint32_t opcode;
uint32_t mstatus_fs;
+ uint32_t misa;
uint32_t mem_idx;
/* Remember the rounding mode encoded in the previous fp instruction,
which we have already installed into env->fp_status. Or -1 for
@@ -75,6 +76,11 @@ static const int tcg_memop_lookup[8] = {
#define CASE_OP_32_64(X) case X
#endif
+static inline bool has_ext(DisasContext *ctx, uint32_t ext)
+{
+ return ctx->misa & ext;
+}
+
static void generate_exception(DisasContext *ctx, int excp)
{
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
@@ -506,14 +512,13 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
tcg_temp_free(source1);
}
-static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
- target_ulong imm)
+static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
/* check misaligned: */
next_pc = ctx->base.pc_next + imm;
- if (!riscv_has_ext(env, RVC)) {
+ if (!has_ext(ctx, RVC)) {
if ((next_pc & 0x3) != 0) {
gen_exception_inst_addr_mis(ctx);
return;
@@ -527,8 +532,8 @@ static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
ctx->base.is_jmp = DISAS_NORETURN;
}
-static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, target_long imm)
+static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+ target_long imm)
{
/* no chaining with JALR */
TCGLabel *misaligned = NULL;
@@ -540,7 +545,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
- if (!riscv_has_ext(env, RVC)) {
+ if (!has_ext(ctx, RVC)) {
misaligned = gen_new_label();
tcg_gen_andi_tl(t0, cpu_pc, 0x2);
tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
@@ -565,8 +570,8 @@ static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
tcg_temp_free(t0);
}
-static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rs1, int rs2, target_long bimm)
+static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
+ target_long bimm)
{
TCGLabel *l = gen_new_label();
TCGv source1, source2;
@@ -603,7 +608,7 @@ static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(l); /* branch taken */
- if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
+ if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
/* misaligned */
gen_exception_inst_addr_mis(ctx);
} else {
@@ -1314,8 +1319,8 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
}
}
-static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
- int rd, int rs1, int csr)
+static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
+ int csr)
{
TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
source1 = tcg_temp_new();
@@ -1361,7 +1366,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_exception_illegal(ctx);
break;
case 0x102: /* SRET */
- if (riscv_has_ext(env, RVS)) {
+ if (has_ext(ctx, RVS)) {
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
@@ -1506,7 +1511,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
}
}
-static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64C1(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
@@ -1526,7 +1531,7 @@ static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
GET_C_IMM(ctx->opcode));
#else
/* C.JAL(RV32) -> jal x1, offset[11:1] */
- gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode));
+ gen_jal(ctx, 1, GET_C_J_IMM(ctx->opcode));
#endif
break;
case 2:
@@ -1605,22 +1610,22 @@ static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
break;
case 5:
/* C.J -> jal x0, offset[11:1]*/
- gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode));
+ gen_jal(ctx, 0, GET_C_J_IMM(ctx->opcode));
break;
case 6:
/* C.BEQZ -> beq rs1', x0, offset[8:1]*/
rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
+ gen_branch(ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
break;
case 7:
/* C.BNEZ -> bne rs1', x0, offset[8:1]*/
rs1s = GET_C_RS1S(ctx->opcode);
- gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
+ gen_branch(ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
break;
}
}
-static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64C2(DisasContext *ctx)
{
uint8_t rd, rs2;
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -1654,7 +1659,7 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
if (extract32(ctx->opcode, 12, 1) == 0) {
if (rs2 == 0) {
/* C.JR -> jalr x0, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0);
+ gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0);
} else {
/* C.MV -> add rd, x0, rs2 */
gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
@@ -1662,11 +1667,11 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
} else {
if (rd == 0) {
/* C.EBREAK -> ebreak*/
- gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1);
+ gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1);
} else {
if (rs2 == 0) {
/* C.JALR -> jalr x1, rs1, 0*/
- gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0);
+ gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0);
} else {
/* C.ADD -> add rd, rd, rs2 */
gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
@@ -1698,7 +1703,7 @@ static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
}
}
-static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64C(DisasContext *ctx)
{
uint8_t op = extract32(ctx->opcode, 0, 2);
@@ -1707,15 +1712,15 @@ static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
decode_RV32_64C0(ctx);
break;
case 1:
- decode_RV32_64C1(env, ctx);
+ decode_RV32_64C1(ctx);
break;
case 2:
- decode_RV32_64C2(env, ctx);
+ decode_RV32_64C2(ctx);
break;
}
}
-static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
+static void decode_RV32_64G(DisasContext *ctx)
{
int rs1;
int rs2;
@@ -1750,13 +1755,13 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
break;
case OPC_RISC_JAL:
imm = GET_JAL_IMM(ctx->opcode);
- gen_jal(env, ctx, rd, imm);
+ gen_jal(ctx, rd, imm);
break;
case OPC_RISC_JALR:
- gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
+ gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
break;
case OPC_RISC_BRANCH:
- gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
+ gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
GET_B_IMM(ctx->opcode));
break;
case OPC_RISC_LOAD:
@@ -1827,7 +1832,7 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
break;
case OPC_RISC_SYSTEM:
- gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
+ gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
break;
default:
@@ -1836,19 +1841,19 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
}
}
-static void decode_opc(CPURISCVState *env, DisasContext *ctx)
+static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
if (extract32(ctx->opcode, 0, 2) != 3) {
- if (!riscv_has_ext(env, RVC)) {
+ if (!has_ext(ctx, RVC)) {
gen_exception_illegal(ctx);
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 2;
- decode_RV32_64C(env, ctx);
+ decode_RV32_64C(ctx);
}
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
- decode_RV32_64G(env, ctx);
+ decode_RV32_64G(ctx);
}
}
@@ -1861,6 +1866,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
ctx->priv_ver = env->priv_ver;
+ ctx->misa = env->misa;
ctx->frm = -1; /* unknown rounding mode */
}
@@ -1891,14 +1897,13 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
return true;
}
-
static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu->env_ptr;
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
- decode_opc(env, ctx);
+ decode_opc(ctx);
ctx->base.pc_next = ctx->pc_succ_insn;
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:58 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
Add misa checks for M, A, F and D extensions and if they are
not present generate illegal instructions. This improves
emulation accurary for harts with a limited set of extensions.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Emilio G. Cota <cota@braap.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 158 +++++++++++++++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7ebea308b4..8593c2170a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -291,24 +291,42 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_and_tl(source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_MUL):
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_mul_tl(source1, source1, source2);
break;
case OPC_RISC_MULH:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_muls2_tl(source2, source1, source1, source2);
break;
case OPC_RISC_MULHSU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
gen_mulhsu(source1, source1, source2);
break;
case OPC_RISC_MULHU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_mulu2_tl(source2, source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_DIVW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
/* fall through to DIV */
#endif
case OPC_RISC_DIV:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
/* Handle by altering args to tcg_gen_div to produce req'd results:
* For overflow: want source1 in source1 and 1 in source2
* For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
@@ -340,11 +358,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_DIVUW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
/* fall through to DIVU */
#endif
case OPC_RISC_DIVU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
@@ -364,11 +388,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_REMW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
/* fall through to REM */
#endif
case OPC_RISC_REM:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
cond1 = tcg_temp_new();
cond2 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
@@ -396,11 +426,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_REMUW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
/* fall through to REMU */
#endif
case OPC_RISC_REMU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
@@ -418,6 +454,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
return;
@@ -698,13 +735,20 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
switch (opc) {
case OPC_RISC_FLW:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
break;
case OPC_RISC_FLD:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -730,11 +774,18 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
switch (opc) {
case OPC_RISC_FSW:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
break;
case OPC_RISC_FSD:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -898,15 +949,22 @@ static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FMADD_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FMADD_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -918,15 +976,22 @@ static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FMSUB_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FMSUB_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -938,15 +1003,22 @@ static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FNMSUB_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FNMSUB_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -958,15 +1030,22 @@ static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FNMADD_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FNMADD_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -985,30 +1064,51 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
switch (opc) {
case OPC_RISC_FADD_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSUB_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FMUL_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FDIV_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSQRT_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
break;
case OPC_RISC_FSGNJ_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
break;
case OPC_RISC_FMIN_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
/* also handles: OPC_RISC_FMAX_S */
switch (rm) {
case 0x0:
@@ -1024,6 +1124,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FEQ_S:
/* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rm) {
case 0x0:
@@ -1045,6 +1148,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_W_S:
/* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rs2) {
case 0: /* FCVT_W_S */
@@ -1075,6 +1181,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_S_W:
/* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
switch (rs2) {
@@ -1104,6 +1213,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMV_X_S:
/* also OPC_RISC_FCLASS_S */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rm) {
case 0: /* FMV */
@@ -1125,6 +1237,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FMV_S_X:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
#if defined(TARGET_RISCV64)
@@ -1137,22 +1252,37 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
/* double */
case OPC_RISC_FADD_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSUB_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FMUL_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FDIV_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSQRT_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
break;
@@ -1162,6 +1292,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMIN_D:
/* also OPC_RISC_FMAX_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rm) {
case 0:
gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
@@ -1175,6 +1308,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FCVT_S_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rs2) {
case 1:
gen_set_rm(ctx, rm);
@@ -1186,6 +1322,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FCVT_D_S:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rs2) {
case 0:
gen_set_rm(ctx, rm);
@@ -1198,6 +1337,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FEQ_D:
/* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rm) {
case 0:
@@ -1219,6 +1361,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_W_D:
/* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rs2) {
case 0:
@@ -1249,6 +1394,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_D_W:
/* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
switch (rs2) {
@@ -1278,6 +1426,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMV_X_D:
/* also OPC_RISC_FCLASS_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rm) {
#if defined(TARGET_RISCV64)
case 0: /* FMV */
@@ -1298,6 +1449,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
#if defined(TARGET_RISCV64)
case OPC_RISC_FMV_D_X:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_mov_tl(cpu_fpr[rd], t0);
@@ -1797,6 +1951,9 @@ static void decode_RV32_64G(DisasContext *ctx)
GET_STORE_IMM(ctx->opcode));
break;
case OPC_RISC_ATOMIC:
+ if (!has_ext(ctx, RVA)) {
+ goto do_illegal;
+ }
gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
break;
case OPC_RISC_FMADD:
@@ -1835,6 +1992,7 @@ static void decode_RV32_64G(DisasContext *ctx)
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate
@ 2019-01-14 23:58 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:58 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
Add misa checks for M, A, F and D extensions and if they are
not present generate illegal instructions. This improves
emulation accurary for harts with a limited set of extensions.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Emilio G. Cota <cota@braap.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 158 +++++++++++++++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7ebea308b4..8593c2170a 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -291,24 +291,42 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_gen_and_tl(source1, source1, source2);
break;
CASE_OP_32_64(OPC_RISC_MUL):
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_mul_tl(source1, source1, source2);
break;
case OPC_RISC_MULH:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_muls2_tl(source2, source1, source1, source2);
break;
case OPC_RISC_MULHSU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
gen_mulhsu(source1, source1, source2);
break;
case OPC_RISC_MULHU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_mulu2_tl(source2, source1, source1, source2);
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_DIVW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
/* fall through to DIV */
#endif
case OPC_RISC_DIV:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
/* Handle by altering args to tcg_gen_div to produce req'd results:
* For overflow: want source1 in source1 and 1 in source2
* For div by zero: want -1 in source1 and 1 in source2 -> -1 result */
@@ -340,11 +358,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_DIVUW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
/* fall through to DIVU */
#endif
case OPC_RISC_DIVU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
@@ -364,11 +388,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_REMW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32s_tl(source1, source1);
tcg_gen_ext32s_tl(source2, source2);
/* fall through to REM */
#endif
case OPC_RISC_REM:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
cond1 = tcg_temp_new();
cond2 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
@@ -396,11 +426,17 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
break;
#if defined(TARGET_RISCV64)
case OPC_RISC_REMUW:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
tcg_gen_ext32u_tl(source1, source1);
tcg_gen_ext32u_tl(source2, source2);
/* fall through to REMU */
#endif
case OPC_RISC_REMU:
+ if (!has_ext(ctx, RVM)) {
+ goto do_illegal;
+ }
cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0);
resultopt1 = tcg_temp_new();
@@ -418,6 +454,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
return;
@@ -698,13 +735,20 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd,
switch (opc) {
case OPC_RISC_FLW:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL);
/* RISC-V requires NaN-boxing of narrower width floating point values */
tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL);
break;
case OPC_RISC_FLD:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -730,11 +774,18 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1,
switch (opc) {
case OPC_RISC_FSW:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL);
break;
case OPC_RISC_FSD:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -898,15 +949,22 @@ static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FMADD_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FMADD_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -918,15 +976,22 @@ static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FMSUB_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FMSUB_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -938,15 +1003,22 @@ static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FNMSUB_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FNMSUB_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -958,15 +1030,22 @@ static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd,
{
switch (opc) {
case OPC_RISC_FNMADD_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
case OPC_RISC_FNMADD_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fnmadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
cpu_fpr[rs2], cpu_fpr[rs3]);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
@@ -985,30 +1064,51 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
switch (opc) {
case OPC_RISC_FADD_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fadd_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSUB_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsub_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FMUL_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmul_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FDIV_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fdiv_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSQRT_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsqrt_s(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
break;
case OPC_RISC_FSGNJ_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN);
break;
case OPC_RISC_FMIN_S:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
/* also handles: OPC_RISC_FMAX_S */
switch (rm) {
case 0x0:
@@ -1024,6 +1124,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FEQ_S:
/* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rm) {
case 0x0:
@@ -1045,6 +1148,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_W_S:
/* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rs2) {
case 0: /* FCVT_W_S */
@@ -1075,6 +1181,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_S_W:
/* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
switch (rs2) {
@@ -1104,6 +1213,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMV_X_S:
/* also OPC_RISC_FCLASS_S */
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rm) {
case 0: /* FMV */
@@ -1125,6 +1237,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FMV_S_X:
+ if (!has_ext(ctx, RVF)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
#if defined(TARGET_RISCV64)
@@ -1137,22 +1252,37 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
/* double */
case OPC_RISC_FADD_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fadd_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSUB_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsub_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FMUL_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fmul_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FDIV_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fdiv_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case OPC_RISC_FSQRT_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
gen_set_rm(ctx, rm);
gen_helper_fsqrt_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1]);
break;
@@ -1162,6 +1292,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMIN_D:
/* also OPC_RISC_FMAX_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rm) {
case 0:
gen_helper_fmin_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1], cpu_fpr[rs2]);
@@ -1175,6 +1308,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FCVT_S_D:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rs2) {
case 1:
gen_set_rm(ctx, rm);
@@ -1186,6 +1322,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
break;
case OPC_RISC_FCVT_D_S:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rs2) {
case 0:
gen_set_rm(ctx, rm);
@@ -1198,6 +1337,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FEQ_D:
/* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rm) {
case 0:
@@ -1219,6 +1361,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_W_D:
/* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
switch (rs2) {
case 0:
@@ -1249,6 +1394,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FCVT_D_W:
/* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
switch (rs2) {
@@ -1278,6 +1426,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
case OPC_RISC_FMV_X_D:
/* also OPC_RISC_FCLASS_D */
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
switch (rm) {
#if defined(TARGET_RISCV64)
case 0: /* FMV */
@@ -1298,6 +1449,9 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd,
#if defined(TARGET_RISCV64)
case OPC_RISC_FMV_D_X:
+ if (!has_ext(ctx, RVD)) {
+ goto do_illegal;
+ }
t0 = tcg_temp_new();
gen_get_gpr(t0, rs1);
tcg_gen_mov_tl(cpu_fpr[rd], t0);
@@ -1797,6 +1951,9 @@ static void decode_RV32_64G(DisasContext *ctx)
GET_STORE_IMM(ctx->opcode));
break;
case OPC_RISC_ATOMIC:
+ if (!has_ext(ctx, RVA)) {
+ goto do_illegal;
+ }
gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2);
break;
case OPC_RISC_FMADD:
@@ -1835,6 +1992,7 @@ static void decode_RV32_64G(DisasContext *ctx)
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
break;
+ do_illegal:
default:
gen_exception_illegal(ctx);
break;
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-devel] [PATCH v1 8/8] RISC-V: Add misa runtime write support
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-14 23:59 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:59 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 4 ++-
target/riscv/cpu_bits.h | 11 +++++++++
target/riscv/csr.c | 54 ++++++++++++++++++++++++++++++++++++++++-
4 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 28d7e5302f..cc3ddc0ae4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,7 +88,7 @@ typedef struct RISCVCPUInfo {
static void set_misa(CPURISCVState *env, target_ulong misa)
{
- env->misa = misa;
+ env->misa_mask = env->misa = misa;
}
static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a97435bd7b..5c2aebf132 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -86,7 +86,8 @@
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU,
- RISCV_FEATURE_PMP
+ RISCV_FEATURE_PMP,
+ RISCV_FEATURE_MISA
};
#define USER_VERSION_2_02_0 0x00020200
@@ -118,6 +119,7 @@ struct CPURISCVState {
target_ulong user_ver;
target_ulong priv_ver;
target_ulong misa;
+ target_ulong misa_mask;
uint32_t features;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5439f4719e..7afcb2468d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -311,10 +311,21 @@
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000ULL
+#define MISA32_MXL 0xC0000000
+#define MISA64_MXL 0xC000000000000000ULL
+
+#define MXL_RV32 1
+#define MXL_RV64 2
+#define MXL_RV128 3
+
#if defined(TARGET_RISCV32)
#define MSTATUS_SD MSTATUS32_SD
+#define MISA_MXL MISA32_MXL
+#define MXL_VAL MXL_RV32
#elif defined(TARGET_RISCV64)
#define MSTATUS_SD MSTATUS64_SD
+#define MISA_MXL MISA64_MXL
+#define MXL_VAL MXL_RV64
#endif
/* sstatus CSR bits */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e2bd374f09..e72fcf1265 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -332,6 +332,58 @@ static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
return 0;
}
+static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
+ /* drop write to misa */
+ return 0;
+ }
+
+ /* 'I' or 'E' must be present */
+ if (!(val & (RVI | RVE))) {
+ /* It is not, drop write to misa */
+ return 0;
+ }
+
+ /* 'E' excludes all other extensions */
+ if (val & RVE) {
+ /* when we support 'E' we can do "val = RVE;" however
+ * for now we just drop writes if 'E' is present.
+ */
+ return 0;
+ }
+
+ /* Mask extensions that are not supported by this hart */
+ val &= env->misa_mask;
+
+ /* Mask extensions that are not supported by QEMU */
+ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+
+ /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
+ if ((val & RVD) && !(val & RVF)) {
+ val &= ~RVD;
+ }
+
+ /* Suppress 'C' if next instruction is not aligned
+ * TODO: this should check next_pc
+ */
+ if ((val & RVC) && (GETPC() & ~3) != 0) {
+ val &= ~RVC;
+ }
+
+ /* misa.MXL writes are not supported by QEMU */
+ val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+
+ /* flush translation cache */
+ if (val != env->misa) {
+ tb_flush(CPU(riscv_env_get_cpu(env)));
+ }
+
+ env->misa = val;
+
+ return 0;
+}
+
static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->medeleg;
@@ -810,7 +862,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine Trap Setup */
[CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
- [CSR_MISA] = { any, read_misa },
+ [CSR_MISA] = { any, read_misa, write_misa },
[CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
[CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
[CSR_MIE] = { any, read_mie, write_mie },
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [Qemu-riscv] [PATCH v1 8/8] RISC-V: Add misa runtime write support
@ 2019-01-14 23:59 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-14 23:59 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: Alistair Francis, alistair23
From: Michael Clark <mjc@sifive.com>
This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 4 ++-
target/riscv/cpu_bits.h | 11 +++++++++
target/riscv/csr.c | 54 ++++++++++++++++++++++++++++++++++++++++-
4 files changed, 68 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 28d7e5302f..cc3ddc0ae4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -88,7 +88,7 @@ typedef struct RISCVCPUInfo {
static void set_misa(CPURISCVState *env, target_ulong misa)
{
- env->misa = misa;
+ env->misa_mask = env->misa = misa;
}
static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a97435bd7b..5c2aebf132 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -86,7 +86,8 @@
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU,
- RISCV_FEATURE_PMP
+ RISCV_FEATURE_PMP,
+ RISCV_FEATURE_MISA
};
#define USER_VERSION_2_02_0 0x00020200
@@ -118,6 +119,7 @@ struct CPURISCVState {
target_ulong user_ver;
target_ulong priv_ver;
target_ulong misa;
+ target_ulong misa_mask;
uint32_t features;
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5439f4719e..7afcb2468d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -311,10 +311,21 @@
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000ULL
+#define MISA32_MXL 0xC0000000
+#define MISA64_MXL 0xC000000000000000ULL
+
+#define MXL_RV32 1
+#define MXL_RV64 2
+#define MXL_RV128 3
+
#if defined(TARGET_RISCV32)
#define MSTATUS_SD MSTATUS32_SD
+#define MISA_MXL MISA32_MXL
+#define MXL_VAL MXL_RV32
#elif defined(TARGET_RISCV64)
#define MSTATUS_SD MSTATUS64_SD
+#define MISA_MXL MISA64_MXL
+#define MXL_VAL MXL_RV64
#endif
/* sstatus CSR bits */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e2bd374f09..e72fcf1265 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -332,6 +332,58 @@ static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
return 0;
}
+static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
+ /* drop write to misa */
+ return 0;
+ }
+
+ /* 'I' or 'E' must be present */
+ if (!(val & (RVI | RVE))) {
+ /* It is not, drop write to misa */
+ return 0;
+ }
+
+ /* 'E' excludes all other extensions */
+ if (val & RVE) {
+ /* when we support 'E' we can do "val = RVE;" however
+ * for now we just drop writes if 'E' is present.
+ */
+ return 0;
+ }
+
+ /* Mask extensions that are not supported by this hart */
+ val &= env->misa_mask;
+
+ /* Mask extensions that are not supported by QEMU */
+ val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+
+ /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
+ if ((val & RVD) && !(val & RVF)) {
+ val &= ~RVD;
+ }
+
+ /* Suppress 'C' if next instruction is not aligned
+ * TODO: this should check next_pc
+ */
+ if ((val & RVC) && (GETPC() & ~3) != 0) {
+ val &= ~RVC;
+ }
+
+ /* misa.MXL writes are not supported by QEMU */
+ val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+
+ /* flush translation cache */
+ if (val != env->misa) {
+ tb_flush(CPU(riscv_env_get_cpu(env)));
+ }
+
+ env->misa = val;
+
+ return 0;
+}
+
static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->medeleg;
@@ -810,7 +862,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* Machine Trap Setup */
[CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
- [CSR_MISA] = { any, read_misa },
+ [CSR_MISA] = { any, read_misa, write_misa },
[CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
[CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
[CSR_MIE] = { any, read_mie, write_mie },
--
2.19.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-15 10:50 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 42+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-01-15 10:50 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
Hi Alistair,
On 1/15/19 12:58 AM, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> * Add riscv prefix to raise_exception function
> * Add riscv prefix to CSR read/write functions
> * Add riscv prefix to signal handler function
> * Add riscv prefix to get fflags function
> * Remove redundant declaration of riscv_cpu_init
> and rename cpu_riscv_init to riscv_cpu_init
> * rename riscv_set_mode to riscv_cpu_set_mode
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> linux-user/riscv/signal.c | 4 ++--
> target/riscv/cpu.h | 21 ++++++++++-----------
> target/riscv/cpu_helper.c | 10 +++++-----
> target/riscv/csr.c | 8 ++++----
> target/riscv/fpu_helper.c | 6 +++---
> target/riscv/op_helper.c | 28 ++++++++++++++--------------
> 6 files changed, 38 insertions(+), 39 deletions(-)
>
> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> index f598d41891..83ecc6f799 100644
> --- a/linux-user/riscv/signal.c
> +++ b/linux-user/riscv/signal.c
> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> __put_user(env->fpr[i], &sc->fpr[i]);
> }
>
> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
> __put_user(fcsr, &sc->fcsr);
> }
>
> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>
> uint32_t fcsr;
> __get_user(fcsr, &sc->fcsr);
> - csr_write_helper(env, fcsr, CSR_FCSR);
> + riscv_csr_write(env, CSR_FCSR, fcsr);
> }
>
> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 681341f5d5..a97435bd7b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
> char *riscv_isa_string(RISCVCPU *cpu);
> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>
> -#define cpu_signal_handler cpu_riscv_signal_handler
> +#define cpu_signal_handler riscv_cpu_signal_handler
> #define cpu_list riscv_cpu_list
> #define cpu_mmu_index riscv_cpu_mmu_index
>
> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> #endif
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>
> void riscv_translate_init(void);
> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> - uint32_t exception, uintptr_t pc);
> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> + uint32_t exception, uintptr_t pc);
>
> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> #define TB_FLAGS_MMU_MASK 3
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask);
>
> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
> - int csrno)
> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
> }
>
> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
Don't you need to update target/riscv/gdbstub.c (in
riscv_cpu_gdb_read_register)?
> {
> target_ulong val = 0;
> riscv_csrrw(env, csrno, &val, 0, 0);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f257050f12..f49e98ed59 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> return old;
> }
>
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> {
> if (newpriv > PRV_M) {
> g_assert_not_reached();
> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> g_assert_not_reached();
> }
> env->badaddr = addr;
> - do_raise_exception_err(env, cs->exception_index, retaddr);
> + riscv_raise_exception(env, cs->exception_index, retaddr);
> }
>
> /* called by qemu's softmmu to fill the qemu tlb */
> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
> if (ret == TRANSLATE_FAIL) {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - do_raise_exception_err(env, cs->exception_index, retaddr);
> + riscv_raise_exception(env, cs->exception_index, retaddr);
> }
> }
>
> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_SPP, env->priv);
> s = set_field(s, MSTATUS_SIE, 0);
> env->mstatus = s;
> - riscv_set_mode(env, PRV_S);
> + riscv_cpu_set_mode(env, PRV_S);
> } else {
> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
> env->pc = env->mtvec;
> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_MPP, env->priv);
> s = set_field(s, MSTATUS_MIE, 0);
> env->mstatus = s;
> - riscv_set_mode(env, PRV_M);
> + riscv_cpu_set_mode(env, PRV_M);
> }
> /* TODO yield load reservation */
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 390d3a9a56..e2bd374f09 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> return -1;
> }
> #endif
> - *val = cpu_riscv_get_fflags(env);
> + *val = riscv_cpu_get_fflags(env);
> return 0;
> }
>
> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
> }
> env->mstatus |= MSTATUS_FS;
> #endif
> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> return 0;
> }
>
> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> return -1;
> }
> #endif
> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> return 0;
> }
> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> return 0;
> }
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 01b45ca0ae..b4f818a646 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -22,7 +22,7 @@
> #include "exec/exec-all.h"
> #include "exec/helper-proto.h"
>
> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
> {
> int soft = get_float_exception_flags(&env->fp_status);
> target_ulong hard = 0;
> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> return hard;
> }
>
> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
> {
> int soft = 0;
>
> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
> softrm = float_round_ties_away;
> break;
> default:
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> set_float_rounding_mode(softrm, &env->fp_status);
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 77c79ba36e..b7dc18a41e 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -25,7 +25,7 @@
> #include "exec/helper-proto.h"
>
> /* Exceptions processing helpers */
> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> uint32_t exception, uintptr_t pc)
> {
> CPUState *cs = CPU(riscv_env_get_cpu(env));
> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>
> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
> {
> - do_raise_exception_err(env, exception, 0);
> + riscv_raise_exception(env, exception, 0);
> }
>
> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_S)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong retpc = env->sepc;
> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> }
>
> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TSR)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong mstatus = env->mstatus;
> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> get_field(mstatus, MSTATUS_SPIE));
> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> - riscv_set_mode(env, prev_priv);
> + riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
>
> return retpc;
> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_M)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong retpc = env->mepc;
> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> }
>
> target_ulong mstatus = env->mstatus;
> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> get_field(mstatus, MSTATUS_MPIE));
> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> - riscv_set_mode(env, prev_priv);
> + riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
>
> return retpc;
> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
> if (env->priv == PRV_S &&
> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TW)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> } else {
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
> if (env->priv == PRV_S &&
> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TVM)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> } else {
> tlb_flush(cs);
> }
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
@ 2019-01-15 10:50 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 42+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-01-15 10:50 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
Hi Alistair,
On 1/15/19 12:58 AM, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> * Add riscv prefix to raise_exception function
> * Add riscv prefix to CSR read/write functions
> * Add riscv prefix to signal handler function
> * Add riscv prefix to get fflags function
> * Remove redundant declaration of riscv_cpu_init
> and rename cpu_riscv_init to riscv_cpu_init
> * rename riscv_set_mode to riscv_cpu_set_mode
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> linux-user/riscv/signal.c | 4 ++--
> target/riscv/cpu.h | 21 ++++++++++-----------
> target/riscv/cpu_helper.c | 10 +++++-----
> target/riscv/csr.c | 8 ++++----
> target/riscv/fpu_helper.c | 6 +++---
> target/riscv/op_helper.c | 28 ++++++++++++++--------------
> 6 files changed, 38 insertions(+), 39 deletions(-)
>
> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> index f598d41891..83ecc6f799 100644
> --- a/linux-user/riscv/signal.c
> +++ b/linux-user/riscv/signal.c
> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> __put_user(env->fpr[i], &sc->fpr[i]);
> }
>
> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
> __put_user(fcsr, &sc->fcsr);
> }
>
> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>
> uint32_t fcsr;
> __get_user(fcsr, &sc->fcsr);
> - csr_write_helper(env, fcsr, CSR_FCSR);
> + riscv_csr_write(env, CSR_FCSR, fcsr);
> }
>
> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 681341f5d5..a97435bd7b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
> char *riscv_isa_string(RISCVCPU *cpu);
> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>
> -#define cpu_signal_handler cpu_riscv_signal_handler
> +#define cpu_signal_handler riscv_cpu_signal_handler
> #define cpu_list riscv_cpu_list
> #define cpu_mmu_index riscv_cpu_mmu_index
>
> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> #endif
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>
> void riscv_translate_init(void);
> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> - uint32_t exception, uintptr_t pc);
> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> + uint32_t exception, uintptr_t pc);
>
> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>
> #define TB_FLAGS_MMU_MASK 3
> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask);
>
> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
> - int csrno)
> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
> + target_ulong val)
> {
> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
> }
>
> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
Don't you need to update target/riscv/gdbstub.c (in
riscv_cpu_gdb_read_register)?
> {
> target_ulong val = 0;
> riscv_csrrw(env, csrno, &val, 0, 0);
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f257050f12..f49e98ed59 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> return old;
> }
>
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> {
> if (newpriv > PRV_M) {
> g_assert_not_reached();
> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> g_assert_not_reached();
> }
> env->badaddr = addr;
> - do_raise_exception_err(env, cs->exception_index, retaddr);
> + riscv_raise_exception(env, cs->exception_index, retaddr);
> }
>
> /* called by qemu's softmmu to fill the qemu tlb */
> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
> if (ret == TRANSLATE_FAIL) {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> - do_raise_exception_err(env, cs->exception_index, retaddr);
> + riscv_raise_exception(env, cs->exception_index, retaddr);
> }
> }
>
> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_SPP, env->priv);
> s = set_field(s, MSTATUS_SIE, 0);
> env->mstatus = s;
> - riscv_set_mode(env, PRV_S);
> + riscv_cpu_set_mode(env, PRV_S);
> } else {
> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
> env->pc = env->mtvec;
> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_MPP, env->priv);
> s = set_field(s, MSTATUS_MIE, 0);
> env->mstatus = s;
> - riscv_set_mode(env, PRV_M);
> + riscv_cpu_set_mode(env, PRV_M);
> }
> /* TODO yield load reservation */
> #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 390d3a9a56..e2bd374f09 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> return -1;
> }
> #endif
> - *val = cpu_riscv_get_fflags(env);
> + *val = riscv_cpu_get_fflags(env);
> return 0;
> }
>
> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
> }
> env->mstatus |= MSTATUS_FS;
> #endif
> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> return 0;
> }
>
> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> return -1;
> }
> #endif
> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> | (env->frm << FSR_RD_SHIFT);
> return 0;
> }
> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> env->mstatus |= MSTATUS_FS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> return 0;
> }
>
> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> index 01b45ca0ae..b4f818a646 100644
> --- a/target/riscv/fpu_helper.c
> +++ b/target/riscv/fpu_helper.c
> @@ -22,7 +22,7 @@
> #include "exec/exec-all.h"
> #include "exec/helper-proto.h"
>
> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
> {
> int soft = get_float_exception_flags(&env->fp_status);
> target_ulong hard = 0;
> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> return hard;
> }
>
> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
> {
> int soft = 0;
>
> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
> softrm = float_round_ties_away;
> break;
> default:
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> set_float_rounding_mode(softrm, &env->fp_status);
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 77c79ba36e..b7dc18a41e 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -25,7 +25,7 @@
> #include "exec/helper-proto.h"
>
> /* Exceptions processing helpers */
> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> uint32_t exception, uintptr_t pc)
> {
> CPUState *cs = CPU(riscv_env_get_cpu(env));
> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>
> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
> {
> - do_raise_exception_err(env, exception, 0);
> + riscv_raise_exception(env, exception, 0);
> }
>
> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> {
> target_ulong val = 0;
> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
> return val;
> }
> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_S)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong retpc = env->sepc;
> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> }
>
> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TSR)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong mstatus = env->mstatus;
> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> get_field(mstatus, MSTATUS_SPIE));
> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> - riscv_set_mode(env, prev_priv);
> + riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
>
> return retpc;
> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> {
> if (!(env->priv >= PRV_M)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> }
>
> target_ulong retpc = env->mepc;
> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> }
>
> target_ulong mstatus = env->mstatus;
> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> get_field(mstatus, MSTATUS_MPIE));
> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> - riscv_set_mode(env, prev_priv);
> + riscv_cpu_set_mode(env, prev_priv);
> env->mstatus = mstatus;
>
> return retpc;
> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
> if (env->priv == PRV_S &&
> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TW)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> } else {
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
> if (env->priv == PRV_S &&
> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> get_field(env->mstatus, MSTATUS_TVM)) {
> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> } else {
> tlb_flush(cs);
> }
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
2019-01-15 10:50 ` [Qemu-riscv] " Philippe Mathieu-Daudé
@ 2019-01-15 17:17 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 42+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-01-15 17:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 11:50 AM, Philippe Mathieu-Daudé wrote:
> Hi Alistair,
>
> On 1/15/19 12:58 AM, Alistair Francis wrote:
>> From: Michael Clark <mjc@sifive.com>
>>
>> * Add riscv prefix to raise_exception function
>> * Add riscv prefix to CSR read/write functions
>> * Add riscv prefix to signal handler function
>> * Add riscv prefix to get fflags function
>> * Remove redundant declaration of riscv_cpu_init
>> and rename cpu_riscv_init to riscv_cpu_init
>> * rename riscv_set_mode to riscv_cpu_set_mode
>>
>> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
>> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>> Cc: Palmer Dabbelt <palmer@sifive.com>
>> Cc: Alistair Francis <Alistair.Francis@wdc.com>
>> Signed-off-by: Michael Clark <mjc@sifive.com>
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> linux-user/riscv/signal.c | 4 ++--
>> target/riscv/cpu.h | 21 ++++++++++-----------
>> target/riscv/cpu_helper.c | 10 +++++-----
>> target/riscv/csr.c | 8 ++++----
>> target/riscv/fpu_helper.c | 6 +++---
>> target/riscv/op_helper.c | 28 ++++++++++++++--------------
>> 6 files changed, 38 insertions(+), 39 deletions(-)
>>
>> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
>> index f598d41891..83ecc6f799 100644
>> --- a/linux-user/riscv/signal.c
>> +++ b/linux-user/riscv/signal.c
>> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
>> __put_user(env->fpr[i], &sc->fpr[i]);
>> }
>>
>> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
>> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
>> __put_user(fcsr, &sc->fcsr);
>> }
>>
>> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>>
>> uint32_t fcsr;
>> __get_user(fcsr, &sc->fcsr);
>> - csr_write_helper(env, fcsr, CSR_FCSR);
>> + riscv_csr_write(env, CSR_FCSR, fcsr);
>> }
>>
>> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 681341f5d5..a97435bd7b 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
>> char *riscv_isa_string(RISCVCPU *cpu);
>> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>>
>> -#define cpu_signal_handler cpu_riscv_signal_handler
>> +#define cpu_signal_handler riscv_cpu_signal_handler
>> #define cpu_list riscv_cpu_list
>> #define cpu_mmu_index riscv_cpu_mmu_index
>>
>> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
>> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
>> #endif
>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>>
>> void riscv_translate_init(void);
>> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
>> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>> - uint32_t exception, uintptr_t pc);
>> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>> + uint32_t exception, uintptr_t pc);
>>
>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>>
>> #define TB_FLAGS_MMU_MASK 3
>> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
>> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>> target_ulong new_value, target_ulong write_mask);
>>
>> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
>> - int csrno)
>> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
>> + target_ulong val)
>> {
>> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
>> }
>>
>> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
>> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
>
> Don't you need to update target/riscv/gdbstub.c (in
> riscv_cpu_gdb_read_register)?
Now than riscv-for-master-3.2-part2 entered /master, I'm more confused
about on which commit this series apply... Don't this diverge since
c7b9517188?
>
>> {
>> target_ulong val = 0;
>> riscv_csrrw(env, csrno, &val, 0, 0);
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index f257050f12..f49e98ed59 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
>> return old;
>> }
>>
>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
>> {
>> if (newpriv > PRV_M) {
>> g_assert_not_reached();
>> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> g_assert_not_reached();
>> }
>> env->badaddr = addr;
>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>> }
>>
>> /* called by qemu's softmmu to fill the qemu tlb */
>> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
>> if (ret == TRANSLATE_FAIL) {
>> RISCVCPU *cpu = RISCV_CPU(cs);
>> CPURISCVState *env = &cpu->env;
>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>> }
>> }
>>
>> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> s = set_field(s, MSTATUS_SPP, env->priv);
>> s = set_field(s, MSTATUS_SIE, 0);
>> env->mstatus = s;
>> - riscv_set_mode(env, PRV_S);
>> + riscv_cpu_set_mode(env, PRV_S);
>> } else {
>> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
>> env->pc = env->mtvec;
>> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> s = set_field(s, MSTATUS_MPP, env->priv);
>> s = set_field(s, MSTATUS_MIE, 0);
>> env->mstatus = s;
>> - riscv_set_mode(env, PRV_M);
>> + riscv_cpu_set_mode(env, PRV_M);
>> }
>> /* TODO yield load reservation */
>> #endif
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 390d3a9a56..e2bd374f09 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>> return -1;
>> }
>> #endif
>> - *val = cpu_riscv_get_fflags(env);
>> + *val = riscv_cpu_get_fflags(env);
>> return 0;
>> }
>>
>> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>> }
>> env->mstatus |= MSTATUS_FS;
>> #endif
>> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>> return 0;
>> }
>>
>> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>> return -1;
>> }
>> #endif
>> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
>> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
>> | (env->frm << FSR_RD_SHIFT);
>> return 0;
>> }
>> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>> env->mstatus |= MSTATUS_FS;
>> #endif
>> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
>> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>> return 0;
>> }
>>
>> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
>> index 01b45ca0ae..b4f818a646 100644
>> --- a/target/riscv/fpu_helper.c
>> +++ b/target/riscv/fpu_helper.c
>> @@ -22,7 +22,7 @@
>> #include "exec/exec-all.h"
>> #include "exec/helper-proto.h"
>>
>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
>> {
>> int soft = get_float_exception_flags(&env->fp_status);
>> target_ulong hard = 0;
>> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>> return hard;
>> }
>>
>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
>> {
>> int soft = 0;
>>
>> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
>> softrm = float_round_ties_away;
>> break;
>> default:
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> set_float_rounding_mode(softrm, &env->fp_status);
>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>> index 77c79ba36e..b7dc18a41e 100644
>> --- a/target/riscv/op_helper.c
>> +++ b/target/riscv/op_helper.c
>> @@ -25,7 +25,7 @@
>> #include "exec/helper-proto.h"
>>
>> /* Exceptions processing helpers */
>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>> uint32_t exception, uintptr_t pc)
>> {
>> CPUState *cs = CPU(riscv_env_get_cpu(env));
>> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>
>> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
>> {
>> - do_raise_exception_err(env, exception, 0);
>> + riscv_raise_exception(env, exception, 0);
>> }
>>
>> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>> {
>> target_ulong val = 0;
>> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>> return val;
>> }
>> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
>> {
>> target_ulong val = 0;
>> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>> return val;
>> }
>> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>> {
>> target_ulong val = 0;
>> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>> return val;
>> }
>> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> {
>> if (!(env->priv >= PRV_S)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> target_ulong retpc = env->sepc;
>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> }
>>
>> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> get_field(env->mstatus, MSTATUS_TSR)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> target_ulong mstatus = env->mstatus;
>> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> get_field(mstatus, MSTATUS_SPIE));
>> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
>> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
>> - riscv_set_mode(env, prev_priv);
>> + riscv_cpu_set_mode(env, prev_priv);
>> env->mstatus = mstatus;
>>
>> return retpc;
>> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> {
>> if (!(env->priv >= PRV_M)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> target_ulong retpc = env->mepc;
>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> }
>>
>> target_ulong mstatus = env->mstatus;
>> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> get_field(mstatus, MSTATUS_MPIE));
>> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
>> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
>> - riscv_set_mode(env, prev_priv);
>> + riscv_cpu_set_mode(env, prev_priv);
>> env->mstatus = mstatus;
>>
>> return retpc;
>> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
>> if (env->priv == PRV_S &&
>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> get_field(env->mstatus, MSTATUS_TW)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> } else {
>> cs->halted = 1;
>> cs->exception_index = EXCP_HLT;
>> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
>> if (env->priv == PRV_S &&
>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> get_field(env->mstatus, MSTATUS_TVM)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> } else {
>> tlb_flush(cs);
>> }
>>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
@ 2019-01-15 17:17 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 42+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-01-15 17:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 11:50 AM, Philippe Mathieu-Daudé wrote:
> Hi Alistair,
>
> On 1/15/19 12:58 AM, Alistair Francis wrote:
>> From: Michael Clark <mjc@sifive.com>
>>
>> * Add riscv prefix to raise_exception function
>> * Add riscv prefix to CSR read/write functions
>> * Add riscv prefix to signal handler function
>> * Add riscv prefix to get fflags function
>> * Remove redundant declaration of riscv_cpu_init
>> and rename cpu_riscv_init to riscv_cpu_init
>> * rename riscv_set_mode to riscv_cpu_set_mode
>>
>> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
>> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>> Cc: Palmer Dabbelt <palmer@sifive.com>
>> Cc: Alistair Francis <Alistair.Francis@wdc.com>
>> Signed-off-by: Michael Clark <mjc@sifive.com>
>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> linux-user/riscv/signal.c | 4 ++--
>> target/riscv/cpu.h | 21 ++++++++++-----------
>> target/riscv/cpu_helper.c | 10 +++++-----
>> target/riscv/csr.c | 8 ++++----
>> target/riscv/fpu_helper.c | 6 +++---
>> target/riscv/op_helper.c | 28 ++++++++++++++--------------
>> 6 files changed, 38 insertions(+), 39 deletions(-)
>>
>> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
>> index f598d41891..83ecc6f799 100644
>> --- a/linux-user/riscv/signal.c
>> +++ b/linux-user/riscv/signal.c
>> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
>> __put_user(env->fpr[i], &sc->fpr[i]);
>> }
>>
>> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
>> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
>> __put_user(fcsr, &sc->fcsr);
>> }
>>
>> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>>
>> uint32_t fcsr;
>> __get_user(fcsr, &sc->fcsr);
>> - csr_write_helper(env, fcsr, CSR_FCSR);
>> + riscv_csr_write(env, CSR_FCSR, fcsr);
>> }
>>
>> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 681341f5d5..a97435bd7b 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
>> char *riscv_isa_string(RISCVCPU *cpu);
>> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>>
>> -#define cpu_signal_handler cpu_riscv_signal_handler
>> +#define cpu_signal_handler riscv_cpu_signal_handler
>> #define cpu_list riscv_cpu_list
>> #define cpu_mmu_index riscv_cpu_mmu_index
>>
>> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
>> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
>> #endif
>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>>
>> void riscv_translate_init(void);
>> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
>> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>> - uint32_t exception, uintptr_t pc);
>> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>> + uint32_t exception, uintptr_t pc);
>>
>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>>
>> #define TB_FLAGS_MMU_MASK 3
>> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
>> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>> target_ulong new_value, target_ulong write_mask);
>>
>> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
>> - int csrno)
>> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
>> + target_ulong val)
>> {
>> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
>> }
>>
>> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
>> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
>
> Don't you need to update target/riscv/gdbstub.c (in
> riscv_cpu_gdb_read_register)?
Now than riscv-for-master-3.2-part2 entered /master, I'm more confused
about on which commit this series apply... Don't this diverge since
c7b9517188?
>
>> {
>> target_ulong val = 0;
>> riscv_csrrw(env, csrno, &val, 0, 0);
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index f257050f12..f49e98ed59 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
>> return old;
>> }
>>
>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
>> {
>> if (newpriv > PRV_M) {
>> g_assert_not_reached();
>> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> g_assert_not_reached();
>> }
>> env->badaddr = addr;
>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>> }
>>
>> /* called by qemu's softmmu to fill the qemu tlb */
>> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
>> if (ret == TRANSLATE_FAIL) {
>> RISCVCPU *cpu = RISCV_CPU(cs);
>> CPURISCVState *env = &cpu->env;
>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>> }
>> }
>>
>> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> s = set_field(s, MSTATUS_SPP, env->priv);
>> s = set_field(s, MSTATUS_SIE, 0);
>> env->mstatus = s;
>> - riscv_set_mode(env, PRV_S);
>> + riscv_cpu_set_mode(env, PRV_S);
>> } else {
>> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
>> env->pc = env->mtvec;
>> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> s = set_field(s, MSTATUS_MPP, env->priv);
>> s = set_field(s, MSTATUS_MIE, 0);
>> env->mstatus = s;
>> - riscv_set_mode(env, PRV_M);
>> + riscv_cpu_set_mode(env, PRV_M);
>> }
>> /* TODO yield load reservation */
>> #endif
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index 390d3a9a56..e2bd374f09 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>> return -1;
>> }
>> #endif
>> - *val = cpu_riscv_get_fflags(env);
>> + *val = riscv_cpu_get_fflags(env);
>> return 0;
>> }
>>
>> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>> }
>> env->mstatus |= MSTATUS_FS;
>> #endif
>> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>> return 0;
>> }
>>
>> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>> return -1;
>> }
>> #endif
>> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
>> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
>> | (env->frm << FSR_RD_SHIFT);
>> return 0;
>> }
>> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>> env->mstatus |= MSTATUS_FS;
>> #endif
>> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
>> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>> return 0;
>> }
>>
>> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
>> index 01b45ca0ae..b4f818a646 100644
>> --- a/target/riscv/fpu_helper.c
>> +++ b/target/riscv/fpu_helper.c
>> @@ -22,7 +22,7 @@
>> #include "exec/exec-all.h"
>> #include "exec/helper-proto.h"
>>
>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
>> {
>> int soft = get_float_exception_flags(&env->fp_status);
>> target_ulong hard = 0;
>> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>> return hard;
>> }
>>
>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
>> {
>> int soft = 0;
>>
>> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
>> softrm = float_round_ties_away;
>> break;
>> default:
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> set_float_rounding_mode(softrm, &env->fp_status);
>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>> index 77c79ba36e..b7dc18a41e 100644
>> --- a/target/riscv/op_helper.c
>> +++ b/target/riscv/op_helper.c
>> @@ -25,7 +25,7 @@
>> #include "exec/helper-proto.h"
>>
>> /* Exceptions processing helpers */
>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>> uint32_t exception, uintptr_t pc)
>> {
>> CPUState *cs = CPU(riscv_env_get_cpu(env));
>> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>
>> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
>> {
>> - do_raise_exception_err(env, exception, 0);
>> + riscv_raise_exception(env, exception, 0);
>> }
>>
>> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>> {
>> target_ulong val = 0;
>> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>> return val;
>> }
>> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
>> {
>> target_ulong val = 0;
>> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>> return val;
>> }
>> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>> {
>> target_ulong val = 0;
>> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>> return val;
>> }
>> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> {
>> if (!(env->priv >= PRV_S)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> target_ulong retpc = env->sepc;
>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> }
>>
>> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> get_field(env->mstatus, MSTATUS_TSR)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> target_ulong mstatus = env->mstatus;
>> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> get_field(mstatus, MSTATUS_SPIE));
>> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
>> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
>> - riscv_set_mode(env, prev_priv);
>> + riscv_cpu_set_mode(env, prev_priv);
>> env->mstatus = mstatus;
>>
>> return retpc;
>> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> {
>> if (!(env->priv >= PRV_M)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> }
>>
>> target_ulong retpc = env->mepc;
>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>> }
>>
>> target_ulong mstatus = env->mstatus;
>> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>> get_field(mstatus, MSTATUS_MPIE));
>> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
>> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
>> - riscv_set_mode(env, prev_priv);
>> + riscv_cpu_set_mode(env, prev_priv);
>> env->mstatus = mstatus;
>>
>> return retpc;
>> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
>> if (env->priv == PRV_S &&
>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> get_field(env->mstatus, MSTATUS_TW)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> } else {
>> cs->halted = 1;
>> cs->exception_index = EXCP_HLT;
>> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
>> if (env->priv == PRV_S &&
>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>> get_field(env->mstatus, MSTATUS_TVM)) {
>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>> } else {
>> tlb_flush(cs);
>> }
>>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
2019-01-15 17:17 ` [Qemu-riscv] " Philippe Mathieu-Daudé
@ 2019-01-15 17:50 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-15 17:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Tue, Jan 15, 2019 at 9:17 AM Philippe Mathieu-Daudé
<philmd@redhat.com> wrote:
>
> On 1/15/19 11:50 AM, Philippe Mathieu-Daudé wrote:
> > Hi Alistair,
> >
> > On 1/15/19 12:58 AM, Alistair Francis wrote:
> >> From: Michael Clark <mjc@sifive.com>
> >>
> >> * Add riscv prefix to raise_exception function
> >> * Add riscv prefix to CSR read/write functions
> >> * Add riscv prefix to signal handler function
> >> * Add riscv prefix to get fflags function
> >> * Remove redundant declaration of riscv_cpu_init
> >> and rename cpu_riscv_init to riscv_cpu_init
> >> * rename riscv_set_mode to riscv_cpu_set_mode
> >>
> >> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> >> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> >> Cc: Palmer Dabbelt <palmer@sifive.com>
> >> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> >> Signed-off-by: Michael Clark <mjc@sifive.com>
> >> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> ---
> >> linux-user/riscv/signal.c | 4 ++--
> >> target/riscv/cpu.h | 21 ++++++++++-----------
> >> target/riscv/cpu_helper.c | 10 +++++-----
> >> target/riscv/csr.c | 8 ++++----
> >> target/riscv/fpu_helper.c | 6 +++---
> >> target/riscv/op_helper.c | 28 ++++++++++++++--------------
> >> 6 files changed, 38 insertions(+), 39 deletions(-)
> >>
> >> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> >> index f598d41891..83ecc6f799 100644
> >> --- a/linux-user/riscv/signal.c
> >> +++ b/linux-user/riscv/signal.c
> >> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> >> __put_user(env->fpr[i], &sc->fpr[i]);
> >> }
> >>
> >> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
> >> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
> >> __put_user(fcsr, &sc->fcsr);
> >> }
> >>
> >> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
> >>
> >> uint32_t fcsr;
> >> __get_user(fcsr, &sc->fcsr);
> >> - csr_write_helper(env, fcsr, CSR_FCSR);
> >> + riscv_csr_write(env, CSR_FCSR, fcsr);
> >> }
> >>
> >> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> >> index 681341f5d5..a97435bd7b 100644
> >> --- a/target/riscv/cpu.h
> >> +++ b/target/riscv/cpu.h
> >> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
> >> char *riscv_isa_string(RISCVCPU *cpu);
> >> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> >>
> >> -#define cpu_signal_handler cpu_riscv_signal_handler
> >> +#define cpu_signal_handler riscv_cpu_signal_handler
> >> #define cpu_list riscv_cpu_list
> >> #define cpu_mmu_index riscv_cpu_mmu_index
> >>
> >> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> >> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> >> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> >> #endif
> >> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
> >> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
> >>
> >> void riscv_translate_init(void);
> >> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
> >> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
> >> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> >> - uint32_t exception, uintptr_t pc);
> >> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> >> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> >> + uint32_t exception, uintptr_t pc);
> >>
> >> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> >> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
> >> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
> >> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
> >>
> >> #define TB_FLAGS_MMU_MASK 3
> >> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> >> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> >> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> >> target_ulong new_value, target_ulong write_mask);
> >>
> >> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
> >> - int csrno)
> >> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
> >> + target_ulong val)
> >> {
> >> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
> >> }
> >>
> >> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
> >> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
> >
> > Don't you need to update target/riscv/gdbstub.c (in
> > riscv_cpu_gdb_read_register)?
I don't think so, in master there is no call to csr_read_helper() in
the gdbstub.c file
>
> Now than riscv-for-master-3.2-part2 entered /master, I'm more confused
> about on which commit this series apply... Don't this diverge since
> c7b9517188?
This applies on top of master (with the riscv-for-master-3.2-part2
patches in master).
Alistair
>
> >
> >> {
> >> target_ulong val = 0;
> >> riscv_csrrw(env, csrno, &val, 0, 0);
> >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >> index f257050f12..f49e98ed59 100644
> >> --- a/target/riscv/cpu_helper.c
> >> +++ b/target/riscv/cpu_helper.c
> >> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> >> return old;
> >> }
> >>
> >> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> >> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> >> {
> >> if (newpriv > PRV_M) {
> >> g_assert_not_reached();
> >> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> >> g_assert_not_reached();
> >> }
> >> env->badaddr = addr;
> >> - do_raise_exception_err(env, cs->exception_index, retaddr);
> >> + riscv_raise_exception(env, cs->exception_index, retaddr);
> >> }
> >>
> >> /* called by qemu's softmmu to fill the qemu tlb */
> >> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
> >> if (ret == TRANSLATE_FAIL) {
> >> RISCVCPU *cpu = RISCV_CPU(cs);
> >> CPURISCVState *env = &cpu->env;
> >> - do_raise_exception_err(env, cs->exception_index, retaddr);
> >> + riscv_raise_exception(env, cs->exception_index, retaddr);
> >> }
> >> }
> >>
> >> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >> s = set_field(s, MSTATUS_SPP, env->priv);
> >> s = set_field(s, MSTATUS_SIE, 0);
> >> env->mstatus = s;
> >> - riscv_set_mode(env, PRV_S);
> >> + riscv_cpu_set_mode(env, PRV_S);
> >> } else {
> >> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
> >> env->pc = env->mtvec;
> >> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >> s = set_field(s, MSTATUS_MPP, env->priv);
> >> s = set_field(s, MSTATUS_MIE, 0);
> >> env->mstatus = s;
> >> - riscv_set_mode(env, PRV_M);
> >> + riscv_cpu_set_mode(env, PRV_M);
> >> }
> >> /* TODO yield load reservation */
> >> #endif
> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> >> index 390d3a9a56..e2bd374f09 100644
> >> --- a/target/riscv/csr.c
> >> +++ b/target/riscv/csr.c
> >> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> >> return -1;
> >> }
> >> #endif
> >> - *val = cpu_riscv_get_fflags(env);
> >> + *val = riscv_cpu_get_fflags(env);
> >> return 0;
> >> }
> >>
> >> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
> >> }
> >> env->mstatus |= MSTATUS_FS;
> >> #endif
> >> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> >> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> >> return 0;
> >> }
> >>
> >> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> >> return -1;
> >> }
> >> #endif
> >> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> >> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> >> | (env->frm << FSR_RD_SHIFT);
> >> return 0;
> >> }
> >> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> >> env->mstatus |= MSTATUS_FS;
> >> #endif
> >> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> >> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> >> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> >> return 0;
> >> }
> >>
> >> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> >> index 01b45ca0ae..b4f818a646 100644
> >> --- a/target/riscv/fpu_helper.c
> >> +++ b/target/riscv/fpu_helper.c
> >> @@ -22,7 +22,7 @@
> >> #include "exec/exec-all.h"
> >> #include "exec/helper-proto.h"
> >>
> >> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> >> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
> >> {
> >> int soft = get_float_exception_flags(&env->fp_status);
> >> target_ulong hard = 0;
> >> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> >> return hard;
> >> }
> >>
> >> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
> >> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
> >> {
> >> int soft = 0;
> >>
> >> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
> >> softrm = float_round_ties_away;
> >> break;
> >> default:
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> set_float_rounding_mode(softrm, &env->fp_status);
> >> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> >> index 77c79ba36e..b7dc18a41e 100644
> >> --- a/target/riscv/op_helper.c
> >> +++ b/target/riscv/op_helper.c
> >> @@ -25,7 +25,7 @@
> >> #include "exec/helper-proto.h"
> >>
> >> /* Exceptions processing helpers */
> >> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> >> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> >> uint32_t exception, uintptr_t pc)
> >> {
> >> CPUState *cs = CPU(riscv_env_get_cpu(env));
> >> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> >>
> >> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
> >> {
> >> - do_raise_exception_err(env, exception, 0);
> >> + riscv_raise_exception(env, exception, 0);
> >> }
> >>
> >> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> >> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> >> {
> >> target_ulong val = 0;
> >> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >> return val;
> >> }
> >> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
> >> {
> >> target_ulong val = 0;
> >> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >> return val;
> >> }
> >> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> >> {
> >> target_ulong val = 0;
> >> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >> return val;
> >> }
> >> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> >> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> {
> >> if (!(env->priv >= PRV_S)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> target_ulong retpc = env->sepc;
> >> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> }
> >>
> >> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
> >> get_field(env->mstatus, MSTATUS_TSR)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> target_ulong mstatus = env->mstatus;
> >> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> get_field(mstatus, MSTATUS_SPIE));
> >> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> >> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> >> - riscv_set_mode(env, prev_priv);
> >> + riscv_cpu_set_mode(env, prev_priv);
> >> env->mstatus = mstatus;
> >>
> >> return retpc;
> >> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> {
> >> if (!(env->priv >= PRV_M)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> target_ulong retpc = env->mepc;
> >> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> }
> >>
> >> target_ulong mstatus = env->mstatus;
> >> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> get_field(mstatus, MSTATUS_MPIE));
> >> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> >> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> >> - riscv_set_mode(env, prev_priv);
> >> + riscv_cpu_set_mode(env, prev_priv);
> >> env->mstatus = mstatus;
> >>
> >> return retpc;
> >> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
> >> if (env->priv == PRV_S &&
> >> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> >> get_field(env->mstatus, MSTATUS_TW)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> } else {
> >> cs->halted = 1;
> >> cs->exception_index = EXCP_HLT;
> >> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
> >> if (env->priv == PRV_S &&
> >> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> >> get_field(env->mstatus, MSTATUS_TVM)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> } else {
> >> tlb_flush(cs);
> >> }
> >>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
@ 2019-01-15 17:50 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-15 17:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Tue, Jan 15, 2019 at 9:17 AM Philippe Mathieu-Daudé
<philmd@redhat.com> wrote:
>
> On 1/15/19 11:50 AM, Philippe Mathieu-Daudé wrote:
> > Hi Alistair,
> >
> > On 1/15/19 12:58 AM, Alistair Francis wrote:
> >> From: Michael Clark <mjc@sifive.com>
> >>
> >> * Add riscv prefix to raise_exception function
> >> * Add riscv prefix to CSR read/write functions
> >> * Add riscv prefix to signal handler function
> >> * Add riscv prefix to get fflags function
> >> * Remove redundant declaration of riscv_cpu_init
> >> and rename cpu_riscv_init to riscv_cpu_init
> >> * rename riscv_set_mode to riscv_cpu_set_mode
> >>
> >> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> >> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> >> Cc: Palmer Dabbelt <palmer@sifive.com>
> >> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> >> Signed-off-by: Michael Clark <mjc@sifive.com>
> >> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> >> ---
> >> linux-user/riscv/signal.c | 4 ++--
> >> target/riscv/cpu.h | 21 ++++++++++-----------
> >> target/riscv/cpu_helper.c | 10 +++++-----
> >> target/riscv/csr.c | 8 ++++----
> >> target/riscv/fpu_helper.c | 6 +++---
> >> target/riscv/op_helper.c | 28 ++++++++++++++--------------
> >> 6 files changed, 38 insertions(+), 39 deletions(-)
> >>
> >> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
> >> index f598d41891..83ecc6f799 100644
> >> --- a/linux-user/riscv/signal.c
> >> +++ b/linux-user/riscv/signal.c
> >> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
> >> __put_user(env->fpr[i], &sc->fpr[i]);
> >> }
> >>
> >> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
> >> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
> >> __put_user(fcsr, &sc->fcsr);
> >> }
> >>
> >> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
> >>
> >> uint32_t fcsr;
> >> __get_user(fcsr, &sc->fcsr);
> >> - csr_write_helper(env, fcsr, CSR_FCSR);
> >> + riscv_csr_write(env, CSR_FCSR, fcsr);
> >> }
> >>
> >> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
> >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> >> index 681341f5d5..a97435bd7b 100644
> >> --- a/target/riscv/cpu.h
> >> +++ b/target/riscv/cpu.h
> >> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
> >> char *riscv_isa_string(RISCVCPU *cpu);
> >> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> >>
> >> -#define cpu_signal_handler cpu_riscv_signal_handler
> >> +#define cpu_signal_handler riscv_cpu_signal_handler
> >> #define cpu_list riscv_cpu_list
> >> #define cpu_mmu_index riscv_cpu_mmu_index
> >>
> >> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> >> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
> >> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
> >> #endif
> >> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
> >> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
> >>
> >> void riscv_translate_init(void);
> >> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
> >> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
> >> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> >> - uint32_t exception, uintptr_t pc);
> >> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> >> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> >> + uint32_t exception, uintptr_t pc);
> >>
> >> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> >> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
> >> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
> >> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
> >>
> >> #define TB_FLAGS_MMU_MASK 3
> >> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
> >> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> >> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> >> target_ulong new_value, target_ulong write_mask);
> >>
> >> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
> >> - int csrno)
> >> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
> >> + target_ulong val)
> >> {
> >> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
> >> }
> >>
> >> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
> >> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
> >
> > Don't you need to update target/riscv/gdbstub.c (in
> > riscv_cpu_gdb_read_register)?
I don't think so, in master there is no call to csr_read_helper() in
the gdbstub.c file
>
> Now than riscv-for-master-3.2-part2 entered /master, I'm more confused
> about on which commit this series apply... Don't this diverge since
> c7b9517188?
This applies on top of master (with the riscv-for-master-3.2-part2
patches in master).
Alistair
>
> >
> >> {
> >> target_ulong val = 0;
> >> riscv_csrrw(env, csrno, &val, 0, 0);
> >> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >> index f257050f12..f49e98ed59 100644
> >> --- a/target/riscv/cpu_helper.c
> >> +++ b/target/riscv/cpu_helper.c
> >> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
> >> return old;
> >> }
> >>
> >> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> >> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> >> {
> >> if (newpriv > PRV_M) {
> >> g_assert_not_reached();
> >> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> >> g_assert_not_reached();
> >> }
> >> env->badaddr = addr;
> >> - do_raise_exception_err(env, cs->exception_index, retaddr);
> >> + riscv_raise_exception(env, cs->exception_index, retaddr);
> >> }
> >>
> >> /* called by qemu's softmmu to fill the qemu tlb */
> >> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
> >> if (ret == TRANSLATE_FAIL) {
> >> RISCVCPU *cpu = RISCV_CPU(cs);
> >> CPURISCVState *env = &cpu->env;
> >> - do_raise_exception_err(env, cs->exception_index, retaddr);
> >> + riscv_raise_exception(env, cs->exception_index, retaddr);
> >> }
> >> }
> >>
> >> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >> s = set_field(s, MSTATUS_SPP, env->priv);
> >> s = set_field(s, MSTATUS_SIE, 0);
> >> env->mstatus = s;
> >> - riscv_set_mode(env, PRV_S);
> >> + riscv_cpu_set_mode(env, PRV_S);
> >> } else {
> >> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
> >> env->pc = env->mtvec;
> >> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >> s = set_field(s, MSTATUS_MPP, env->priv);
> >> s = set_field(s, MSTATUS_MIE, 0);
> >> env->mstatus = s;
> >> - riscv_set_mode(env, PRV_M);
> >> + riscv_cpu_set_mode(env, PRV_M);
> >> }
> >> /* TODO yield load reservation */
> >> #endif
> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> >> index 390d3a9a56..e2bd374f09 100644
> >> --- a/target/riscv/csr.c
> >> +++ b/target/riscv/csr.c
> >> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
> >> return -1;
> >> }
> >> #endif
> >> - *val = cpu_riscv_get_fflags(env);
> >> + *val = riscv_cpu_get_fflags(env);
> >> return 0;
> >> }
> >>
> >> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
> >> }
> >> env->mstatus |= MSTATUS_FS;
> >> #endif
> >> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> >> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
> >> return 0;
> >> }
> >>
> >> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
> >> return -1;
> >> }
> >> #endif
> >> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
> >> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
> >> | (env->frm << FSR_RD_SHIFT);
> >> return 0;
> >> }
> >> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
> >> env->mstatus |= MSTATUS_FS;
> >> #endif
> >> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> >> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> >> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
> >> return 0;
> >> }
> >>
> >> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
> >> index 01b45ca0ae..b4f818a646 100644
> >> --- a/target/riscv/fpu_helper.c
> >> +++ b/target/riscv/fpu_helper.c
> >> @@ -22,7 +22,7 @@
> >> #include "exec/exec-all.h"
> >> #include "exec/helper-proto.h"
> >>
> >> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> >> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
> >> {
> >> int soft = get_float_exception_flags(&env->fp_status);
> >> target_ulong hard = 0;
> >> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
> >> return hard;
> >> }
> >>
> >> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
> >> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
> >> {
> >> int soft = 0;
> >>
> >> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
> >> softrm = float_round_ties_away;
> >> break;
> >> default:
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> set_float_rounding_mode(softrm, &env->fp_status);
> >> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> >> index 77c79ba36e..b7dc18a41e 100644
> >> --- a/target/riscv/op_helper.c
> >> +++ b/target/riscv/op_helper.c
> >> @@ -25,7 +25,7 @@
> >> #include "exec/helper-proto.h"
> >>
> >> /* Exceptions processing helpers */
> >> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> >> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
> >> uint32_t exception, uintptr_t pc)
> >> {
> >> CPUState *cs = CPU(riscv_env_get_cpu(env));
> >> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
> >>
> >> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
> >> {
> >> - do_raise_exception_err(env, exception, 0);
> >> + riscv_raise_exception(env, exception, 0);
> >> }
> >>
> >> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> >> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
> >> {
> >> target_ulong val = 0;
> >> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >> return val;
> >> }
> >> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
> >> {
> >> target_ulong val = 0;
> >> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >> return val;
> >> }
> >> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> >> {
> >> target_ulong val = 0;
> >> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >> return val;
> >> }
> >> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
> >> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> {
> >> if (!(env->priv >= PRV_S)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> target_ulong retpc = env->sepc;
> >> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> }
> >>
> >> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
> >> get_field(env->mstatus, MSTATUS_TSR)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> target_ulong mstatus = env->mstatus;
> >> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> get_field(mstatus, MSTATUS_SPIE));
> >> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
> >> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
> >> - riscv_set_mode(env, prev_priv);
> >> + riscv_cpu_set_mode(env, prev_priv);
> >> env->mstatus = mstatus;
> >>
> >> return retpc;
> >> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> {
> >> if (!(env->priv >= PRV_M)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> }
> >>
> >> target_ulong retpc = env->mepc;
> >> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
> >> }
> >>
> >> target_ulong mstatus = env->mstatus;
> >> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
> >> get_field(mstatus, MSTATUS_MPIE));
> >> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
> >> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
> >> - riscv_set_mode(env, prev_priv);
> >> + riscv_cpu_set_mode(env, prev_priv);
> >> env->mstatus = mstatus;
> >>
> >> return retpc;
> >> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
> >> if (env->priv == PRV_S &&
> >> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> >> get_field(env->mstatus, MSTATUS_TW)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> } else {
> >> cs->halted = 1;
> >> cs->exception_index = EXCP_HLT;
> >> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
> >> if (env->priv == PRV_S &&
> >> env->priv_ver >= PRIV_VERSION_1_10_0 &&
> >> get_field(env->mstatus, MSTATUS_TVM)) {
> >> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> >> } else {
> >> tlb_flush(cs);
> >> }
> >>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
2019-01-15 17:50 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-15 19:03 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 42+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-01-15 19:03 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On 1/15/19 6:50 PM, Alistair Francis wrote:
> On Tue, Jan 15, 2019 at 9:17 AM Philippe Mathieu-Daudé
> <philmd@redhat.com> wrote:
>>
>> On 1/15/19 11:50 AM, Philippe Mathieu-Daudé wrote:
>>> Hi Alistair,
>>>
>>> On 1/15/19 12:58 AM, Alistair Francis wrote:
>>>> From: Michael Clark <mjc@sifive.com>
>>>>
>>>> * Add riscv prefix to raise_exception function
>>>> * Add riscv prefix to CSR read/write functions
>>>> * Add riscv prefix to signal handler function
>>>> * Add riscv prefix to get fflags function
>>>> * Remove redundant declaration of riscv_cpu_init
>>>> and rename cpu_riscv_init to riscv_cpu_init
>>>> * rename riscv_set_mode to riscv_cpu_set_mode
>>>>
>>>> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
>>>> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>>>> Cc: Palmer Dabbelt <palmer@sifive.com>
>>>> Cc: Alistair Francis <Alistair.Francis@wdc.com>
>>>> Signed-off-by: Michael Clark <mjc@sifive.com>
>>>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>>>> ---
>>>> linux-user/riscv/signal.c | 4 ++--
>>>> target/riscv/cpu.h | 21 ++++++++++-----------
>>>> target/riscv/cpu_helper.c | 10 +++++-----
>>>> target/riscv/csr.c | 8 ++++----
>>>> target/riscv/fpu_helper.c | 6 +++---
>>>> target/riscv/op_helper.c | 28 ++++++++++++++--------------
>>>> 6 files changed, 38 insertions(+), 39 deletions(-)
>>>>
>>>> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
>>>> index f598d41891..83ecc6f799 100644
>>>> --- a/linux-user/riscv/signal.c
>>>> +++ b/linux-user/riscv/signal.c
>>>> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
>>>> __put_user(env->fpr[i], &sc->fpr[i]);
>>>> }
>>>>
>>>> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
>>>> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
>>>> __put_user(fcsr, &sc->fcsr);
>>>> }
>>>>
>>>> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>>>>
>>>> uint32_t fcsr;
>>>> __get_user(fcsr, &sc->fcsr);
>>>> - csr_write_helper(env, fcsr, CSR_FCSR);
>>>> + riscv_csr_write(env, CSR_FCSR, fcsr);
>>>> }
>>>>
>>>> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>>> index 681341f5d5..a97435bd7b 100644
>>>> --- a/target/riscv/cpu.h
>>>> +++ b/target/riscv/cpu.h
>>>> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
>>>> char *riscv_isa_string(RISCVCPU *cpu);
>>>> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>>>>
>>>> -#define cpu_signal_handler cpu_riscv_signal_handler
>>>> +#define cpu_signal_handler riscv_cpu_signal_handler
>>>> #define cpu_list riscv_cpu_list
>>>> #define cpu_mmu_index riscv_cpu_mmu_index
>>>>
>>>> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>>>> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
>>>> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
>>>> #endif
>>>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
>>>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>>>>
>>>> void riscv_translate_init(void);
>>>> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
>>>> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
>>>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>>> - uint32_t exception, uintptr_t pc);
>>>> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
>>>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>>>> + uint32_t exception, uintptr_t pc);
>>>>
>>>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
>>>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
>>>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>>>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>>>>
>>>> #define TB_FLAGS_MMU_MASK 3
>>>> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
>>>> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>>>> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>>>> target_ulong new_value, target_ulong write_mask);
>>>>
>>>> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
>>>> - int csrno)
>>>> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
>>>> + target_ulong val)
>>>> {
>>>> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
>>>> }
>>>>
>>>> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
>>>> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
>>>
>>> Don't you need to update target/riscv/gdbstub.c (in
>>> riscv_cpu_gdb_read_register)?
>
> I don't think so, in master there is no call to csr_read_helper() in
> the gdbstub.c file
>
>>
>> Now than riscv-for-master-3.2-part2 entered /master, I'm more confused
>> about on which commit this series apply... Don't this diverge since
>> c7b9517188?
>
> This applies on top of master (with the riscv-for-master-3.2-part2
> patches in master).
Indeed. The series was missing a note about using
'riscv-for-master-3.2-part2' as a base in the cover when I first tried;
2nd try I messed locally and was in incorrect branch ;)
>
> Alistair
>
>>
>>>
>>>> {
>>>> target_ulong val = 0;
>>>> riscv_csrrw(env, csrno, &val, 0, 0);
>>>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>>>> index f257050f12..f49e98ed59 100644
>>>> --- a/target/riscv/cpu_helper.c
>>>> +++ b/target/riscv/cpu_helper.c
>>>> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
>>>> return old;
>>>> }
>>>>
>>>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
>>>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
>>>> {
>>>> if (newpriv > PRV_M) {
>>>> g_assert_not_reached();
>>>> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>>>> g_assert_not_reached();
>>>> }
>>>> env->badaddr = addr;
>>>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>>>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>>>> }
>>>>
>>>> /* called by qemu's softmmu to fill the qemu tlb */
>>>> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
>>>> if (ret == TRANSLATE_FAIL) {
>>>> RISCVCPU *cpu = RISCV_CPU(cs);
>>>> CPURISCVState *env = &cpu->env;
>>>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>>>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>>>> }
>>>> }
>>>>
>>>> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>>> s = set_field(s, MSTATUS_SPP, env->priv);
>>>> s = set_field(s, MSTATUS_SIE, 0);
>>>> env->mstatus = s;
>>>> - riscv_set_mode(env, PRV_S);
>>>> + riscv_cpu_set_mode(env, PRV_S);
>>>> } else {
>>>> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
>>>> env->pc = env->mtvec;
>>>> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>>> s = set_field(s, MSTATUS_MPP, env->priv);
>>>> s = set_field(s, MSTATUS_MIE, 0);
>>>> env->mstatus = s;
>>>> - riscv_set_mode(env, PRV_M);
>>>> + riscv_cpu_set_mode(env, PRV_M);
>>>> }
>>>> /* TODO yield load reservation */
>>>> #endif
>>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>>>> index 390d3a9a56..e2bd374f09 100644
>>>> --- a/target/riscv/csr.c
>>>> +++ b/target/riscv/csr.c
>>>> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>>>> return -1;
>>>> }
>>>> #endif
>>>> - *val = cpu_riscv_get_fflags(env);
>>>> + *val = riscv_cpu_get_fflags(env);
>>>> return 0;
>>>> }
>>>>
>>>> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>>>> }
>>>> env->mstatus |= MSTATUS_FS;
>>>> #endif
>>>> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>>>> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>>>> return 0;
>>>> }
>>>>
>>>> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>>>> return -1;
>>>> }
>>>> #endif
>>>> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
>>>> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
>>>> | (env->frm << FSR_RD_SHIFT);
>>>> return 0;
>>>> }
>>>> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>>>> env->mstatus |= MSTATUS_FS;
>>>> #endif
>>>> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
>>>> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>>>> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>>>> return 0;
>>>> }
>>>>
>>>> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
>>>> index 01b45ca0ae..b4f818a646 100644
>>>> --- a/target/riscv/fpu_helper.c
>>>> +++ b/target/riscv/fpu_helper.c
>>>> @@ -22,7 +22,7 @@
>>>> #include "exec/exec-all.h"
>>>> #include "exec/helper-proto.h"
>>>>
>>>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>>>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
>>>> {
>>>> int soft = get_float_exception_flags(&env->fp_status);
>>>> target_ulong hard = 0;
>>>> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>>>> return hard;
>>>> }
>>>>
>>>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
>>>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
>>>> {
>>>> int soft = 0;
>>>>
>>>> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
>>>> softrm = float_round_ties_away;
>>>> break;
>>>> default:
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> set_float_rounding_mode(softrm, &env->fp_status);
>>>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>>>> index 77c79ba36e..b7dc18a41e 100644
>>>> --- a/target/riscv/op_helper.c
>>>> +++ b/target/riscv/op_helper.c
>>>> @@ -25,7 +25,7 @@
>>>> #include "exec/helper-proto.h"
>>>>
>>>> /* Exceptions processing helpers */
>>>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>>>> uint32_t exception, uintptr_t pc)
>>>> {
>>>> CPUState *cs = CPU(riscv_env_get_cpu(env));
>>>> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>>>
>>>> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
>>>> {
>>>> - do_raise_exception_err(env, exception, 0);
>>>> + riscv_raise_exception(env, exception, 0);
>>>> }
>>>>
>>>> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>>>> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>>>> {
>>>> target_ulong val = 0;
>>>> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>> return val;
>>>> }
>>>> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
>>>> {
>>>> target_ulong val = 0;
>>>> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>> return val;
>>>> }
>>>> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>>>> {
>>>> target_ulong val = 0;
>>>> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>> return val;
>>>> }
>>>> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>>>> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> {
>>>> if (!(env->priv >= PRV_S)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> target_ulong retpc = env->sepc;
>>>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> }
>>>>
>>>> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>>> get_field(env->mstatus, MSTATUS_TSR)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> target_ulong mstatus = env->mstatus;
>>>> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> get_field(mstatus, MSTATUS_SPIE));
>>>> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
>>>> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
>>>> - riscv_set_mode(env, prev_priv);
>>>> + riscv_cpu_set_mode(env, prev_priv);
>>>> env->mstatus = mstatus;
>>>>
>>>> return retpc;
>>>> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> {
>>>> if (!(env->priv >= PRV_M)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> target_ulong retpc = env->mepc;
>>>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> }
>>>>
>>>> target_ulong mstatus = env->mstatus;
>>>> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> get_field(mstatus, MSTATUS_MPIE));
>>>> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
>>>> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
>>>> - riscv_set_mode(env, prev_priv);
>>>> + riscv_cpu_set_mode(env, prev_priv);
>>>> env->mstatus = mstatus;
>>>>
>>>> return retpc;
>>>> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
>>>> if (env->priv == PRV_S &&
>>>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>>> get_field(env->mstatus, MSTATUS_TW)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> } else {
>>>> cs->halted = 1;
>>>> cs->exception_index = EXCP_HLT;
>>>> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
>>>> if (env->priv == PRV_S &&
>>>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>>> get_field(env->mstatus, MSTATUS_TVM)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> } else {
>>>> tlb_flush(cs);
>>>> }
>>>>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
@ 2019-01-15 19:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 42+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-01-15 19:03 UTC (permalink / raw)
To: Alistair Francis; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On 1/15/19 6:50 PM, Alistair Francis wrote:
> On Tue, Jan 15, 2019 at 9:17 AM Philippe Mathieu-Daudé
> <philmd@redhat.com> wrote:
>>
>> On 1/15/19 11:50 AM, Philippe Mathieu-Daudé wrote:
>>> Hi Alistair,
>>>
>>> On 1/15/19 12:58 AM, Alistair Francis wrote:
>>>> From: Michael Clark <mjc@sifive.com>
>>>>
>>>> * Add riscv prefix to raise_exception function
>>>> * Add riscv prefix to CSR read/write functions
>>>> * Add riscv prefix to signal handler function
>>>> * Add riscv prefix to get fflags function
>>>> * Remove redundant declaration of riscv_cpu_init
>>>> and rename cpu_riscv_init to riscv_cpu_init
>>>> * rename riscv_set_mode to riscv_cpu_set_mode
>>>>
>>>> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
>>>> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
>>>> Cc: Palmer Dabbelt <palmer@sifive.com>
>>>> Cc: Alistair Francis <Alistair.Francis@wdc.com>
>>>> Signed-off-by: Michael Clark <mjc@sifive.com>
>>>> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
>>>> ---
>>>> linux-user/riscv/signal.c | 4 ++--
>>>> target/riscv/cpu.h | 21 ++++++++++-----------
>>>> target/riscv/cpu_helper.c | 10 +++++-----
>>>> target/riscv/csr.c | 8 ++++----
>>>> target/riscv/fpu_helper.c | 6 +++---
>>>> target/riscv/op_helper.c | 28 ++++++++++++++--------------
>>>> 6 files changed, 38 insertions(+), 39 deletions(-)
>>>>
>>>> diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c
>>>> index f598d41891..83ecc6f799 100644
>>>> --- a/linux-user/riscv/signal.c
>>>> +++ b/linux-user/riscv/signal.c
>>>> @@ -83,7 +83,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPURISCVState *env)
>>>> __put_user(env->fpr[i], &sc->fpr[i]);
>>>> }
>>>>
>>>> - uint32_t fcsr = csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env);*/
>>>> + uint32_t fcsr = riscv_csr_read(env, CSR_FCSR);
>>>> __put_user(fcsr, &sc->fcsr);
>>>> }
>>>>
>>>> @@ -159,7 +159,7 @@ static void restore_sigcontext(CPURISCVState *env, struct target_sigcontext *sc)
>>>>
>>>> uint32_t fcsr;
>>>> __get_user(fcsr, &sc->fcsr);
>>>> - csr_write_helper(env, fcsr, CSR_FCSR);
>>>> + riscv_csr_write(env, CSR_FCSR, fcsr);
>>>> }
>>>>
>>>> static void restore_ucontext(CPURISCVState *env, struct target_ucontext *uc)
>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>>> index 681341f5d5..a97435bd7b 100644
>>>> --- a/target/riscv/cpu.h
>>>> +++ b/target/riscv/cpu.h
>>>> @@ -256,7 +256,7 @@ int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
>>>> char *riscv_isa_string(RISCVCPU *cpu);
>>>> void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>>>>
>>>> -#define cpu_signal_handler cpu_riscv_signal_handler
>>>> +#define cpu_signal_handler riscv_cpu_signal_handler
>>>> #define cpu_list riscv_cpu_list
>>>> #define cpu_mmu_index riscv_cpu_mmu_index
>>>>
>>>> @@ -264,16 +264,15 @@ void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>>>> uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
>>>> #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
>>>> #endif
>>>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv);
>>>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
>>>>
>>>> void riscv_translate_init(void);
>>>> -RISCVCPU *cpu_riscv_init(const char *cpu_model);
>>>> -int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc);
>>>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>>> - uint32_t exception, uintptr_t pc);
>>>> +int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
>>>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>>>> + uint32_t exception, uintptr_t pc);
>>>>
>>>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
>>>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
>>>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
>>>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
>>>>
>>>> #define TB_FLAGS_MMU_MASK 3
>>>> #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
>>>> @@ -293,13 +292,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>>>> int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>>>> target_ulong new_value, target_ulong write_mask);
>>>>
>>>> -static inline void csr_write_helper(CPURISCVState *env, target_ulong val,
>>>> - int csrno)
>>>> +static inline void riscv_csr_write(CPURISCVState *env, int csrno,
>>>> + target_ulong val)
>>>> {
>>>> riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
>>>> }
>>>>
>>>> -static inline target_ulong csr_read_helper(CPURISCVState *env, int csrno)
>>>> +static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
>>>
>>> Don't you need to update target/riscv/gdbstub.c (in
>>> riscv_cpu_gdb_read_register)?
>
> I don't think so, in master there is no call to csr_read_helper() in
> the gdbstub.c file
>
>>
>> Now than riscv-for-master-3.2-part2 entered /master, I'm more confused
>> about on which commit this series apply... Don't this diverge since
>> c7b9517188?
>
> This applies on top of master (with the riscv-for-master-3.2-part2
> patches in master).
Indeed. The series was missing a note about using
'riscv-for-master-3.2-part2' as a base in the cover when I first tried;
2nd try I messed locally and was in incorrect branch ;)
>
> Alistair
>
>>
>>>
>>>> {
>>>> target_ulong val = 0;
>>>> riscv_csrrw(env, csrno, &val, 0, 0);
>>>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>>>> index f257050f12..f49e98ed59 100644
>>>> --- a/target/riscv/cpu_helper.c
>>>> +++ b/target/riscv/cpu_helper.c
>>>> @@ -93,7 +93,7 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
>>>> return old;
>>>> }
>>>>
>>>> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
>>>> +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
>>>> {
>>>> if (newpriv > PRV_M) {
>>>> g_assert_not_reached();
>>>> @@ -366,7 +366,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>>>> g_assert_not_reached();
>>>> }
>>>> env->badaddr = addr;
>>>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>>>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>>>> }
>>>>
>>>> /* called by qemu's softmmu to fill the qemu tlb */
>>>> @@ -378,7 +378,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
>>>> if (ret == TRANSLATE_FAIL) {
>>>> RISCVCPU *cpu = RISCV_CPU(cs);
>>>> CPURISCVState *env = &cpu->env;
>>>> - do_raise_exception_err(env, cs->exception_index, retaddr);
>>>> + riscv_raise_exception(env, cs->exception_index, retaddr);
>>>> }
>>>> }
>>>>
>>>> @@ -530,7 +530,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>>> s = set_field(s, MSTATUS_SPP, env->priv);
>>>> s = set_field(s, MSTATUS_SIE, 0);
>>>> env->mstatus = s;
>>>> - riscv_set_mode(env, PRV_S);
>>>> + riscv_cpu_set_mode(env, PRV_S);
>>>> } else {
>>>> /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */
>>>> env->pc = env->mtvec;
>>>> @@ -555,7 +555,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>>> s = set_field(s, MSTATUS_MPP, env->priv);
>>>> s = set_field(s, MSTATUS_MIE, 0);
>>>> env->mstatus = s;
>>>> - riscv_set_mode(env, PRV_M);
>>>> + riscv_cpu_set_mode(env, PRV_M);
>>>> }
>>>> /* TODO yield load reservation */
>>>> #endif
>>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>>>> index 390d3a9a56..e2bd374f09 100644
>>>> --- a/target/riscv/csr.c
>>>> +++ b/target/riscv/csr.c
>>>> @@ -90,7 +90,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
>>>> return -1;
>>>> }
>>>> #endif
>>>> - *val = cpu_riscv_get_fflags(env);
>>>> + *val = riscv_cpu_get_fflags(env);
>>>> return 0;
>>>> }
>>>>
>>>> @@ -102,7 +102,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
>>>> }
>>>> env->mstatus |= MSTATUS_FS;
>>>> #endif
>>>> - cpu_riscv_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>>>> + riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
>>>> return 0;
>>>> }
>>>>
>>>> @@ -136,7 +136,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
>>>> return -1;
>>>> }
>>>> #endif
>>>> - *val = (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT)
>>>> + *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
>>>> | (env->frm << FSR_RD_SHIFT);
>>>> return 0;
>>>> }
>>>> @@ -150,7 +150,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
>>>> env->mstatus |= MSTATUS_FS;
>>>> #endif
>>>> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
>>>> - cpu_riscv_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>>>> + riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
>>>> return 0;
>>>> }
>>>>
>>>> diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
>>>> index 01b45ca0ae..b4f818a646 100644
>>>> --- a/target/riscv/fpu_helper.c
>>>> +++ b/target/riscv/fpu_helper.c
>>>> @@ -22,7 +22,7 @@
>>>> #include "exec/exec-all.h"
>>>> #include "exec/helper-proto.h"
>>>>
>>>> -target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>>>> +target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
>>>> {
>>>> int soft = get_float_exception_flags(&env->fp_status);
>>>> target_ulong hard = 0;
>>>> @@ -36,7 +36,7 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env)
>>>> return hard;
>>>> }
>>>>
>>>> -void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard)
>>>> +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
>>>> {
>>>> int soft = 0;
>>>>
>>>> @@ -73,7 +73,7 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
>>>> softrm = float_round_ties_away;
>>>> break;
>>>> default:
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> set_float_rounding_mode(softrm, &env->fp_status);
>>>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
>>>> index 77c79ba36e..b7dc18a41e 100644
>>>> --- a/target/riscv/op_helper.c
>>>> +++ b/target/riscv/op_helper.c
>>>> @@ -25,7 +25,7 @@
>>>> #include "exec/helper-proto.h"
>>>>
>>>> /* Exceptions processing helpers */
>>>> -void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>>> +void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
>>>> uint32_t exception, uintptr_t pc)
>>>> {
>>>> CPUState *cs = CPU(riscv_env_get_cpu(env));
>>>> @@ -36,7 +36,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env,
>>>>
>>>> void helper_raise_exception(CPURISCVState *env, uint32_t exception)
>>>> {
>>>> - do_raise_exception_err(env, exception, 0);
>>>> + riscv_raise_exception(env, exception, 0);
>>>> }
>>>>
>>>> target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>>>> @@ -44,7 +44,7 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong src,
>>>> {
>>>> target_ulong val = 0;
>>>> if (riscv_csrrw(env, csr, &val, src, -1) < 0) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>> return val;
>>>> }
>>>> @@ -54,7 +54,7 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong src,
>>>> {
>>>> target_ulong val = 0;
>>>> if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>> return val;
>>>> }
>>>> @@ -64,7 +64,7 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>>>> {
>>>> target_ulong val = 0;
>>>> if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>> return val;
>>>> }
>>>> @@ -74,17 +74,17 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong src,
>>>> target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> {
>>>> if (!(env->priv >= PRV_S)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> target_ulong retpc = env->sepc;
>>>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> }
>>>>
>>>> if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>>> get_field(env->mstatus, MSTATUS_TSR)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> target_ulong mstatus = env->mstatus;
>>>> @@ -95,7 +95,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> get_field(mstatus, MSTATUS_SPIE));
>>>> mstatus = set_field(mstatus, MSTATUS_SPIE, 0);
>>>> mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
>>>> - riscv_set_mode(env, prev_priv);
>>>> + riscv_cpu_set_mode(env, prev_priv);
>>>> env->mstatus = mstatus;
>>>>
>>>> return retpc;
>>>> @@ -104,12 +104,12 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> {
>>>> if (!(env->priv >= PRV_M)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> }
>>>>
>>>> target_ulong retpc = env->mepc;
>>>> if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
>>>> }
>>>>
>>>> target_ulong mstatus = env->mstatus;
>>>> @@ -120,7 +120,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
>>>> get_field(mstatus, MSTATUS_MPIE));
>>>> mstatus = set_field(mstatus, MSTATUS_MPIE, 0);
>>>> mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
>>>> - riscv_set_mode(env, prev_priv);
>>>> + riscv_cpu_set_mode(env, prev_priv);
>>>> env->mstatus = mstatus;
>>>>
>>>> return retpc;
>>>> @@ -133,7 +133,7 @@ void helper_wfi(CPURISCVState *env)
>>>> if (env->priv == PRV_S &&
>>>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>>> get_field(env->mstatus, MSTATUS_TW)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> } else {
>>>> cs->halted = 1;
>>>> cs->exception_index = EXCP_HLT;
>>>> @@ -148,7 +148,7 @@ void helper_tlb_flush(CPURISCVState *env)
>>>> if (env->priv == PRV_S &&
>>>> env->priv_ver >= PRIV_VERSION_1_10_0 &&
>>>> get_field(env->mstatus, MSTATUS_TVM)) {
>>>> - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
>>>> } else {
>>>> tlb_flush(cs);
>>>> }
>>>>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-15 22:21 ` Richard Henderson
-1 siblings, 0 replies; 42+ messages in thread
From: Richard Henderson @ 2019-01-15 22:21 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 10:58 AM, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> * Add riscv prefix to raise_exception function
> * Add riscv prefix to CSR read/write functions
> * Add riscv prefix to signal handler function
> * Add riscv prefix to get fflags function
> * Remove redundant declaration of riscv_cpu_init
> and rename cpu_riscv_init to riscv_cpu_init
> * rename riscv_set_mode to riscv_cpu_set_mode
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers
@ 2019-01-15 22:21 ` Richard Henderson
0 siblings, 0 replies; 42+ messages in thread
From: Richard Henderson @ 2019-01-15 22:21 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 10:58 AM, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> * Add riscv prefix to raise_exception function
> * Add riscv prefix to CSR read/write functions
> * Add riscv prefix to signal handler function
> * Add riscv prefix to get fflags function
> * Remove redundant declaration of riscv_cpu_init
> and rename cpu_riscv_init to riscv_cpu_init
> * rename riscv_set_mode to riscv_cpu_set_mode
>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-15 22:23 ` Richard Henderson
-1 siblings, 0 replies; 42+ messages in thread
From: Richard Henderson @ 2019-01-15 22:23 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 10:58 AM, Alistair Francis wrote:
> -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
Why change this? I know there is variation in the naming, but my
preferred default mapping is CPUState *cs, RISCVCPU *cpu.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
@ 2019-01-15 22:23 ` Richard Henderson
0 siblings, 0 replies; 42+ messages in thread
From: Richard Henderson @ 2019-01-15 22:23 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 10:58 AM, Alistair Francis wrote:
> -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
Why change this? I know there is variation in the naming, but my
preferred default mapping is CPUState *cs, RISCVCPU *cpu.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
2019-01-15 22:23 ` [Qemu-riscv] " Richard Henderson
@ 2019-01-15 22:25 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-15 22:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 1/15/19 10:58 AM, Alistair Francis wrote:
> > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
>
> Why change this? I know there is variation in the naming, but my
> preferred default mapping is CPUState *cs, RISCVCPU *cpu.
Good point, I have changed it back to cs.
Alistair
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
@ 2019-01-15 22:25 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-15 22:25 UTC (permalink / raw)
To: Richard Henderson; +Cc: Alistair Francis, qemu-devel, qemu-riscv
On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 1/15/19 10:58 AM, Alistair Francis wrote:
> > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
>
> Why change this? I know there is variation in the naming, but my
> preferred default mapping is CPUState *cs, RISCVCPU *cpu.
Good point, I have changed it back to cs.
Alistair
>
> Otherwise,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-15 22:26 ` Richard Henderson
-1 siblings, 0 replies; 42+ messages in thread
From: Richard Henderson @ 2019-01-15 22:26 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 10:58 AM, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> Add misa checks for M, A, F and D extensions and if they are
> not present generate illegal instructions. This improves
> emulation accurary for harts with a limited set of extensions.
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Emilio G. Cota <cota@braap.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/translate.c | 158 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 158 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate
@ 2019-01-15 22:26 ` Richard Henderson
0 siblings, 0 replies; 42+ messages in thread
From: Richard Henderson @ 2019-01-15 22:26 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23
On 1/15/19 10:58 AM, Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> Add misa checks for M, A, F and D extensions and if they are
> not present generate illegal instructions. This improves
> emulation accurary for harts with a limited set of extensions.
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Cc: Emilio G. Cota <cota@braap.org>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/translate.c | 158 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 158 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
2019-01-15 22:25 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-25 0:36 ` Palmer Dabbelt
-1 siblings, 0 replies; 42+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 0:36 UTC (permalink / raw)
To: alistair23; +Cc: richard.henderson, qemu-riscv, Alistair Francis, qemu-devel
On Tue, 15 Jan 2019 14:25:44 PST (-0800), alistair23@gmail.com wrote:
> On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 1/15/19 10:58 AM, Alistair Francis wrote:
>> > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>> > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
>>
>> Why change this? I know there is variation in the naming, but my
>> preferred default mapping is CPUState *cs, RISCVCPU *cpu.
>
> Good point, I have changed it back to cs.
I don't see a v2, so I'm just going to go ahead and squash in
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8593c2170af4..b7176cbf98e1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -2015,10 +2015,10 @@ static void decode_opc(DisasContext *ctx)
}
}
-static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
+static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cs->env_ptr;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
and add Richard's tag.
>
> Alistair
>
>>
>> Otherwise,
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
@ 2019-01-25 0:36 ` Palmer Dabbelt
0 siblings, 0 replies; 42+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 0:36 UTC (permalink / raw)
To: alistair23; +Cc: richard.henderson, qemu-riscv, Alistair Francis, qemu-devel
On Tue, 15 Jan 2019 14:25:44 PST (-0800), alistair23@gmail.com wrote:
> On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 1/15/19 10:58 AM, Alistair Francis wrote:
>> > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
>> > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
>>
>> Why change this? I know there is variation in the naming, but my
>> preferred default mapping is CPUState *cs, RISCVCPU *cpu.
>
> Good point, I have changed it back to cs.
I don't see a v2, so I'm just going to go ahead and squash in
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8593c2170af4..b7176cbf98e1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -2015,10 +2015,10 @@ static void decode_opc(DisasContext *ctx)
}
}
-static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
+static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- CPURISCVState *env = cpu->env_ptr;
+ CPURISCVState *env = cs->env_ptr;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
and add Richard's tag.
>
> Alistair
>
>>
>> Otherwise,
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 8/8] RISC-V: Add misa runtime write support
2019-01-14 23:59 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-25 0:37 ` Palmer Dabbelt
-1 siblings, 0 replies; 42+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 0:37 UTC (permalink / raw)
Cc: qemu-devel, qemu-riscv, alistair23, Alistair Francis
On Mon, 14 Jan 2019 15:59:00 PST (-0800), Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> This patch adds support for writing misa. misa is validated based
> on rules in the ISA specification. 'E' is mutually exclusive with
> all other extensions. 'D' depends on 'F' so 'D' bit is dropped
> if 'F' is not present. A conservative approach to consistency is
> taken by flushing the translation cache on misa writes. misa_mask
> is added to the CPU struct to store the original set of extensions.
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 4 ++-
> target/riscv/cpu_bits.h | 11 +++++++++
> target/riscv/csr.c | 54 ++++++++++++++++++++++++++++++++++++++++-
> 4 files changed, 68 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 28d7e5302f..cc3ddc0ae4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -88,7 +88,7 @@ typedef struct RISCVCPUInfo {
>
> static void set_misa(CPURISCVState *env, target_ulong misa)
> {
> - env->misa = misa;
> + env->misa_mask = env->misa = misa;
> }
>
> static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a97435bd7b..5c2aebf132 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -86,7 +86,8 @@
> so a cpu features bitfield is required, likewise for optional PMP support */
> enum {
> RISCV_FEATURE_MMU,
> - RISCV_FEATURE_PMP
> + RISCV_FEATURE_PMP,
> + RISCV_FEATURE_MISA
> };
>
> #define USER_VERSION_2_02_0 0x00020200
> @@ -118,6 +119,7 @@ struct CPURISCVState {
> target_ulong user_ver;
> target_ulong priv_ver;
> target_ulong misa;
> + target_ulong misa_mask;
>
> uint32_t features;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5439f4719e..7afcb2468d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -311,10 +311,21 @@
> #define MSTATUS32_SD 0x80000000
> #define MSTATUS64_SD 0x8000000000000000ULL
>
> +#define MISA32_MXL 0xC0000000
> +#define MISA64_MXL 0xC000000000000000ULL
> +
> +#define MXL_RV32 1
> +#define MXL_RV64 2
> +#define MXL_RV128 3
> +
> #if defined(TARGET_RISCV32)
> #define MSTATUS_SD MSTATUS32_SD
> +#define MISA_MXL MISA32_MXL
> +#define MXL_VAL MXL_RV32
> #elif defined(TARGET_RISCV64)
> #define MSTATUS_SD MSTATUS64_SD
> +#define MISA_MXL MISA64_MXL
> +#define MXL_VAL MXL_RV64
> #endif
>
> /* sstatus CSR bits */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e2bd374f09..e72fcf1265 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -332,6 +332,58 @@ static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
> return 0;
> }
>
> +static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
> + /* drop write to misa */
> + return 0;
> + }
> +
> + /* 'I' or 'E' must be present */
> + if (!(val & (RVI | RVE))) {
> + /* It is not, drop write to misa */
> + return 0;
> + }
> +
> + /* 'E' excludes all other extensions */
> + if (val & RVE) {
> + /* when we support 'E' we can do "val = RVE;" however
> + * for now we just drop writes if 'E' is present.
> + */
> + return 0;
> + }
> +
> + /* Mask extensions that are not supported by this hart */
> + val &= env->misa_mask;
> +
> + /* Mask extensions that are not supported by QEMU */
> + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +
> + /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
> + if ((val & RVD) && !(val & RVF)) {
> + val &= ~RVD;
> + }
> +
> + /* Suppress 'C' if next instruction is not aligned
> + * TODO: this should check next_pc
> + */
> + if ((val & RVC) && (GETPC() & ~3) != 0) {
> + val &= ~RVC;
> + }
> +
> + /* misa.MXL writes are not supported by QEMU */
> + val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
> +
> + /* flush translation cache */
> + if (val != env->misa) {
> + tb_flush(CPU(riscv_env_get_cpu(env)));
> + }
> +
> + env->misa = val;
> +
> + return 0;
> +}
> +
> static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
> {
> *val = env->medeleg;
> @@ -810,7 +862,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> /* Machine Trap Setup */
> [CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
> - [CSR_MISA] = { any, read_misa },
> + [CSR_MISA] = { any, read_misa, write_misa },
> [CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
> [CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
> [CSR_MIE] = { any, read_mie, write_mie },
> --
> 2.19.1
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 8/8] RISC-V: Add misa runtime write support
@ 2019-01-25 0:37 ` Palmer Dabbelt
0 siblings, 0 replies; 42+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 0:37 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, qemu-riscv, alistair23, Alistair Francis
On Mon, 14 Jan 2019 15:59:00 PST (-0800), Alistair Francis wrote:
> From: Michael Clark <mjc@sifive.com>
>
> This patch adds support for writing misa. misa is validated based
> on rules in the ISA specification. 'E' is mutually exclusive with
> all other extensions. 'D' depends on 'F' so 'D' bit is dropped
> if 'F' is not present. A conservative approach to consistency is
> taken by flushing the translation cache on misa writes. misa_mask
> is added to the CPU struct to store the original set of extensions.
>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 4 ++-
> target/riscv/cpu_bits.h | 11 +++++++++
> target/riscv/csr.c | 54 ++++++++++++++++++++++++++++++++++++++++-
> 4 files changed, 68 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 28d7e5302f..cc3ddc0ae4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -88,7 +88,7 @@ typedef struct RISCVCPUInfo {
>
> static void set_misa(CPURISCVState *env, target_ulong misa)
> {
> - env->misa = misa;
> + env->misa_mask = env->misa = misa;
> }
>
> static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index a97435bd7b..5c2aebf132 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -86,7 +86,8 @@
> so a cpu features bitfield is required, likewise for optional PMP support */
> enum {
> RISCV_FEATURE_MMU,
> - RISCV_FEATURE_PMP
> + RISCV_FEATURE_PMP,
> + RISCV_FEATURE_MISA
> };
>
> #define USER_VERSION_2_02_0 0x00020200
> @@ -118,6 +119,7 @@ struct CPURISCVState {
> target_ulong user_ver;
> target_ulong priv_ver;
> target_ulong misa;
> + target_ulong misa_mask;
>
> uint32_t features;
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 5439f4719e..7afcb2468d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -311,10 +311,21 @@
> #define MSTATUS32_SD 0x80000000
> #define MSTATUS64_SD 0x8000000000000000ULL
>
> +#define MISA32_MXL 0xC0000000
> +#define MISA64_MXL 0xC000000000000000ULL
> +
> +#define MXL_RV32 1
> +#define MXL_RV64 2
> +#define MXL_RV128 3
> +
> #if defined(TARGET_RISCV32)
> #define MSTATUS_SD MSTATUS32_SD
> +#define MISA_MXL MISA32_MXL
> +#define MXL_VAL MXL_RV32
> #elif defined(TARGET_RISCV64)
> #define MSTATUS_SD MSTATUS64_SD
> +#define MISA_MXL MISA64_MXL
> +#define MXL_VAL MXL_RV64
> #endif
>
> /* sstatus CSR bits */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e2bd374f09..e72fcf1265 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -332,6 +332,58 @@ static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
> return 0;
> }
>
> +static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
> + /* drop write to misa */
> + return 0;
> + }
> +
> + /* 'I' or 'E' must be present */
> + if (!(val & (RVI | RVE))) {
> + /* It is not, drop write to misa */
> + return 0;
> + }
> +
> + /* 'E' excludes all other extensions */
> + if (val & RVE) {
> + /* when we support 'E' we can do "val = RVE;" however
> + * for now we just drop writes if 'E' is present.
> + */
> + return 0;
> + }
> +
> + /* Mask extensions that are not supported by this hart */
> + val &= env->misa_mask;
> +
> + /* Mask extensions that are not supported by QEMU */
> + val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> +
> + /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
> + if ((val & RVD) && !(val & RVF)) {
> + val &= ~RVD;
> + }
> +
> + /* Suppress 'C' if next instruction is not aligned
> + * TODO: this should check next_pc
> + */
> + if ((val & RVC) && (GETPC() & ~3) != 0) {
> + val &= ~RVC;
> + }
> +
> + /* misa.MXL writes are not supported by QEMU */
> + val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
> +
> + /* flush translation cache */
> + if (val != env->misa) {
> + tb_flush(CPU(riscv_env_get_cpu(env)));
> + }
> +
> + env->misa = val;
> +
> + return 0;
> +}
> +
> static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
> {
> *val = env->medeleg;
> @@ -810,7 +862,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
> /* Machine Trap Setup */
> [CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
> - [CSR_MISA] = { any, read_misa },
> + [CSR_MISA] = { any, read_misa, write_misa },
> [CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
> [CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
> [CSR_MIE] = { any, read_mie, write_mie },
> --
> 2.19.1
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
@ 2019-01-25 0:37 ` Palmer Dabbelt
-1 siblings, 0 replies; 42+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 0:37 UTC (permalink / raw)
Cc: qemu-devel, qemu-riscv, alistair23, Alistair Francis
On Mon, 14 Jan 2019 15:57:41 PST (-0800), Alistair Francis wrote:
>
> Alistair Francis (1):
> RISC-V: Add priv_ver to DisasContext
>
> Michael Clark (5):
> RISC-V: Implement mstatus.TSR/TW/TVM
> RISC-V: Use riscv prefix consistently on cpu helpers
> RISC-V: Add misa to DisasContext
> RISC-V: Add misa.MAFD checks to translate
> RISC-V: Add misa runtime write support
>
> Richard Henderson (2):
> RISC-V: Split out mstatus_fs from tb_flags
> RISC-V: Mark mstatus.fs dirty
>
> linux-user/riscv/signal.c | 4 +-
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 31 ++--
> target/riscv/cpu_bits.h | 11 ++
> target/riscv/cpu_helper.c | 10 +-
> target/riscv/csr.c | 91 +++++++++---
> target/riscv/fpu_helper.c | 6 +-
> target/riscv/op_helper.c | 47 ++++--
> target/riscv/translate.c | 292 ++++++++++++++++++++++++++++++++------
> 9 files changed, 388 insertions(+), 106 deletions(-)
Thanks. Assuming that squash is OK I'll include these in my next PR, otherwise
just send me a v2 and I'll swap them out.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3
@ 2019-01-25 0:37 ` Palmer Dabbelt
0 siblings, 0 replies; 42+ messages in thread
From: Palmer Dabbelt @ 2019-01-25 0:37 UTC (permalink / raw)
To: Alistair Francis; +Cc: qemu-devel, qemu-riscv, alistair23, Alistair Francis
On Mon, 14 Jan 2019 15:57:41 PST (-0800), Alistair Francis wrote:
>
> Alistair Francis (1):
> RISC-V: Add priv_ver to DisasContext
>
> Michael Clark (5):
> RISC-V: Implement mstatus.TSR/TW/TVM
> RISC-V: Use riscv prefix consistently on cpu helpers
> RISC-V: Add misa to DisasContext
> RISC-V: Add misa.MAFD checks to translate
> RISC-V: Add misa runtime write support
>
> Richard Henderson (2):
> RISC-V: Split out mstatus_fs from tb_flags
> RISC-V: Mark mstatus.fs dirty
>
> linux-user/riscv/signal.c | 4 +-
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu.h | 31 ++--
> target/riscv/cpu_bits.h | 11 ++
> target/riscv/cpu_helper.c | 10 +-
> target/riscv/csr.c | 91 +++++++++---
> target/riscv/fpu_helper.c | 6 +-
> target/riscv/op_helper.c | 47 ++++--
> target/riscv/translate.c | 292 ++++++++++++++++++++++++++++++++------
> 9 files changed, 388 insertions(+), 106 deletions(-)
Thanks. Assuming that squash is OK I'll include these in my next PR, otherwise
just send me a v2 and I'll swap them out.
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
2019-01-25 0:36 ` [Qemu-riscv] " Palmer Dabbelt
@ 2019-01-25 0:45 ` Alistair Francis
-1 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-25 0:45 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Richard Henderson, qemu-riscv, Alistair Francis,
qemu-devel@nongnu.org Developers
On Thu, Jan 24, 2019 at 4:37 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Tue, 15 Jan 2019 14:25:44 PST (-0800), alistair23@gmail.com wrote:
> > On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> On 1/15/19 10:58 AM, Alistair Francis wrote:
> >> > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> >> > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
> >>
> >> Why change this? I know there is variation in the naming, but my
> >> preferred default mapping is CPUState *cs, RISCVCPU *cpu.
> >
> > Good point, I have changed it back to cs.
>
> I don't see a v2, so I'm just going to go ahead and squash in
Yeah, I was waiting for more comments before sending a v2 on such a
trivial change.
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 8593c2170af4..b7176cbf98e1 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -2015,10 +2015,10 @@ static void decode_opc(DisasContext *ctx)
> }
> }
>
> -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
> +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> - CPURISCVState *env = cpu->env_ptr;
> + CPURISCVState *env = cs->env_ptr;
>
> ctx->pc_succ_insn = ctx->base.pc_first;
> ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
>
> and add Richard's tag.
Sounds good.
Alistair
>
> >
> > Alistair
> >
> >>
> >> Otherwise,
> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
@ 2019-01-25 0:45 ` Alistair Francis
0 siblings, 0 replies; 42+ messages in thread
From: Alistair Francis @ 2019-01-25 0:45 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Richard Henderson, qemu-riscv, Alistair Francis,
qemu-devel@nongnu.org Developers
On Thu, Jan 24, 2019 at 4:37 PM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Tue, 15 Jan 2019 14:25:44 PST (-0800), alistair23@gmail.com wrote:
> > On Tue, Jan 15, 2019 at 2:24 PM Richard Henderson
> > <richard.henderson@linaro.org> wrote:
> >>
> >> On 1/15/19 10:58 AM, Alistair Francis wrote:
> >> > -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> >> > +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
> >>
> >> Why change this? I know there is variation in the naming, but my
> >> preferred default mapping is CPUState *cs, RISCVCPU *cpu.
> >
> > Good point, I have changed it back to cs.
>
> I don't see a v2, so I'm just going to go ahead and squash in
Yeah, I was waiting for more comments before sending a v2 on such a
trivial change.
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 8593c2170af4..b7176cbf98e1 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -2015,10 +2015,10 @@ static void decode_opc(DisasContext *ctx)
> }
> }
>
> -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
> +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> - CPURISCVState *env = cpu->env_ptr;
> + CPURISCVState *env = cs->env_ptr;
>
> ctx->pc_succ_insn = ctx->base.pc_first;
> ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
>
> and add Richard's tag.
Sounds good.
Alistair
>
> >
> > Alistair
> >
> >>
> >> Otherwise,
> >> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2019-01-25 0:50 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-01-14 23:57 [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3 Alistair Francis
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
2019-01-14 23:57 ` [Qemu-devel] [PATCH v1 1/8] RISC-V: Split out mstatus_fs from tb_flags Alistair Francis
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
2019-01-14 23:57 ` [Qemu-devel] [PATCH v1 2/8] RISC-V: Mark mstatus.fs dirty Alistair Francis
2019-01-14 23:57 ` [Qemu-riscv] " Alistair Francis
2019-01-14 23:58 ` [Qemu-devel] [PATCH v1 3/8] RISC-V: Implement mstatus.TSR/TW/TVM Alistair Francis
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
2019-01-14 23:58 ` [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers Alistair Francis
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
2019-01-15 10:50 ` [Qemu-devel] " Philippe Mathieu-Daudé
2019-01-15 10:50 ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-01-15 17:17 ` Philippe Mathieu-Daudé
2019-01-15 17:17 ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-01-15 17:50 ` Alistair Francis
2019-01-15 17:50 ` [Qemu-riscv] " Alistair Francis
2019-01-15 19:03 ` Philippe Mathieu-Daudé
2019-01-15 19:03 ` [Qemu-riscv] " Philippe Mathieu-Daudé
2019-01-15 22:21 ` Richard Henderson
2019-01-15 22:21 ` [Qemu-riscv] " Richard Henderson
2019-01-14 23:58 ` [Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext Alistair Francis
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
2019-01-15 22:23 ` [Qemu-devel] " Richard Henderson
2019-01-15 22:23 ` [Qemu-riscv] " Richard Henderson
2019-01-15 22:25 ` Alistair Francis
2019-01-15 22:25 ` [Qemu-riscv] " Alistair Francis
2019-01-25 0:36 ` Palmer Dabbelt
2019-01-25 0:36 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-25 0:45 ` Alistair Francis
2019-01-25 0:45 ` [Qemu-riscv] " Alistair Francis
2019-01-14 23:58 ` [Qemu-devel] [PATCH v1 6/8] RISC-V: Add misa " Alistair Francis
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
2019-01-14 23:58 ` [Qemu-devel] [PATCH v1 7/8] RISC-V: Add misa.MAFD checks to translate Alistair Francis
2019-01-14 23:58 ` [Qemu-riscv] " Alistair Francis
2019-01-15 22:26 ` [Qemu-devel] " Richard Henderson
2019-01-15 22:26 ` [Qemu-riscv] " Richard Henderson
2019-01-14 23:59 ` [Qemu-devel] [PATCH v1 8/8] RISC-V: Add misa runtime write support Alistair Francis
2019-01-14 23:59 ` [Qemu-riscv] " Alistair Francis
2019-01-25 0:37 ` [Qemu-devel] " Palmer Dabbelt
2019-01-25 0:37 ` [Qemu-riscv] " Palmer Dabbelt
2019-01-25 0:37 ` [Qemu-devel] [PATCH v1 0/8] Upstream RISC-V fork patches, part 3 Palmer Dabbelt
2019-01-25 0:37 ` [Qemu-riscv] " Palmer Dabbelt
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