* [Qemu-riscv] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt @ 2019-03-17 8:03 Bin Meng 2019-03-17 8:03 ` [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree Bin Meng 2019-03-18 17:58 ` [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt Alistair Francis 0 siblings, 2 replies; 4+ messages in thread From: Bin Meng @ 2019-03-17 8:03 UTC (permalink / raw) To: qemu-riscv, qemu-devel, Alistair Francis, Palmer Dabbelt, Bastian Koppelmann, Sagar Karandikar At present the sifive uart model only generates RX interrupt. This updates it to generate TX interrupt so that it is more useful. Note the TX fifo is still unimplemented. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- hw/riscv/sifive_uart.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 456a3d3..3b3f94f 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -51,7 +51,8 @@ static uint64_t uart_ip(SiFiveUARTState *s) static void update_irq(SiFiveUARTState *s) { int cond = 0; - if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { + if ((s->ie & SIFIVE_UART_IE_TXWM) || + ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) { cond = 1; } if (cond) { @@ -108,6 +109,7 @@ uart_write(void *opaque, hwaddr addr, switch (addr) { case SIFIVE_UART_TXFIFO: qemu_chr_fe_write(&s->chr, &ch, 1); + update_irq(s); return; case SIFIVE_UART_IE: s->ie = val64; -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree 2019-03-17 8:03 [Qemu-riscv] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt Bin Meng @ 2019-03-17 8:03 ` Bin Meng 2019-03-18 17:57 ` [Qemu-riscv] [Qemu-devel] " Alistair Francis 2019-03-18 17:58 ` [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt Alistair Francis 1 sibling, 1 reply; 4+ messages in thread From: Bin Meng @ 2019-03-17 8:03 UTC (permalink / raw) To: qemu-riscv, qemu-devel, Alistair Francis, Palmer Dabbelt, Bastian Koppelmann, Sagar Karandikar The UART0's interrupt vector is wrongly set to 1 in the device tree. Use SIFIVE_U_UART0_IRQ instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- hw/riscv/sifive_u.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7bc2582..57741c2 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -244,7 +244,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ / 2); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); -- 2.7.4 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree 2019-03-17 8:03 ` [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree Bin Meng @ 2019-03-18 17:57 ` Alistair Francis 0 siblings, 0 replies; 4+ messages in thread From: Alistair Francis @ 2019-03-18 17:57 UTC (permalink / raw) To: Bin Meng Cc: open list:RISC-V, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bastian Koppelmann, Sagar Karandikar On Sun, Mar 17, 2019 at 1:24 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > The UART0's interrupt vector is wrongly set to 1 in the device tree. > Use SIFIVE_U_UART0_IRQ instead. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_u.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 7bc2582..57741c2 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -244,7 +244,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", > SIFIVE_U_CLOCK_FREQ / 2); > qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); > - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); > + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); > > qemu_fdt_add_subnode(fdt, "/chosen"); > qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); > -- > 2.7.4 > > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt 2019-03-17 8:03 [Qemu-riscv] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt Bin Meng 2019-03-17 8:03 ` [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree Bin Meng @ 2019-03-18 17:58 ` Alistair Francis 1 sibling, 0 replies; 4+ messages in thread From: Alistair Francis @ 2019-03-18 17:58 UTC (permalink / raw) To: Bin Meng Cc: open list:RISC-V, qemu-devel@nongnu.org Developers, Alistair Francis, Palmer Dabbelt, Bastian Koppelmann, Sagar Karandikar On Sun, Mar 17, 2019 at 1:24 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > At present the sifive uart model only generates RX interrupt. This > updates it to generate TX interrupt so that it is more useful. > > Note the TX fifo is still unimplemented. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_uart.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c > index 456a3d3..3b3f94f 100644 > --- a/hw/riscv/sifive_uart.c > +++ b/hw/riscv/sifive_uart.c > @@ -51,7 +51,8 @@ static uint64_t uart_ip(SiFiveUARTState *s) > static void update_irq(SiFiveUARTState *s) > { > int cond = 0; > - if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) { > + if ((s->ie & SIFIVE_UART_IE_TXWM) || > + ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) { > cond = 1; > } > if (cond) { > @@ -108,6 +109,7 @@ uart_write(void *opaque, hwaddr addr, > switch (addr) { > case SIFIVE_UART_TXFIFO: > qemu_chr_fe_write(&s->chr, &ch, 1); > + update_irq(s); > return; > case SIFIVE_UART_IE: > s->ie = val64; > -- > 2.7.4 > > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-03-18 17:59 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-03-17 8:03 [Qemu-riscv] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt Bin Meng 2019-03-17 8:03 ` [Qemu-riscv] [PATCH 2/2] riscv: sifive_u: Correct UART0's IRQ in the device tree Bin Meng 2019-03-18 17:57 ` [Qemu-riscv] [Qemu-devel] " Alistair Francis 2019-03-18 17:58 ` [Qemu-riscv] [Qemu-devel] [PATCH 1/2] riscv: sifive_uart: Generate TX interrupt Alistair Francis
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.