* [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
@ 2022-04-22 4:04 ` frank.chang
0 siblings, 0 replies; 4+ messages in thread
From: frank.chang @ 2022-04-22 4:04 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Frank Chang, Bin Meng, Jim Shu, Alistair Francis,
Palmer Dabbelt, Bin Meng
From: Frank Chang <frank.chang@sifive.com>
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.c | 9 +++++++++
target/riscv/cpu.h | 4 ++++
target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0c774056c5..ace68ed855 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,11 @@
/* RISC-V CPU definitions */
+#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
+ (QEMU_VERSION_MINOR << 8) | \
+ (QEMU_VERSION_MICRO))
+#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
+
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
struct isa_ext_data {
@@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+ DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+ DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34c22d5d3b..46c66fbf8e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -393,6 +393,10 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
+ uint32_t mvendorid;
+ uint64_t marchid;
+ uint64_t mipid;
+
/* Vendor-specific custom extensions */
bool ext_XVentanaCondOps;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6ba85e7b5d..1c2d3f7193 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.mvendorid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_marchid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.marchid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.mipid;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
/* Machine Information Registers */
- [CSR_MVENDORID] = { "mvendorid", any, read_zero },
- [CSR_MARCHID] = { "marchid", any, read_zero },
- [CSR_MIMPID] = { "mimpid", any, read_zero },
- [CSR_MHARTID] = { "mhartid", any, read_mhartid },
+ [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
+ [CSR_MARCHID] = { "marchid", any, read_marchid },
+ [CSR_MIMPID] = { "mimpid", any, read_mipid },
+ [CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
.min_priv_ver = PRIV_VERSION_1_12_0 },
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
@ 2022-04-22 4:04 ` frank.chang
0 siblings, 0 replies; 4+ messages in thread
From: frank.chang @ 2022-04-22 4:04 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Frank Chang, Jim Shu, Alistair Francis, Bin Meng,
Palmer Dabbelt, Bin Meng
From: Frank Chang <frank.chang@sifive.com>
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.c | 9 +++++++++
target/riscv/cpu.h | 4 ++++
target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0c774056c5..ace68ed855 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,11 @@
/* RISC-V CPU definitions */
+#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
+ (QEMU_VERSION_MINOR << 8) | \
+ (QEMU_VERSION_MICRO))
+#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
+
static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
struct isa_ext_data {
@@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+ DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
+ DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34c22d5d3b..46c66fbf8e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -393,6 +393,10 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
+ uint32_t mvendorid;
+ uint64_t marchid;
+ uint64_t mipid;
+
/* Vendor-specific custom extensions */
bool ext_XVentanaCondOps;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6ba85e7b5d..1c2d3f7193 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.mvendorid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_marchid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.marchid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs = env_cpu(env);
+ RISCVCPU *cpu = RISCV_CPU(cs);
+
+ *val = cpu->cfg.mipid;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
/* Machine Information Registers */
- [CSR_MVENDORID] = { "mvendorid", any, read_zero },
- [CSR_MARCHID] = { "marchid", any, read_zero },
- [CSR_MIMPID] = { "mimpid", any, read_zero },
- [CSR_MHARTID] = { "mhartid", any, read_mhartid },
+ [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
+ [CSR_MARCHID] = { "marchid", any, read_marchid },
+ [CSR_MIMPID] = { "mimpid", any, read_mipid },
+ [CSR_MHARTID] = { "mhartid", any, read_mhartid },
[CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
.min_priv_ver = PRIV_VERSION_1_12_0 },
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
2022-04-22 4:04 ` frank.chang
@ 2022-04-22 23:05 ` Alistair Francis
-1 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-04-22 23:05 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, qemu-devel@nongnu.org Developers,
Jim Shu, Alistair Francis, Palmer Dabbelt, Bin Meng
On Fri, Apr 22, 2022 at 2:05 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Allow user to set core's marchid, mvendorid, mipid CSRs through
> -cpu command line option.
>
> The default values of marchid and mipid are built with QEMU's version
> numbers.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 9 +++++++++
> target/riscv/cpu.h | 4 ++++
> target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
> 3 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0c774056c5..ace68ed855 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V CPU definitions */
>
> +#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
> + (QEMU_VERSION_MINOR << 8) | \
> + (QEMU_VERSION_MICRO))
> +#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
> +
> static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
>
> struct isa_ext_data {
> @@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
> + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> + DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
> +
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 34c22d5d3b..46c66fbf8e 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -393,6 +393,10 @@ struct RISCVCPUConfig {
> bool ext_zve32f;
> bool ext_zve64f;
>
> + uint32_t mvendorid;
> + uint64_t marchid;
> + uint64_t mipid;
> +
> /* Vendor-specific custom extensions */
> bool ext_XVentanaCondOps;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6ba85e7b5d..1c2d3f7193 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + *val = cpu->cfg.mvendorid;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_marchid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + *val = cpu->cfg.marchid;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_mipid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + *val = cpu->cfg.mipid;
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_mhartid(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
>
> /* Machine Information Registers */
> - [CSR_MVENDORID] = { "mvendorid", any, read_zero },
> - [CSR_MARCHID] = { "marchid", any, read_zero },
> - [CSR_MIMPID] = { "mimpid", any, read_zero },
> - [CSR_MHARTID] = { "mhartid", any, read_mhartid },
> + [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
> + [CSR_MARCHID] = { "marchid", any, read_marchid },
> + [CSR_MIMPID] = { "mimpid", any, read_mipid },
> + [CSR_MHARTID] = { "mhartid", any, read_mhartid },
>
> [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
> .min_priv_ver = PRIV_VERSION_1_12_0 },
> --
> 2.35.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
@ 2022-04-22 23:05 ` Alistair Francis
0 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-04-22 23:05 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Jim Shu, Alistair Francis, Palmer Dabbelt, Bin Meng
On Fri, Apr 22, 2022 at 2:05 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Allow user to set core's marchid, mvendorid, mipid CSRs through
> -cpu command line option.
>
> The default values of marchid and mipid are built with QEMU's version
> numbers.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 9 +++++++++
> target/riscv/cpu.h | 4 ++++
> target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
> 3 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 0c774056c5..ace68ed855 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -34,6 +34,11 @@
>
> /* RISC-V CPU definitions */
>
> +#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
> + (QEMU_VERSION_MINOR << 8) | \
> + (QEMU_VERSION_MICRO))
> +#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
> +
> static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
>
> struct isa_ext_data {
> @@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>
> + DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
> + DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> + DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
> +
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 34c22d5d3b..46c66fbf8e 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -393,6 +393,10 @@ struct RISCVCPUConfig {
> bool ext_zve32f;
> bool ext_zve64f;
>
> + uint32_t mvendorid;
> + uint64_t marchid;
> + uint64_t mipid;
> +
> /* Vendor-specific custom extensions */
> bool ext_XVentanaCondOps;
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6ba85e7b5d..1c2d3f7193 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> +static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + *val = cpu->cfg.mvendorid;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_marchid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + *val = cpu->cfg.marchid;
> + return RISCV_EXCP_NONE;
> +}
> +
> +static RISCVException read_mipid(CPURISCVState *env, int csrno,
> + target_ulong *val)
> +{
> + CPUState *cs = env_cpu(env);
> + RISCVCPU *cpu = RISCV_CPU(cs);
> +
> + *val = cpu->cfg.mipid;
> + return RISCV_EXCP_NONE;
> +}
> +
> static RISCVException read_mhartid(CPURISCVState *env, int csrno,
> target_ulong *val)
> {
> @@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
>
> /* Machine Information Registers */
> - [CSR_MVENDORID] = { "mvendorid", any, read_zero },
> - [CSR_MARCHID] = { "marchid", any, read_zero },
> - [CSR_MIMPID] = { "mimpid", any, read_zero },
> - [CSR_MHARTID] = { "mhartid", any, read_mhartid },
> + [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid },
> + [CSR_MARCHID] = { "marchid", any, read_marchid },
> + [CSR_MIMPID] = { "mimpid", any, read_mipid },
> + [CSR_MHARTID] = { "mhartid", any, read_mhartid },
>
> [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,
> .min_priv_ver = PRIV_VERSION_1_12_0 },
> --
> 2.35.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-04-22 23:07 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-04-22 4:04 [PATCH v3] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values frank.chang
2022-04-22 4:04 ` frank.chang
2022-04-22 23:05 ` Alistair Francis
2022-04-22 23:05 ` Alistair Francis
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