* [PATCH v0 0/2] hw/riscv/opentitan: bump opentitan version
@ 2022-10-25 1:10 Wilfred Mallawa
2022-10-25 1:10 ` [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan Wilfred Mallawa
2022-10-25 1:10 ` [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl Wilfred Mallawa
0 siblings, 2 replies; 7+ messages in thread
From: Wilfred Mallawa @ 2022-10-25 1:10 UTC (permalink / raw)
To: Alistair.Francis, palmer, bin.meng, qemu-riscv
Cc: qemu-devel, Wilfred Mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This patch provides updates to the OpenTitan model to bump to RTL
version <d072ac505f82152678d6e04be95c72b728a347b8>.
A unique change here is the merger of hwip `padctrl` into `pinmux`, to
reflect this change, any references to `padctrl` are removed.
Additionally, an unimplemented device for `aon_timer` is added and IRQ
numbers are updated.
Patch was tested by running the latest master of
TockOS as of this patch.
Wilfred Mallawa (2):
hw/riscv/opentitan: bump opentitan
hw/riscv/opentitan: add aon_timer base unimpl
hw/riscv/opentitan.c | 16 ++++++++--------
include/hw/riscv/opentitan.h | 10 +++++-----
2 files changed, 13 insertions(+), 13 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan
2022-10-25 1:10 [PATCH v0 0/2] hw/riscv/opentitan: bump opentitan version Wilfred Mallawa
@ 2022-10-25 1:10 ` Wilfred Mallawa
2022-10-25 1:34 ` Bin Meng
2022-10-25 4:05 ` Alistair Francis
2022-10-25 1:10 ` [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl Wilfred Mallawa
1 sibling, 2 replies; 7+ messages in thread
From: Wilfred Mallawa @ 2022-10-25 1:10 UTC (permalink / raw)
To: Alistair.Francis, palmer, bin.meng, qemu-riscv
Cc: qemu-devel, Wilfred Mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This patch updates the OpenTitan model to match
the specified register layout as per [1]. Which is also the latest
commit of OpenTitan supported by TockOS.
Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
any references to Padctrl. Note: OpenTitan doc [2] has not yet specified
much detail regarding this, except for a note that states `TODO: this
section needs to be updated to reflect the pinmux/padctrl merger`
[1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
[2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/
[3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
hw/riscv/opentitan.c | 13 +++++--------
include/hw/riscv/opentitan.h | 9 ++++-----
2 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index be7ff1eea0..373fed36b6 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -29,7 +29,7 @@
#include "sysemu/sysemu.h"
static const MemMapEntry ibex_memmap[] = {
- [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
+ [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
[IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
[IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
[IBEX_DEV_UART] = { 0x40000000, 0x1000 },
@@ -38,17 +38,17 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
[IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
- [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
[IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 },
- [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
+ [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 },
[IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
[IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
+ [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
- [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
+ [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
[IBEX_DEV_AES] = { 0x41100000, 0x1000 },
[IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
@@ -59,10 +59,9 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
[IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
[IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
- [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
[IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
[IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
- [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
+ [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
[IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
};
@@ -265,8 +264,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
- create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
- memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 6665cd5794..1fc055cdff 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -81,7 +81,6 @@ enum {
IBEX_DEV_RSTMGR,
IBEX_DEV_CLKMGR,
IBEX_DEV_PINMUX,
- IBEX_DEV_PADCTRL,
IBEX_DEV_USBDEV,
IBEX_DEV_FLASH_CTRL,
IBEX_DEV_PLIC,
@@ -109,10 +108,10 @@ enum {
IBEX_UART0_RX_TIMEOUT_IRQ = 7,
IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
IBEX_TIMER_TIMEREXPIRED0_0 = 127,
- IBEX_SPI_HOST0_ERR_IRQ = 151,
- IBEX_SPI_HOST0_SPI_EVENT_IRQ = 152,
- IBEX_SPI_HOST1_ERR_IRQ = 153,
- IBEX_SPI_HOST1_SPI_EVENT_IRQ = 154,
+ IBEX_SPI_HOST0_ERR_IRQ = 134,
+ IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
+ IBEX_SPI_HOST1_ERR_IRQ = 136,
+ IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
};
#endif
--
2.37.3
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl
2022-10-25 1:10 [PATCH v0 0/2] hw/riscv/opentitan: bump opentitan version Wilfred Mallawa
2022-10-25 1:10 ` [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan Wilfred Mallawa
@ 2022-10-25 1:10 ` Wilfred Mallawa
2022-10-25 1:34 ` Bin Meng
2022-10-25 4:05 ` Alistair Francis
1 sibling, 2 replies; 7+ messages in thread
From: Wilfred Mallawa @ 2022-10-25 1:10 UTC (permalink / raw)
To: Alistair.Francis, palmer, bin.meng, qemu-riscv
Cc: qemu-devel, Wilfred Mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Adds the updated `aon_timer` base as an unimplemented device. This is
used by TockOS, patch ensures the guest doesn't hit load faults.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
hw/riscv/opentitan.c | 3 +++
include/hw/riscv/opentitan.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 373fed36b6..50452f792a 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -48,6 +48,7 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
[IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
+ [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
[IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
[IBEX_DEV_AES] = { 0x41100000, 0x1000 },
@@ -264,6 +265,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
+ memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 1fc055cdff..7659d1bc5b 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -81,6 +81,7 @@ enum {
IBEX_DEV_RSTMGR,
IBEX_DEV_CLKMGR,
IBEX_DEV_PINMUX,
+ IBEX_DEV_AON_TIMER,
IBEX_DEV_USBDEV,
IBEX_DEV_FLASH_CTRL,
IBEX_DEV_PLIC,
--
2.37.3
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan
2022-10-25 1:10 ` [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan Wilfred Mallawa
@ 2022-10-25 1:34 ` Bin Meng
2022-10-25 4:05 ` Alistair Francis
1 sibling, 0 replies; 7+ messages in thread
From: Bin Meng @ 2022-10-25 1:34 UTC (permalink / raw)
To: Wilfred Mallawa
Cc: Alistair.Francis, palmer, bin.meng, qemu-riscv, qemu-devel,
Wilfred Mallawa
On Tue, Oct 25, 2022 at 9:17 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> This patch updates the OpenTitan model to match
> the specified register layout as per [1]. Which is also the latest
> commit of OpenTitan supported by TockOS.
>
> Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
> any references to Padctrl. Note: OpenTitan doc [2] has not yet specified
> much detail regarding this, except for a note that states `TODO: this
> section needs to be updated to reflect the pinmux/padctrl merger`
>
> [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
> [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/
> [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/riscv/opentitan.c | 13 +++++--------
> include/hw/riscv/opentitan.h | 9 ++++-----
> 2 files changed, 9 insertions(+), 13 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl
2022-10-25 1:10 ` [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl Wilfred Mallawa
@ 2022-10-25 1:34 ` Bin Meng
2022-10-25 4:05 ` Alistair Francis
1 sibling, 0 replies; 7+ messages in thread
From: Bin Meng @ 2022-10-25 1:34 UTC (permalink / raw)
To: Wilfred Mallawa
Cc: Alistair.Francis, palmer, bin.meng, qemu-riscv, qemu-devel,
Wilfred Mallawa
On Tue, Oct 25, 2022 at 9:19 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Adds the updated `aon_timer` base as an unimplemented device. This is
> used by TockOS, patch ensures the guest doesn't hit load faults.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/riscv/opentitan.c | 3 +++
> include/hw/riscv/opentitan.h | 1 +
> 2 files changed, 4 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan
2022-10-25 1:10 ` [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan Wilfred Mallawa
2022-10-25 1:34 ` Bin Meng
@ 2022-10-25 4:05 ` Alistair Francis
1 sibling, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-10-25 4:05 UTC (permalink / raw)
To: Wilfred Mallawa
Cc: Alistair.Francis, palmer, bin.meng, qemu-riscv, qemu-devel,
Wilfred Mallawa
On Tue, Oct 25, 2022 at 11:18 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> This patch updates the OpenTitan model to match
> the specified register layout as per [1]. Which is also the latest
> commit of OpenTitan supported by TockOS.
>
> Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
> any references to Padctrl. Note: OpenTitan doc [2] has not yet specified
> much detail regarding this, except for a note that states `TODO: this
> section needs to be updated to reflect the pinmux/padctrl merger`
>
> [1] https://github.com/lowRISC/opentitan/blob/d072ac505f82152678d6e04be95c72b728a347b8/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
> [2] https://docs.opentitan.org/hw/top_earlgrey/doc/design/
> [3] https://docs.opentitan.org/hw/ip/pinmux/doc/#overview
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Can you add a comment to the OpenTitan machine in QEMU specifying what
git SHA of OT we are targeting?
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/opentitan.c | 13 +++++--------
> include/hw/riscv/opentitan.h | 9 ++++-----
> 2 files changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index be7ff1eea0..373fed36b6 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -29,7 +29,7 @@
> #include "sysemu/sysemu.h"
>
> static const MemMapEntry ibex_memmap[] = {
> - [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
> + [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
> [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
> [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
> [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
> @@ -38,17 +38,17 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
> [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
> [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
> - [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
> [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
> [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 },
> - [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
> + [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 },
> [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
> [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
> + [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
> [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
> [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
> [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
> [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
> - [IBEX_DEV_PADCTRL] = { 0x40470000, 0x1000 },
> + [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
> [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
> [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
> [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
> @@ -59,10 +59,9 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 },
> [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 },
> [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 },
> - [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 },
> [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 },
> [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 },
> - [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
> + [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 },
> [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
> };
>
> @@ -265,8 +264,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
> create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
> memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
> - create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
> - memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
> create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
> memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
> create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 6665cd5794..1fc055cdff 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -81,7 +81,6 @@ enum {
> IBEX_DEV_RSTMGR,
> IBEX_DEV_CLKMGR,
> IBEX_DEV_PINMUX,
> - IBEX_DEV_PADCTRL,
> IBEX_DEV_USBDEV,
> IBEX_DEV_FLASH_CTRL,
> IBEX_DEV_PLIC,
> @@ -109,10 +108,10 @@ enum {
> IBEX_UART0_RX_TIMEOUT_IRQ = 7,
> IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
> IBEX_TIMER_TIMEREXPIRED0_0 = 127,
> - IBEX_SPI_HOST0_ERR_IRQ = 151,
> - IBEX_SPI_HOST0_SPI_EVENT_IRQ = 152,
> - IBEX_SPI_HOST1_ERR_IRQ = 153,
> - IBEX_SPI_HOST1_SPI_EVENT_IRQ = 154,
> + IBEX_SPI_HOST0_ERR_IRQ = 134,
> + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135,
> + IBEX_SPI_HOST1_ERR_IRQ = 136,
> + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137,
> };
>
> #endif
> --
> 2.37.3
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl
2022-10-25 1:10 ` [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl Wilfred Mallawa
2022-10-25 1:34 ` Bin Meng
@ 2022-10-25 4:05 ` Alistair Francis
1 sibling, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-10-25 4:05 UTC (permalink / raw)
To: Wilfred Mallawa
Cc: Alistair.Francis, palmer, bin.meng, qemu-riscv, qemu-devel,
Wilfred Mallawa
On Tue, Oct 25, 2022 at 11:19 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Adds the updated `aon_timer` base as an unimplemented device. This is
> used by TockOS, patch ensures the guest doesn't hit load faults.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/opentitan.c | 3 +++
> include/hw/riscv/opentitan.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 373fed36b6..50452f792a 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -48,6 +48,7 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
> [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
> [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
> + [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 },
> [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 },
> [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 },
> [IBEX_DEV_AES] = { 0x41100000, 0x1000 },
> @@ -264,6 +265,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
> create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
> memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
> + create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
> + memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
> create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
> memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
> create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 1fc055cdff..7659d1bc5b 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -81,6 +81,7 @@ enum {
> IBEX_DEV_RSTMGR,
> IBEX_DEV_CLKMGR,
> IBEX_DEV_PINMUX,
> + IBEX_DEV_AON_TIMER,
> IBEX_DEV_USBDEV,
> IBEX_DEV_FLASH_CTRL,
> IBEX_DEV_PLIC,
> --
> 2.37.3
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-10-25 4:07 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-25 1:10 [PATCH v0 0/2] hw/riscv/opentitan: bump opentitan version Wilfred Mallawa
2022-10-25 1:10 ` [PATCH v0 1/2] hw/riscv/opentitan: bump opentitan Wilfred Mallawa
2022-10-25 1:34 ` Bin Meng
2022-10-25 4:05 ` Alistair Francis
2022-10-25 1:10 ` [PATCH v0 2/2] hw/riscv/opentitan: add aon_timer base unimpl Wilfred Mallawa
2022-10-25 1:34 ` Bin Meng
2022-10-25 4:05 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.