* [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
@ 2022-05-16 3:33 Weiwei Li
2022-05-16 3:33 ` [PATCH 2/2] target/riscv: disable zb* extensions by default Weiwei Li
2022-05-17 0:23 ` [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Alistair Francis
0 siblings, 2 replies; 7+ messages in thread
From: Weiwei Li @ 2022-05-16 3:33 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
- setting ext_g will implicitly set ext_i
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
slirp | 2 +-
target/riscv/cpu.c | 23 ++++++++++++-----------
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/slirp b/slirp
index 9d59bb775d..a88d9ace23 160000
--- a/slirp
+++ b/slirp
@@ -1 +1 @@
-Subproject commit 9d59bb775d6294c8b447a88512f7bb43f12a25a8
+Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ccacdee215..b12f69c584 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -583,6 +583,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (env->misa_ext == 0) {
uint32_t ext = 0;
+ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+ cpu->cfg.ext_a & cpu->cfg.ext_f &
+ cpu->cfg.ext_d)) {
+ warn_report("Setting G will also set IMAFD");
+ cpu->cfg.ext_i = true;
+ cpu->cfg.ext_m = true;
+ cpu->cfg.ext_a = true;
+ cpu->cfg.ext_f = true;
+ cpu->cfg.ext_d = true;
+ }
+
+
/* Do some ISA extension error checking */
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
@@ -596,17 +608,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
- cpu->cfg.ext_a & cpu->cfg.ext_f &
- cpu->cfg.ext_d)) {
- warn_report("Setting G will also set IMAFD");
- cpu->cfg.ext_i = true;
- cpu->cfg.ext_m = true;
- cpu->cfg.ext_a = true;
- cpu->cfg.ext_f = true;
- cpu->cfg.ext_d = true;
- }
-
if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
cpu->cfg.ext_zhinxmin) {
cpu->cfg.ext_zfinx = true;
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] target/riscv: disable zb* extensions by default
2022-05-16 3:33 [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Weiwei Li
@ 2022-05-16 3:33 ` Weiwei Li
2022-05-17 0:33 ` Alistair Francis
2022-05-17 0:23 ` [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Alistair Francis
1 sibling, 1 reply; 7+ messages in thread
From: Weiwei Li @ 2022-05-16 3:33 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, lazyparser, Weiwei Li
- enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/cpu.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b12f69c584..a3a17323e7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -847,13 +847,13 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
- DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
- DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
- DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
+ DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
+ DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
+ DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
- DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
+ DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
2022-05-16 3:33 [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Weiwei Li
2022-05-16 3:33 ` [PATCH 2/2] target/riscv: disable zb* extensions by default Weiwei Li
@ 2022-05-17 0:23 ` Alistair Francis
2022-05-17 1:32 ` Weiwei Li
1 sibling, 1 reply; 7+ messages in thread
From: Alistair Francis @ 2022-05-17 0:23 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟)
On Mon, May 16, 2022 at 1:36 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - setting ext_g will implicitly set ext_i
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> slirp | 2 +-
> target/riscv/cpu.c | 23 ++++++++++++-----------
> 2 files changed, 13 insertions(+), 12 deletions(-)
>
> diff --git a/slirp b/slirp
> index 9d59bb775d..a88d9ace23 160000
> --- a/slirp
> +++ b/slirp
> @@ -1 +1 @@
> -Subproject commit 9d59bb775d6294c8b447a88512f7bb43f12a25a8
> +Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0
Looks like you accidentally included a submodule change
Alistair
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ccacdee215..b12f69c584 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -583,6 +583,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> if (env->misa_ext == 0) {
> uint32_t ext = 0;
>
> + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> + cpu->cfg.ext_a & cpu->cfg.ext_f &
> + cpu->cfg.ext_d)) {
> + warn_report("Setting G will also set IMAFD");
> + cpu->cfg.ext_i = true;
> + cpu->cfg.ext_m = true;
> + cpu->cfg.ext_a = true;
> + cpu->cfg.ext_f = true;
> + cpu->cfg.ext_d = true;
> + }
> +
> +
> /* Do some ISA extension error checking */
> if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
> error_setg(errp,
> @@ -596,17 +608,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> return;
> }
>
> - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> - cpu->cfg.ext_a & cpu->cfg.ext_f &
> - cpu->cfg.ext_d)) {
> - warn_report("Setting G will also set IMAFD");
> - cpu->cfg.ext_i = true;
> - cpu->cfg.ext_m = true;
> - cpu->cfg.ext_a = true;
> - cpu->cfg.ext_f = true;
> - cpu->cfg.ext_d = true;
> - }
> -
> if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
> cpu->cfg.ext_zhinxmin) {
> cpu->cfg.ext_zfinx = true;
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: disable zb* extensions by default
2022-05-16 3:33 ` [PATCH 2/2] target/riscv: disable zb* extensions by default Weiwei Li
@ 2022-05-17 0:33 ` Alistair Francis
2022-05-17 0:54 ` Alistair Francis
0 siblings, 1 reply; 7+ messages in thread
From: Alistair Francis @ 2022-05-17 0:33 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟)
On Mon, May 16, 2022 at 1:34 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions
Agh, this is a pain.
Can you enable these by default for the base machines then? That way
they will be enabled for the virt machine
Alistair
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/cpu.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b12f69c584..a3a17323e7 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -847,13 +847,13 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>
> - DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> - DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> - DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
> + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
> + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
> DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
> DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> - DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
> DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: disable zb* extensions by default
2022-05-17 0:33 ` Alistair Francis
@ 2022-05-17 0:54 ` Alistair Francis
2022-05-17 1:34 ` Weiwei Li
0 siblings, 1 reply; 7+ messages in thread
From: Alistair Francis @ 2022-05-17 0:54 UTC (permalink / raw)
To: Weiwei Li
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟)
On Tue, May 17, 2022 at 10:33 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Mon, May 16, 2022 at 1:34 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
> >
> > - enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions
>
> Agh, this is a pain.
>
> Can you enable these by default for the base machines then? That way
> they will be enabled for the virt machine
Actually, come to think of it, we can probably just register the
riscv_cpu_properties for the base cpus. That way only those CPUs can
be configured by the user. Can you do that instead?
Alistair
>
> Alistair
>
> >
> > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> > ---
> > target/riscv/cpu.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index b12f69c584..a3a17323e7 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -847,13 +847,13 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> > DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
> >
> > - DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
> > - DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
> > - DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
> > + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
> > + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
> > + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
> > DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
> > DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
> > DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
> > - DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
> > + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
> > DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
> > DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
> > DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
> > --
> > 2.17.1
> >
> >
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize
2022-05-17 0:23 ` [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Alistair Francis
@ 2022-05-17 1:32 ` Weiwei Li
0 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-05-17 1:32 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟)
在 2022/5/17 上午8:23, Alistair Francis 写道:
> On Mon, May 16, 2022 at 1:36 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>> - setting ext_g will implicitly set ext_i
>>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>> slirp | 2 +-
>> target/riscv/cpu.c | 23 ++++++++++++-----------
>> 2 files changed, 13 insertions(+), 12 deletions(-)
>>
>> diff --git a/slirp b/slirp
>> index 9d59bb775d..a88d9ace23 160000
>> --- a/slirp
>> +++ b/slirp
>> @@ -1 +1 @@
>> -Subproject commit 9d59bb775d6294c8b447a88512f7bb43f12a25a8
>> +Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0
> Looks like you accidentally included a submodule change
>
> Alistair
Sorry. I'll fix this later.
Regards,
Weiwei Li
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index ccacdee215..b12f69c584 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -583,6 +583,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> if (env->misa_ext == 0) {
>> uint32_t ext = 0;
>>
>> + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
>> + cpu->cfg.ext_a & cpu->cfg.ext_f &
>> + cpu->cfg.ext_d)) {
>> + warn_report("Setting G will also set IMAFD");
>> + cpu->cfg.ext_i = true;
>> + cpu->cfg.ext_m = true;
>> + cpu->cfg.ext_a = true;
>> + cpu->cfg.ext_f = true;
>> + cpu->cfg.ext_d = true;
>> + }
>> +
>> +
>> /* Do some ISA extension error checking */
>> if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
>> error_setg(errp,
>> @@ -596,17 +608,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>> return;
>> }
>>
>> - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
>> - cpu->cfg.ext_a & cpu->cfg.ext_f &
>> - cpu->cfg.ext_d)) {
>> - warn_report("Setting G will also set IMAFD");
>> - cpu->cfg.ext_i = true;
>> - cpu->cfg.ext_m = true;
>> - cpu->cfg.ext_a = true;
>> - cpu->cfg.ext_f = true;
>> - cpu->cfg.ext_d = true;
>> - }
>> -
>> if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
>> cpu->cfg.ext_zhinxmin) {
>> cpu->cfg.ext_zfinx = true;
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: disable zb* extensions by default
2022-05-17 0:54 ` Alistair Francis
@ 2022-05-17 1:34 ` Weiwei Li
0 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-05-17 1:34 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, open list:RISC-V,
qemu-devel@nongnu.org Developers, wangjunqiang,
Wei Wu (吴伟)
在 2022/5/17 上午8:54, Alistair Francis 写道:
> On Tue, May 17, 2022 at 10:33 AM Alistair Francis <alistair23@gmail.com> wrote:
>> On Mon, May 16, 2022 at 1:34 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>>> - enable zb* extensions by default will make cpu types(such as sifive-u34) implicitly support zb* extensions
>> Agh, this is a pain.
>>
>> Can you enable these by default for the base machines then? That way
>> they will be enabled for the virt machine
> Actually, come to think of it, we can probably just register the
> riscv_cpu_properties for the base cpus. That way only those CPUs can
> be configured by the user. Can you do that instead?
>
> Alistair
>
Yeah, This is OK. I'll do this later.
Regards,
Weiwei Li
>> Alistair
>>
>>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>>> ---
>>> target/riscv/cpu.c | 8 ++++----
>>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>> index b12f69c584..a3a17323e7 100644
>>> --- a/target/riscv/cpu.c
>>> +++ b/target/riscv/cpu.c
>>> @@ -847,13 +847,13 @@ static Property riscv_cpu_properties[] = {
>>> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>>> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
>>>
>>> - DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
>>> - DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
>>> - DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
>>> + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, false),
>>> + DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, false),
>>> + DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, false),
>>> DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
>>> DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
>>> DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
>>> - DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
>>> + DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, false),
>>> DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
>>> DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
>>> DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
>>> --
>>> 2.17.1
>>>
>>>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-05-17 1:35 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-16 3:33 [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Weiwei Li
2022-05-16 3:33 ` [PATCH 2/2] target/riscv: disable zb* extensions by default Weiwei Li
2022-05-17 0:33 ` Alistair Francis
2022-05-17 0:54 ` Alistair Francis
2022-05-17 1:34 ` Weiwei Li
2022-05-17 0:23 ` [PATCH 1/2] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize Alistair Francis
2022-05-17 1:32 ` Weiwei Li
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.