* [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
@ 2018-10-26 18:04 Dayeol Lee
2018-10-26 18:13 ` Dayeol Lee
0 siblings, 1 reply; 4+ messages in thread
From: Dayeol Lee @ 2018-10-26 18:04 UTC (permalink / raw)
To: qemu-devel
Cc: Dayeol Lee, Michael Clark, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
pmp_read_cfg() returns 8-bit value, which is combined together to form a single pmpcfg CSR.
The default promotion rules will result in an integer here ("i*8" is integer, which
flows through) resulting in a 32-bit signed value on most hosts.
That's bogus on RV64I, with the high bits of the CSR being wrong.
Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index c828950..3d3906a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index)
{
int i;
target_ulong cfg_val = 0;
- uint8_t val = 0;
+ target_ulong val = 0;
if(sizeof(target_ulong) == 8)
reg_index /= 2;
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
2018-10-26 18:04 [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 Dayeol Lee
@ 2018-10-26 18:13 ` Dayeol Lee
2018-10-27 8:42 ` Alistair Francis
0 siblings, 1 reply; 4+ messages in thread
From: Dayeol Lee @ 2018-10-26 18:13 UTC (permalink / raw)
To: qemu-devel
Cc: Michael Clark, Palmer Dabbelt, Sagar Karandikar, Bastian Koppelmann
Hi,
I submitted the patch, but just found this has been already fixed by
Michael Clark
and pushed to riscv/riscv-qemu https://github.com/riscv/riscv-qemu/pull/166
but not in the upstream.
Do we still need this patch?
Thanks,
Dayeol
On Fri, Oct 26, 2018 at 11:04 AM Dayeol Lee <dayeol@berkeley.edu> wrote:
> pmp_read_cfg() returns 8-bit value, which is combined together to form a
> single pmpcfg CSR.
> The default promotion rules will result in an integer here ("i*8" is
> integer, which
> flows through) resulting in a 32-bit signed value on most hosts.
> That's bogus on RV64I, with the high bits of the CSR being wrong.
>
> Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> ---
> target/riscv/pmp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index c828950..3d3906a 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env,
> uint32_t reg_index)
> {
> int i;
> target_ulong cfg_val = 0;
> - uint8_t val = 0;
> + target_ulong val = 0;
>
> if(sizeof(target_ulong) == 8)
> reg_index /= 2;
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
2018-10-26 18:13 ` Dayeol Lee
@ 2018-10-27 8:42 ` Alistair Francis
2018-10-29 19:59 ` Palmer Dabbelt
0 siblings, 1 reply; 4+ messages in thread
From: Alistair Francis @ 2018-10-27 8:42 UTC (permalink / raw)
To: dayeol
Cc: qemu-devel@nongnu.org Developers, Bastian Koppelmann,
Michael Clark, Palmer Dabbelt, Sagar Karandikar
On Fri, Oct 26, 2018 at 7:14 PM Dayeol Lee <dayeol@berkeley.edu> wrote:
>
> Hi,
>
> I submitted the patch, but just found this has been already fixed by
> Michael Clark
> and pushed to riscv/riscv-qemu https://github.com/riscv/riscv-qemu/pull/166
> but not in the upstream.
>
> Do we still need this patch?
Yeah, this patch is still needed as it fixes the problem in mainline.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> Thanks,
>
> Dayeol
>
> On Fri, Oct 26, 2018 at 11:04 AM Dayeol Lee <dayeol@berkeley.edu> wrote:
>
> > pmp_read_cfg() returns 8-bit value, which is combined together to form a
> > single pmpcfg CSR.
> > The default promotion rules will result in an integer here ("i*8" is
> > integer, which
> > flows through) resulting in a 32-bit signed value on most hosts.
> > That's bogus on RV64I, with the high bits of the CSR being wrong.
> >
> > Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
> > Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
> > ---
> > target/riscv/pmp.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> > index c828950..3d3906a 100644
> > --- a/target/riscv/pmp.c
> > +++ b/target/riscv/pmp.c
> > @@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env,
> > uint32_t reg_index)
> > {
> > int i;
> > target_ulong cfg_val = 0;
> > - uint8_t val = 0;
> > + target_ulong val = 0;
> >
> > if(sizeof(target_ulong) == 8)
> > reg_index /= 2;
> > --
> > 2.7.4
> >
> >
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64
2018-10-27 8:42 ` Alistair Francis
@ 2018-10-29 19:59 ` Palmer Dabbelt
0 siblings, 0 replies; 4+ messages in thread
From: Palmer Dabbelt @ 2018-10-29 19:59 UTC (permalink / raw)
To: alistair23; +Cc: dayeol, qemu-devel, Bastian Koppelmann, Michael Clark, sagark
On Sat, 27 Oct 2018 01:42:02 PDT (-0700), alistair23@gmail.com wrote:
> On Fri, Oct 26, 2018 at 7:14 PM Dayeol Lee <dayeol@berkeley.edu> wrote:
>>
>> Hi,
>>
>> I submitted the patch, but just found this has been already fixed by
>> Michael Clark
>> and pushed to riscv/riscv-qemu https://github.com/riscv/riscv-qemu/pull/166
>> but not in the upstream.
>>
>> Do we still need this patch?
>
> Yeah, this patch is still needed as it fixes the problem in mainline.
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
Thanks. I added this to for-master, I'll include it with this week's PR.
>
>>
>> Thanks,
>>
>> Dayeol
>>
>> On Fri, Oct 26, 2018 at 11:04 AM Dayeol Lee <dayeol@berkeley.edu> wrote:
>>
>> > pmp_read_cfg() returns 8-bit value, which is combined together to form a
>> > single pmpcfg CSR.
>> > The default promotion rules will result in an integer here ("i*8" is
>> > integer, which
>> > flows through) resulting in a 32-bit signed value on most hosts.
>> > That's bogus on RV64I, with the high bits of the CSR being wrong.
>> >
>> > Signed-off-by: Dayeol Lee <dayeol@berkeley.edu>
>> > Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>> > ---
>> > target/riscv/pmp.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
>> > index c828950..3d3906a 100644
>> > --- a/target/riscv/pmp.c
>> > +++ b/target/riscv/pmp.c
>> > @@ -330,7 +330,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env,
>> > uint32_t reg_index)
>> > {
>> > int i;
>> > target_ulong cfg_val = 0;
>> > - uint8_t val = 0;
>> > + target_ulong val = 0;
>> >
>> > if(sizeof(target_ulong) == 8)
>> > reg_index /= 2;
>> > --
>> > 2.7.4
>> >
>> >
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-10-29 20:00 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-26 18:04 [Qemu-devel] [PATCH] target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64 Dayeol Lee
2018-10-26 18:13 ` Dayeol Lee
2018-10-27 8:42 ` Alistair Francis
2018-10-29 19:59 ` Palmer Dabbelt
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.