* [Qemu-devel] [Qemu devel v5 PATCH 1/5] msf2: Add Smartfusion2 System timer
2017-05-16 15:38 [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
@ 2017-05-16 15:38 ` Subbaraya Sundeep
2017-05-30 12:43 ` Philippe Mathieu-Daudé
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
` (4 subsequent siblings)
5 siblings, 1 reply; 35+ messages in thread
From: Subbaraya Sundeep @ 2017-05-16 15:38 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Modelled System Timer in Microsemi's Smartfusion2 Soc.
Timer has two 32bit down counters and two interrupts.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/timer/Makefile.objs | 1 +
hw/timer/mss-timer.c | 249 +++++++++++++++++++++++++++++++++++++++++++
include/hw/timer/mss-timer.h | 80 ++++++++++++++
3 files changed, 330 insertions(+)
create mode 100644 hw/timer/mss-timer.c
create mode 100644 include/hw/timer/mss-timer.h
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index dd6f27e..fc4d2da 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
+common-obj-$(CONFIG_MSF2) += mss-timer.o
diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
new file mode 100644
index 0000000..7041965
--- /dev/null
+++ b/hw/timer/mss-timer.c
@@ -0,0 +1,249 @@
+/*
+ * Block model of System timer present in
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/timer/mss-timer.h"
+
+#ifndef MSS_TIMER_ERR_DEBUG
+#define MSS_TIMER_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSS_TIMER_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void timer_update_irq(struct Msf2Timer *st)
+{
+ bool isr, ier;
+
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+
+ qemu_set_irq(st->irq, (ier && isr));
+}
+
+static void timer_update(struct Msf2Timer *st)
+{
+ uint64_t count;
+
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
+ ptimer_stop(st->ptimer);
+ return;
+ }
+
+ count = st->regs[R_TIM_LOADVAL];
+ ptimer_set_limit(st->ptimer, count, 1);
+ ptimer_run(st->ptimer, 1);
+}
+
+static uint64_t
+timer_read(void *opaque, hwaddr offset, unsigned int size)
+{
+ MSSTimerState *t = opaque;
+ hwaddr addr;
+ struct Msf2Timer *st;
+ uint32_t ret = 0;
+ int timer = 0;
+ int isr;
+ int ier;
+
+ addr = offset >> 2;
+ /*
+ * Two independent timers has same base address.
+ * Based on address passed figure out which timer is being used.
+ */
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
+ timer = 1;
+ addr -= R_TIM1_MAX;
+ }
+
+ st = &t->timers[timer];
+
+ switch (addr) {
+ case R_TIM_VAL:
+ ret = ptimer_get_count(st->ptimer);
+ break;
+
+ case R_TIM_MIS:
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+ ret = ier & isr;
+ break;
+
+ default:
+ if (addr < NUM_TIMERS * R_TIM1_MAX) {
+ ret = st->regs[addr];
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
+ }
+ break;
+ }
+
+ DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32 "\n", timer, offset,
+ ret);
+ return ret;
+}
+
+static void
+timer_write(void *opaque, hwaddr offset,
+ uint64_t val64, unsigned int size)
+{
+ MSSTimerState *t = opaque;
+ hwaddr addr;
+ struct Msf2Timer *st;
+ int timer = 0;
+ uint32_t value = val64;
+
+ addr = offset >> 2;
+ /*
+ * Two independent timers has same base address.
+ * Based on addr passed figure out which timer is being used.
+ */
+ if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
+ timer = 1;
+ addr -= R_TIM1_MAX;
+ }
+
+ st = &t->timers[timer];
+
+ DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)\n", offset,
+ value, timer);
+
+ switch (addr) {
+ case R_TIM_CTRL:
+ st->regs[R_TIM_CTRL] = value;
+ timer_update(st);
+ break;
+
+ case R_TIM_RIS:
+ if (value & TIMER_RIS_ACK) {
+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
+ }
+ break;
+
+ case R_TIM_LOADVAL:
+ st->regs[R_TIM_LOADVAL] = value;
+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
+ timer_update(st);
+ }
+ break;
+
+ case R_TIM_BGLOADVAL:
+ st->regs[R_TIM_BGLOADVAL] = value;
+ st->regs[R_TIM_LOADVAL] = value;
+ break;
+
+ case R_TIM_VAL:
+ case R_TIM_MIS:
+ break;
+
+ default:
+ if (addr < NUM_TIMERS * R_TIM1_MAX) {
+ st->regs[addr] = value;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSS_TIMER": 64-bit mode not supported\n");
+ return;
+ }
+ break;
+ }
+ timer_update_irq(st);
+}
+
+static const MemoryRegionOps timer_ops = {
+ .read = timer_read,
+ .write = timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ }
+};
+
+static void timer_hit(void *opaque)
+{
+ struct Msf2Timer *st = opaque;
+
+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
+
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
+ timer_update(st);
+ }
+ timer_update_irq(st);
+}
+
+static void mss_timer_init(Object *obj)
+{
+ MSSTimerState *t = MSS_TIMER(obj);
+ int i;
+
+ /* Init all the ptimers. */
+ t->timers = g_malloc0((sizeof t->timers[0]) * NUM_TIMERS);
+ for (i = 0; i < NUM_TIMERS; i++) {
+ struct Msf2Timer *st = &t->timers[i];
+
+ st->bh = qemu_bh_new(timer_hit, st);
+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
+ ptimer_set_freq(st->ptimer, t->freq_hz);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
+ }
+
+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
+ NUM_TIMERS * R_TIM1_MAX * 4);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
+}
+
+static Property mss_timer_properties[] = {
+ /* Libero GUI shows 100Mhz as default for clocks */
+ DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
+ 100 * 1000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void mss_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->props = mss_timer_properties;
+}
+
+static const TypeInfo mss_timer_info = {
+ .name = TYPE_MSS_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSSTimerState),
+ .instance_init = mss_timer_init,
+ .class_init = mss_timer_class_init,
+};
+
+static void mss_timer_register_types(void)
+{
+ type_register_static(&mss_timer_info);
+}
+
+type_init(mss_timer_register_types)
diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
new file mode 100644
index 0000000..4caacfd
--- /dev/null
+++ b/include/hw/timer/mss-timer.h
@@ -0,0 +1,80 @@
+/*
+ * Microsemi SmartFusion2 Timer.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSS_TIMER_H
+#define HW_MSS_TIMER_H
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+
+#define TYPE_MSS_TIMER "mss-timer"
+#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
+ (obj), TYPE_MSS_TIMER)
+
+/*
+ * There are two 32-bit down counting timers.
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
+ * that operates either in Periodic mode or in One-shot mode.
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
+ * has no effect. Only two 32-bit timers are supported currently.
+ */
+#define NUM_TIMERS 2
+
+#define R_TIM_VAL 0
+#define R_TIM_LOADVAL 1
+#define R_TIM_BGLOADVAL 2
+#define R_TIM_CTRL 3
+#define R_TIM_RIS 4
+#define R_TIM_MIS 5
+#define R_TIM1_MAX 6
+
+#define TIMER_CTRL_ENBL (1 << 0)
+#define TIMER_CTRL_ONESHOT (1 << 1)
+#define TIMER_CTRL_INTR (1 << 2)
+#define TIMER_RIS_ACK (1 << 0)
+#define TIMER_RST_CLR (1 << 6)
+#define TIMER_MODE (1 << 0)
+
+struct Msf2Timer {
+ QEMUBH *bh;
+ ptimer_state *ptimer;
+
+ uint32_t regs[NUM_TIMERS * R_TIM1_MAX];
+ qemu_irq irq;
+};
+
+typedef struct MSSTimerState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+ uint32_t freq_hz;
+ struct Msf2Timer *timers;
+} MSSTimerState;
+
+#endif /* HW_MSS_TIMER_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 1/5] msf2: Add Smartfusion2 System timer
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
@ 2017-05-30 12:43 ` Philippe Mathieu-Daudé
2017-06-24 12:25 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-05-30 12:43 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
Hi Subbaraya,
I have some comments, see inlined.
On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
> Modelled System Timer in Microsemi's Smartfusion2 Soc.
> Timer has two 32bit down counters and two interrupts.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> hw/timer/Makefile.objs | 1 +
> hw/timer/mss-timer.c | 249 +++++++++++++++++++++++++++++++++++++++++++
> include/hw/timer/mss-timer.h | 80 ++++++++++++++
> 3 files changed, 330 insertions(+)
> create mode 100644 hw/timer/mss-timer.c
> create mode 100644 include/hw/timer/mss-timer.h
>
> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> index dd6f27e..fc4d2da 100644
> --- a/hw/timer/Makefile.objs
> +++ b/hw/timer/Makefile.objs
> @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
>
> common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
> +common-obj-$(CONFIG_MSF2) += mss-timer.o
> diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
> new file mode 100644
> index 0000000..7041965
> --- /dev/null
> +++ b/hw/timer/mss-timer.c
> @@ -0,0 +1,249 @@
> +/*
> + * Block model of System timer present in
> + * Microsemi's SmartFusion2 and SmartFusion SoCs.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/timer/mss-timer.h"
> +
> +#ifndef MSS_TIMER_ERR_DEBUG
> +#define MSS_TIMER_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSS_TIMER_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt, __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void timer_update_irq(struct Msf2Timer *st)
> +{
> + bool isr, ier;
> +
> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
> +
> + qemu_set_irq(st->irq, (ier && isr));
> +}
> +
> +static void timer_update(struct Msf2Timer *st)
> +{
> + uint64_t count;
> +
> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
> + ptimer_stop(st->ptimer);
> + return;
> + }
> +
> + count = st->regs[R_TIM_LOADVAL];
> + ptimer_set_limit(st->ptimer, count, 1);
> + ptimer_run(st->ptimer, 1);
> +}
> +
> +static uint64_t
> +timer_read(void *opaque, hwaddr offset, unsigned int size)
> +{
> + MSSTimerState *t = opaque;
> + hwaddr addr;
> + struct Msf2Timer *st;
> + uint32_t ret = 0;
> + int timer = 0;
> + int isr;
> + int ier;
> +
> + addr = offset >> 2;
> + /*
> + * Two independent timers has same base address.
> + * Based on address passed figure out which timer is being used.
> + */
> + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
> + timer = 1;
> + addr -= R_TIM1_MAX;
> + }
> +
> + st = &t->timers[timer];
> +
> + switch (addr) {
> + case R_TIM_VAL:
> + ret = ptimer_get_count(st->ptimer);
> + break;
> +
> + case R_TIM_MIS:
> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
> + ret = ier & isr;
> + break;
> +
> + default:
> + if (addr < NUM_TIMERS * R_TIM1_MAX) {
> + ret = st->regs[addr];
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + TYPE_MSS_TIMER": 64-bit mode not supported\n");
> + }
> + break;
> + }
> +
> + DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32 "\n", timer, offset,
> + ret);
> + return ret;
> +}
> +
> +static void
> +timer_write(void *opaque, hwaddr offset,
> + uint64_t val64, unsigned int size)
> +{
> + MSSTimerState *t = opaque;
> + hwaddr addr;
> + struct Msf2Timer *st;
> + int timer = 0;
> + uint32_t value = val64;
> +
> + addr = offset >> 2;
> + /*
> + * Two independent timers has same base address.
> + * Based on addr passed figure out which timer is being used.
> + */
> + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
> + timer = 1;
> + addr -= R_TIM1_MAX;
> + }
> +
> + st = &t->timers[timer];
> +
> + DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)\n", offset,
> + value, timer);
> +
> + switch (addr) {
> + case R_TIM_CTRL:
> + st->regs[R_TIM_CTRL] = value;
> + timer_update(st);
> + break;
> +
> + case R_TIM_RIS:
> + if (value & TIMER_RIS_ACK) {
> + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
> + }
> + break;
> +
> + case R_TIM_LOADVAL:
> + st->regs[R_TIM_LOADVAL] = value;
> + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
> + timer_update(st);
> + }
> + break;
> +
> + case R_TIM_BGLOADVAL:
> + st->regs[R_TIM_BGLOADVAL] = value;
> + st->regs[R_TIM_LOADVAL] = value;
> + break;
> +
> + case R_TIM_VAL:
> + case R_TIM_MIS:
> + break;
> +
> + default:
> + if (addr < NUM_TIMERS * R_TIM1_MAX) {
> + st->regs[addr] = value;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + TYPE_MSS_TIMER": 64-bit mode not supported\n");
> + return;
> + }
> + break;
> + }
> + timer_update_irq(st);
> +}
> +
> +static const MemoryRegionOps timer_ops = {
> + .read = timer_read,
> + .write = timer_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4
> + }
> +};
> +
> +static void timer_hit(void *opaque)
> +{
> + struct Msf2Timer *st = opaque;
> +
> + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
> +
> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
> + timer_update(st);
> + }
> + timer_update_irq(st);
> +}
> +
> +static void mss_timer_init(Object *obj)
> +{
> + MSSTimerState *t = MSS_TIMER(obj);
> + int i;
> +
> + /* Init all the ptimers. */
> + t->timers = g_malloc0((sizeof t->timers[0]) * NUM_TIMERS);
> + for (i = 0; i < NUM_TIMERS; i++) {
> + struct Msf2Timer *st = &t->timers[i];
> +
> + st->bh = qemu_bh_new(timer_hit, st);
> + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
> + ptimer_set_freq(st->ptimer, t->freq_hz);
> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
> + }
> +
> + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER,
> + NUM_TIMERS * R_TIM1_MAX * 4);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
> +}
> +
> +static Property mss_timer_properties[] = {
> + /* Libero GUI shows 100Mhz as default for clocks */
> + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
> + 100 * 1000000),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void mss_timer_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->props = mss_timer_properties;
> +}
> +
> +static const TypeInfo mss_timer_info = {
> + .name = TYPE_MSS_TIMER,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSSTimerState),
> + .instance_init = mss_timer_init,
> + .class_init = mss_timer_class_init,
> +};
> +
> +static void mss_timer_register_types(void)
> +{
> + type_register_static(&mss_timer_info);
> +}
> +
> +type_init(mss_timer_register_types)
> diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
> new file mode 100644
> index 0000000..4caacfd
> --- /dev/null
> +++ b/include/hw/timer/mss-timer.h
> @@ -0,0 +1,80 @@
> +/*
> + * Microsemi SmartFusion2 Timer.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MSS_TIMER_H
> +#define HW_MSS_TIMER_H
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/ptimer.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/log.h"
> +
> +#define TYPE_MSS_TIMER "mss-timer"
> +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
> + (obj), TYPE_MSS_TIMER)
> +
> +/*
> + * There are two 32-bit down counting timers.
> + * Timers 1 and 2 can be concatenated into a single 64-bit Timer
> + * that operates either in Periodic mode or in One-shot mode.
> + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
> + * In 64-bit mode, writing to the 32-bit registers has no effect.
> + * Similarly, in 32-bit mode, writing to the 64-bit mode registers
> + * has no effect. Only two 32-bit timers are supported currently.
> + */
> +#define NUM_TIMERS 2
> +
> +#define R_TIM_VAL 0
> +#define R_TIM_LOADVAL 1
> +#define R_TIM_BGLOADVAL 2
> +#define R_TIM_CTRL 3
> +#define R_TIM_RIS 4
> +#define R_TIM_MIS 5
> +#define R_TIM1_MAX 6
> +
From here ...
> +#define TIMER_CTRL_ENBL (1 << 0)
> +#define TIMER_CTRL_ONESHOT (1 << 1)
> +#define TIMER_CTRL_INTR (1 << 2)
> +#define TIMER_RIS_ACK (1 << 0)
> +#define TIMER_RST_CLR (1 << 6)
> +#define TIMER_MODE (1 << 0)
.. to here, can go in the .c source file.
I'd also move R_TIM_* to the source, only keeping R_TIM_MAX in this
header, or also moving it and exposing some TIMER_IO_SIZE of 0x30 instead.
> +
> +struct Msf2Timer {
> + QEMUBH *bh;
> + ptimer_state *ptimer;
> +
> + uint32_t regs[NUM_TIMERS * R_TIM1_MAX];
Beware, you are declaring 2 sets of register for each timer. I think
it'd be safer to declare these registers once in MSSTimerState, the code
would get easier.
> + qemu_irq irq;
> +};
> +
> +typedef struct MSSTimerState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> + uint32_t freq_hz;
> + struct Msf2Timer *timers;
The number of timers is fixed (NUM_TIMERS), so you can declare it here
and avoid to use g_malloc0() in mss_timer_init(), this will get
allocated before mss_timer_init() using mss_timer_info.instance_size.
This should simplify a bit.
> +} MSSTimerState;
> +
> +#endif /* HW_MSS_TIMER_H */
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 1/5] msf2: Add Smartfusion2 System timer
2017-05-30 12:43 ` Philippe Mathieu-Daudé
@ 2017-06-24 12:25 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-24 12:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Tue, May 30, 2017 at 6:13 PM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Subbaraya,
>
> I have some comments, see inlined.
>
>
> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>
>> Modelled System Timer in Microsemi's Smartfusion2 Soc.
>> Timer has two 32bit down counters and two interrupts.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> ---
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/mss-timer.c | 249 ++++++++++++++++++++++++++++++
>> +++++++++++++
>> include/hw/timer/mss-timer.h | 80 ++++++++++++++
>> 3 files changed, 330 insertions(+)
>> create mode 100644 hw/timer/mss-timer.c
>> create mode 100644 include/hw/timer/mss-timer.h
>>
>> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
>> index dd6f27e..fc4d2da 100644
>> --- a/hw/timer/Makefile.objs
>> +++ b/hw/timer/Makefile.objs
>> @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) +=
>> stm32f2xx_timer.o
>> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
>>
>> common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
>> +common-obj-$(CONFIG_MSF2) += mss-timer.o
>> diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
>> new file mode 100644
>> index 0000000..7041965
>> --- /dev/null
>> +++ b/hw/timer/mss-timer.c
>> @@ -0,0 +1,249 @@
>> +/*
>> + * Block model of System timer present in
>> + * Microsemi's SmartFusion2 and SmartFusion SoCs.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/timer/mss-timer.h"
>> +
>> +#ifndef MSS_TIMER_ERR_DEBUG
>> +#define MSS_TIMER_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> + if (MSS_TIMER_ERR_DEBUG >= lvl) { \
>> + qemu_log("%s: " fmt, __func__, ## args); \
>> + } \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static void timer_update_irq(struct Msf2Timer *st)
>> +{
>> + bool isr, ier;
>> +
>> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
>> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
>> +
>> + qemu_set_irq(st->irq, (ier && isr));
>> +}
>> +
>> +static void timer_update(struct Msf2Timer *st)
>> +{
>> + uint64_t count;
>> +
>> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
>> + ptimer_stop(st->ptimer);
>> + return;
>> + }
>> +
>> + count = st->regs[R_TIM_LOADVAL];
>> + ptimer_set_limit(st->ptimer, count, 1);
>> + ptimer_run(st->ptimer, 1);
>> +}
>> +
>> +static uint64_t
>> +timer_read(void *opaque, hwaddr offset, unsigned int size)
>> +{
>> + MSSTimerState *t = opaque;
>> + hwaddr addr;
>> + struct Msf2Timer *st;
>> + uint32_t ret = 0;
>> + int timer = 0;
>> + int isr;
>> + int ier;
>> +
>> + addr = offset >> 2;
>> + /*
>> + * Two independent timers has same base address.
>> + * Based on address passed figure out which timer is being used.
>> + */
>> + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
>> + timer = 1;
>> + addr -= R_TIM1_MAX;
>> + }
>> +
>> + st = &t->timers[timer];
>> +
>> + switch (addr) {
>> + case R_TIM_VAL:
>> + ret = ptimer_get_count(st->ptimer);
>> + break;
>> +
>> + case R_TIM_MIS:
>> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
>> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
>> + ret = ier & isr;
>> + break;
>> +
>> + default:
>> + if (addr < NUM_TIMERS * R_TIM1_MAX) {
>> + ret = st->regs[addr];
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + TYPE_MSS_TIMER": 64-bit mode not supported\n");
>> + }
>> + break;
>> + }
>> +
>> + DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32 "\n", timer,
>> offset,
>> + ret);
>> + return ret;
>> +}
>> +
>> +static void
>> +timer_write(void *opaque, hwaddr offset,
>> + uint64_t val64, unsigned int size)
>> +{
>> + MSSTimerState *t = opaque;
>> + hwaddr addr;
>> + struct Msf2Timer *st;
>> + int timer = 0;
>> + uint32_t value = val64;
>> +
>> + addr = offset >> 2;
>> + /*
>> + * Two independent timers has same base address.
>> + * Based on addr passed figure out which timer is being used.
>> + */
>> + if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
>> + timer = 1;
>> + addr -= R_TIM1_MAX;
>> + }
>> +
>> + st = &t->timers[timer];
>> +
>> + DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)\n",
>> offset,
>> + value, timer);
>> +
>> + switch (addr) {
>> + case R_TIM_CTRL:
>> + st->regs[R_TIM_CTRL] = value;
>> + timer_update(st);
>> + break;
>> +
>> + case R_TIM_RIS:
>> + if (value & TIMER_RIS_ACK) {
>> + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
>> + }
>> + break;
>> +
>> + case R_TIM_LOADVAL:
>> + st->regs[R_TIM_LOADVAL] = value;
>> + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
>> + timer_update(st);
>> + }
>> + break;
>> +
>> + case R_TIM_BGLOADVAL:
>> + st->regs[R_TIM_BGLOADVAL] = value;
>> + st->regs[R_TIM_LOADVAL] = value;
>> + break;
>> +
>> + case R_TIM_VAL:
>> + case R_TIM_MIS:
>> + break;
>> +
>> + default:
>> + if (addr < NUM_TIMERS * R_TIM1_MAX) {
>> + st->regs[addr] = value;
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + TYPE_MSS_TIMER": 64-bit mode not supported\n");
>> + return;
>> + }
>> + break;
>> + }
>> + timer_update_irq(st);
>> +}
>> +
>> +static const MemoryRegionOps timer_ops = {
>> + .read = timer_read,
>> + .write = timer_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 1,
>> + .max_access_size = 4
>> + }
>> +};
>> +
>> +static void timer_hit(void *opaque)
>> +{
>> + struct Msf2Timer *st = opaque;
>> +
>> + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
>> +
>> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
>> + timer_update(st);
>> + }
>> + timer_update_irq(st);
>> +}
>> +
>> +static void mss_timer_init(Object *obj)
>> +{
>> + MSSTimerState *t = MSS_TIMER(obj);
>> + int i;
>> +
>> + /* Init all the ptimers. */
>> + t->timers = g_malloc0((sizeof t->timers[0]) * NUM_TIMERS);
>> + for (i = 0; i < NUM_TIMERS; i++) {
>> + struct Msf2Timer *st = &t->timers[i];
>> +
>> + st->bh = qemu_bh_new(timer_hit, st);
>> + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
>> + ptimer_set_freq(st->ptimer, t->freq_hz);
>> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
>> + }
>> +
>> + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
>> TYPE_MSS_TIMER,
>> + NUM_TIMERS * R_TIM1_MAX * 4);
>> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
>> +}
>> +
>> +static Property mss_timer_properties[] = {
>> + /* Libero GUI shows 100Mhz as default for clocks */
>> + DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz,
>> + 100 * 1000000),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void mss_timer_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->props = mss_timer_properties;
>> +}
>> +
>> +static const TypeInfo mss_timer_info = {
>> + .name = TYPE_MSS_TIMER,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(MSSTimerState),
>> + .instance_init = mss_timer_init,
>> + .class_init = mss_timer_class_init,
>> +};
>> +
>> +static void mss_timer_register_types(void)
>> +{
>> + type_register_static(&mss_timer_info);
>> +}
>> +
>> +type_init(mss_timer_register_types)
>> diff --git a/include/hw/timer/mss-timer.h b/include/hw/timer/mss-timer.h
>> new file mode 100644
>> index 0000000..4caacfd
>> --- /dev/null
>> +++ b/include/hw/timer/mss-timer.h
>> @@ -0,0 +1,80 @@
>> +/*
>> + * Microsemi SmartFusion2 Timer.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_MSS_TIMER_H
>> +#define HW_MSS_TIMER_H
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/ptimer.h"
>> +#include "sysemu/sysemu.h"
>> +#include "qemu/log.h"
>> +
>> +#define TYPE_MSS_TIMER "mss-timer"
>> +#define MSS_TIMER(obj) OBJECT_CHECK(MSSTimerState, \
>> + (obj), TYPE_MSS_TIMER)
>> +
>> +/*
>> + * There are two 32-bit down counting timers.
>> + * Timers 1 and 2 can be concatenated into a single 64-bit Timer
>> + * that operates either in Periodic mode or in One-shot mode.
>> + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit
>> mode.
>> + * In 64-bit mode, writing to the 32-bit registers has no effect.
>> + * Similarly, in 32-bit mode, writing to the 64-bit mode registers
>> + * has no effect. Only two 32-bit timers are supported currently.
>> + */
>> +#define NUM_TIMERS 2
>> +
>> +#define R_TIM_VAL 0
>> +#define R_TIM_LOADVAL 1
>> +#define R_TIM_BGLOADVAL 2
>> +#define R_TIM_CTRL 3
>> +#define R_TIM_RIS 4
>> +#define R_TIM_MIS 5
>> +#define R_TIM1_MAX 6
>> +
>>
>
> From here ...
>
> +#define TIMER_CTRL_ENBL (1 << 0)
>> +#define TIMER_CTRL_ONESHOT (1 << 1)
>> +#define TIMER_CTRL_INTR (1 << 2)
>> +#define TIMER_RIS_ACK (1 << 0)
>> +#define TIMER_RST_CLR (1 << 6)
>> +#define TIMER_MODE (1 << 0)
>>
>
> .. to here, can go in the .c source file.
>
> I'd also move R_TIM_* to the source, only keeping R_TIM_MAX in this
> header, or also moving it and exposing some TIMER_IO_SIZE of 0x30 instead.
>
Ok will move to .c source file.
>
> +
>> +struct Msf2Timer {
>> + QEMUBH *bh;
>> + ptimer_state *ptimer;
>> +
>> + uint32_t regs[NUM_TIMERS * R_TIM1_MAX];
>>
>
> Beware, you are declaring 2 sets of register for each timer. I think it'd
> be safer to declare these registers once in MSSTimerState, the code would
> get easier.
>
Thanks for catching this. I will use regs[R_TIM1_MAX] so that Msf2Timer
represents
one timer block.
>
> + qemu_irq irq;
>> +};
>> +
>> +typedef struct MSSTimerState {
>> + SysBusDevice parent_obj;
>> +
>> + MemoryRegion mmio;
>> + uint32_t freq_hz;
>> + struct Msf2Timer *timers;
>>
>
> The number of timers is fixed (NUM_TIMERS), so you can declare it here and
> avoid to use g_malloc0() in mss_timer_init(), this will get allocated
> before mss_timer_init() using mss_timer_info.instance_size.
>
> This should simplify a bit.
Yes will remove g_malloc and declare here in MSSTimerState.
Thanks,
Sundeep
>
>
> +} MSSTimerState;
>> +
>> +#endif /* HW_MSS_TIMER_H */
>>
>>
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [Qemu devel v5 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block.
2017-05-16 15:38 [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
@ 2017-05-16 15:38 ` Subbaraya Sundeep
2017-05-30 12:51 ` Philippe Mathieu-Daudé
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
` (3 subsequent siblings)
5 siblings, 1 reply; 35+ messages in thread
From: Subbaraya Sundeep @ 2017-05-16 15:38 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Added Sytem register block of Smartfusion2.
This block has PLL registers which are accessed by guest.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/msf2-sysreg.c | 161 ++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/msf2-sysreg.h | 80 +++++++++++++++++++++
3 files changed, 242 insertions(+)
create mode 100644 hw/misc/msf2-sysreg.c
create mode 100644 include/hw/misc/msf2-sysreg.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c8b4893..0f52354 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) += edu.o
obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
+obj-$(CONFIG_MSF2) += msf2-sysreg.o
diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
new file mode 100644
index 0000000..8d3118f
--- /dev/null
+++ b/hw/misc/msf2-sysreg.c
@@ -0,0 +1,161 @@
+/*
+ * System Register block model of Microsemi SmartFusion2.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "hw/misc/msf2-sysreg.h"
+
+#ifndef MSF2_SYSREG_ERR_DEBUG
+#define MSF2_SYSREG_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void msf2_sysreg_reset(DeviceState *d)
+{
+ MSF2SysregState *s = MSF2_SYSREG(d);
+
+ DB_PRINT("RESET\n");
+
+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
+ s->regs[MSSDDR_FACC1_CR] = 0x0B800124;
+ s->regs[MSSDDR_PLL_STATUS] = 0x3;
+}
+
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ MSF2SysregState *s = opaque;
+ offset /= 4;
+ uint32_t ret = 0;
+
+ if (offset < ARRAY_SIZE(s->regs)) {
+ ret = s->regs[offset];
+ DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32 "\n",
+ offset * 4, ret);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
+ offset * 4);
+ }
+
+ return ret;
+}
+
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ MSF2SysregState *s = (MSF2SysregState *)opaque;
+ uint32_t newval = val;
+ uint32_t oldval;
+
+ offset /= 4;
+
+ DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64 "\n",
+ offset * 4, val);
+
+ switch (offset) {
+ case MSSDDR_PLL_STATUS:
+ break;
+
+ case ESRAM_CR:
+ oldval = s->regs[ESRAM_CR];
+ if (oldval ^ newval) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSF2_SYSREG": eSRAM remapping not supported\n");
+ abort();
+ }
+ break;
+
+ case DDR_CR:
+ oldval = s->regs[DDR_CR];
+ if (oldval ^ newval) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSF2_SYSREG": DDR remapping not supported\n");
+ abort();
+ }
+ break;
+
+ case ENVM_REMAP_BASE_CR:
+ oldval = s->regs[ENVM_REMAP_BASE_CR];
+ if (oldval ^ newval) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ TYPE_MSF2_SYSREG": eNVM remapping not supported\n");
+ abort();
+ }
+ break;
+
+ default:
+ if (offset < ARRAY_SIZE(s->regs)) {
+ s->regs[offset] = val;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
+ offset * 4);
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps sysreg_ops = {
+ .read = msf2_sysreg_read,
+ .write = msf2_sysreg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void msf2_sysreg_init(Object *obj)
+{
+ MSF2SysregState *s = MSF2_SYSREG(obj);
+
+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
+ MSF2_SYSREG_MMIO_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static const VMStateDescription vmstate_msf2_sysreg = {
+ .name = TYPE_MSF2_SYSREG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_NUM_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_msf2_sysreg;
+ dc->reset = msf2_sysreg_reset;
+}
+
+static const TypeInfo msf2_sysreg_info = {
+ .name = TYPE_MSF2_SYSREG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .class_init = msf2_sysreg_class_init,
+ .instance_size = sizeof(MSF2SysregState),
+ .instance_init = msf2_sysreg_init,
+};
+
+static void msf2_sysreg_register_types(void)
+{
+ type_register_static(&msf2_sysreg_info);
+}
+
+type_init(msf2_sysreg_register_types)
diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
new file mode 100644
index 0000000..a485ed6
--- /dev/null
+++ b/include/hw/misc/msf2-sysreg.h
@@ -0,0 +1,80 @@
+/*
+ * Microsemi SmartFusion2 SYSREG
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSF2_SYSREG_H
+#define HW_MSF2_SYSREG_H
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+
+enum {
+ ESRAM_CR = 0x00 / 4,
+ ESRAM_MAX_LAT,
+ DDR_CR,
+ ENVM_CR,
+ ENVM_REMAP_BASE_CR,
+ ENVM_REMAP_FAB_CR,
+ CC_CR,
+ CC_REGION_CR,
+ CC_LOCK_BASE_ADDR_CR,
+ CC_FLUSH_INDX_CR,
+ DDRB_BUF_TIMER_CR,
+ DDRB_NB_ADDR_CR,
+ DDRB_NB_SIZE_CR,
+ DDRB_CR,
+
+ SOFT_RESET_CR = 0x48 / 4,
+ M3_CR,
+
+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,
+
+ MDDR_CR = 0x60 / 4,
+
+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
+ MSSDDR_PLL_STATUS_HIGH_CR,
+ MSSDDR_FACC1_CR,
+ MSSDDR_FACC2_CR,
+
+ MSSDDR_PLL_STATUS = 0x150 / 4,
+
+};
+
+#define MSF2_SYSREG_MMIO_SIZE 0x300
+#define MSF2_SYSREG_NUM_REGS (MSF2_SYSREG_MMIO_SIZE / 4)
+
+#define TYPE_MSF2_SYSREG "msf2-sysreg"
+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
+
+typedef struct MSF2SysregState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ uint32_t regs[MSF2_SYSREG_NUM_REGS];
+} MSF2SysregState;
+
+#endif /* HW_MSF2_SYSREG_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block.
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
@ 2017-05-30 12:51 ` Philippe Mathieu-Daudé
2017-06-24 12:48 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-05-30 12:51 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
Hi Subbaraya,
This patch looks good.
On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
> Added Sytem register block of Smartfusion2.
> This block has PLL registers which are accessed by guest.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> hw/misc/Makefile.objs | 1 +
> hw/misc/msf2-sysreg.c | 161 ++++++++++++++++++++++++++++++++++++++++++
> include/hw/misc/msf2-sysreg.h | 80 +++++++++++++++++++++
> 3 files changed, 242 insertions(+)
> create mode 100644 hw/misc/msf2-sysreg.c
> create mode 100644 include/hw/misc/msf2-sysreg.h
>
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index c8b4893..0f52354 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) += edu.o
> obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
> obj-$(CONFIG_AUX) += auxbus.o
> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
> +obj-$(CONFIG_MSF2) += msf2-sysreg.o
> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
> new file mode 100644
> index 0000000..8d3118f
> --- /dev/null
> +++ b/hw/misc/msf2-sysreg.c
> @@ -0,0 +1,161 @@
> +/*
> + * System Register block model of Microsemi SmartFusion2.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "hw/misc/msf2-sysreg.h"
> +
> +#ifndef MSF2_SYSREG_ERR_DEBUG
> +#define MSF2_SYSREG_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt, __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void msf2_sysreg_reset(DeviceState *d)
> +{
> + MSF2SysregState *s = MSF2_SYSREG(d);
> +
> + DB_PRINT("RESET\n");
> +
> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
> + s->regs[MSSDDR_FACC1_CR] = 0x0B800124;
> + s->regs[MSSDDR_PLL_STATUS] = 0x3;
I'll have a closer look a those values.
> +}
> +
> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + MSF2SysregState *s = opaque;
> + offset /= 4;
> + uint32_t ret = 0;
> +
> + if (offset < ARRAY_SIZE(s->regs)) {
> + ret = s->regs[offset];
> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32 "\n",
> + offset * 4, ret);
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
> + offset * 4);
> + }
> +
> + return ret;
> +}
> +
> +static void msf2_sysreg_write(void *opaque, hwaddr offset,
> + uint64_t val, unsigned size)
> +{
> + MSF2SysregState *s = (MSF2SysregState *)opaque;
> + uint32_t newval = val;
> + uint32_t oldval;
> +
> + offset /= 4;
> +
> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64 "\n",
> + offset * 4, val);
> +
> + switch (offset) {
> + case MSSDDR_PLL_STATUS:
> + break;
> +
> + case ESRAM_CR:
> + oldval = s->regs[ESRAM_CR];
> + if (oldval ^ newval) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + TYPE_MSF2_SYSREG": eSRAM remapping not supported\n");
> + abort();
> + }
> + break;
> +
> + case DDR_CR:
> + oldval = s->regs[DDR_CR];
> + if (oldval ^ newval) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + TYPE_MSF2_SYSREG": DDR remapping not supported\n");
> + abort();
> + }
> + break;
> +
> + case ENVM_REMAP_BASE_CR:
> + oldval = s->regs[ENVM_REMAP_BASE_CR];
> + if (oldval ^ newval) {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + TYPE_MSF2_SYSREG": eNVM remapping not supported\n");
> + abort();
> + }
> + break;
Thanks for adding the remap checks :)
> +
> + default:
> + if (offset < ARRAY_SIZE(s->regs)) {
> + s->regs[offset] = val;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
> + offset * 4);
> + }
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps sysreg_ops = {
> + .read = msf2_sysreg_read,
> + .write = msf2_sysreg_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void msf2_sysreg_init(Object *obj)
> +{
> + MSF2SysregState *s = MSF2_SYSREG(obj);
> +
> + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
> + MSF2_SYSREG_MMIO_SIZE);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
> +}
> +
> +static const VMStateDescription vmstate_msf2_sysreg = {
> + .name = TYPE_MSF2_SYSREG,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_NUM_REGS),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->vmsd = &vmstate_msf2_sysreg;
> + dc->reset = msf2_sysreg_reset;
> +}
> +
> +static const TypeInfo msf2_sysreg_info = {
> + .name = TYPE_MSF2_SYSREG,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .class_init = msf2_sysreg_class_init,
> + .instance_size = sizeof(MSF2SysregState),
> + .instance_init = msf2_sysreg_init,
> +};
> +
> +static void msf2_sysreg_register_types(void)
> +{
> + type_register_static(&msf2_sysreg_info);
> +}
> +
> +type_init(msf2_sysreg_register_types)
> diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h
> new file mode 100644
> index 0000000..a485ed6
> --- /dev/null
> +++ b/include/hw/misc/msf2-sysreg.h
> @@ -0,0 +1,80 @@
> +/*
> + * Microsemi SmartFusion2 SYSREG
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MSF2_SYSREG_H
> +#define HW_MSF2_SYSREG_H
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/hw.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/log.h"
> +
> +enum {
> + ESRAM_CR = 0x00 / 4,
> + ESRAM_MAX_LAT,
> + DDR_CR,
> + ENVM_CR,
> + ENVM_REMAP_BASE_CR,
> + ENVM_REMAP_FAB_CR,
> + CC_CR,
> + CC_REGION_CR,
> + CC_LOCK_BASE_ADDR_CR,
> + CC_FLUSH_INDX_CR,
> + DDRB_BUF_TIMER_CR,
> + DDRB_NB_ADDR_CR,
> + DDRB_NB_SIZE_CR,
> + DDRB_CR,
> +
> + SOFT_RESET_CR = 0x48 / 4,
> + M3_CR,
> +
> + GPIO_SYSRESET_SEL_CR = 0x58 / 4,
> +
> + MDDR_CR = 0x60 / 4,
> +
> + MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
> + MSSDDR_PLL_STATUS_HIGH_CR,
> + MSSDDR_FACC1_CR,
> + MSSDDR_FACC2_CR,
> +
> + MSSDDR_PLL_STATUS = 0x150 / 4,
> +
> +};
> +
> +#define MSF2_SYSREG_MMIO_SIZE 0x300
> +#define MSF2_SYSREG_NUM_REGS (MSF2_SYSREG_MMIO_SIZE / 4)
I don't think this define is very useful.
> +
> +#define TYPE_MSF2_SYSREG "msf2-sysreg"
> +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
> +
> +typedef struct MSF2SysregState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> +
> + uint32_t regs[MSF2_SYSREG_NUM_REGS];
> +} MSF2SysregState;
> +
> +#endif /* HW_MSF2_SYSREG_H */
>
Regards,
Phil.
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block.
2017-05-30 12:51 ` Philippe Mathieu-Daudé
@ 2017-06-24 12:48 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-24 12:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Tue, May 30, 2017 at 6:21 PM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Subbaraya,
>
> This patch looks good.
>
>
> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>
>> Added Sytem register block of Smartfusion2.
>> This block has PLL registers which are accessed by guest.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> ---
>> hw/misc/Makefile.objs | 1 +
>> hw/misc/msf2-sysreg.c | 161 ++++++++++++++++++++++++++++++
>> ++++++++++++
>> include/hw/misc/msf2-sysreg.h | 80 +++++++++++++++++++++
>> 3 files changed, 242 insertions(+)
>> create mode 100644 hw/misc/msf2-sysreg.c
>> create mode 100644 include/hw/misc/msf2-sysreg.h
>>
>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
>> index c8b4893..0f52354 100644
>> --- a/hw/misc/Makefile.objs
>> +++ b/hw/misc/Makefile.objs
>> @@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) += edu.o
>> obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
>> obj-$(CONFIG_AUX) += auxbus.o
>> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
>> +obj-$(CONFIG_MSF2) += msf2-sysreg.o
>> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c
>> new file mode 100644
>> index 0000000..8d3118f
>> --- /dev/null
>> +++ b/hw/misc/msf2-sysreg.c
>> @@ -0,0 +1,161 @@
>> +/*
>> + * System Register block model of Microsemi SmartFusion2.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version
>> + * 2 of the License, or (at your option) any later version.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include "hw/misc/msf2-sysreg.h"
>> +
>> +#ifndef MSF2_SYSREG_ERR_DEBUG
>> +#define MSF2_SYSREG_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> + if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \
>> + qemu_log("%s: " fmt, __func__, ## args); \
>> + } \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static void msf2_sysreg_reset(DeviceState *d)
>> +{
>> + MSF2SysregState *s = MSF2_SYSREG(d);
>> +
>> + DB_PRINT("RESET\n");
>> +
>> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;
>> + s->regs[MSSDDR_FACC1_CR] = 0x0B800124;
>> + s->regs[MSSDDR_PLL_STATUS] = 0x3;
>>
>
> I'll have a closer look a those values.
I just used values from real hardware board.
>
>
> +}
>> +
>> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
>> + unsigned size)
>> +{
>> + MSF2SysregState *s = opaque;
>> + offset /= 4;
>> + uint32_t ret = 0;
>> +
>> + if (offset < ARRAY_SIZE(s->regs)) {
>> + ret = s->regs[offset];
>> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32 "\n",
>> + offset * 4, ret);
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__,
>> + offset * 4);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,
>> + uint64_t val, unsigned size)
>> +{
>> + MSF2SysregState *s = (MSF2SysregState *)opaque;
>> + uint32_t newval = val;
>> + uint32_t oldval;
>> +
>> + offset /= 4;
>> +
>> + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64 "\n",
>> + offset * 4, val);
>> +
>> + switch (offset) {
>> + case MSSDDR_PLL_STATUS:
>> + break;
>> +
>> + case ESRAM_CR:
>> + oldval = s->regs[ESRAM_CR];
>> + if (oldval ^ newval) {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + TYPE_MSF2_SYSREG": eSRAM remapping not
>> supported\n");
>> + abort();
>> + }
>> + break;
>> +
>> + case DDR_CR:
>> + oldval = s->regs[DDR_CR];
>> + if (oldval ^ newval) {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + TYPE_MSF2_SYSREG": DDR remapping not
>> supported\n");
>> + abort();
>> + }
>> + break;
>> +
>> + case ENVM_REMAP_BASE_CR:
>> + oldval = s->regs[ENVM_REMAP_BASE_CR];
>> + if (oldval ^ newval) {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + TYPE_MSF2_SYSREG": eNVM remapping not
>> supported\n");
>> + abort();
>> + }
>> + break;
>>
>
> Thanks for adding the remap checks :)
>
> :)
>
> +
>> + default:
>> + if (offset < ARRAY_SIZE(s->regs)) {
>> + s->regs[offset] = val;
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: Bad offset 0x%08" HWADDR_PRIx "\n",
>> __func__,
>> + offset * 4);
>> + }
>> + break;
>> + }
>> +}
>> +
>> +static const MemoryRegionOps sysreg_ops = {
>> + .read = msf2_sysreg_read,
>> + .write = msf2_sysreg_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +static void msf2_sysreg_init(Object *obj)
>> +{
>> + MSF2SysregState *s = MSF2_SYSREG(obj);
>> +
>> + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s,
>> TYPE_MSF2_SYSREG,
>> + MSF2_SYSREG_MMIO_SIZE);
>> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
>> +}
>> +
>> +static const VMStateDescription vmstate_msf2_sysreg = {
>> + .name = TYPE_MSF2_SYSREG,
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState,
>> MSF2_SYSREG_NUM_REGS),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->vmsd = &vmstate_msf2_sysreg;
>> + dc->reset = msf2_sysreg_reset;
>> +}
>> +
>> +static const TypeInfo msf2_sysreg_info = {
>> + .name = TYPE_MSF2_SYSREG,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .class_init = msf2_sysreg_class_init,
>> + .instance_size = sizeof(MSF2SysregState),
>> + .instance_init = msf2_sysreg_init,
>> +};
>> +
>> +static void msf2_sysreg_register_types(void)
>> +{
>> + type_register_static(&msf2_sysreg_info);
>> +}
>> +
>> +type_init(msf2_sysreg_register_types)
>> diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.
>> h
>> new file mode 100644
>> index 0000000..a485ed6
>> --- /dev/null
>> +++ b/include/hw/misc/msf2-sysreg.h
>> @@ -0,0 +1,80 @@
>> +/*
>> + * Microsemi SmartFusion2 SYSREG
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_MSF2_SYSREG_H
>> +#define HW_MSF2_SYSREG_H
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/hw.h"
>> +#include "sysemu/sysemu.h"
>> +#include "qemu/log.h"
>> +
>> +enum {
>> + ESRAM_CR = 0x00 / 4,
>> + ESRAM_MAX_LAT,
>> + DDR_CR,
>> + ENVM_CR,
>> + ENVM_REMAP_BASE_CR,
>> + ENVM_REMAP_FAB_CR,
>> + CC_CR,
>> + CC_REGION_CR,
>> + CC_LOCK_BASE_ADDR_CR,
>> + CC_FLUSH_INDX_CR,
>> + DDRB_BUF_TIMER_CR,
>> + DDRB_NB_ADDR_CR,
>> + DDRB_NB_SIZE_CR,
>> + DDRB_CR,
>> +
>> + SOFT_RESET_CR = 0x48 / 4,
>> + M3_CR,
>> +
>> + GPIO_SYSRESET_SEL_CR = 0x58 / 4,
>> +
>> + MDDR_CR = 0x60 / 4,
>> +
>> + MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
>> + MSSDDR_PLL_STATUS_HIGH_CR,
>> + MSSDDR_FACC1_CR,
>> + MSSDDR_FACC2_CR,
>> +
>> + MSSDDR_PLL_STATUS = 0x150 / 4,
>> +
>> +};
>> +
>> +#define MSF2_SYSREG_MMIO_SIZE 0x300
>> +#define MSF2_SYSREG_NUM_REGS (MSF2_SYSREG_MMIO_SIZE / 4)
>>
>
> I don't think this define is very useful.
>
It is used in VMSTATE_UINT32_ARRAY(regs, MSF2SysregState,
MSF2_SYSREG_NUM_REGS).
Ok I will use MSF2_SYSREG_MMIO_SIZE / 4 directly instead.
>
> +
>> +#define TYPE_MSF2_SYSREG "msf2-sysreg"
>> +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj),
>> TYPE_MSF2_SYSREG)
>> +
>> +typedef struct MSF2SysregState {
>> + SysBusDevice parent_obj;
>> +
>> + MemoryRegion iomem;
>> +
>> + uint32_t regs[MSF2_SYSREG_NUM_REGS];
>> +} MSF2SysregState;
>> +
>> +#endif /* HW_MSF2_SYSREG_H */
>>
>>
> Thanks,
Sundeep
> Regards,
>
> Phil.
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [Qemu devel v5 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
2017-05-16 15:38 [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
@ 2017-05-16 15:38 ` Subbaraya Sundeep
2017-05-30 13:15 ` Philippe Mathieu-Daudé
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
` (2 subsequent siblings)
5 siblings, 1 reply; 35+ messages in thread
From: Subbaraya Sundeep @ 2017-05-16 15:38 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Modelled Microsemi's Smartfusion2 SPI controller.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/ssi/Makefile.objs | 1 +
hw/ssi/mss-spi.c | 378 +++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ssi/mss-spi.h | 104 +++++++++++++
3 files changed, 483 insertions(+)
create mode 100644 hw/ssi/mss-spi.c
create mode 100644 include/hw/ssi/mss-spi.h
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index 487add2..f5bcc65 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
+common-obj-$(CONFIG_MSF2) += mss-spi.o
obj-$(CONFIG_OMAP) += omap_spi.o
obj-$(CONFIG_IMX) += imx_spi.o
diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
new file mode 100644
index 0000000..0b88ec9
--- /dev/null
+++ b/hw/ssi/mss-spi.c
@@ -0,0 +1,378 @@
+/*
+ * Block model of SPI controller present in
+ * Microsemi's SmartFusion2 and SmartFusion SoCs.
+ *
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/ssi/mss-spi.h"
+
+#ifndef MSS_SPI_ERR_DEBUG
+#define MSS_SPI_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSS_SPI_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void txfifo_reset(MSSSpiState *s)
+{
+ fifo32_reset(&s->tx_fifo);
+
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
+}
+
+static void rxfifo_reset(MSSSpiState *s)
+{
+ fifo32_reset(&s->rx_fifo);
+
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+}
+
+static void set_fifodepth(MSSSpiState *s)
+{
+ int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
+
+ if (0 <= size && size <= 8) {
+ s->fifo_depth = 32;
+ }
+ if (9 <= size && size <= 16) {
+ s->fifo_depth = 16;
+ }
+ if (17 <= size && size <= 32) {
+ s->fifo_depth = 8;
+ }
+}
+
+static void mss_spi_do_reset(MSSSpiState *s)
+{
+ memset(s->regs, 0, sizeof s->regs);
+ s->regs[R_SPI_CONTROL] = 0x80000102;
+ s->regs[R_SPI_DFSIZE] = 0x4;
+ s->regs[R_SPI_STATUS] = 0x2440;
+ s->regs[R_SPI_CLKGEN] = 0x7;
+ s->regs[R_SPI_RIS] = 0x0;
+
+ s->fifo_depth = 4;
+ s->frame_count = 1;
+ s->enabled = false;
+
+ rxfifo_reset(s);
+ txfifo_reset(s);
+}
+
+static void update_mis(MSSSpiState *s)
+{
+ uint32_t reg = s->regs[R_SPI_CONTROL];
+ uint32_t tmp;
+
+ /*
+ * form the Control register interrupt enable bits
+ * same as RIS, MIS and Interrupt clear registers for simplicity
+ */
+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
+ ((reg & C_INTTXDATA) >> 5);
+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
+}
+
+static void spi_update_irq(MSSSpiState *s)
+{
+ int irq;
+
+ update_mis(s);
+ irq = !!(s->regs[R_SPI_MIS]);
+
+ qemu_set_irq(s->irq, irq);
+}
+
+static void mss_spi_reset(DeviceState *d)
+{
+ mss_spi_do_reset(MSS_SPI(d));
+}
+
+static uint64_t
+spi_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ MSSSpiState *s = opaque;
+ uint32_t ret = 0;
+
+ addr >>= 2;
+ switch (addr) {
+ case R_SPI_RX:
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+ s->regs[R_SPI_STATUS] &= ~RXCHOVRF;
+ ret = fifo32_pop(&s->rx_fifo);
+ if (fifo32_is_empty(&s->rx_fifo)) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+ }
+ break;
+
+ case R_SPI_MIS:
+ update_mis(s);
+ ret = s->regs[R_SPI_MIS];
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ ret = s->regs[addr];
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
+ addr * 4);
+ }
+ break;
+ }
+
+ DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32 "\n", addr * 4, ret);
+ spi_update_irq(s);
+ return ret;
+}
+
+static void assert_cs(MSSSpiState *s)
+{
+ qemu_set_irq(s->cs_line, 0);
+}
+
+static void deassert_cs(MSSSpiState *s)
+{
+ qemu_set_irq(s->cs_line, 1);
+}
+
+static void spi_flush_txfifo(MSSSpiState *s)
+{
+ uint32_t tx;
+ uint32_t rx;
+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
+
+ /*
+ * Chip Select(CS) is automatically controlled by this controller.
+ * If SPS bit is set in Control register then CS is asserted
+ * until all the frames set in frame count of Control register are
+ * transferred. If SPS is not set then CS pulses between frames.
+ * Note that Slave Select register specifies which of the CS line
+ * has to be controlled automatically by controller. Bits SS[7:1] are for
+ * masters in FPGA fabric since we model only Microcontroller subsystem
+ * of Smartfusion2 we control only one CS(SS[0]) line.
+ */
+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
+ assert_cs(s);
+
+ s->regs[R_SPI_STATUS] &= ~TXDONE;
+ s->regs[R_SPI_STATUS] &= ~RXRDY;
+
+ tx = fifo32_pop(&s->tx_fifo);
+ DB_PRINT("data tx:0x%" PRIx32 "\n", tx);
+ rx = ssi_transfer(s->spi, tx);
+ DB_PRINT("data rx:0x%" PRIx32 "\n", rx);
+
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= RXCHOVRF;
+ s->regs[R_SPI_RIS] |= RXCHOVRF;
+ } else {
+ fifo32_push(&s->rx_fifo, rx);
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
+ }
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
+ }
+ }
+ s->frame_count--;
+ if (!sps) {
+ deassert_cs(s);
+ assert_cs(s);
+ }
+ }
+
+ if (!sps) {
+ deassert_cs(s);
+ }
+
+ if (!s->frame_count) {
+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
+ FMCOUNT_SHIFT;
+ if (sps) {
+ deassert_cs(s);
+ }
+ s->regs[R_SPI_RIS] |= TXDONE;
+ s->regs[R_SPI_RIS] |= RXRDY;
+ s->regs[R_SPI_STATUS] |= TXDONE;
+ s->regs[R_SPI_STATUS] |= RXRDY;
+ }
+}
+
+static void spi_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ MSSSpiState *s = opaque;
+ uint32_t value = val64;
+
+ DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32 "\n", addr, value);
+ addr >>= 2;
+
+ switch (addr) {
+ case R_SPI_TX:
+ /* adding to already full FIFO */
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+ break;
+ }
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
+ fifo32_push(&s->tx_fifo, value);
+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
+ }
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
+ }
+ if (s->enabled) {
+ spi_flush_txfifo(s);
+ }
+ break;
+
+ case R_SPI_CONTROL:
+ s->regs[R_SPI_CONTROL] = value;
+ if (value & C_BIGFIFO) {
+ set_fifodepth(s);
+ } else {
+ s->fifo_depth = 4;
+ }
+ if (value & C_ENABLE) {
+ s->enabled = true;
+ } else {
+ s->enabled = false;
+ }
+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
+ if (value & C_RESET) {
+ mss_spi_do_reset(s);
+ }
+ break;
+
+ case R_SPI_DFSIZE:
+ if (s->enabled) {
+ break;
+ }
+ s->regs[R_SPI_DFSIZE] = value;
+ break;
+
+ case R_SPI_INTCLR:
+ s->regs[R_SPI_INTCLR] = value;
+ if (value & TXDONE) {
+ s->regs[R_SPI_RIS] &= ~TXDONE;
+ }
+ if (value & RXRDY) {
+ s->regs[R_SPI_RIS] &= ~RXRDY;
+ }
+ if (value & RXCHOVRF) {
+ s->regs[R_SPI_RIS] &= ~RXCHOVRF;
+ }
+ break;
+
+ case R_SPI_MIS:
+ case R_SPI_STATUS:
+ case R_SPI_RIS:
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ s->regs[addr] = value;
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
+ addr * 4);
+ }
+ break;
+ }
+
+ spi_update_irq(s);
+}
+
+static const MemoryRegionOps spi_ops = {
+ .read = spi_read,
+ .write = spi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4
+ }
+};
+
+static void mss_spi_realize(DeviceState *dev, Error **errp)
+{
+ MSSSpiState *s = MSS_SPI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ DB_PRINT("\n");
+
+ s->spi = ssi_create_bus(dev, "spi0");
+
+ sysbus_init_irq(sbd, &s->irq);
+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
+ sysbus_init_irq(sbd, &s->cs_line);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
+ TYPE_MSS_SPI, R_SPI_MAX * 4);
+ sysbus_init_mmio(sbd, &s->mmio);
+
+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
+}
+
+static const VMStateDescription vmstate_mss_spi = {
+ .name = TYPE_MSS_SPI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_FIFO32(tx_fifo, MSSSpiState),
+ VMSTATE_FIFO32(rx_fifo, MSSSpiState),
+ VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void mss_spi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = mss_spi_realize;
+ dc->reset = mss_spi_reset;
+ dc->vmsd = &vmstate_mss_spi;
+}
+
+static const TypeInfo mss_spi_info = {
+ .name = TYPE_MSS_SPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSSSpiState),
+ .class_init = mss_spi_class_init,
+};
+
+static void mss_spi_register_types(void)
+{
+ type_register_static(&mss_spi_info);
+}
+
+type_init(mss_spi_register_types)
diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
new file mode 100644
index 0000000..091307a
--- /dev/null
+++ b/include/hw/ssi/mss-spi.h
@@ -0,0 +1,104 @@
+/*
+ * Microsemi SmartFusion2 SPI
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSS_SPI_H
+#define HW_MSS_SPI_H
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/ssi/ssi.h"
+#include "qemu/fifo32.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+
+#define FIFO_CAPACITY 32
+#define FIFO_CAPACITY 32
+
+#define R_SPI_CONTROL 0
+#define R_SPI_DFSIZE 1
+#define R_SPI_STATUS 2
+#define R_SPI_INTCLR 3
+#define R_SPI_RX 4
+#define R_SPI_TX 5
+#define R_SPI_CLKGEN 6
+#define R_SPI_SS 7
+#define R_SPI_MIS 8
+#define R_SPI_RIS 9
+#define R_SPI_MAX 16
+
+#define S_RXFIFOFUL (1 << 4)
+#define S_RXFIFOFULNXT (1 << 5)
+#define S_RXFIFOEMP (1 << 6)
+#define S_RXFIFOEMPNXT (1 << 7)
+#define S_TXFIFOFUL (1 << 8)
+#define S_TXFIFOFULNXT (1 << 9)
+#define S_TXFIFOEMP (1 << 10)
+#define S_TXFIFOEMPNXT (1 << 11)
+#define S_FRAMESTART (1 << 12)
+#define S_SSEL (1 << 13)
+#define S_ACTIVE (1 << 14)
+
+#define C_ENABLE (1 << 0)
+#define C_MODE (1 << 1)
+#define C_INTRXDATA (1 << 4)
+#define C_INTTXDATA (1 << 5)
+#define C_INTRXOVRFLO (1 << 6)
+#define C_SPS (1 << 26)
+#define C_BIGFIFO (1 << 29)
+#define C_RESET (1 << 31)
+
+#define FRAMESZ_MASK 0x1F
+#define FMCOUNT_MASK 0x00FFFF00
+#define FMCOUNT_SHIFT 8
+
+#define TXDONE (1 << 0)
+#define RXRDY (1 << 1)
+#define RXCHOVRF (1 << 2)
+
+#define TYPE_MSS_SPI "mss-spi"
+#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
+
+typedef struct MSSSpiState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ qemu_irq irq;
+
+ qemu_irq cs_line;
+
+ SSIBus *spi;
+
+ Fifo32 rx_fifo;
+ Fifo32 tx_fifo;
+
+ int fifo_depth;
+ uint32_t frame_count;
+ bool enabled;
+
+ uint32_t regs[R_SPI_MAX];
+} MSSSpiState;
+
+#endif /* HW_MSS_SPI_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
@ 2017-05-30 13:15 ` Philippe Mathieu-Daudé
2017-06-24 7:42 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-05-30 13:15 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
> Modelled Microsemi's Smartfusion2 SPI controller.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/mss-spi.c | 378 +++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ssi/mss-spi.h | 104 +++++++++++++
> 3 files changed, 483 insertions(+)
> create mode 100644 hw/ssi/mss-spi.c
> create mode 100644 include/hw/ssi/mss-spi.h
>
> diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
> index 487add2..f5bcc65 100644
> --- a/hw/ssi/Makefile.objs
> +++ b/hw/ssi/Makefile.objs
> @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
> common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
> +common-obj-$(CONFIG_MSF2) += mss-spi.o
>
> obj-$(CONFIG_OMAP) += omap_spi.o
> obj-$(CONFIG_IMX) += imx_spi.o
> diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
> new file mode 100644
> index 0000000..0b88ec9
> --- /dev/null
> +++ b/hw/ssi/mss-spi.c
> @@ -0,0 +1,378 @@
> +/*
> + * Block model of SPI controller present in
> + * Microsemi's SmartFusion2 and SmartFusion SoCs.
> + *
> + * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "hw/ssi/mss-spi.h"
> +
> +#ifndef MSS_SPI_ERR_DEBUG
> +#define MSS_SPI_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSS_SPI_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt, __func__, ## args); \
Since you use newline in all your calls, you could move it here:
qemu_log("%s: " fmt "\n", __func__, ## args);
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void txfifo_reset(MSSSpiState *s)
> +{
> + fifo32_reset(&s->tx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
> +}
> +
> +static void rxfifo_reset(MSSSpiState *s)
> +{
> + fifo32_reset(&s->rx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> +}
> +
> +static void set_fifodepth(MSSSpiState *s)
> +{
> + int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
This size is unsigned, isn't it?
> +
> + if (0 <= size && size <= 8) {
So "if (size <= 8)"
> + s->fifo_depth = 32;
> + }
> + if (9 <= size && size <= 16) {
"else if (size <= 16)"
> + s->fifo_depth = 16;
> + }
> + if (17 <= size && size <= 32) {
else if
> + s->fifo_depth = 8;
> + }
else
s->fifo_depth = 4;
?
> +}
> +
> +static void mss_spi_do_reset(MSSSpiState *s)
> +{
> + memset(s->regs, 0, sizeof s->regs);
> + s->regs[R_SPI_CONTROL] = 0x80000102;
> + s->regs[R_SPI_DFSIZE] = 0x4;
> + s->regs[R_SPI_STATUS] = 0x2440;
" = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;"
> + s->regs[R_SPI_CLKGEN] = 0x7;
> + s->regs[R_SPI_RIS] = 0x0;
> +
> + s->fifo_depth = 4;
Resetting R_SPI_DFSIZE to 4, shouldn't fifo_depth be 32?
> + s->frame_count = 1;
> + s->enabled = false;
> +
> + rxfifo_reset(s);
> + txfifo_reset(s);
> +}
> +
> +static void update_mis(MSSSpiState *s)
> +{
> + uint32_t reg = s->regs[R_SPI_CONTROL];
> + uint32_t tmp;
> +
> + /*
> + * form the Control register interrupt enable bits
> + * same as RIS, MIS and Interrupt clear registers for simplicity
> + */
> + tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
> + ((reg & C_INTTXDATA) >> 5);
> + s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
> +}
> +
> +static void spi_update_irq(MSSSpiState *s)
> +{
> + int irq;
> +
> + update_mis(s);
> + irq = !!(s->regs[R_SPI_MIS]);
> +
> + qemu_set_irq(s->irq, irq);
> +}
> +
> +static void mss_spi_reset(DeviceState *d)
> +{
> + mss_spi_do_reset(MSS_SPI(d));
> +}
> +
> +static uint64_t
> +spi_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + MSSSpiState *s = opaque;
> + uint32_t ret = 0;
> +
> + addr >>= 2;
> + switch (addr) {
> + case R_SPI_RX:
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] &= ~RXCHOVRF;
> + ret = fifo32_pop(&s->rx_fifo);
> + if (fifo32_is_empty(&s->rx_fifo)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + update_mis(s);
> + ret = s->regs[R_SPI_MIS];
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + ret = s->regs[addr];
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
> + addr * 4);
> + }
> + break;
> + }
> +
> + DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32 "\n", addr * 4, ret);
> + spi_update_irq(s);
> + return ret;
> +}
> +
> +static void assert_cs(MSSSpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 0);
> +}
> +
> +static void deassert_cs(MSSSpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 1);
> +}
> +
> +static void spi_flush_txfifo(MSSSpiState *s)
> +{
> + uint32_t tx;
> + uint32_t rx;
> + bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
> +
> + /*
> + * Chip Select(CS) is automatically controlled by this controller.
> + * If SPS bit is set in Control register then CS is asserted
> + * until all the frames set in frame count of Control register are
> + * transferred. If SPS is not set then CS pulses between frames.
> + * Note that Slave Select register specifies which of the CS line
> + * has to be controlled automatically by controller. Bits SS[7:1] are for
> + * masters in FPGA fabric since we model only Microcontroller subsystem
> + * of Smartfusion2 we control only one CS(SS[0]) line.
> + */
> + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
> + assert_cs(s);
> +
> + s->regs[R_SPI_STATUS] &= ~TXDONE;
> + s->regs[R_SPI_STATUS] &= ~RXRDY;
You can simplify as "&= ~(S_TXDONE | S_RXRDY);"
> +
> + tx = fifo32_pop(&s->tx_fifo);
> + DB_PRINT("data tx:0x%" PRIx32 "\n", tx);
> + rx = ssi_transfer(s->spi, tx);
> + DB_PRINT("data rx:0x%" PRIx32 "\n", rx);
> +
> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= RXCHOVRF;
> + s->regs[R_SPI_RIS] |= RXCHOVRF;
> + } else {
> + fifo32_push(&s->rx_fifo, rx);
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
> + if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
> + }
> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
> + }
> + }
> + s->frame_count--;
> + if (!sps) {
> + deassert_cs(s);
> + assert_cs(s);
> + }
> + }
> +
> + if (!sps) {
> + deassert_cs(s);
> + }
> +
> + if (!s->frame_count) {
> + s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
> + FMCOUNT_SHIFT;
> + if (sps) {
> + deassert_cs(s);
> + }
> + s->regs[R_SPI_RIS] |= TXDONE;
> + s->regs[R_SPI_RIS] |= RXRDY;
Same, "|= S_TXDONE | S_RXDRY;"
> + s->regs[R_SPI_STATUS] |= TXDONE;
> + s->regs[R_SPI_STATUS] |= RXRDY;
> + }
> +}
> +
> +static void spi_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + MSSSpiState *s = opaque;
> + uint32_t value = val64;
> +
> + DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32 "\n", addr, value);
> + addr >>= 2;
> +
> + switch (addr) {
> + case R_SPI_TX:
> + /* adding to already full FIFO */
> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + break;
> + }
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
> + fifo32_push(&s->tx_fifo, value);
> + if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
> + }
> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
> + }
> + if (s->enabled) {
> + spi_flush_txfifo(s);
> + }
> + break;
> +
> + case R_SPI_CONTROL:
> + s->regs[R_SPI_CONTROL] = value;
> + if (value & C_BIGFIFO) {
> + set_fifodepth(s);
> + } else {
> + s->fifo_depth = 4;
> + }
> + if (value & C_ENABLE) {
> + s->enabled = true;
> + } else {
> + s->enabled = false;
> + }
"s->enabled = value & C_ENABLE;" ?
> + s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
> + if (value & C_RESET) {
> + mss_spi_do_reset(s);
> + }
> + break;
> +
> + case R_SPI_DFSIZE:
> + if (s->enabled) {
> + break;
> + }
> + s->regs[R_SPI_DFSIZE] = value;
> + break;
> +
> + case R_SPI_INTCLR:
> + s->regs[R_SPI_INTCLR] = value;
> + if (value & TXDONE) {
> + s->regs[R_SPI_RIS] &= ~TXDONE;
> + }
> + if (value & RXRDY) {
> + s->regs[R_SPI_RIS] &= ~RXRDY;
> + }
> + if (value & RXCHOVRF) {
> + s->regs[R_SPI_RIS] &= ~RXCHOVRF;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + case R_SPI_STATUS:
> + case R_SPI_RIS:
> + break;
Those registers are read-only right? Maybe you should LOG_GUEST_ERROR
here too?
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + s->regs[addr] = value;
> + } else {
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
> + addr * 4);
> + }
> + break;
> + }
> +
> + spi_update_irq(s);
> +}
> +
> +static const MemoryRegionOps spi_ops = {
> + .read = spi_read,
> + .write = spi_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 1,
> + .max_access_size = 4
> + }
> +};
> +
> +static void mss_spi_realize(DeviceState *dev, Error **errp)
> +{
> + MSSSpiState *s = MSS_SPI(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + DB_PRINT("\n");
> +
> + s->spi = ssi_create_bus(dev, "spi0");
"0" is the Linux representation?
> +
> + sysbus_init_irq(sbd, &s->irq);
> + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
> + sysbus_init_irq(sbd, &s->cs_line);
> +
> + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
> + TYPE_MSS_SPI, R_SPI_MAX * 4);
> + sysbus_init_mmio(sbd, &s->mmio);
> +
> + fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
> + fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
> +}
> +
> +static const VMStateDescription vmstate_mss_spi = {
> + .name = TYPE_MSS_SPI,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_FIFO32(tx_fifo, MSSSpiState),
> + VMSTATE_FIFO32(rx_fifo, MSSSpiState),
> + VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void mss_spi_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = mss_spi_realize;
> + dc->reset = mss_spi_reset;
> + dc->vmsd = &vmstate_mss_spi;
> +}
> +
> +static const TypeInfo mss_spi_info = {
> + .name = TYPE_MSS_SPI,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSSSpiState),
> + .class_init = mss_spi_class_init,
> +};
> +
> +static void mss_spi_register_types(void)
> +{
> + type_register_static(&mss_spi_info);
> +}
> +
> +type_init(mss_spi_register_types)
> diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
> new file mode 100644
> index 0000000..091307a
> --- /dev/null
> +++ b/include/hw/ssi/mss-spi.h
> @@ -0,0 +1,104 @@
> +/*
> + * Microsemi SmartFusion2 SPI
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MSS_SPI_H
> +#define HW_MSS_SPI_H
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/hw.h"
> +#include "hw/ssi/ssi.h"
> +#include "qemu/fifo32.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/log.h"
> +
> +#define FIFO_CAPACITY 32
> +#define FIFO_CAPACITY 32
> +
> +#define R_SPI_CONTROL 0
> +#define R_SPI_DFSIZE 1
> +#define R_SPI_STATUS 2
> +#define R_SPI_INTCLR 3
> +#define R_SPI_RX 4
> +#define R_SPI_TX 5
> +#define R_SPI_CLKGEN 6
> +#define R_SPI_SS 7
> +#define R_SPI_MIS 8
> +#define R_SPI_RIS 9
> +#define R_SPI_MAX 16
> +
> +#define S_RXFIFOFUL (1 << 4)
> +#define S_RXFIFOFULNXT (1 << 5)
> +#define S_RXFIFOEMP (1 << 6)
> +#define S_RXFIFOEMPNXT (1 << 7)
> +#define S_TXFIFOFUL (1 << 8)
> +#define S_TXFIFOFULNXT (1 << 9)
> +#define S_TXFIFOEMP (1 << 10)
> +#define S_TXFIFOEMPNXT (1 << 11)
> +#define S_FRAMESTART (1 << 12)
> +#define S_SSEL (1 << 13)
> +#define S_ACTIVE (1 << 14)
> +
> +#define C_ENABLE (1 << 0)
> +#define C_MODE (1 << 1)
> +#define C_INTRXDATA (1 << 4)
> +#define C_INTTXDATA (1 << 5)
> +#define C_INTRXOVRFLO (1 << 6)
> +#define C_SPS (1 << 26)
> +#define C_BIGFIFO (1 << 29)
> +#define C_RESET (1 << 31)
> +
> +#define FRAMESZ_MASK 0x1F
> +#define FMCOUNT_MASK 0x00FFFF00
> +#define FMCOUNT_SHIFT 8
> +
Try to keep the previous definitions in the C source, since there are
not useful outside of it. Except R_SPI_MAX I think you can move all of them.
> +#define TXDONE (1 << 0)
> +#define RXRDY (1 << 1)
> +#define RXCHOVRF (1 << 2)
> +
These last 3 seems to be S_TXDONE, S_RXRDY, S_RXCHOVRF.
> +#define TYPE_MSS_SPI "mss-spi"
> +#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
> +
> +typedef struct MSSSpiState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> +
> + qemu_irq irq;
> +
> + qemu_irq cs_line;
> +
> + SSIBus *spi;
> +
> + Fifo32 rx_fifo;
> + Fifo32 tx_fifo;
> +
> + int fifo_depth;
> + uint32_t frame_count;
> + bool enabled;
> +
> + uint32_t regs[R_SPI_MAX];
> +} MSSSpiState;
> +
> +#endif /* HW_MSS_SPI_H */
>
Regards,
Phil.
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 3/5] msf2: Add Smartfusion2 SPI controller
2017-05-30 13:15 ` Philippe Mathieu-Daudé
@ 2017-06-24 7:42 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-24 7:42 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Tue, May 30, 2017 at 6:45 PM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
>
>
> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>
>> Modelled Microsemi's Smartfusion2 SPI controller.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> ---
>> hw/ssi/Makefile.objs | 1 +
>> hw/ssi/mss-spi.c | 378 ++++++++++++++++++++++++++++++
>> +++++++++++++++++
>> include/hw/ssi/mss-spi.h | 104 +++++++++++++
>> 3 files changed, 483 insertions(+)
>> create mode 100644 hw/ssi/mss-spi.c
>> create mode 100644 include/hw/ssi/mss-spi.h
>>
>> diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
>> index 487add2..f5bcc65 100644
>> --- a/hw/ssi/Makefile.objs
>> +++ b/hw/ssi/Makefile.objs
>> @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
>> common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
>> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
>> common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
>> +common-obj-$(CONFIG_MSF2) += mss-spi.o
>>
>> obj-$(CONFIG_OMAP) += omap_spi.o
>> obj-$(CONFIG_IMX) += imx_spi.o
>> diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c
>> new file mode 100644
>> index 0000000..0b88ec9
>> --- /dev/null
>> +++ b/hw/ssi/mss-spi.c
>> @@ -0,0 +1,378 @@
>> +/*
>> + * Block model of SPI controller present in
>> + * Microsemi's SmartFusion2 and SmartFusion SoCs.
>> + *
>> + * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "hw/ssi/mss-spi.h"
>> +
>> +#ifndef MSS_SPI_ERR_DEBUG
>> +#define MSS_SPI_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> + if (MSS_SPI_ERR_DEBUG >= lvl) { \
>> + qemu_log("%s: " fmt, __func__, ## args); \
>>
>
> Since you use newline in all your calls, you could move it here:
>
> qemu_log("%s: " fmt "\n", __func__, ## args);
>
> Ok
> + } \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static void txfifo_reset(MSSSpiState *s)
>> +{
>> + fifo32_reset(&s->tx_fifo);
>> +
>> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
>> + s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
>> +}
>> +
>> +static void rxfifo_reset(MSSSpiState *s)
>> +{
>> + fifo32_reset(&s->rx_fifo);
>> +
>> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
>> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
>> +}
>> +
>> +static void set_fifodepth(MSSSpiState *s)
>> +{
>> + int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
>>
>
> This size is unsigned, isn't it?
Yes will change it.
>
>
> +
>> + if (0 <= size && size <= 8) {
>>
>
> So "if (size <= 8)"
>
> + s->fifo_depth = 32;
>> + }
>> + if (9 <= size && size <= 16) {
>>
>
> "else if (size <= 16)"
>
> + s->fifo_depth = 16;
>> + }
>> + if (17 <= size && size <= 32) {
>>
>
> else if
>
> + s->fifo_depth = 8;
>> + }
>>
>
> else
>
> s->fifo_depth = 4;
>
> ?
>
> Ok will change it.
> +}
>> +
>> +static void mss_spi_do_reset(MSSSpiState *s)
>> +{
>> + memset(s->regs, 0, sizeof s->regs);
>> + s->regs[R_SPI_CONTROL] = 0x80000102;
>> + s->regs[R_SPI_DFSIZE] = 0x4;
>> + s->regs[R_SPI_STATUS] = 0x2440;
>>
>
> " = S_SSEL | S_TXFIFOEMP | S_RXFIFOEMP;"
OK.
>
>
> + s->regs[R_SPI_CLKGEN] = 0x7;
>> + s->regs[R_SPI_RIS] = 0x0;
>> +
>> + s->fifo_depth = 4;
>>
>
> Resetting R_SPI_DFSIZE to 4, shouldn't fifo_depth be 32?
FIFO depth is 4 by default and it varies based on BIGFIFO bit in control
register and frame size.
>
>
> + s->frame_count = 1;
>> + s->enabled = false;
>> +
>> + rxfifo_reset(s);
>> + txfifo_reset(s);
>> +}
>> +
>> +static void update_mis(MSSSpiState *s)
>> +{
>> + uint32_t reg = s->regs[R_SPI_CONTROL];
>> + uint32_t tmp;
>> +
>> + /*
>> + * form the Control register interrupt enable bits
>> + * same as RIS, MIS and Interrupt clear registers for simplicity
>> + */
>> + tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
>> + ((reg & C_INTTXDATA) >> 5);
>> + s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
>> +}
>> +
>> +static void spi_update_irq(MSSSpiState *s)
>> +{
>> + int irq;
>> +
>> + update_mis(s);
>> + irq = !!(s->regs[R_SPI_MIS]);
>> +
>> + qemu_set_irq(s->irq, irq);
>> +}
>> +
>> +static void mss_spi_reset(DeviceState *d)
>> +{
>> + mss_spi_do_reset(MSS_SPI(d));
>> +}
>> +
>> +static uint64_t
>> +spi_read(void *opaque, hwaddr addr, unsigned int size)
>> +{
>> + MSSSpiState *s = opaque;
>> + uint32_t ret = 0;
>> +
>> + addr >>= 2;
>> + switch (addr) {
>> + case R_SPI_RX:
>> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
>> + s->regs[R_SPI_STATUS] &= ~RXCHOVRF;
>> + ret = fifo32_pop(&s->rx_fifo);
>> + if (fifo32_is_empty(&s->rx_fifo)) {
>> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
>> + }
>> + break;
>> +
>> + case R_SPI_MIS:
>> + update_mis(s);
>> + ret = s->regs[R_SPI_MIS];
>> + break;
>> +
>> + default:
>> + if (addr < ARRAY_SIZE(s->regs)) {
>> + ret = s->regs[addr];
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
>> + addr * 4);
>> + }
>> + break;
>> + }
>> +
>> + DB_PRINT("addr=0x%" HWADDR_PRIx " = 0x%" PRIx32 "\n", addr * 4, ret);
>> + spi_update_irq(s);
>> + return ret;
>> +}
>> +
>> +static void assert_cs(MSSSpiState *s)
>> +{
>> + qemu_set_irq(s->cs_line, 0);
>> +}
>> +
>> +static void deassert_cs(MSSSpiState *s)
>> +{
>> + qemu_set_irq(s->cs_line, 1);
>> +}
>> +
>> +static void spi_flush_txfifo(MSSSpiState *s)
>> +{
>> + uint32_t tx;
>> + uint32_t rx;
>> + bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
>> +
>> + /*
>> + * Chip Select(CS) is automatically controlled by this controller.
>> + * If SPS bit is set in Control register then CS is asserted
>> + * until all the frames set in frame count of Control register are
>> + * transferred. If SPS is not set then CS pulses between frames.
>> + * Note that Slave Select register specifies which of the CS line
>> + * has to be controlled automatically by controller. Bits SS[7:1]
>> are for
>> + * masters in FPGA fabric since we model only Microcontroller
>> subsystem
>> + * of Smartfusion2 we control only one CS(SS[0]) line.
>> + */
>> + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
>> + assert_cs(s);
>> +
>> + s->regs[R_SPI_STATUS] &= ~TXDONE;
>> + s->regs[R_SPI_STATUS] &= ~RXRDY;
>>
>
> You can simplify as "&= ~(S_TXDONE | S_RXRDY);"
Ok.
>
>
> +
>> + tx = fifo32_pop(&s->tx_fifo);
>> + DB_PRINT("data tx:0x%" PRIx32 "\n", tx);
>> + rx = ssi_transfer(s->spi, tx);
>> + DB_PRINT("data rx:0x%" PRIx32 "\n", rx);
>> +
>> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
>> + s->regs[R_SPI_STATUS] |= RXCHOVRF;
>> + s->regs[R_SPI_RIS] |= RXCHOVRF;
>> + } else {
>> + fifo32_push(&s->rx_fifo, rx);
>> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
>> + if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
>> + s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
>> + }
>> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
>> + s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
>> + }
>> + }
>> + s->frame_count--;
>> + if (!sps) {
>> + deassert_cs(s);
>> + assert_cs(s);
>> + }
>> + }
>> +
>> + if (!sps) {
>> + deassert_cs(s);
>> + }
>> +
>> + if (!s->frame_count) {
>> + s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
>> + FMCOUNT_SHIFT;
>> + if (sps) {
>> + deassert_cs(s);
>> + }
>> + s->regs[R_SPI_RIS] |= TXDONE;
>> + s->regs[R_SPI_RIS] |= RXRDY;
>>
>
> Same, "|= S_TXDONE | S_RXDRY;"
Ok.
>
>
> + s->regs[R_SPI_STATUS] |= TXDONE;
>> + s->regs[R_SPI_STATUS] |= RXRDY;
>> + }
>> +}
>> +
>> +static void spi_write(void *opaque, hwaddr addr,
>> + uint64_t val64, unsigned int size)
>> +{
>> + MSSSpiState *s = opaque;
>> + uint32_t value = val64;
>> +
>> + DB_PRINT("addr=0x%" HWADDR_PRIx " =0x%" PRIx32 "\n", addr, value);
>> + addr >>= 2;
>> +
>> + switch (addr) {
>> + case R_SPI_TX:
>> + /* adding to already full FIFO */
>> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
>> + break;
>> + }
>> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
>> + fifo32_push(&s->tx_fifo, value);
>> + if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
>> + s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
>> + }
>> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
>> + s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
>> + }
>> + if (s->enabled) {
>> + spi_flush_txfifo(s);
>> + }
>> + break;
>> +
>> + case R_SPI_CONTROL:
>> + s->regs[R_SPI_CONTROL] = value;
>> + if (value & C_BIGFIFO) {
>> + set_fifodepth(s);
>> + } else {
>> + s->fifo_depth = 4;
>> + }
>> + if (value & C_ENABLE) {
>> + s->enabled = true;
>> + } else {
>> + s->enabled = false;
>> + }
>>
>
> "s->enabled = value & C_ENABLE;" ?
Ok.
>
>
> + s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
>> + if (value & C_RESET) {
>> + mss_spi_do_reset(s);
>> + }
>> + break;
>> +
>> + case R_SPI_DFSIZE:
>> + if (s->enabled) {
>> + break;
>> + }
>> + s->regs[R_SPI_DFSIZE] = value;
>> + break;
>> +
>> + case R_SPI_INTCLR:
>> + s->regs[R_SPI_INTCLR] = value;
>> + if (value & TXDONE) {
>> + s->regs[R_SPI_RIS] &= ~TXDONE;
>> + }
>> + if (value & RXRDY) {
>> + s->regs[R_SPI_RIS] &= ~RXRDY;
>> + }
>> + if (value & RXCHOVRF) {
>> + s->regs[R_SPI_RIS] &= ~RXCHOVRF;
>> + }
>> + break;
>> +
>> + case R_SPI_MIS:
>> + case R_SPI_STATUS:
>> + case R_SPI_RIS:
>> + break;
>>
>
> Those registers are read-only right? Maybe you should LOG_GUEST_ERROR here
> too?
Ok.
>
>
> +
>> + default:
>> + if (addr < ARRAY_SIZE(s->regs)) {
>> + s->regs[addr] = value;
>> + } else {
>> + qemu_log_mask(LOG_GUEST_ERROR,
>> + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__,
>> + addr * 4);
>> + }
>> + break;
>> + }
>> +
>> + spi_update_irq(s);
>> +}
>> +
>> +static const MemoryRegionOps spi_ops = {
>> + .read = spi_read,
>> + .write = spi_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 1,
>> + .max_access_size = 4
>> + }
>> +};
>> +
>> +static void mss_spi_realize(DeviceState *dev, Error **errp)
>> +{
>> + MSSSpiState *s = MSS_SPI(dev);
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
>> +
>> + DB_PRINT("\n");
>> +
>> + s->spi = ssi_create_bus(dev, "spi0");
>>
>
> "0" is the Linux representation?
Yeah will remove 0.
>
>
> +
>> + sysbus_init_irq(sbd, &s->irq);
>> + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
>> + sysbus_init_irq(sbd, &s->cs_line);
>> +
>> + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
>> + TYPE_MSS_SPI, R_SPI_MAX * 4);
>> + sysbus_init_mmio(sbd, &s->mmio);
>> +
>> + fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
>> + fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
>> +}
>> +
>> +static const VMStateDescription vmstate_mss_spi = {
>> + .name = TYPE_MSS_SPI,
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_FIFO32(tx_fifo, MSSSpiState),
>> + VMSTATE_FIFO32(rx_fifo, MSSSpiState),
>> + VMSTATE_UINT32_ARRAY(regs, MSSSpiState, R_SPI_MAX),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static void mss_spi_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->realize = mss_spi_realize;
>> + dc->reset = mss_spi_reset;
>> + dc->vmsd = &vmstate_mss_spi;
>> +}
>> +
>> +static const TypeInfo mss_spi_info = {
>> + .name = TYPE_MSS_SPI,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(MSSSpiState),
>> + .class_init = mss_spi_class_init,
>> +};
>> +
>> +static void mss_spi_register_types(void)
>> +{
>> + type_register_static(&mss_spi_info);
>> +}
>> +
>> +type_init(mss_spi_register_types)
>> diff --git a/include/hw/ssi/mss-spi.h b/include/hw/ssi/mss-spi.h
>> new file mode 100644
>> index 0000000..091307a
>> --- /dev/null
>> +++ b/include/hw/ssi/mss-spi.h
>> @@ -0,0 +1,104 @@
>> +/*
>> + * Microsemi SmartFusion2 SPI
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_MSS_SPI_H
>> +#define HW_MSS_SPI_H
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/hw.h"
>> +#include "hw/ssi/ssi.h"
>> +#include "qemu/fifo32.h"
>> +#include "sysemu/sysemu.h"
>> +#include "qemu/log.h"
>> +
>> +#define FIFO_CAPACITY 32
>> +#define FIFO_CAPACITY 32
>> +
>> +#define R_SPI_CONTROL 0
>> +#define R_SPI_DFSIZE 1
>> +#define R_SPI_STATUS 2
>> +#define R_SPI_INTCLR 3
>> +#define R_SPI_RX 4
>> +#define R_SPI_TX 5
>> +#define R_SPI_CLKGEN 6
>> +#define R_SPI_SS 7
>> +#define R_SPI_MIS 8
>> +#define R_SPI_RIS 9
>> +#define R_SPI_MAX 16
>> +
>> +#define S_RXFIFOFUL (1 << 4)
>> +#define S_RXFIFOFULNXT (1 << 5)
>> +#define S_RXFIFOEMP (1 << 6)
>> +#define S_RXFIFOEMPNXT (1 << 7)
>> +#define S_TXFIFOFUL (1 << 8)
>> +#define S_TXFIFOFULNXT (1 << 9)
>> +#define S_TXFIFOEMP (1 << 10)
>> +#define S_TXFIFOEMPNXT (1 << 11)
>> +#define S_FRAMESTART (1 << 12)
>> +#define S_SSEL (1 << 13)
>> +#define S_ACTIVE (1 << 14)
>> +
>> +#define C_ENABLE (1 << 0)
>> +#define C_MODE (1 << 1)
>> +#define C_INTRXDATA (1 << 4)
>> +#define C_INTTXDATA (1 << 5)
>> +#define C_INTRXOVRFLO (1 << 6)
>> +#define C_SPS (1 << 26)
>> +#define C_BIGFIFO (1 << 29)
>> +#define C_RESET (1 << 31)
>> +
>> +#define FRAMESZ_MASK 0x1F
>> +#define FMCOUNT_MASK 0x00FFFF00
>> +#define FMCOUNT_SHIFT 8
>> +
>>
>
> Try to keep the previous definitions in the C source, since there are not
> useful outside of it. Except R_SPI_MAX I think you can move all of them.
>
> OK
> +#define TXDONE (1 << 0)
>> +#define RXRDY (1 << 1)
>> +#define RXCHOVRF (1 << 2)
>> +
>>
>
> These last 3 seems to be S_TXDONE, S_RXRDY, S_RXCHOVRF.
>
>
> Ok
Thanks,
Sundeep
>
> +#define TYPE_MSS_SPI "mss-spi"
>> +#define MSS_SPI(obj) OBJECT_CHECK(MSSSpiState, (obj), TYPE_MSS_SPI)
>> +
>> +typedef struct MSSSpiState {
>> + SysBusDevice parent_obj;
>> +
>> + MemoryRegion mmio;
>> +
>> + qemu_irq irq;
>> +
>> + qemu_irq cs_line;
>> +
>> + SSIBus *spi;
>> +
>> + Fifo32 rx_fifo;
>> + Fifo32 tx_fifo;
>> +
>> + int fifo_depth;
>> + uint32_t frame_count;
>> + bool enabled;
>> +
>> + uint32_t regs[R_SPI_MAX];
>> +} MSSSpiState;
>> +
>> +#endif /* HW_MSS_SPI_H */
>>
>>
> Regards,
>
> Phil.
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC.
2017-05-16 15:38 [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (2 preceding siblings ...)
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
@ 2017-05-16 15:38 ` Subbaraya Sundeep
2017-05-26 23:48 ` Alistair Francis
2017-05-31 5:43 ` Philippe Mathieu-Daudé
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
2017-05-17 4:27 ` [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Philippe Mathieu-Daudé
5 siblings, 2 replies; 35+ messages in thread
From: Subbaraya Sundeep @ 2017-05-16 15:38 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 1 +
hw/arm/msf2-soc.c | 201 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/msf2-soc.h | 69 ++++++++++++++
4 files changed, 272 insertions(+)
create mode 100644 hw/arm/msf2-soc.c
create mode 100644 include/hw/arm/msf2-soc.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 78d7af0..7062512 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -122,3 +122,4 @@ CONFIG_ACPI=y
CONFIG_SMBIOS=y
CONFIG_ASPEED_SOC=y
CONFIG_GPIO_KEY=y
+CONFIG_MSF2=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 4c5c4ee..c828061 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
+obj-$(CONFIG_MSF2) += msf2-soc.o
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
new file mode 100644
index 0000000..329e30c
--- /dev/null
+++ b/hw/arm/msf2-soc.c
@@ -0,0 +1,201 @@
+/*
+ * SmartFusion2 SoC emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/serial.h"
+#include "hw/boards.h"
+#include "sysemu/block-backend.h"
+#include "hw/arm/msf2-soc.h"
+
+#define MSF2_TIMER_BASE 0x40004000
+#define MSF2_SYSREG_BASE 0x40038000
+
+#define MSF2_TIMER_IRQ0 14
+#define MSF2_TIMER_IRQ1 15
+
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
+
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
+
+static void m2sxxx_soc_initfn(Object *obj)
+{
+ MSF2State *s = MSF2_SOC(obj);
+ int i;
+
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
+
+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
+
+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
+
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
+ TYPE_MSS_SPI);
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+ }
+}
+
+static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ MSF2State *s = MSF2_SOC(dev_soc);
+ DeviceState *dev, *armv7m;
+ SysBusDevice *busdev;
+ Error *err = NULL;
+ int i;
+
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *nvm = g_new(MemoryRegion, 1);
+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
+
+ memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size,
+ &error_fatal);
+
+ /*
+ * On power-on, the eNVM region 0x60000000 is automatically
+ * remapped to the Cortex-M3 processor executable region
+ * start address (0x0). We do not support remapping other eNVM,
+ * eSRAM and DDR regions by guest(via Sysreg) currently.
+ */
+ memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
+ nvm, 0, s->envm_size);
+ vmstate_register_ram_global(nvm);
+
+ memory_region_set_readonly(nvm, true);
+ memory_region_set_readonly(nvm_alias, true);
+
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
+ memory_region_add_subregion(system_memory, 0, nvm_alias);
+
+ memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
+ &error_fatal);
+ vmstate_register_ram_global(sram);
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+ armv7m = DEVICE(&s->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 81);
+ qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
+ "memory", &error_abort);
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ for (i = 0; i < MSF2_NUM_UARTS; i++) {
+ if (serial_hds[i]) {
+ serial_mm_init(get_system_memory(), uart_addr[i], 2,
+ qdev_get_gpio_in(armv7m, uart_irq[i]),
+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
+ }
+ }
+
+ dev = DEVICE(&s->timer);
+ /* pclk0 is the timer input clock */
+ qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0);
+ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
+ sysbus_connect_irq(busdev, 1,
+ qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
+
+ dev = DEVICE(&s->sysreg);
+ object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
+
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
+ gchar *bus_name = g_strdup_printf("spi%d", i);
+
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ if (err != NULL) {
+ g_free(bus_name);
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ qdev_get_gpio_in(armv7m, spi_irq[i]));
+
+ /* Alias controller SPI bus to the SoC itself */
+ object_property_add_alias(OBJECT(s), bus_name,
+ OBJECT(&s->spi[i]), "spi0",
+ &error_abort);
+ g_free(bus_name);
+ }
+}
+
+static Property m2sxxx_soc_properties[] = {
+ DEFINE_PROP_STRING("part-name", MSF2State, part_name),
+ DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE),
+ DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZE),
+ /* Libero GUI shows 100Mhz as default for clocks */
+ DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000),
+ DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = m2sxxx_soc_realize;
+ dc->props = m2sxxx_soc_properties;
+}
+
+static const TypeInfo m2sxxx_soc_info = {
+ .name = TYPE_MSF2_SOC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSF2State),
+ .instance_init = m2sxxx_soc_initfn,
+ .class_init = m2sxxx_soc_class_init,
+};
+
+static void m2sxxx_soc_types(void)
+{
+ type_register_static(&m2sxxx_soc_info);
+}
+
+type_init(m2sxxx_soc_types)
diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
new file mode 100644
index 0000000..67adddb
--- /dev/null
+++ b/include/hw/arm/msf2-soc.h
@@ -0,0 +1,69 @@
+/*
+ * Microsemi Smartfusion2 SoC
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_MSF2_SOC_H
+#define HW_ARM_MSF2_SOC_H
+
+#include "hw/misc/msf2-sysreg.h"
+#include "hw/timer/mss-timer.h"
+#include "hw/ssi/mss-spi.h"
+#include "hw/arm/armv7m.h"
+#include "qemu/cutils.h"
+
+#define TYPE_MSF2_SOC "msf2-soc"
+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
+
+#define MSF2_NUM_SPIS 2
+#define MSF2_NUM_UARTS 2
+
+#define ENVM_BASE_ADDRESS 0x60000000
+
+#define SRAM_BASE_ADDRESS 0x20000000
+
+#define MSF2_ENVM_SIZE (512 * K_BYTE)
+#define MSF2_ESRAM_SIZE (64 * K_BYTE)
+
+#define M2S010_ENVM_SIZE (256 * K_BYTE)
+#define M2S010_ESRAM_SIZE (64 * K_BYTE)
+
+typedef struct MSF2State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ ARMv7MState armv7m;
+
+ char *part_name;
+ uint64_t envm_size;
+ uint64_t esram_size;
+
+ uint32_t pclk0;
+ uint32_t pclk1;
+
+ MSF2SysregState sysreg;
+ MSSTimerState timer;
+ MSSSpiState spi[MSF2_NUM_SPIS];
+} MSF2State;
+
+#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC.
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
@ 2017-05-26 23:48 ` Alistair Francis
2017-05-29 5:17 ` sundeep subbaraya
2017-05-31 5:43 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2017-05-26 23:48 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
<sundeep.lkml@gmail.com> wrote:
> Smartfusion2 SoC has hardened Microcontroller subsystem
> and flash based FPGA fabric. This patch adds support for
> Microcontroller subsystem in the SoC.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 1 +
> hw/arm/msf2-soc.c | 201 ++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/msf2-soc.h | 69 ++++++++++++++
> 4 files changed, 272 insertions(+)
> create mode 100644 hw/arm/msf2-soc.c
> create mode 100644 include/hw/arm/msf2-soc.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 78d7af0..7062512 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -122,3 +122,4 @@ CONFIG_ACPI=y
> CONFIG_SMBIOS=y
> CONFIG_ASPEED_SOC=y
> CONFIG_GPIO_KEY=y
> +CONFIG_MSF2=y
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 4c5c4ee..c828061 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
> +obj-$(CONFIG_MSF2) += msf2-soc.o
> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
> new file mode 100644
> index 0000000..329e30c
> --- /dev/null
> +++ b/hw/arm/msf2-soc.c
> @@ -0,0 +1,201 @@
> +/*
> + * SmartFusion2 SoC emulation.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/arm/arm.h"
> +#include "exec/address-spaces.h"
> +#include "hw/char/serial.h"
> +#include "hw/boards.h"
> +#include "sysemu/block-backend.h"
> +#include "hw/arm/msf2-soc.h"
> +
> +#define MSF2_TIMER_BASE 0x40004000
> +#define MSF2_SYSREG_BASE 0x40038000
> +
> +#define MSF2_TIMER_IRQ0 14
> +#define MSF2_TIMER_IRQ1 15
> +
> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
> +
> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
> +
> +static void m2sxxx_soc_initfn(Object *obj)
> +{
> + MSF2State *s = MSF2_SOC(obj);
> + int i;
> +
> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
> +
> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
> +
> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
> + TYPE_MSS_SPI);
> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> + }
> +}
> +
> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> + MSF2State *s = MSF2_SOC(dev_soc);
> + DeviceState *dev, *armv7m;
> + SysBusDevice *busdev;
> + Error *err = NULL;
> + int i;
> +
> + MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
> + MemoryRegion *sram = g_new(MemoryRegion, 1);
> +
> + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size,
> + &error_fatal);
> +
> + /*
> + * On power-on, the eNVM region 0x60000000 is automatically
> + * remapped to the Cortex-M3 processor executable region
> + * start address (0x0). We do not support remapping other eNVM,
> + * eSRAM and DDR regions by guest(via Sysreg) currently.
> + */
> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
> + nvm, 0, s->envm_size);
> + vmstate_register_ram_global(nvm);
> +
> + memory_region_set_readonly(nvm, true);
> + memory_region_set_readonly(nvm_alias, true);
> +
> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
> + memory_region_add_subregion(system_memory, 0, nvm_alias);
> +
> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
> + &error_fatal);
> + vmstate_register_ram_global(sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> +
> + armv7m = DEVICE(&s->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 81);
> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
> + "memory", &error_abort);
> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
> + if (serial_hds[i]) {
> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
> + qdev_get_gpio_in(armv7m, uart_irq[i]),
> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
> + }
> + }
> +
> + dev = DEVICE(&s->timer);
> + /* pclk0 is the timer input clock */
> + qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0);
> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
> + sysbus_connect_irq(busdev, 0,
> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
> + sysbus_connect_irq(busdev, 1,
> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
> +
> + dev = DEVICE(&s->sysreg);
> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + gchar *bus_name = g_strdup_printf("spi%d", i);
> +
> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
> + if (err != NULL) {
> + g_free(bus_name);
> + error_propagate(errp, err);
> + return;
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
> + qdev_get_gpio_in(armv7m, spi_irq[i]));
> +
> + /* Alias controller SPI bus to the SoC itself */
> + object_property_add_alias(OBJECT(s), bus_name,
> + OBJECT(&s->spi[i]), "spi0",
> + &error_abort);
> + g_free(bus_name);
> + }
> +}
> +
> +static Property m2sxxx_soc_properties[] = {
> + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
This is never used, why have it here?
> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE),
> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZE),
> + /* Libero GUI shows 100Mhz as default for clocks */
> + DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000),
> + DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000),
Same with this one.
Thanks,
Alistair
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = m2sxxx_soc_realize;
> + dc->props = m2sxxx_soc_properties;
> +}
> +
> +static const TypeInfo m2sxxx_soc_info = {
> + .name = TYPE_MSF2_SOC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSF2State),
> + .instance_init = m2sxxx_soc_initfn,
> + .class_init = m2sxxx_soc_class_init,
> +};
> +
> +static void m2sxxx_soc_types(void)
> +{
> + type_register_static(&m2sxxx_soc_info);
> +}
> +
> +type_init(m2sxxx_soc_types)
> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
> new file mode 100644
> index 0000000..67adddb
> --- /dev/null
> +++ b/include/hw/arm/msf2-soc.h
> @@ -0,0 +1,69 @@
> +/*
> + * Microsemi Smartfusion2 SoC
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_ARM_MSF2_SOC_H
> +#define HW_ARM_MSF2_SOC_H
> +
> +#include "hw/misc/msf2-sysreg.h"
> +#include "hw/timer/mss-timer.h"
> +#include "hw/ssi/mss-spi.h"
> +#include "hw/arm/armv7m.h"
> +#include "qemu/cutils.h"
> +
> +#define TYPE_MSF2_SOC "msf2-soc"
> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
> +
> +#define MSF2_NUM_SPIS 2
> +#define MSF2_NUM_UARTS 2
> +
> +#define ENVM_BASE_ADDRESS 0x60000000
> +
> +#define SRAM_BASE_ADDRESS 0x20000000
> +
> +#define MSF2_ENVM_SIZE (512 * K_BYTE)
> +#define MSF2_ESRAM_SIZE (64 * K_BYTE)
> +
> +#define M2S010_ENVM_SIZE (256 * K_BYTE)
> +#define M2S010_ESRAM_SIZE (64 * K_BYTE)
> +
> +typedef struct MSF2State {
> + /*< private >*/
> + SysBusDevice parent_obj;
> + /*< public >*/
> +
> + ARMv7MState armv7m;
> +
> + char *part_name;
> + uint64_t envm_size;
> + uint64_t esram_size;
> +
> + uint32_t pclk0;
> + uint32_t pclk1;
> +
> + MSF2SysregState sysreg;
> + MSSTimerState timer;
> + MSSSpiState spi[MSF2_NUM_SPIS];
> +} MSF2State;
> +
> +#endif
> --
> 2.5.0
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC.
2017-05-26 23:48 ` Alistair Francis
@ 2017-05-29 5:17 ` sundeep subbaraya
2017-05-30 22:33 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-05-29 5:17 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
Hi Alistair,
On Sat, May 27, 2017 at 5:18 AM, Alistair Francis <alistair23@gmail.com>
wrote:
> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
> <sundeep.lkml@gmail.com> wrote:
> > Smartfusion2 SoC has hardened Microcontroller subsystem
> > and flash based FPGA fabric. This patch adds support for
> > Microcontroller subsystem in the SoC.
> >
> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> > ---
> > default-configs/arm-softmmu.mak | 1 +
> > hw/arm/Makefile.objs | 1 +
> > hw/arm/msf2-soc.c | 201 ++++++++++++++++++++++++++++++
> ++++++++++
> > include/hw/arm/msf2-soc.h | 69 ++++++++++++++
> > 4 files changed, 272 insertions(+)
> > create mode 100644 hw/arm/msf2-soc.c
> > create mode 100644 include/hw/arm/msf2-soc.h
> >
> > diff --git a/default-configs/arm-softmmu.mak
> b/default-configs/arm-softmmu.mak
> > index 78d7af0..7062512 100644
> > --- a/default-configs/arm-softmmu.mak
> > +++ b/default-configs/arm-softmmu.mak
> > @@ -122,3 +122,4 @@ CONFIG_ACPI=y
> > CONFIG_SMBIOS=y
> > CONFIG_ASPEED_SOC=y
> > CONFIG_GPIO_KEY=y
> > +CONFIG_MSF2=y
> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> > index 4c5c4ee..c828061 100644
> > --- a/hw/arm/Makefile.objs
> > +++ b/hw/arm/Makefile.objs
> > @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> > obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> > obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
> > obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
> > +obj-$(CONFIG_MSF2) += msf2-soc.o
> > diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
> > new file mode 100644
> > index 0000000..329e30c
> > --- /dev/null
> > +++ b/hw/arm/msf2-soc.c
> > @@ -0,0 +1,201 @@
> > +/*
> > + * SmartFusion2 SoC emulation.
> > + *
> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> > + * of this software and associated documentation files (the
> "Software"), to deal
> > + * in the Software without restriction, including without limitation
> the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "qemu-common.h"
> > +#include "hw/arm/arm.h"
> > +#include "exec/address-spaces.h"
> > +#include "hw/char/serial.h"
> > +#include "hw/boards.h"
> > +#include "sysemu/block-backend.h"
> > +#include "hw/arm/msf2-soc.h"
> > +
> > +#define MSF2_TIMER_BASE 0x40004000
> > +#define MSF2_SYSREG_BASE 0x40038000
> > +
> > +#define MSF2_TIMER_IRQ0 14
> > +#define MSF2_TIMER_IRQ1 15
> > +
> > +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,
> 0x40011000 };
> > +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,
> 0x40010000 };
> > +
> > +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
> > +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
> > +
> > +static void m2sxxx_soc_initfn(Object *obj)
> > +{
> > + MSF2State *s = MSF2_SOC(obj);
> > + int i;
> > +
> > + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
> > + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
> > +
> > + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
> > + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
> > +
> > + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
> > + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
> > +
> > + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> > + object_initialize(&s->spi[i], sizeof(s->spi[i]),
> > + TYPE_MSS_SPI);
> > + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> > + }
> > +}
> > +
> > +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> > +{
> > + MSF2State *s = MSF2_SOC(dev_soc);
> > + DeviceState *dev, *armv7m;
> > + SysBusDevice *busdev;
> > + Error *err = NULL;
> > + int i;
> > +
> > + MemoryRegion *system_memory = get_system_memory();
> > + MemoryRegion *nvm = g_new(MemoryRegion, 1);
> > + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
> > + MemoryRegion *sram = g_new(MemoryRegion, 1);
> > +
> > + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size,
> > + &error_fatal);
> > +
> > + /*
> > + * On power-on, the eNVM region 0x60000000 is automatically
> > + * remapped to the Cortex-M3 processor executable region
> > + * start address (0x0). We do not support remapping other eNVM,
> > + * eSRAM and DDR regions by guest(via Sysreg) currently.
> > + */
> > + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
> > + nvm, 0, s->envm_size);
> > + vmstate_register_ram_global(nvm);
> > +
> > + memory_region_set_readonly(nvm, true);
> > + memory_region_set_readonly(nvm_alias, true);
> > +
> > + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
> > + memory_region_add_subregion(system_memory, 0, nvm_alias);
> > +
> > + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
> > + &error_fatal);
> > + vmstate_register_ram_global(sram);
> > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS,
> sram);
> > +
> > + armv7m = DEVICE(&s->armv7m);
> > + qdev_prop_set_uint32(armv7m, "num-irq", 81);
> > + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
> > + object_property_set_link(OBJECT(&s->armv7m),
> OBJECT(get_system_memory()),
> > + "memory", &error_abort);
> > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized",
> &err);
> > + if (err != NULL) {
> > + error_propagate(errp, err);
> > + return;
> > + }
> > +
> > + for (i = 0; i < MSF2_NUM_UARTS; i++) {
> > + if (serial_hds[i]) {
> > + serial_mm_init(get_system_memory(), uart_addr[i], 2,
> > + qdev_get_gpio_in(armv7m, uart_irq[i]),
> > + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
> > + }
> > + }
> > +
> > + dev = DEVICE(&s->timer);
> > + /* pclk0 is the timer input clock */
> > + qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0);
> > + object_property_set_bool(OBJECT(&s->timer), true, "realized",
> &err);
> > + if (err != NULL) {
> > + error_propagate(errp, err);
> > + return;
> > + }
> > + busdev = SYS_BUS_DEVICE(dev);
> > + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
> > + sysbus_connect_irq(busdev, 0,
> > + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
> > + sysbus_connect_irq(busdev, 1,
> > + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
> > +
> > + dev = DEVICE(&s->sysreg);
> > + object_property_set_bool(OBJECT(&s->sysreg), true, "realized",
> &err);
> > + if (err != NULL) {
> > + error_propagate(errp, err);
> > + return;
> > + }
> > + busdev = SYS_BUS_DEVICE(dev);
> > + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
> > +
> > + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> > + gchar *bus_name = g_strdup_printf("spi%d", i);
> > +
> > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
> &err);
> > + if (err != NULL) {
> > + g_free(bus_name);
> > + error_propagate(errp, err);
> > + return;
> > + }
> > +
> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
> > + qdev_get_gpio_in(armv7m, spi_irq[i]));
> > +
> > + /* Alias controller SPI bus to the SoC itself */
> > + object_property_add_alias(OBJECT(s), bus_name,
> > + OBJECT(&s->spi[i]), "spi0",
> > + &error_abort);
> > + g_free(bus_name);
> > + }
> > +}
> > +
> > +static Property m2sxxx_soc_properties[] = {
> > + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
>
> This is never used, why have it here?
>
Just for information purpose as there are many variants. I thought it would
be good to
show this in qtree to user.
>
> > + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size,
> MSF2_ENVM_SIZE),
> > + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
> MSF2_ESRAM_SIZE),
> > + /* Libero GUI shows 100Mhz as default for clocks */
> > + DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000),
> > + DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000),
>
> Same with this one.
>
Yeah currently not used maybe it will be useful in future. I will remove it
for now.
Thanks,
Sundeep
>
> Thanks,
> Alistair
>
> > + DEFINE_PROP_END_OF_LIST(),
> > +};
> > +
> > +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
> > +{
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > +
> > + dc->realize = m2sxxx_soc_realize;
> > + dc->props = m2sxxx_soc_properties;
> > +}
> > +
> > +static const TypeInfo m2sxxx_soc_info = {
> > + .name = TYPE_MSF2_SOC,
> > + .parent = TYPE_SYS_BUS_DEVICE,
> > + .instance_size = sizeof(MSF2State),
> > + .instance_init = m2sxxx_soc_initfn,
> > + .class_init = m2sxxx_soc_class_init,
> > +};
> > +
> > +static void m2sxxx_soc_types(void)
> > +{
> > + type_register_static(&m2sxxx_soc_info);
> > +}
> > +
> > +type_init(m2sxxx_soc_types)
> > diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
> > new file mode 100644
> > index 0000000..67adddb
> > --- /dev/null
> > +++ b/include/hw/arm/msf2-soc.h
> > @@ -0,0 +1,69 @@
> > +/*
> > + * Microsemi Smartfusion2 SoC
> > + *
> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> > + * of this software and associated documentation files (the
> "Software"), to deal
> > + * in the Software without restriction, including without limitation
> the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#ifndef HW_ARM_MSF2_SOC_H
> > +#define HW_ARM_MSF2_SOC_H
> > +
> > +#include "hw/misc/msf2-sysreg.h"
> > +#include "hw/timer/mss-timer.h"
> > +#include "hw/ssi/mss-spi.h"
> > +#include "hw/arm/armv7m.h"
> > +#include "qemu/cutils.h"
> > +
> > +#define TYPE_MSF2_SOC "msf2-soc"
> > +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
> > +
> > +#define MSF2_NUM_SPIS 2
> > +#define MSF2_NUM_UARTS 2
> > +
> > +#define ENVM_BASE_ADDRESS 0x60000000
> > +
> > +#define SRAM_BASE_ADDRESS 0x20000000
> > +
> > +#define MSF2_ENVM_SIZE (512 * K_BYTE)
> > +#define MSF2_ESRAM_SIZE (64 * K_BYTE)
> > +
> > +#define M2S010_ENVM_SIZE (256 * K_BYTE)
> > +#define M2S010_ESRAM_SIZE (64 * K_BYTE)
> > +
> > +typedef struct MSF2State {
> > + /*< private >*/
> > + SysBusDevice parent_obj;
> > + /*< public >*/
> > +
> > + ARMv7MState armv7m;
> > +
> > + char *part_name;
> > + uint64_t envm_size;
> > + uint64_t esram_size;
> > +
> > + uint32_t pclk0;
> > + uint32_t pclk1;
> > +
> > + MSF2SysregState sysreg;
> > + MSSTimerState timer;
> > + MSSSpiState spi[MSF2_NUM_SPIS];
> > +} MSF2State;
> > +
> > +#endif
> > --
> > 2.5.0
> >
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC.
2017-05-29 5:17 ` sundeep subbaraya
@ 2017-05-30 22:33 ` Alistair Francis
2017-06-06 7:33 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2017-05-30 22:33 UTC (permalink / raw)
To: sundeep subbaraya
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
On Sun, May 28, 2017 at 10:17 PM, sundeep subbaraya
<sundeep.lkml@gmail.com> wrote:
> Hi Alistair,
>
> On Sat, May 27, 2017 at 5:18 AM, Alistair Francis <alistair23@gmail.com>
> wrote:
>>
>> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
>> <sundeep.lkml@gmail.com> wrote:
>> > Smartfusion2 SoC has hardened Microcontroller subsystem
>> > and flash based FPGA fabric. This patch adds support for
>> > Microcontroller subsystem in the SoC.
>> >
>> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> > ---
>> > default-configs/arm-softmmu.mak | 1 +
>> > hw/arm/Makefile.objs | 1 +
>> > hw/arm/msf2-soc.c | 201
>> > ++++++++++++++++++++++++++++++++++++++++
>> > include/hw/arm/msf2-soc.h | 69 ++++++++++++++
>> > 4 files changed, 272 insertions(+)
>> > create mode 100644 hw/arm/msf2-soc.c
>> > create mode 100644 include/hw/arm/msf2-soc.h
>> >
>> > diff --git a/default-configs/arm-softmmu.mak
>> > b/default-configs/arm-softmmu.mak
>> > index 78d7af0..7062512 100644
>> > --- a/default-configs/arm-softmmu.mak
>> > +++ b/default-configs/arm-softmmu.mak
>> > @@ -122,3 +122,4 @@ CONFIG_ACPI=y
>> > CONFIG_SMBIOS=y
>> > CONFIG_ASPEED_SOC=y
>> > CONFIG_GPIO_KEY=y
>> > +CONFIG_MSF2=y
>> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> > index 4c5c4ee..c828061 100644
>> > --- a/hw/arm/Makefile.objs
>> > +++ b/hw/arm/Makefile.objs
>> > @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
>> > obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
>> > obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
>> > obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
>> > +obj-$(CONFIG_MSF2) += msf2-soc.o
>> > diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
>> > new file mode 100644
>> > index 0000000..329e30c
>> > --- /dev/null
>> > +++ b/hw/arm/msf2-soc.c
>> > @@ -0,0 +1,201 @@
>> > +/*
>> > + * SmartFusion2 SoC emulation.
>> > + *
>> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> > + *
>> > + * Permission is hereby granted, free of charge, to any person
>> > obtaining a copy
>> > + * of this software and associated documentation files (the
>> > "Software"), to deal
>> > + * in the Software without restriction, including without limitation
>> > the rights
>> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> > sell
>> > + * copies of the Software, and to permit persons to whom the Software
>> > is
>> > + * furnished to do so, subject to the following conditions:
>> > + *
>> > + * The above copyright notice and this permission notice shall be
>> > included in
>> > + * all copies or substantial portions of the Software.
>> > + *
>> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> > EXPRESS OR
>> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> > MERCHANTABILITY,
>> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> > SHALL
>> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> > OTHER
>> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> > ARISING FROM,
>> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> > DEALINGS IN
>> > + * THE SOFTWARE.
>> > + */
>> > +
>> > +#include "qemu/osdep.h"
>> > +#include "qapi/error.h"
>> > +#include "qemu-common.h"
>> > +#include "hw/arm/arm.h"
>> > +#include "exec/address-spaces.h"
>> > +#include "hw/char/serial.h"
>> > +#include "hw/boards.h"
>> > +#include "sysemu/block-backend.h"
>> > +#include "hw/arm/msf2-soc.h"
>> > +
>> > +#define MSF2_TIMER_BASE 0x40004000
>> > +#define MSF2_SYSREG_BASE 0x40038000
>> > +
>> > +#define MSF2_TIMER_IRQ0 14
>> > +#define MSF2_TIMER_IRQ1 15
>> > +
>> > +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,
>> > 0x40011000 };
>> > +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,
>> > 0x40010000 };
>> > +
>> > +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>> > +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>> > +
>> > +static void m2sxxx_soc_initfn(Object *obj)
>> > +{
>> > + MSF2State *s = MSF2_SOC(obj);
>> > + int i;
>> > +
>> > + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>> > + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>> > +
>> > + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>> > + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>> > +
>> > + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
>> > + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>> > +
>> > + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> > + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>> > + TYPE_MSS_SPI);
>> > + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>> > + }
>> > +}
>> > +
>> > +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
>> > +{
>> > + MSF2State *s = MSF2_SOC(dev_soc);
>> > + DeviceState *dev, *armv7m;
>> > + SysBusDevice *busdev;
>> > + Error *err = NULL;
>> > + int i;
>> > +
>> > + MemoryRegion *system_memory = get_system_memory();
>> > + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>> > + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>> > + MemoryRegion *sram = g_new(MemoryRegion, 1);
>> > +
>> > + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size,
>> > + &error_fatal);
>> > +
>> > + /*
>> > + * On power-on, the eNVM region 0x60000000 is automatically
>> > + * remapped to the Cortex-M3 processor executable region
>> > + * start address (0x0). We do not support remapping other eNVM,
>> > + * eSRAM and DDR regions by guest(via Sysreg) currently.
>> > + */
>> > + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
>> > + nvm, 0, s->envm_size);
>> > + vmstate_register_ram_global(nvm);
>> > +
>> > + memory_region_set_readonly(nvm, true);
>> > + memory_region_set_readonly(nvm_alias, true);
>> > +
>> > + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
>> > + memory_region_add_subregion(system_memory, 0, nvm_alias);
>> > +
>> > + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
>> > + &error_fatal);
>> > + vmstate_register_ram_global(sram);
>> > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS,
>> > sram);
>> > +
>> > + armv7m = DEVICE(&s->armv7m);
>> > + qdev_prop_set_uint32(armv7m, "num-irq", 81);
>> > + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
>> > + object_property_set_link(OBJECT(&s->armv7m),
>> > OBJECT(get_system_memory()),
>> > + "memory", &error_abort);
>> > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized",
>> > &err);
>> > + if (err != NULL) {
>> > + error_propagate(errp, err);
>> > + return;
>> > + }
>> > +
>> > + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>> > + if (serial_hds[i]) {
>> > + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>> > + qdev_get_gpio_in(armv7m, uart_irq[i]),
>> > + 115200, serial_hds[i],
>> > DEVICE_NATIVE_ENDIAN);
>> > + }
>> > + }
>> > +
>> > + dev = DEVICE(&s->timer);
>> > + /* pclk0 is the timer input clock */
>> > + qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0);
>> > + object_property_set_bool(OBJECT(&s->timer), true, "realized",
>> > &err);
>> > + if (err != NULL) {
>> > + error_propagate(errp, err);
>> > + return;
>> > + }
>> > + busdev = SYS_BUS_DEVICE(dev);
>> > + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>> > + sysbus_connect_irq(busdev, 0,
>> > + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
>> > + sysbus_connect_irq(busdev, 1,
>> > + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
>> > +
>> > + dev = DEVICE(&s->sysreg);
>> > + object_property_set_bool(OBJECT(&s->sysreg), true, "realized",
>> > &err);
>> > + if (err != NULL) {
>> > + error_propagate(errp, err);
>> > + return;
>> > + }
>> > + busdev = SYS_BUS_DEVICE(dev);
>> > + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>> > +
>> > + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> > + gchar *bus_name = g_strdup_printf("spi%d", i);
>> > +
>> > + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>> > &err);
>> > + if (err != NULL) {
>> > + g_free(bus_name);
>> > + error_propagate(errp, err);
>> > + return;
>> > + }
>> > +
>> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>> > + qdev_get_gpio_in(armv7m, spi_irq[i]));
>> > +
>> > + /* Alias controller SPI bus to the SoC itself */
>> > + object_property_add_alias(OBJECT(s), bus_name,
>> > + OBJECT(&s->spi[i]), "spi0",
>> > + &error_abort);
>> > + g_free(bus_name);
>> > + }
>> > +}
>> > +
>> > +static Property m2sxxx_soc_properties[] = {
>> > + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
>>
>> This is never used, why have it here?
>
> Just for information purpose as there are many variants. I thought it would
> be good to
> show this in qtree to user.
Aw, cool. That is fine with me. Just add a comment saying that,
otherwise it is confusing why it isn't used.
>>
>>
>> > + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size,
>> > MSF2_ENVM_SIZE),
>> > + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
>> > MSF2_ESRAM_SIZE),
>> > + /* Libero GUI shows 100Mhz as default for clocks */
>> > + DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000),
>> > + DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000),
>>
>> Same with this one.
>
> Yeah currently not used maybe it will be useful in future. I will remove it
> for now.
I think that is best, if you end up using it in the future you can add
it back in.
Thanks,
Alistair
>
> Thanks,
> Sundeep
>>
>>
>> Thanks,
>> Alistair
>>
>> > + DEFINE_PROP_END_OF_LIST(),
>> > +};
>> > +
>> > +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
>> > +{
>> > + DeviceClass *dc = DEVICE_CLASS(klass);
>> > +
>> > + dc->realize = m2sxxx_soc_realize;
>> > + dc->props = m2sxxx_soc_properties;
>> > +}
>> > +
>> > +static const TypeInfo m2sxxx_soc_info = {
>> > + .name = TYPE_MSF2_SOC,
>> > + .parent = TYPE_SYS_BUS_DEVICE,
>> > + .instance_size = sizeof(MSF2State),
>> > + .instance_init = m2sxxx_soc_initfn,
>> > + .class_init = m2sxxx_soc_class_init,
>> > +};
>> > +
>> > +static void m2sxxx_soc_types(void)
>> > +{
>> > + type_register_static(&m2sxxx_soc_info);
>> > +}
>> > +
>> > +type_init(m2sxxx_soc_types)
>> > diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
>> > new file mode 100644
>> > index 0000000..67adddb
>> > --- /dev/null
>> > +++ b/include/hw/arm/msf2-soc.h
>> > @@ -0,0 +1,69 @@
>> > +/*
>> > + * Microsemi Smartfusion2 SoC
>> > + *
>> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> > + *
>> > + * Permission is hereby granted, free of charge, to any person
>> > obtaining a copy
>> > + * of this software and associated documentation files (the
>> > "Software"), to deal
>> > + * in the Software without restriction, including without limitation
>> > the rights
>> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> > sell
>> > + * copies of the Software, and to permit persons to whom the Software
>> > is
>> > + * furnished to do so, subject to the following conditions:
>> > + *
>> > + * The above copyright notice and this permission notice shall be
>> > included in
>> > + * all copies or substantial portions of the Software.
>> > + *
>> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> > EXPRESS OR
>> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> > MERCHANTABILITY,
>> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> > SHALL
>> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> > OTHER
>> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> > ARISING FROM,
>> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> > DEALINGS IN
>> > + * THE SOFTWARE.
>> > + */
>> > +
>> > +#ifndef HW_ARM_MSF2_SOC_H
>> > +#define HW_ARM_MSF2_SOC_H
>> > +
>> > +#include "hw/misc/msf2-sysreg.h"
>> > +#include "hw/timer/mss-timer.h"
>> > +#include "hw/ssi/mss-spi.h"
>> > +#include "hw/arm/armv7m.h"
>> > +#include "qemu/cutils.h"
>> > +
>> > +#define TYPE_MSF2_SOC "msf2-soc"
>> > +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>> > +
>> > +#define MSF2_NUM_SPIS 2
>> > +#define MSF2_NUM_UARTS 2
>> > +
>> > +#define ENVM_BASE_ADDRESS 0x60000000
>> > +
>> > +#define SRAM_BASE_ADDRESS 0x20000000
>> > +
>> > +#define MSF2_ENVM_SIZE (512 * K_BYTE)
>> > +#define MSF2_ESRAM_SIZE (64 * K_BYTE)
>> > +
>> > +#define M2S010_ENVM_SIZE (256 * K_BYTE)
>> > +#define M2S010_ESRAM_SIZE (64 * K_BYTE)
>> > +
>> > +typedef struct MSF2State {
>> > + /*< private >*/
>> > + SysBusDevice parent_obj;
>> > + /*< public >*/
>> > +
>> > + ARMv7MState armv7m;
>> > +
>> > + char *part_name;
>> > + uint64_t envm_size;
>> > + uint64_t esram_size;
>> > +
>> > + uint32_t pclk0;
>> > + uint32_t pclk1;
>> > +
>> > + MSF2SysregState sysreg;
>> > + MSSTimerState timer;
>> > + MSSSpiState spi[MSF2_NUM_SPIS];
>> > +} MSF2State;
>> > +
>> > +#endif
>> > --
>> > 2.5.0
>> >
>
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC.
2017-05-30 22:33 ` Alistair Francis
@ 2017-06-06 7:33 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-06 7:33 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
Hi Alistair,
On Wed, May 31, 2017 at 4:03 AM, Alistair Francis <alistair23@gmail.com>
wrote:
> On Sun, May 28, 2017 at 10:17 PM, sundeep subbaraya
> <sundeep.lkml@gmail.com> wrote:
> > Hi Alistair,
> >
> > On Sat, May 27, 2017 at 5:18 AM, Alistair Francis <alistair23@gmail.com>
> > wrote:
> >>
> >> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
> >> <sundeep.lkml@gmail.com> wrote:
> >> > Smartfusion2 SoC has hardened Microcontroller subsystem
> >> > and flash based FPGA fabric. This patch adds support for
> >> > Microcontroller subsystem in the SoC.
> >> >
> >> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> >> > ---
> >> > default-configs/arm-softmmu.mak | 1 +
> >> > hw/arm/Makefile.objs | 1 +
> >> > hw/arm/msf2-soc.c | 201
> >> > ++++++++++++++++++++++++++++++++++++++++
> >> > include/hw/arm/msf2-soc.h | 69 ++++++++++++++
> >> > 4 files changed, 272 insertions(+)
> >> > create mode 100644 hw/arm/msf2-soc.c
> >> > create mode 100644 include/hw/arm/msf2-soc.h
> >> >
> >> > diff --git a/default-configs/arm-softmmu.mak
> >> > b/default-configs/arm-softmmu.mak
> >> > index 78d7af0..7062512 100644
> >> > --- a/default-configs/arm-softmmu.mak
> >> > +++ b/default-configs/arm-softmmu.mak
> >> > @@ -122,3 +122,4 @@ CONFIG_ACPI=y
> >> > CONFIG_SMBIOS=y
> >> > CONFIG_ASPEED_SOC=y
> >> > CONFIG_GPIO_KEY=y
> >> > +CONFIG_MSF2=y
> >> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> >> > index 4c5c4ee..c828061 100644
> >> > --- a/hw/arm/Makefile.objs
> >> > +++ b/hw/arm/Makefile.objs
> >> > @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> >> > obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> >> > obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
> >> > obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
> >> > +obj-$(CONFIG_MSF2) += msf2-soc.o
> >> > diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
> >> > new file mode 100644
> >> > index 0000000..329e30c
> >> > --- /dev/null
> >> > +++ b/hw/arm/msf2-soc.c
> >> > @@ -0,0 +1,201 @@
> >> > +/*
> >> > + * SmartFusion2 SoC emulation.
> >> > + *
> >> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> >> > + *
> >> > + * Permission is hereby granted, free of charge, to any person
> >> > obtaining a copy
> >> > + * of this software and associated documentation files (the
> >> > "Software"), to deal
> >> > + * in the Software without restriction, including without limitation
> >> > the rights
> >> > + * to use, copy, modify, merge, publish, distribute, sublicense,
> and/or
> >> > sell
> >> > + * copies of the Software, and to permit persons to whom the Software
> >> > is
> >> > + * furnished to do so, subject to the following conditions:
> >> > + *
> >> > + * The above copyright notice and this permission notice shall be
> >> > included in
> >> > + * all copies or substantial portions of the Software.
> >> > + *
> >> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> > EXPRESS OR
> >> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> > MERCHANTABILITY,
> >> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> >> > SHALL
> >> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR
> >> > OTHER
> >> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >> > ARISING FROM,
> >> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> >> > DEALINGS IN
> >> > + * THE SOFTWARE.
> >> > + */
> >> > +
> >> > +#include "qemu/osdep.h"
> >> > +#include "qapi/error.h"
> >> > +#include "qemu-common.h"
> >> > +#include "hw/arm/arm.h"
> >> > +#include "exec/address-spaces.h"
> >> > +#include "hw/char/serial.h"
> >> > +#include "hw/boards.h"
> >> > +#include "sysemu/block-backend.h"
> >> > +#include "hw/arm/msf2-soc.h"
> >> > +
> >> > +#define MSF2_TIMER_BASE 0x40004000
> >> > +#define MSF2_SYSREG_BASE 0x40038000
> >> > +
> >> > +#define MSF2_TIMER_IRQ0 14
> >> > +#define MSF2_TIMER_IRQ1 15
> >> > +
> >> > +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,
> >> > 0x40011000 };
> >> > +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,
> >> > 0x40010000 };
> >> > +
> >> > +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
> >> > +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
> >> > +
> >> > +static void m2sxxx_soc_initfn(Object *obj)
> >> > +{
> >> > + MSF2State *s = MSF2_SOC(obj);
> >> > + int i;
> >> > +
> >> > + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
> >> > + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
> >> > +
> >> > + object_initialize(&s->sysreg, sizeof(s->sysreg),
> TYPE_MSF2_SYSREG);
> >> > + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
> >> > +
> >> > + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
> >> > + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
> >> > +
> >> > + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> >> > + object_initialize(&s->spi[i], sizeof(s->spi[i]),
> >> > + TYPE_MSS_SPI);
> >> > + qdev_set_parent_bus(DEVICE(&s->spi[i]),
> sysbus_get_default());
> >> > + }
> >> > +}
> >> > +
> >> > +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> >> > +{
> >> > + MSF2State *s = MSF2_SOC(dev_soc);
> >> > + DeviceState *dev, *armv7m;
> >> > + SysBusDevice *busdev;
> >> > + Error *err = NULL;
> >> > + int i;
> >> > +
> >> > + MemoryRegion *system_memory = get_system_memory();
> >> > + MemoryRegion *nvm = g_new(MemoryRegion, 1);
> >> > + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
> >> > + MemoryRegion *sram = g_new(MemoryRegion, 1);
> >> > +
> >> > + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size,
> >> > + &error_fatal);
> >> > +
> >> > + /*
> >> > + * On power-on, the eNVM region 0x60000000 is automatically
> >> > + * remapped to the Cortex-M3 processor executable region
> >> > + * start address (0x0). We do not support remapping other eNVM,
> >> > + * eSRAM and DDR regions by guest(via Sysreg) currently.
> >> > + */
> >> > + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
> >> > + nvm, 0, s->envm_size);
> >> > + vmstate_register_ram_global(nvm);
> >> > +
> >> > + memory_region_set_readonly(nvm, true);
> >> > + memory_region_set_readonly(nvm_alias, true);
> >> > +
> >> > + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS,
> nvm);
> >> > + memory_region_add_subregion(system_memory, 0, nvm_alias);
> >> > +
> >> > + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
> >> > + &error_fatal);
> >> > + vmstate_register_ram_global(sram);
> >> > + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS,
> >> > sram);
> >> > +
> >> > + armv7m = DEVICE(&s->armv7m);
> >> > + qdev_prop_set_uint32(armv7m, "num-irq", 81);
> >> > + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
> >> > + object_property_set_link(OBJECT(&s->armv7m),
> >> > OBJECT(get_system_memory()),
> >> > + "memory", &error_abort);
> >> > + object_property_set_bool(OBJECT(&s->armv7m), true, "realized",
> >> > &err);
> >> > + if (err != NULL) {
> >> > + error_propagate(errp, err);
> >> > + return;
> >> > + }
> >> > +
> >> > + for (i = 0; i < MSF2_NUM_UARTS; i++) {
> >> > + if (serial_hds[i]) {
> >> > + serial_mm_init(get_system_memory(), uart_addr[i], 2,
> >> > + qdev_get_gpio_in(armv7m, uart_irq[i]),
> >> > + 115200, serial_hds[i],
> >> > DEVICE_NATIVE_ENDIAN);
> >> > + }
> >> > + }
> >> > +
> >> > + dev = DEVICE(&s->timer);
> >> > + /* pclk0 is the timer input clock */
> >> > + qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0);
> >> > + object_property_set_bool(OBJECT(&s->timer), true, "realized",
> >> > &err);
> >> > + if (err != NULL) {
> >> > + error_propagate(errp, err);
> >> > + return;
> >> > + }
> >> > + busdev = SYS_BUS_DEVICE(dev);
> >> > + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
> >> > + sysbus_connect_irq(busdev, 0,
> >> > + qdev_get_gpio_in(armv7m,
> MSF2_TIMER_IRQ0));
> >> > + sysbus_connect_irq(busdev, 1,
> >> > + qdev_get_gpio_in(armv7m,
> MSF2_TIMER_IRQ1));
> >> > +
> >> > + dev = DEVICE(&s->sysreg);
> >> > + object_property_set_bool(OBJECT(&s->sysreg), true, "realized",
> >> > &err);
> >> > + if (err != NULL) {
> >> > + error_propagate(errp, err);
> >> > + return;
> >> > + }
> >> > + busdev = SYS_BUS_DEVICE(dev);
> >> > + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
> >> > +
> >> > + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> >> > + gchar *bus_name = g_strdup_printf("spi%d", i);
> >> > +
> >> > + object_property_set_bool(OBJECT(&s->spi[i]), true,
> "realized",
> >> > &err);
> >> > + if (err != NULL) {
> >> > + g_free(bus_name);
> >> > + error_propagate(errp, err);
> >> > + return;
> >> > + }
> >> > +
> >> > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
> >> > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
> >> > + qdev_get_gpio_in(armv7m, spi_irq[i]));
> >> > +
> >> > + /* Alias controller SPI bus to the SoC itself */
> >> > + object_property_add_alias(OBJECT(s), bus_name,
> >> > + OBJECT(&s->spi[i]), "spi0",
> >> > + &error_abort);
> >> > + g_free(bus_name);
> >> > + }
> >> > +}
> >> > +
> >> > +static Property m2sxxx_soc_properties[] = {
> >> > + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
> >>
> >> This is never used, why have it here?
> >
> > Just for information purpose as there are many variants. I thought it
> would
> > be good to
> > show this in qtree to user.
>
> Aw, cool. That is fine with me. Just add a comment saying that,
> otherwise it is confusing why it isn't used.
>
Ok I will add the comment.
>
> >>
> >>
> >> > + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size,
> >> > MSF2_ENVM_SIZE),
> >> > + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
> >> > MSF2_ESRAM_SIZE),
> >> > + /* Libero GUI shows 100Mhz as default for clocks */
> >> > + DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000),
> >> > + DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000),
> >>
> >> Same with this one.
> >
> > Yeah currently not used maybe it will be useful in future. I will remove
> it
> > for now.
>
> I think that is best, if you end up using it in the future you can add
> it back in.
Ok we will add in future if required.
Thanks,
Sundeep
>
> Thanks,
> Alistair
>
> >
> > Thanks,
> > Sundeep
> >>
> >>
> >> Thanks,
> >> Alistair
> >>
> >> > + DEFINE_PROP_END_OF_LIST(),
> >> > +};
> >> > +
> >> > +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
> >> > +{
> >> > + DeviceClass *dc = DEVICE_CLASS(klass);
> >> > +
> >> > + dc->realize = m2sxxx_soc_realize;
> >> > + dc->props = m2sxxx_soc_properties;
> >> > +}
> >> > +
> >> > +static const TypeInfo m2sxxx_soc_info = {
> >> > + .name = TYPE_MSF2_SOC,
> >> > + .parent = TYPE_SYS_BUS_DEVICE,
> >> > + .instance_size = sizeof(MSF2State),
> >> > + .instance_init = m2sxxx_soc_initfn,
> >> > + .class_init = m2sxxx_soc_class_init,
> >> > +};
> >> > +
> >> > +static void m2sxxx_soc_types(void)
> >> > +{
> >> > + type_register_static(&m2sxxx_soc_info);
> >> > +}
> >> > +
> >> > +type_init(m2sxxx_soc_types)
> >> > diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
> >> > new file mode 100644
> >> > index 0000000..67adddb
> >> > --- /dev/null
> >> > +++ b/include/hw/arm/msf2-soc.h
> >> > @@ -0,0 +1,69 @@
> >> > +/*
> >> > + * Microsemi Smartfusion2 SoC
> >> > + *
> >> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> >> > + *
> >> > + * Permission is hereby granted, free of charge, to any person
> >> > obtaining a copy
> >> > + * of this software and associated documentation files (the
> >> > "Software"), to deal
> >> > + * in the Software without restriction, including without limitation
> >> > the rights
> >> > + * to use, copy, modify, merge, publish, distribute, sublicense,
> and/or
> >> > sell
> >> > + * copies of the Software, and to permit persons to whom the Software
> >> > is
> >> > + * furnished to do so, subject to the following conditions:
> >> > + *
> >> > + * The above copyright notice and this permission notice shall be
> >> > included in
> >> > + * all copies or substantial portions of the Software.
> >> > + *
> >> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> > EXPRESS OR
> >> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> > MERCHANTABILITY,
> >> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> >> > SHALL
> >> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR
> >> > OTHER
> >> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >> > ARISING FROM,
> >> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> >> > DEALINGS IN
> >> > + * THE SOFTWARE.
> >> > + */
> >> > +
> >> > +#ifndef HW_ARM_MSF2_SOC_H
> >> > +#define HW_ARM_MSF2_SOC_H
> >> > +
> >> > +#include "hw/misc/msf2-sysreg.h"
> >> > +#include "hw/timer/mss-timer.h"
> >> > +#include "hw/ssi/mss-spi.h"
> >> > +#include "hw/arm/armv7m.h"
> >> > +#include "qemu/cutils.h"
> >> > +
> >> > +#define TYPE_MSF2_SOC "msf2-soc"
> >> > +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj),
> TYPE_MSF2_SOC)
> >> > +
> >> > +#define MSF2_NUM_SPIS 2
> >> > +#define MSF2_NUM_UARTS 2
> >> > +
> >> > +#define ENVM_BASE_ADDRESS 0x60000000
> >> > +
> >> > +#define SRAM_BASE_ADDRESS 0x20000000
> >> > +
> >> > +#define MSF2_ENVM_SIZE (512 * K_BYTE)
> >> > +#define MSF2_ESRAM_SIZE (64 * K_BYTE)
> >> > +
> >> > +#define M2S010_ENVM_SIZE (256 * K_BYTE)
> >> > +#define M2S010_ESRAM_SIZE (64 * K_BYTE)
> >> > +
> >> > +typedef struct MSF2State {
> >> > + /*< private >*/
> >> > + SysBusDevice parent_obj;
> >> > + /*< public >*/
> >> > +
> >> > + ARMv7MState armv7m;
> >> > +
> >> > + char *part_name;
> >> > + uint64_t envm_size;
> >> > + uint64_t esram_size;
> >> > +
> >> > + uint32_t pclk0;
> >> > + uint32_t pclk1;
> >> > +
> >> > + MSF2SysregState sysreg;
> >> > + MSSTimerState timer;
> >> > + MSSSpiState spi[MSF2_NUM_SPIS];
> >> > +} MSF2State;
> >> > +
> >> > +#endif
> >> > --
> >> > 2.5.0
> >> >
> >
> >
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC.
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
2017-05-26 23:48 ` Alistair Francis
@ 2017-05-31 5:43 ` Philippe Mathieu-Daudé
2017-06-06 7:35 ` sundeep subbaraya
1 sibling, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-05-31 5:43 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
Hi Subbaraya,
So far so good!
On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
> Smartfusion2 SoC has hardened Microcontroller subsystem
> and flash based FPGA fabric. This patch adds support for
> Microcontroller subsystem in the SoC.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 1 +
> hw/arm/msf2-soc.c | 201 ++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/msf2-soc.h | 69 ++++++++++++++
> 4 files changed, 272 insertions(+)
> create mode 100644 hw/arm/msf2-soc.c
> create mode 100644 include/hw/arm/msf2-soc.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 78d7af0..7062512 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -122,3 +122,4 @@ CONFIG_ACPI=y
> CONFIG_SMBIOS=y
> CONFIG_ASPEED_SOC=y
> CONFIG_GPIO_KEY=y
> +CONFIG_MSF2=y
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 4c5c4ee..c828061 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
> obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
> +obj-$(CONFIG_MSF2) += msf2-soc.o
> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
> new file mode 100644
> index 0000000..329e30c
> --- /dev/null
> +++ b/hw/arm/msf2-soc.c
> @@ -0,0 +1,201 @@
> +/*
> + * SmartFusion2 SoC emulation.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/arm/arm.h"
> +#include "exec/address-spaces.h"
> +#include "hw/char/serial.h"
> +#include "hw/boards.h"
> +#include "sysemu/block-backend.h"
> +#include "hw/arm/msf2-soc.h"
> +
> +#define MSF2_TIMER_BASE 0x40004000
> +#define MSF2_SYSREG_BASE 0x40038000
> +
> +#define MSF2_TIMER_IRQ0 14
> +#define MSF2_TIMER_IRQ1 15
> +
> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
> +
> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
Maybe you can declare timer_irq[] here instead of the defines, to keep a
common style.
> +
> +static void m2sxxx_soc_initfn(Object *obj)
> +{
> + MSF2State *s = MSF2_SOC(obj);
> + int i;
> +
> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
> +
> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
> +
> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
> + TYPE_MSS_SPI);
> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> + }
> +}
> +
> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> + MSF2State *s = MSF2_SOC(dev_soc);
> + DeviceState *dev, *armv7m;
> + SysBusDevice *busdev;
> + Error *err = NULL;
> + int i;
> +
> + MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
> + MemoryRegion *sram = g_new(MemoryRegion, 1);
> +
> + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size,
> + &error_fatal);
> +
> + /*
> + * On power-on, the eNVM region 0x60000000 is automatically
> + * remapped to the Cortex-M3 processor executable region
> + * start address (0x0). We do not support remapping other eNVM,
> + * eSRAM and DDR regions by guest(via Sysreg) currently.
> + */
> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
> + nvm, 0, s->envm_size);
> + vmstate_register_ram_global(nvm);
> +
> + memory_region_set_readonly(nvm, true);
> + memory_region_set_readonly(nvm_alias, true);
> +
> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
> + memory_region_add_subregion(system_memory, 0, nvm_alias);
> +
> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
> + &error_fatal);
> + vmstate_register_ram_global(sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> +
> + armv7m = DEVICE(&s->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 81);
> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
> + "memory", &error_abort);
> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
> + if (serial_hds[i]) {
> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
> + qdev_get_gpio_in(armv7m, uart_irq[i]),
> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
> + }
> + }
> +
> + dev = DEVICE(&s->timer);
> + /* pclk0 is the timer input clock */
> + qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0);
> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
> + sysbus_connect_irq(busdev, 0,
> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
> + sysbus_connect_irq(busdev, 1,
> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
> +
> + dev = DEVICE(&s->sysreg);
> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + gchar *bus_name = g_strdup_printf("spi%d", i);
> +
> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
> + if (err != NULL) {
> + g_free(bus_name);
> + error_propagate(errp, err);
> + return;
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
> + qdev_get_gpio_in(armv7m, spi_irq[i]));
> +
> + /* Alias controller SPI bus to the SoC itself */
> + object_property_add_alias(OBJECT(s), bus_name,
> + OBJECT(&s->spi[i]), "spi0",
> + &error_abort);
> + g_free(bus_name);
> + }
> +}
> +
> +static Property m2sxxx_soc_properties[] = {
> + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_SIZE),
> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, MSF2_ESRAM_SIZE),
> + /* Libero GUI shows 100Mhz as default for clocks */
> + DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000),
> + DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = m2sxxx_soc_realize;
> + dc->props = m2sxxx_soc_properties;
> +}
> +
> +static const TypeInfo m2sxxx_soc_info = {
> + .name = TYPE_MSF2_SOC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSF2State),
> + .instance_init = m2sxxx_soc_initfn,
> + .class_init = m2sxxx_soc_class_init,
> +};
> +
> +static void m2sxxx_soc_types(void)
> +{
> + type_register_static(&m2sxxx_soc_info);
> +}
> +
> +type_init(m2sxxx_soc_types)
> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
> new file mode 100644
> index 0000000..67adddb
> --- /dev/null
> +++ b/include/hw/arm/msf2-soc.h
> @@ -0,0 +1,69 @@
> +/*
> + * Microsemi Smartfusion2 SoC
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_ARM_MSF2_SOC_H
> +#define HW_ARM_MSF2_SOC_H
> +
> +#include "hw/misc/msf2-sysreg.h"
> +#include "hw/timer/mss-timer.h"
> +#include "hw/ssi/mss-spi.h"
> +#include "hw/arm/armv7m.h"
> +#include "qemu/cutils.h"
> +
> +#define TYPE_MSF2_SOC "msf2-soc"
> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
> +
> +#define MSF2_NUM_SPIS 2
> +#define MSF2_NUM_UARTS 2
> +
from here ...
> +#define ENVM_BASE_ADDRESS 0x60000000
> +
> +#define SRAM_BASE_ADDRESS 0x20000000
> +
> +#define MSF2_ENVM_SIZE (512 * K_BYTE)
> +#define MSF2_ESRAM_SIZE (64 * K_BYTE)
> +
> +#define M2S010_ENVM_SIZE (256 * K_BYTE)
> +#define M2S010_ESRAM_SIZE (64 * K_BYTE)
> +
... to here can go in C source.
> +typedef struct MSF2State {
> + /*< private >*/
> + SysBusDevice parent_obj;
> + /*< public >*/
> +
> + ARMv7MState armv7m;
> +
> + char *part_name;
> + uint64_t envm_size;
> + uint64_t esram_size;
> +
> + uint32_t pclk0;
> + uint32_t pclk1;
> +
> + MSF2SysregState sysreg;
> + MSSTimerState timer;
> + MSSSpiState spi[MSF2_NUM_SPIS];
> +} MSF2State;
> +
> +#endif
>
Regards,
Phil.
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC.
2017-05-31 5:43 ` Philippe Mathieu-Daudé
@ 2017-06-06 7:35 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-06 7:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Wed, May 31, 2017 at 11:13 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Subbaraya,
>
> So far so good!
>
>
> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>
>> Smartfusion2 SoC has hardened Microcontroller subsystem
>> and flash based FPGA fabric. This patch adds support for
>> Microcontroller subsystem in the SoC.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> ---
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/Makefile.objs | 1 +
>> hw/arm/msf2-soc.c | 201 ++++++++++++++++++++++++++++++
>> ++++++++++
>> include/hw/arm/msf2-soc.h | 69 ++++++++++++++
>> 4 files changed, 272 insertions(+)
>> create mode 100644 hw/arm/msf2-soc.c
>> create mode 100644 include/hw/arm/msf2-soc.h
>>
>> diff --git a/default-configs/arm-softmmu.mak
>> b/default-configs/arm-softmmu.mak
>> index 78d7af0..7062512 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -122,3 +122,4 @@ CONFIG_ACPI=y
>> CONFIG_SMBIOS=y
>> CONFIG_ASPEED_SOC=y
>> CONFIG_GPIO_KEY=y
>> +CONFIG_MSF2=y
>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> index 4c5c4ee..c828061 100644
>> --- a/hw/arm/Makefile.objs
>> +++ b/hw/arm/Makefile.objs
>> @@ -18,3 +18,4 @@ obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
>> obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o
>> obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o
>> obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o
>> +obj-$(CONFIG_MSF2) += msf2-soc.o
>> diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
>> new file mode 100644
>> index 0000000..329e30c
>> --- /dev/null
>> +++ b/hw/arm/msf2-soc.c
>> @@ -0,0 +1,201 @@
>> +/*
>> + * SmartFusion2 SoC emulation.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "qemu-common.h"
>> +#include "hw/arm/arm.h"
>> +#include "exec/address-spaces.h"
>> +#include "hw/char/serial.h"
>> +#include "hw/boards.h"
>> +#include "sysemu/block-backend.h"
>> +#include "hw/arm/msf2-soc.h"
>> +
>> +#define MSF2_TIMER_BASE 0x40004000
>> +#define MSF2_SYSREG_BASE 0x40038000
>> +
>> +#define MSF2_TIMER_IRQ0 14
>> +#define MSF2_TIMER_IRQ1 15
>> +
>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 ,
>> 0x40011000 };
>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 ,
>> 0x40010000 };
>> +
>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>>
>
> Maybe you can declare timer_irq[] here instead of the defines, to keep a
> common style.
Ok will change.
>
>
> +
>> +static void m2sxxx_soc_initfn(Object *obj)
>> +{
>> + MSF2State *s = MSF2_SOC(obj);
>> + int i;
>> +
>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>> +
>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>> +
>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSS_TIMER);
>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>> +
>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>> + TYPE_MSS_SPI);
>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>> + }
>> +}
>> +
>> +static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp)
>> +{
>> + MSF2State *s = MSF2_SOC(dev_soc);
>> + DeviceState *dev, *armv7m;
>> + SysBusDevice *busdev;
>> + Error *err = NULL;
>> + int i;
>> +
>> + MemoryRegion *system_memory = get_system_memory();
>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>> +
>> + memory_region_init_ram(nvm, NULL, "MSF2.eNVM", s->envm_size,
>> + &error_fatal);
>> +
>> + /*
>> + * On power-on, the eNVM region 0x60000000 is automatically
>> + * remapped to the Cortex-M3 processor executable region
>> + * start address (0x0). We do not support remapping other eNVM,
>> + * eSRAM and DDR regions by guest(via Sysreg) currently.
>> + */
>> + memory_region_init_alias(nvm_alias, NULL, "MSF2.eNVM.alias",
>> + nvm, 0, s->envm_size);
>> + vmstate_register_ram_global(nvm);
>> +
>> + memory_region_set_readonly(nvm, true);
>> + memory_region_set_readonly(nvm_alias, true);
>> +
>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
>> + memory_region_add_subregion(system_memory, 0, nvm_alias);
>> +
>> + memory_region_init_ram(sram, NULL, "MSF2.eSRAM", s->esram_size,
>> + &error_fatal);
>> + vmstate_register_ram_global(sram);
>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
>> +
>> + armv7m = DEVICE(&s->armv7m);
>> + qdev_prop_set_uint32(armv7m, "num-irq", 81);
>> + qdev_prop_set_string(armv7m, "cpu-model", "cortex-m3");
>> + object_property_set_link(OBJECT(&s->armv7m),
>> OBJECT(get_system_memory()),
>> + "memory", &error_abort);
>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized",
>> &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> +
>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>> + if (serial_hds[i]) {
>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>> + qdev_get_gpio_in(armv7m, uart_irq[i]),
>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
>> + }
>> + }
>> +
>> + dev = DEVICE(&s->timer);
>> + /* pclk0 is the timer input clock */
>> + qdev_prop_set_uint32(dev, "clock-frequency", s->pclk0);
>> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> + busdev = SYS_BUS_DEVICE(dev);
>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>> + sysbus_connect_irq(busdev, 0,
>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
>> + sysbus_connect_irq(busdev, 1,
>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
>> +
>> + dev = DEVICE(&s->sysreg);
>> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized",
>> &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> + busdev = SYS_BUS_DEVICE(dev);
>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>> +
>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> + gchar *bus_name = g_strdup_printf("spi%d", i);
>> +
>> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
>> &err);
>> + if (err != NULL) {
>> + g_free(bus_name);
>> + error_propagate(errp, err);
>> + return;
>> + }
>> +
>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>> + qdev_get_gpio_in(armv7m, spi_irq[i]));
>> +
>> + /* Alias controller SPI bus to the SoC itself */
>> + object_property_add_alias(OBJECT(s), bus_name,
>> + OBJECT(&s->spi[i]), "spi0",
>> + &error_abort);
>> + g_free(bus_name);
>> + }
>> +}
>> +
>> +static Property m2sxxx_soc_properties[] = {
>> + DEFINE_PROP_STRING("part-name", MSF2State, part_name),
>> + DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size,
>> MSF2_ENVM_SIZE),
>> + DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size,
>> MSF2_ESRAM_SIZE),
>> + /* Libero GUI shows 100Mhz as default for clocks */
>> + DEFINE_PROP_UINT32("pclk0", MSF2State, pclk0, 100 * 1000000),
>> + DEFINE_PROP_UINT32("pclk1", MSF2State, pclk1, 100 * 1000000),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void m2sxxx_soc_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->realize = m2sxxx_soc_realize;
>> + dc->props = m2sxxx_soc_properties;
>> +}
>> +
>> +static const TypeInfo m2sxxx_soc_info = {
>> + .name = TYPE_MSF2_SOC,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(MSF2State),
>> + .instance_init = m2sxxx_soc_initfn,
>> + .class_init = m2sxxx_soc_class_init,
>> +};
>> +
>> +static void m2sxxx_soc_types(void)
>> +{
>> + type_register_static(&m2sxxx_soc_info);
>> +}
>> +
>> +type_init(m2sxxx_soc_types)
>> diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h
>> new file mode 100644
>> index 0000000..67adddb
>> --- /dev/null
>> +++ b/include/hw/arm/msf2-soc.h
>> @@ -0,0 +1,69 @@
>> +/*
>> + * Microsemi Smartfusion2 SoC
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_ARM_MSF2_SOC_H
>> +#define HW_ARM_MSF2_SOC_H
>> +
>> +#include "hw/misc/msf2-sysreg.h"
>> +#include "hw/timer/mss-timer.h"
>> +#include "hw/ssi/mss-spi.h"
>> +#include "hw/arm/armv7m.h"
>> +#include "qemu/cutils.h"
>> +
>> +#define TYPE_MSF2_SOC "msf2-soc"
>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>> +
>> +#define MSF2_NUM_SPIS 2
>> +#define MSF2_NUM_UARTS 2
>> +
>>
>
> from here ...
>
> +#define ENVM_BASE_ADDRESS 0x60000000
>> +
>> +#define SRAM_BASE_ADDRESS 0x20000000
>> +
>> +#define MSF2_ENVM_SIZE (512 * K_BYTE)
>> +#define MSF2_ESRAM_SIZE (64 * K_BYTE)
>> +
>> +#define M2S010_ENVM_SIZE (256 * K_BYTE)
>> +#define M2S010_ESRAM_SIZE (64 * K_BYTE)
>> +
>>
>
> ... to here can go in C source.
Ok will change it.
>
>
> +typedef struct MSF2State {
>> + /*< private >*/
>> + SysBusDevice parent_obj;
>> + /*< public >*/
>> +
>> + ARMv7MState armv7m;
>> +
>> + char *part_name;
>> + uint64_t envm_size;
>> + uint64_t esram_size;
>> +
>> + uint32_t pclk0;
>> + uint32_t pclk1;
>> +
>> + MSF2SysregState sysreg;
>> + MSSTimerState timer;
>> + MSSSpiState spi[MSF2_NUM_SPIS];
>> +} MSF2State;
>> +
>> +#endif
>>
>>
> Regards,
>
> Phil.
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-05-16 15:38 [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (3 preceding siblings ...)
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
@ 2017-05-16 15:38 ` Subbaraya Sundeep
2017-05-27 0:00 ` Alistair Francis
2017-05-31 6:04 ` Philippe Mathieu-Daudé
2017-05-17 4:27 ` [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Philippe Mathieu-Daudé
5 siblings, 2 replies; 35+ messages in thread
From: Subbaraya Sundeep @ 2017-05-16 15:38 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, f4bug, Subbaraya Sundeep
Emulated Emcraft's Smartfusion2 System On Module starter
kit.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/arm/Makefile.objs | 1 +
hw/arm/msf2-som.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 90 insertions(+)
create mode 100644 hw/arm/msf2-som.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index c828061..4b02093 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
obj-$(CONFIG_ACPI) += virt-acpi-build.o
obj-y += netduino2.o
+obj-y += msf2-som.o
obj-y += sysbus-fdt.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
new file mode 100644
index 0000000..cd2b759
--- /dev/null
+++ b/hw/arm/msf2-som.c
@@ -0,0 +1,89 @@
+/*
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/arm/msf2-soc.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+
+#define DDR_BASE_ADDRESS 0xA0000000
+#define DDR_SIZE (64 * M_BYTE)
+
+static void emcraft_sf2_init(MachineState *machine)
+{
+ DeviceState *dev;
+ DeviceState *spi_flash;
+ MSF2State *soc;
+ DriveInfo *dinfo = drive_get_next(IF_MTD);
+ qemu_irq cs_line;
+ SSIBus *spi_bus;
+ MemoryRegion *sysmem = get_system_memory();
+ MemoryRegion *ddr = g_new(MemoryRegion, 1);
+
+ memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
+ &error_fatal);
+ vmstate_register_ram_global(ddr);
+ memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
+
+ dev = qdev_create(NULL, TYPE_MSF2_SOC);
+ qdev_prop_set_string(dev, "part-name", "M2S010");
+ qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
+ qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
+
+ /*
+ * pclk0 and pclk1 are configurable in Libero.
+ * Emcraft's SoM kit comes with these settings by default.
+ */
+ qdev_prop_set_uint32(dev, "pclk0", 71 * 1000000);
+ qdev_prop_set_uint32(dev, "pclk1", 71 * 1000000);
+
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
+
+ soc = MSF2_SOC(dev);
+
+ /* Attach SPI flash to SPI0 controller */
+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
+ if (dinfo) {
+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_fatal);
+ }
+ qdev_init_nofail(spi_flash);
+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
+
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ soc->envm_size);
+}
+
+static void emcraft_sf2_machine_init(MachineClass *mc)
+{
+ mc->desc = "SmartFusion2 SOM kit from Emcraft";
+ mc->init = emcraft_sf2_init;
+}
+
+DEFINE_MACHINE("smartfusion2-som", emcraft_sf2_machine_init)
--
2.5.0
^ permalink raw reply related [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
@ 2017-05-27 0:00 ` Alistair Francis
2017-05-29 5:26 ` sundeep subbaraya
2017-05-31 6:04 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2017-05-27 0:00 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
<sundeep.lkml@gmail.com> wrote:
> Emulated Emcraft's Smartfusion2 System On Module starter
> kit.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> hw/arm/Makefile.objs | 1 +
> hw/arm/msf2-som.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 90 insertions(+)
> create mode 100644 hw/arm/msf2-som.c
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index c828061..4b02093 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
> obj-$(CONFIG_ACPI) += virt-acpi-build.o
> obj-y += netduino2.o
> +obj-y += msf2-som.o
This should be obj-$(CONFIG_MSF2).
> obj-y += sysbus-fdt.o
>
> obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
> diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> new file mode 100644
> index 0000000..cd2b759
> --- /dev/null
> +++ b/hw/arm/msf2-som.c
> @@ -0,0 +1,89 @@
> +/*
> + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/boards.h"
> +#include "hw/arm/msf2-soc.h"
> +#include "hw/arm/arm.h"
> +#include "exec/address-spaces.h"
> +
> +#define DDR_BASE_ADDRESS 0xA0000000
> +#define DDR_SIZE (64 * M_BYTE)
> +
> +static void emcraft_sf2_init(MachineState *machine)
> +{
> + DeviceState *dev;
> + DeviceState *spi_flash;
> + MSF2State *soc;
> + DriveInfo *dinfo = drive_get_next(IF_MTD);
> + qemu_irq cs_line;
> + SSIBus *spi_bus;
> + MemoryRegion *sysmem = get_system_memory();
> + MemoryRegion *ddr = g_new(MemoryRegion, 1);
> +
> + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
> + &error_fatal);
> + vmstate_register_ram_global(ddr);
> + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
The user can use -m to specify the amount of RAM to create in the
machine. Unless this board only ever includes 64MB of RAM you should
use that option (you will need to sanity check it though). If the
board only ever has 64MB it might be worth printing a warning to the
user if they specify an something. Although there might be a default
if they don't use -m, which makes it hard to print out a warning
message.
> +
> + dev = qdev_create(NULL, TYPE_MSF2_SOC);
> + qdev_prop_set_string(dev, "part-name", "M2S010");
> + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
> + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
> +
> + /*
> + * pclk0 and pclk1 are configurable in Libero.
> + * Emcraft's SoM kit comes with these settings by default.
> + */
> + qdev_prop_set_uint32(dev, "pclk0", 71 * 1000000);
> + qdev_prop_set_uint32(dev, "pclk1", 71 * 1000000);
> +
> + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
> +
> + soc = MSF2_SOC(dev);
> +
> + /* Attach SPI flash to SPI0 controller */
> + spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
> + spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
> + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
> + if (dinfo) {
> + qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
> + &error_fatal);
> + }
> + qdev_init_nofail(spi_flash);
Can you just set realized instead?
Thanks,
Alistair
> + cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
> +
> + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + soc->envm_size);
> +}
> +
> +static void emcraft_sf2_machine_init(MachineClass *mc)
> +{
> + mc->desc = "SmartFusion2 SOM kit from Emcraft";
> + mc->init = emcraft_sf2_init;
> +}
> +
> +DEFINE_MACHINE("smartfusion2-som", emcraft_sf2_machine_init)
> --
> 2.5.0
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-05-27 0:00 ` Alistair Francis
@ 2017-05-29 5:26 ` sundeep subbaraya
2017-05-30 22:32 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-05-29 5:26 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
Hi Alistair,
On Sat, May 27, 2017 at 5:30 AM, Alistair Francis <alistair23@gmail.com>
wrote:
> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
> <sundeep.lkml@gmail.com> wrote:
> > Emulated Emcraft's Smartfusion2 System On Module starter
> > kit.
> >
> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> > ---
> > hw/arm/Makefile.objs | 1 +
> > hw/arm/msf2-som.c | 89 ++++++++++++++++++++++++++++++
> ++++++++++++++++++++++
> > 2 files changed, 90 insertions(+)
> > create mode 100644 hw/arm/msf2-som.c
> >
> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> > index c828061..4b02093 100644
> > --- a/hw/arm/Makefile.objs
> > +++ b/hw/arm/Makefile.objs
> > @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
> > obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
> > obj-$(CONFIG_ACPI) += virt-acpi-build.o
> > obj-y += netduino2.o
> > +obj-y += msf2-som.o
>
> This should be obj-$(CONFIG_MSF2).
>
Ok will change it.
>
> > obj-y += sysbus-fdt.o
> >
> > obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
> > diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> > new file mode 100644
> > index 0000000..cd2b759
> > --- /dev/null
> > +++ b/hw/arm/msf2-som.c
> > @@ -0,0 +1,89 @@
> > +/*
> > + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
> > + *
> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> > + * of this software and associated documentation files (the
> "Software"), to deal
> > + * in the Software without restriction, including without limitation
> the rights
> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
> sell
> > + * copies of the Software, and to permit persons to whom the Software is
> > + * furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> included in
> > + * all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING FROM,
> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS IN
> > + * THE SOFTWARE.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "hw/boards.h"
> > +#include "hw/arm/msf2-soc.h"
> > +#include "hw/arm/arm.h"
> > +#include "exec/address-spaces.h"
> > +
> > +#define DDR_BASE_ADDRESS 0xA0000000
> > +#define DDR_SIZE (64 * M_BYTE)
> > +
> > +static void emcraft_sf2_init(MachineState *machine)
> > +{
> > + DeviceState *dev;
> > + DeviceState *spi_flash;
> > + MSF2State *soc;
> > + DriveInfo *dinfo = drive_get_next(IF_MTD);
> > + qemu_irq cs_line;
> > + SSIBus *spi_bus;
> > + MemoryRegion *sysmem = get_system_memory();
> > + MemoryRegion *ddr = g_new(MemoryRegion, 1);
> > +
> > + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
> > + &error_fatal);
> > + vmstate_register_ram_global(ddr);
> > + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
>
> The user can use -m to specify the amount of RAM to create in the
> machine. Unless this board only ever includes 64MB of RAM you should
> use that option (you will need to sanity check it though). If the
> board only ever has 64MB it might be worth printing a warning to the
> user if they specify an something. Although there might be a default
> if they don't use -m, which makes it hard to print out a warning
> message.
>
This -m confuses me. Why is it necessary for an embedded board? RAM chip
is fixed and not extendable. Whereas normal PC may have extra RAM slots.
If another board has more RAM then we would instantiate another machine for
it
with that RAM size. Please explain. Maybe I am thinking in wrong direction.
Thanks,
Sundeep
>
> > +
> > + dev = qdev_create(NULL, TYPE_MSF2_SOC);
> > + qdev_prop_set_string(dev, "part-name", "M2S010");
> > + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
> > + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
> > +
> > + /*
> > + * pclk0 and pclk1 are configurable in Libero.
> > + * Emcraft's SoM kit comes with these settings by default.
> > + */
> > + qdev_prop_set_uint32(dev, "pclk0", 71 * 1000000);
> > + qdev_prop_set_uint32(dev, "pclk1", 71 * 1000000);
> > +
> > + object_property_set_bool(OBJECT(dev), true, "realized",
> &error_fatal);
> > +
> > + soc = MSF2_SOC(dev);
> > +
> > + /* Attach SPI flash to SPI0 controller */
> > + spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
> > + spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
> > + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
> > + if (dinfo) {
> > + qdev_prop_set_drive(spi_flash, "drive",
> blk_by_legacy_dinfo(dinfo),
> > + &error_fatal);
> > + }
> > + qdev_init_nofail(spi_flash);
>
> Can you just set realized instead?
>
Ok I will check and change.
Thanks,
Sundeep
>
> Thanks,
> Alistair
>
> > + cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
> > +
> > + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> > + soc->envm_size);
> > +}
> > +
> > +static void emcraft_sf2_machine_init(MachineClass *mc)
> > +{
> > + mc->desc = "SmartFusion2 SOM kit from Emcraft";
> > + mc->init = emcraft_sf2_init;
> > +}
> > +
> > +DEFINE_MACHINE("smartfusion2-som", emcraft_sf2_machine_init)
> > --
> > 2.5.0
> >
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-05-29 5:26 ` sundeep subbaraya
@ 2017-05-30 22:32 ` Alistair Francis
2017-06-26 16:01 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2017-05-30 22:32 UTC (permalink / raw)
To: sundeep subbaraya
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
On Sun, May 28, 2017 at 10:26 PM, sundeep subbaraya
<sundeep.lkml@gmail.com> wrote:
> Hi Alistair,
>
> On Sat, May 27, 2017 at 5:30 AM, Alistair Francis <alistair23@gmail.com>
> wrote:
>>
>> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
>> <sundeep.lkml@gmail.com> wrote:
>> > Emulated Emcraft's Smartfusion2 System On Module starter
>> > kit.
>> >
>> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> > ---
>> > hw/arm/Makefile.objs | 1 +
>> > hw/arm/msf2-som.c | 89
>> > ++++++++++++++++++++++++++++++++++++++++++++++++++++
>> > 2 files changed, 90 insertions(+)
>> > create mode 100644 hw/arm/msf2-som.c
>> >
>> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> > index c828061..4b02093 100644
>> > --- a/hw/arm/Makefile.objs
>> > +++ b/hw/arm/Makefile.objs
>> > @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o
>> > stellaris.o
>> > obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
>> > obj-$(CONFIG_ACPI) += virt-acpi-build.o
>> > obj-y += netduino2.o
>> > +obj-y += msf2-som.o
>>
>> This should be obj-$(CONFIG_MSF2).
>
>
> Ok will change it.
>>
>>
>> > obj-y += sysbus-fdt.o
>> >
>> > obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
>> > diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
>> > new file mode 100644
>> > index 0000000..cd2b759
>> > --- /dev/null
>> > +++ b/hw/arm/msf2-som.c
>> > @@ -0,0 +1,89 @@
>> > +/*
>> > + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
>> > + *
>> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> > + *
>> > + * Permission is hereby granted, free of charge, to any person
>> > obtaining a copy
>> > + * of this software and associated documentation files (the
>> > "Software"), to deal
>> > + * in the Software without restriction, including without limitation
>> > the rights
>> > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> > sell
>> > + * copies of the Software, and to permit persons to whom the Software
>> > is
>> > + * furnished to do so, subject to the following conditions:
>> > + *
>> > + * The above copyright notice and this permission notice shall be
>> > included in
>> > + * all copies or substantial portions of the Software.
>> > + *
>> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> > EXPRESS OR
>> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> > MERCHANTABILITY,
>> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> > SHALL
>> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> > OTHER
>> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> > ARISING FROM,
>> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> > DEALINGS IN
>> > + * THE SOFTWARE.
>> > + */
>> > +
>> > +#include "qemu/osdep.h"
>> > +#include "qapi/error.h"
>> > +#include "hw/boards.h"
>> > +#include "hw/arm/msf2-soc.h"
>> > +#include "hw/arm/arm.h"
>> > +#include "exec/address-spaces.h"
>> > +
>> > +#define DDR_BASE_ADDRESS 0xA0000000
>> > +#define DDR_SIZE (64 * M_BYTE)
>> > +
>> > +static void emcraft_sf2_init(MachineState *machine)
>> > +{
>> > + DeviceState *dev;
>> > + DeviceState *spi_flash;
>> > + MSF2State *soc;
>> > + DriveInfo *dinfo = drive_get_next(IF_MTD);
>> > + qemu_irq cs_line;
>> > + SSIBus *spi_bus;
>> > + MemoryRegion *sysmem = get_system_memory();
>> > + MemoryRegion *ddr = g_new(MemoryRegion, 1);
>> > +
>> > + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
>> > + &error_fatal);
>> > + vmstate_register_ram_global(ddr);
>> > + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
>>
>> The user can use -m to specify the amount of RAM to create in the
>> machine. Unless this board only ever includes 64MB of RAM you should
>> use that option (you will need to sanity check it though). If the
>> board only ever has 64MB it might be worth printing a warning to the
>> user if they specify an something. Although there might be a default
>> if they don't use -m, which makes it hard to print out a warning
>> message.
>
>
> This -m confuses me. Why is it necessary for an embedded board? RAM chip
> is fixed and not extendable. Whereas normal PC may have extra RAM slots.
> If another board has more RAM then we would instantiate another machine for
> it
> with that RAM size. Please explain. Maybe I am thinking in wrong direction.
I agree with you, it doesn't make sense for every board. For some
embedded boards it does make sense (ZynqMP can have a customisable
amount of memory) but for most it doesn't make too much sense.
In saying that it is a commonly used QEMU option, if you can find a
way to report a warning if the user tries to specify a custom amount
of memory I think that would be beneficial as QEMU will just ignore
their input. I have a feeling that the ram_size variable will be set
even if the user doesn't specify anything, which we don't want to
report a warning on.
Thanks,
Alistair
>
> Thanks,
> Sundeep
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-05-30 22:32 ` Alistair Francis
@ 2017-06-26 16:01 ` sundeep subbaraya
2017-06-26 22:49 ` Alistair Francis
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-26 16:01 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
Hi Alistair,
On Wed, May 31, 2017 at 4:02 AM, Alistair Francis <alistair23@gmail.com>
wrote:
> On Sun, May 28, 2017 at 10:26 PM, sundeep subbaraya
> <sundeep.lkml@gmail.com> wrote:
> > Hi Alistair,
> >
> > On Sat, May 27, 2017 at 5:30 AM, Alistair Francis <alistair23@gmail.com>
> > wrote:
> >>
> >> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
> >> <sundeep.lkml@gmail.com> wrote:
> >> > Emulated Emcraft's Smartfusion2 System On Module starter
> >> > kit.
> >> >
> >> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> >> > ---
> >> > hw/arm/Makefile.objs | 1 +
> >> > hw/arm/msf2-som.c | 89
> >> > ++++++++++++++++++++++++++++++++++++++++++++++++++++
> >> > 2 files changed, 90 insertions(+)
> >> > create mode 100644 hw/arm/msf2-som.c
> >> >
> >> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> >> > index c828061..4b02093 100644
> >> > --- a/hw/arm/Makefile.objs
> >> > +++ b/hw/arm/Makefile.objs
> >> > @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o
> >> > stellaris.o
> >> > obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
> >> > obj-$(CONFIG_ACPI) += virt-acpi-build.o
> >> > obj-y += netduino2.o
> >> > +obj-y += msf2-som.o
> >>
> >> This should be obj-$(CONFIG_MSF2).
> >
> >
> > Ok will change it.
> >>
> >>
> >> > obj-y += sysbus-fdt.o
> >> >
> >> > obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
> >> > diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> >> > new file mode 100644
> >> > index 0000000..cd2b759
> >> > --- /dev/null
> >> > +++ b/hw/arm/msf2-som.c
> >> > @@ -0,0 +1,89 @@
> >> > +/*
> >> > + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
> >> > + *
> >> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> >> > + *
> >> > + * Permission is hereby granted, free of charge, to any person
> >> > obtaining a copy
> >> > + * of this software and associated documentation files (the
> >> > "Software"), to deal
> >> > + * in the Software without restriction, including without limitation
> >> > the rights
> >> > + * to use, copy, modify, merge, publish, distribute, sublicense,
> and/or
> >> > sell
> >> > + * copies of the Software, and to permit persons to whom the Software
> >> > is
> >> > + * furnished to do so, subject to the following conditions:
> >> > + *
> >> > + * The above copyright notice and this permission notice shall be
> >> > included in
> >> > + * all copies or substantial portions of the Software.
> >> > + *
> >> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> > EXPRESS OR
> >> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> > MERCHANTABILITY,
> >> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> >> > SHALL
> >> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR
> >> > OTHER
> >> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >> > ARISING FROM,
> >> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> >> > DEALINGS IN
> >> > + * THE SOFTWARE.
> >> > + */
> >> > +
> >> > +#include "qemu/osdep.h"
> >> > +#include "qapi/error.h"
> >> > +#include "hw/boards.h"
> >> > +#include "hw/arm/msf2-soc.h"
> >> > +#include "hw/arm/arm.h"
> >> > +#include "exec/address-spaces.h"
> >> > +
> >> > +#define DDR_BASE_ADDRESS 0xA0000000
> >> > +#define DDR_SIZE (64 * M_BYTE)
> >> > +
> >> > +static void emcraft_sf2_init(MachineState *machine)
> >> > +{
> >> > + DeviceState *dev;
> >> > + DeviceState *spi_flash;
> >> > + MSF2State *soc;
> >> > + DriveInfo *dinfo = drive_get_next(IF_MTD);
> >> > + qemu_irq cs_line;
> >> > + SSIBus *spi_bus;
> >> > + MemoryRegion *sysmem = get_system_memory();
> >> > + MemoryRegion *ddr = g_new(MemoryRegion, 1);
> >> > +
> >> > + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
> >> > + &error_fatal);
> >> > + vmstate_register_ram_global(ddr);
> >> > + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
> >>
> >> The user can use -m to specify the amount of RAM to create in the
> >> machine. Unless this board only ever includes 64MB of RAM you should
> >> use that option (you will need to sanity check it though). If the
> >> board only ever has 64MB it might be worth printing a warning to the
> >> user if they specify an something. Although there might be a default
> >> if they don't use -m, which makes it hard to print out a warning
> >> message.
> >
> >
> > This -m confuses me. Why is it necessary for an embedded board? RAM chip
> > is fixed and not extendable. Whereas normal PC may have extra RAM slots.
> > If another board has more RAM then we would instantiate another machine
> for
> > it
> > with that RAM size. Please explain. Maybe I am thinking in wrong
> direction.
>
> I agree with you, it doesn't make sense for every board. For some
> embedded boards it does make sense (ZynqMP can have a customisable
> amount of memory) but for most it doesn't make too much sense.
>
> In saying that it is a commonly used QEMU option, if you can find a
> way to report a warning if the user tries to specify a custom amount
> of memory I think that would be beneficial as QEMU will just ignore
> their input. I have a feeling that the ram_size variable will be set
> even if the user doesn't specify anything, which we don't want to
> report a warning on.
>
Do we need to report and exit if user specifies custom amount of memory?
Thanks,
Sundeep
>
> Thanks,
> Alistair
>
> >
> > Thanks,
> > Sundeep
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-06-26 16:01 ` sundeep subbaraya
@ 2017-06-26 22:49 ` Alistair Francis
2017-06-28 6:04 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Alistair Francis @ 2017-06-26 22:49 UTC (permalink / raw)
To: sundeep subbaraya
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
On Mon, Jun 26, 2017 at 9:01 AM, sundeep subbaraya
<sundeep.lkml@gmail.com> wrote:
> Hi Alistair,
>
> On Wed, May 31, 2017 at 4:02 AM, Alistair Francis <alistair23@gmail.com>
> wrote:
>>
>> On Sun, May 28, 2017 at 10:26 PM, sundeep subbaraya
>> <sundeep.lkml@gmail.com> wrote:
>> > Hi Alistair,
>> >
>> > On Sat, May 27, 2017 at 5:30 AM, Alistair Francis <alistair23@gmail.com>
>> > wrote:
>> >>
>> >> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
>> >> <sundeep.lkml@gmail.com> wrote:
>> >> > Emulated Emcraft's Smartfusion2 System On Module starter
>> >> > kit.
>> >> >
>> >> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> >> > ---
>> >> > hw/arm/Makefile.objs | 1 +
>> >> > hw/arm/msf2-som.c | 89
>> >> > ++++++++++++++++++++++++++++++++++++++++++++++++++++
>> >> > 2 files changed, 90 insertions(+)
>> >> > create mode 100644 hw/arm/msf2-som.c
>> >> >
>> >> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> >> > index c828061..4b02093 100644
>> >> > --- a/hw/arm/Makefile.objs
>> >> > +++ b/hw/arm/Makefile.objs
>> >> > @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o
>> >> > stellaris.o
>> >> > obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
>> >> > obj-$(CONFIG_ACPI) += virt-acpi-build.o
>> >> > obj-y += netduino2.o
>> >> > +obj-y += msf2-som.o
>> >>
>> >> This should be obj-$(CONFIG_MSF2).
>> >
>> >
>> > Ok will change it.
>> >>
>> >>
>> >> > obj-y += sysbus-fdt.o
>> >> >
>> >> > obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
>> >> > diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
>> >> > new file mode 100644
>> >> > index 0000000..cd2b759
>> >> > --- /dev/null
>> >> > +++ b/hw/arm/msf2-som.c
>> >> > @@ -0,0 +1,89 @@
>> >> > +/*
>> >> > + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
>> >> > + *
>> >> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> >> > + *
>> >> > + * Permission is hereby granted, free of charge, to any person
>> >> > obtaining a copy
>> >> > + * of this software and associated documentation files (the
>> >> > "Software"), to deal
>> >> > + * in the Software without restriction, including without limitation
>> >> > the rights
>> >> > + * to use, copy, modify, merge, publish, distribute, sublicense,
>> >> > and/or
>> >> > sell
>> >> > + * copies of the Software, and to permit persons to whom the
>> >> > Software
>> >> > is
>> >> > + * furnished to do so, subject to the following conditions:
>> >> > + *
>> >> > + * The above copyright notice and this permission notice shall be
>> >> > included in
>> >> > + * all copies or substantial portions of the Software.
>> >> > + *
>> >> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> >> > EXPRESS OR
>> >> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> >> > MERCHANTABILITY,
>> >> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> >> > SHALL
>> >> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
>> >> > OR
>> >> > OTHER
>> >> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> >> > ARISING FROM,
>> >> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> >> > DEALINGS IN
>> >> > + * THE SOFTWARE.
>> >> > + */
>> >> > +
>> >> > +#include "qemu/osdep.h"
>> >> > +#include "qapi/error.h"
>> >> > +#include "hw/boards.h"
>> >> > +#include "hw/arm/msf2-soc.h"
>> >> > +#include "hw/arm/arm.h"
>> >> > +#include "exec/address-spaces.h"
>> >> > +
>> >> > +#define DDR_BASE_ADDRESS 0xA0000000
>> >> > +#define DDR_SIZE (64 * M_BYTE)
>> >> > +
>> >> > +static void emcraft_sf2_init(MachineState *machine)
>> >> > +{
>> >> > + DeviceState *dev;
>> >> > + DeviceState *spi_flash;
>> >> > + MSF2State *soc;
>> >> > + DriveInfo *dinfo = drive_get_next(IF_MTD);
>> >> > + qemu_irq cs_line;
>> >> > + SSIBus *spi_bus;
>> >> > + MemoryRegion *sysmem = get_system_memory();
>> >> > + MemoryRegion *ddr = g_new(MemoryRegion, 1);
>> >> > +
>> >> > + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
>> >> > + &error_fatal);
>> >> > + vmstate_register_ram_global(ddr);
>> >> > + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
>> >>
>> >> The user can use -m to specify the amount of RAM to create in the
>> >> machine. Unless this board only ever includes 64MB of RAM you should
>> >> use that option (you will need to sanity check it though). If the
>> >> board only ever has 64MB it might be worth printing a warning to the
>> >> user if they specify an something. Although there might be a default
>> >> if they don't use -m, which makes it hard to print out a warning
>> >> message.
>> >
>> >
>> > This -m confuses me. Why is it necessary for an embedded board? RAM chip
>> > is fixed and not extendable. Whereas normal PC may have extra RAM slots.
>> > If another board has more RAM then we would instantiate another machine
>> > for
>> > it
>> > with that RAM size. Please explain. Maybe I am thinking in wrong
>> > direction.
>>
>> I agree with you, it doesn't make sense for every board. For some
>> embedded boards it does make sense (ZynqMP can have a customisable
>> amount of memory) but for most it doesn't make too much sense.
>>
>> In saying that it is a commonly used QEMU option, if you can find a
>> way to report a warning if the user tries to specify a custom amount
>> of memory I think that would be beneficial as QEMU will just ignore
>> their input. I have a feeling that the ram_size variable will be set
>> even if the user doesn't specify anything, which we don't want to
>> report a warning on.
>
>
> Do we need to report and exit if user specifies custom amount of memory?
I had a quick look at other ARM machines and it looks like a lot of
them use the ram_size variable from the machine to set the size of the
memory, but some have just hard coded values.
I'm not sure if there is an accepted "right" way to do this. If the
board only ever has 64MB of memory then it's probably ok to just hard
code it. Like you said, I don't think user have a high expectation of
adjusting the memory in embedded boards.
Thanks,
Alistair
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-06-26 22:49 ` Alistair Francis
@ 2017-06-28 6:04 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-28 6:04 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite, Philippe Mathieu-Daudé
Hi Alistair,
On Tue, Jun 27, 2017 at 4:19 AM, Alistair Francis <alistair23@gmail.com>
wrote:
> On Mon, Jun 26, 2017 at 9:01 AM, sundeep subbaraya
> <sundeep.lkml@gmail.com> wrote:
> > Hi Alistair,
> >
> > On Wed, May 31, 2017 at 4:02 AM, Alistair Francis <alistair23@gmail.com>
> > wrote:
> >>
> >> On Sun, May 28, 2017 at 10:26 PM, sundeep subbaraya
> >> <sundeep.lkml@gmail.com> wrote:
> >> > Hi Alistair,
> >> >
> >> > On Sat, May 27, 2017 at 5:30 AM, Alistair Francis <
> alistair23@gmail.com>
> >> > wrote:
> >> >>
> >> >> On Tue, May 16, 2017 at 8:38 AM, Subbaraya Sundeep
> >> >> <sundeep.lkml@gmail.com> wrote:
> >> >> > Emulated Emcraft's Smartfusion2 System On Module starter
> >> >> > kit.
> >> >> >
> >> >> > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> >> >> > ---
> >> >> > hw/arm/Makefile.objs | 1 +
> >> >> > hw/arm/msf2-som.c | 89
> >> >> > ++++++++++++++++++++++++++++++++++++++++++++++++++++
> >> >> > 2 files changed, 90 insertions(+)
> >> >> > create mode 100644 hw/arm/msf2-som.c
> >> >> >
> >> >> > diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> >> >> > index c828061..4b02093 100644
> >> >> > --- a/hw/arm/Makefile.objs
> >> >> > +++ b/hw/arm/Makefile.objs
> >> >> > @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o
> >> >> > stellaris.o
> >> >> > obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
> >> >> > obj-$(CONFIG_ACPI) += virt-acpi-build.o
> >> >> > obj-y += netduino2.o
> >> >> > +obj-y += msf2-som.o
> >> >>
> >> >> This should be obj-$(CONFIG_MSF2).
> >> >
> >> >
> >> > Ok will change it.
> >> >>
> >> >>
> >> >> > obj-y += sysbus-fdt.o
> >> >> >
> >> >> > obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
> >> >> > diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> >> >> > new file mode 100644
> >> >> > index 0000000..cd2b759
> >> >> > --- /dev/null
> >> >> > +++ b/hw/arm/msf2-som.c
> >> >> > @@ -0,0 +1,89 @@
> >> >> > +/*
> >> >> > + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
> >> >> > + *
> >> >> > + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> >> >> > + *
> >> >> > + * Permission is hereby granted, free of charge, to any person
> >> >> > obtaining a copy
> >> >> > + * of this software and associated documentation files (the
> >> >> > "Software"), to deal
> >> >> > + * in the Software without restriction, including without
> limitation
> >> >> > the rights
> >> >> > + * to use, copy, modify, merge, publish, distribute, sublicense,
> >> >> > and/or
> >> >> > sell
> >> >> > + * copies of the Software, and to permit persons to whom the
> >> >> > Software
> >> >> > is
> >> >> > + * furnished to do so, subject to the following conditions:
> >> >> > + *
> >> >> > + * The above copyright notice and this permission notice shall be
> >> >> > included in
> >> >> > + * all copies or substantial portions of the Software.
> >> >> > + *
> >> >> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> >> > EXPRESS OR
> >> >> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> >> > MERCHANTABILITY,
> >> >> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> >> >> > SHALL
> >> >> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> >> >> > OR
> >> >> > OTHER
> >> >> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> >> >> > ARISING FROM,
> >> >> > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> >> >> > DEALINGS IN
> >> >> > + * THE SOFTWARE.
> >> >> > + */
> >> >> > +
> >> >> > +#include "qemu/osdep.h"
> >> >> > +#include "qapi/error.h"
> >> >> > +#include "hw/boards.h"
> >> >> > +#include "hw/arm/msf2-soc.h"
> >> >> > +#include "hw/arm/arm.h"
> >> >> > +#include "exec/address-spaces.h"
> >> >> > +
> >> >> > +#define DDR_BASE_ADDRESS 0xA0000000
> >> >> > +#define DDR_SIZE (64 * M_BYTE)
> >> >> > +
> >> >> > +static void emcraft_sf2_init(MachineState *machine)
> >> >> > +{
> >> >> > + DeviceState *dev;
> >> >> > + DeviceState *spi_flash;
> >> >> > + MSF2State *soc;
> >> >> > + DriveInfo *dinfo = drive_get_next(IF_MTD);
> >> >> > + qemu_irq cs_line;
> >> >> > + SSIBus *spi_bus;
> >> >> > + MemoryRegion *sysmem = get_system_memory();
> >> >> > + MemoryRegion *ddr = g_new(MemoryRegion, 1);
> >> >> > +
> >> >> > + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
> >> >> > + &error_fatal);
> >> >> > + vmstate_register_ram_global(ddr);
> >> >> > + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
> >> >>
> >> >> The user can use -m to specify the amount of RAM to create in the
> >> >> machine. Unless this board only ever includes 64MB of RAM you should
> >> >> use that option (you will need to sanity check it though). If the
> >> >> board only ever has 64MB it might be worth printing a warning to the
> >> >> user if they specify an something. Although there might be a default
> >> >> if they don't use -m, which makes it hard to print out a warning
> >> >> message.
> >> >
> >> >
> >> > This -m confuses me. Why is it necessary for an embedded board? RAM
> chip
> >> > is fixed and not extendable. Whereas normal PC may have extra RAM
> slots.
> >> > If another board has more RAM then we would instantiate another
> machine
> >> > for
> >> > it
> >> > with that RAM size. Please explain. Maybe I am thinking in wrong
> >> > direction.
> >>
> >> I agree with you, it doesn't make sense for every board. For some
> >> embedded boards it does make sense (ZynqMP can have a customisable
> >> amount of memory) but for most it doesn't make too much sense.
> >>
> >> In saying that it is a commonly used QEMU option, if you can find a
> >> way to report a warning if the user tries to specify a custom amount
> >> of memory I think that would be beneficial as QEMU will just ignore
> >> their input. I have a feeling that the ram_size variable will be set
> >> even if the user doesn't specify anything, which we don't want to
> >> report a warning on.
> >
> >
> > Do we need to report and exit if user specifies custom amount of memory?
>
> I had a quick look at other ARM machines and it looks like a lot of
> them use the ram_size variable from the machine to set the size of the
> memory, but some have just hard coded values.
>
> I'm not sure if there is an accepted "right" way to do this. If the
> board only ever has 64MB of memory then it's probably ok to just hard
> code it. Like you said, I don't think user have a high expectation of
> adjusting the memory in embedded boards.
>
Thank you, I will drop the -m option.
Regards,
Sundeep
>
> Thanks,
> Alistair
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
2017-05-27 0:00 ` Alistair Francis
@ 2017-05-31 6:04 ` Philippe Mathieu-Daudé
2017-06-06 7:31 ` sundeep subbaraya
1 sibling, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-05-31 6:04 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
Hi Subbaraya,
On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
> Emulated Emcraft's Smartfusion2 System On Module starter
> kit.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> hw/arm/Makefile.objs | 1 +
> hw/arm/msf2-som.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 90 insertions(+)
> create mode 100644 hw/arm/msf2-som.c
>
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index c828061..4b02093 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
> obj-$(CONFIG_ACPI) += virt-acpi-build.o
> obj-y += netduino2.o
> +obj-y += msf2-som.o
> obj-y += sysbus-fdt.o
>
> obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
> diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
> new file mode 100644
> index 0000000..cd2b759
> --- /dev/null
> +++ b/hw/arm/msf2-som.c
> @@ -0,0 +1,89 @@
> +/*
> + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/boards.h"
> +#include "hw/arm/msf2-soc.h"
> +#include "hw/arm/arm.h"
> +#include "exec/address-spaces.h"
> +
> +#define DDR_BASE_ADDRESS 0xA0000000
> +#define DDR_SIZE (64 * M_BYTE)
> +
> +static void emcraft_sf2_init(MachineState *machine)
> +{
> + DeviceState *dev;
> + DeviceState *spi_flash;
> + MSF2State *soc;
> + DriveInfo *dinfo = drive_get_next(IF_MTD);
> + qemu_irq cs_line;
> + SSIBus *spi_bus;
> + MemoryRegion *sysmem = get_system_memory();
> + MemoryRegion *ddr = g_new(MemoryRegion, 1);
> +
> + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
> + &error_fatal);
> + vmstate_register_ram_global(ddr);
> + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
> +
> + dev = qdev_create(NULL, TYPE_MSF2_SOC);
> + qdev_prop_set_string(dev, "part-name", "M2S010");
> + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
> + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
> +
> + /*
> + * pclk0 and pclk1 are configurable in Libero.
> + * Emcraft's SoM kit comes with these settings by default.
> + */
> + qdev_prop_set_uint32(dev, "pclk0", 71 * 1000000);
> + qdev_prop_set_uint32(dev, "pclk1", 71 * 1000000);
> +
> + object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
> +
> + soc = MSF2_SOC(dev);
> +
> + /* Attach SPI flash to SPI0 controller */
> + spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
> + spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
> + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
> + if (dinfo) {
> + qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
> + &error_fatal);
> + }
> + qdev_init_nofail(spi_flash);
> + cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
> +
> + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
> + soc->envm_size);
> +}
> +
> +static void emcraft_sf2_machine_init(MachineClass *mc)
> +{
> + mc->desc = "SmartFusion2 SOM kit from Emcraft";
> + mc->init = emcraft_sf2_init;
> +}
> +
> +DEFINE_MACHINE("smartfusion2-som", emcraft_sf2_machine_init)
Here I still disagree with the machine name, what do you think about
"emcraft-sf2" or "emcraft-m2s[-fg484-som]" as described by Emcraft in
their website (but shorter is easier to type)?
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-05-31 6:04 ` Philippe Mathieu-Daudé
@ 2017-06-06 7:31 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-06 7:31 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Wed, May 31, 2017 at 11:34 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Subbaraya,
>
>
> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>
>> Emulated Emcraft's Smartfusion2 System On Module starter
>> kit.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> ---
>> hw/arm/Makefile.objs | 1 +
>> hw/arm/msf2-som.c | 89 ++++++++++++++++++++++++++++++
>> ++++++++++++++++++++++
>> 2 files changed, 90 insertions(+)
>> create mode 100644 hw/arm/msf2-som.c
>>
>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> index c828061..4b02093 100644
>> --- a/hw/arm/Makefile.objs
>> +++ b/hw/arm/Makefile.objs
>> @@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
>> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
>> obj-$(CONFIG_ACPI) += virt-acpi-build.o
>> obj-y += netduino2.o
>> +obj-y += msf2-som.o
>> obj-y += sysbus-fdt.o
>>
>> obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
>> diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
>> new file mode 100644
>> index 0000000..cd2b759
>> --- /dev/null
>> +++ b/hw/arm/msf2-som.c
>> @@ -0,0 +1,89 @@
>> +/*
>> + * SmartFusion2 SOM starter kit(from Emcraft) emulation.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining
>> a copy
>> + * of this software and associated documentation files (the "Software"),
>> to deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or
>> sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be
>> included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
>> SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "hw/boards.h"
>> +#include "hw/arm/msf2-soc.h"
>> +#include "hw/arm/arm.h"
>> +#include "exec/address-spaces.h"
>> +
>> +#define DDR_BASE_ADDRESS 0xA0000000
>> +#define DDR_SIZE (64 * M_BYTE)
>> +
>> +static void emcraft_sf2_init(MachineState *machine)
>> +{
>> + DeviceState *dev;
>> + DeviceState *spi_flash;
>> + MSF2State *soc;
>> + DriveInfo *dinfo = drive_get_next(IF_MTD);
>> + qemu_irq cs_line;
>> + SSIBus *spi_bus;
>> + MemoryRegion *sysmem = get_system_memory();
>> + MemoryRegion *ddr = g_new(MemoryRegion, 1);
>> +
>> + memory_region_init_ram(ddr, NULL, "ddr-ram", DDR_SIZE,
>> + &error_fatal);
>> + vmstate_register_ram_global(ddr);
>> + memory_region_add_subregion(sysmem, DDR_BASE_ADDRESS, ddr);
>> +
>> + dev = qdev_create(NULL, TYPE_MSF2_SOC);
>> + qdev_prop_set_string(dev, "part-name", "M2S010");
>> + qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE);
>> + qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE);
>> +
>> + /*
>> + * pclk0 and pclk1 are configurable in Libero.
>> + * Emcraft's SoM kit comes with these settings by default.
>> + */
>> + qdev_prop_set_uint32(dev, "pclk0", 71 * 1000000);
>> + qdev_prop_set_uint32(dev, "pclk1", 71 * 1000000);
>> +
>> + object_property_set_bool(OBJECT(dev), true, "realized",
>> &error_fatal);
>> +
>> + soc = MSF2_SOC(dev);
>> +
>> + /* Attach SPI flash to SPI0 controller */
>> + spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
>> + spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
>> + qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
>> + if (dinfo) {
>> + qdev_prop_set_drive(spi_flash, "drive",
>> blk_by_legacy_dinfo(dinfo),
>> + &error_fatal);
>> + }
>> + qdev_init_nofail(spi_flash);
>> + cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
>> + sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
>> +
>> + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
>> + soc->envm_size);
>> +}
>> +
>> +static void emcraft_sf2_machine_init(MachineClass *mc)
>> +{
>> + mc->desc = "SmartFusion2 SOM kit from Emcraft";
>> + mc->init = emcraft_sf2_init;
>> +}
>> +
>> +DEFINE_MACHINE("smartfusion2-som", emcraft_sf2_machine_init)
>>
>
> Here I still disagree with the machine name, what do you think about
> "emcraft-sf2" or "emcraft-m2s[-fg484-som]" as described by Emcraft in their
> website (but shorter is easier to type)?
>
I missed this. I will use emcraft-sf2 for machine name.
Thanks,
Sundeep
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-05-16 15:38 [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (4 preceding siblings ...)
2017-05-16 15:38 ` [Qemu-devel] [Qemu devel v5 PATCH 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
@ 2017-05-17 4:27 ` Philippe Mathieu-Daudé
2017-05-17 9:39 ` sundeep subbaraya
5 siblings, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-05-17 4:27 UTC (permalink / raw)
To: Subbaraya Sundeep, qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23
Hi Sundeep,
This patchset is way cleaner!
I had a fast look and I like it, I'll try to make some time soon to
review details and test it.
Is your work interested on U-Boot or more focused in Linux kernel?
If you compile QEMU with libfdt support you can use the -dtb option to
pass the blob to the kernel directly, bypassing the bootloader.
If you need a bootloader you may give a look at coreboot which supports
dts well, see how Vladimir Serbinenko used Linux's dt to boot a QEMU
Versatile Express board:
https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-February/040899.html
Regards,
Phil.
On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
> Hi Qemu-devel,
>
> I am trying to add Smartfusion2 SoC.
> SoC is from Microsemi and System on Module(SOM)
> board is from Emcraft systems. Smartfusion2 has hardened
> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
> At the moment only system timer, sysreg and SPI
> controller are modelled.
>
> Testing:
> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \
> -kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw
>
> Binaries u-boot.bin and spi.bin are at:
> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>
> U-boot is from Emcraft with modified
> - SPI driver not to use PDMA.
> - ugly hack to pass dtb to kernel in r1.
> @
> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>
> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
> driver added by myself @
> https://github.com/Subbaraya-Sundeep/linux.git
>
> v5
> As per Philippe comments:
> Added abort in Sysreg if guest tries to remap memory
> other than default mapping.
> Use of CONFIG_MSF2 in Makefile for soc.c
> Fixed incorrect logic in timer model.
> Renamed msf2-timer.c -> mss-timer.c
> msf2-spi.c -> mss-spi.c also type names
> Renamed function msf2_init->emcraft_sf2_init in msf2-som.c
> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
> properties to soc.
> Pass soc part-name,memory size and clock rate properties from som.
> v4:
> Fixed build failure by using PRIx macros.
> v3:
> Added SoC file and board file as per Alistair comments.
> v2:
> Added SPI controller so that u-boot loads kernel from spi flash.
> v1:
> Initial patch set with timer and sysreg
>
> Thanks,
> Sundeep
>
> Subbaraya Sundeep (5):
> msf2: Add Smartfusion2 System timer
> msf2: Microsemi Smartfusion2 System Register block.
> msf2: Add Smartfusion2 SPI controller
> msf2: Add Smartfusion2 SoC.
> msf2: Add Emcraft's Smartfusion2 SOM kit.
>
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 2 +
> hw/arm/msf2-soc.c | 201 +++++++++++++++++++++
> hw/arm/msf2-som.c | 89 ++++++++++
> hw/misc/Makefile.objs | 1 +
> hw/misc/msf2-sysreg.c | 161 +++++++++++++++++
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/mss-spi.c | 378 ++++++++++++++++++++++++++++++++++++++++
> hw/timer/Makefile.objs | 1 +
> hw/timer/mss-timer.c | 249 ++++++++++++++++++++++++++
> include/hw/arm/msf2-soc.h | 69 ++++++++
> include/hw/misc/msf2-sysreg.h | 80 +++++++++
> include/hw/ssi/mss-spi.h | 104 +++++++++++
> include/hw/timer/mss-timer.h | 80 +++++++++
> 14 files changed, 1417 insertions(+)
> create mode 100644 hw/arm/msf2-soc.c
> create mode 100644 hw/arm/msf2-som.c
> create mode 100644 hw/misc/msf2-sysreg.c
> create mode 100644 hw/ssi/mss-spi.c
> create mode 100644 hw/timer/mss-timer.c
> create mode 100644 include/hw/arm/msf2-soc.h
> create mode 100644 include/hw/misc/msf2-sysreg.h
> create mode 100644 include/hw/ssi/mss-spi.h
> create mode 100644 include/hw/timer/mss-timer.h
>
^ permalink raw reply [flat|nested] 35+ messages in thread* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-05-17 4:27 ` [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC Philippe Mathieu-Daudé
@ 2017-05-17 9:39 ` sundeep subbaraya
2017-05-29 5:28 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-05-17 9:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Wed, May 17, 2017 at 9:57 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Sundeep,
>
> This patchset is way cleaner!
> I had a fast look and I like it, I'll try to make some time soon to review
> details and test it.
Thank you
>
> Is your work interested on U-Boot or more focused in Linux kernel?
>
I am interested more in kernel. I had to look into u-boot for first time
for Qemu only.
I worked only on FPGAs(load kernel with debugger) till now so never got a
chance to look into u-boot.
>
> If you compile QEMU with libfdt support you can use the -dtb option to
> pass the blob to the kernel directly, bypassing the bootloader.
>
> Yeah for armv7m I could not find any thing like that in tree.
> If you need a bootloader you may give a look at coreboot which supports
> dts well, see how Vladimir Serbinenko used Linux's dt to boot a QEMU
> Versatile Express board:
> https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-
> February/040899.html
>
> Cool. I will look into it.
Thanks,
Sundeep
> Regards,
>
> Phil.
>
>
> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>
>> Hi Qemu-devel,
>>
>> I am trying to add Smartfusion2 SoC.
>> SoC is from Microsemi and System on Module(SOM)
>> board is from Emcraft systems. Smartfusion2 has hardened
>> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
>> At the moment only system timer, sysreg and SPI
>> controller are modelled.
>>
>> Testing:
>> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \
>> -kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw
>>
>> Binaries u-boot.bin and spi.bin are at:
>> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>>
>> U-boot is from Emcraft with modified
>> - SPI driver not to use PDMA.
>> - ugly hack to pass dtb to kernel in r1.
>> @
>> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>>
>> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
>> driver added by myself @
>> https://github.com/Subbaraya-Sundeep/linux.git
>>
>> v5
>> As per Philippe comments:
>> Added abort in Sysreg if guest tries to remap memory
>> other than default mapping.
>> Use of CONFIG_MSF2 in Makefile for soc.c
>> Fixed incorrect logic in timer model.
>> Renamed msf2-timer.c -> mss-timer.c
>> msf2-spi.c -> mss-spi.c also type names
>> Renamed function msf2_init->emcraft_sf2_init in msf2-som.c
>> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
>> properties to soc.
>> Pass soc part-name,memory size and clock rate properties from som.
>> v4:
>> Fixed build failure by using PRIx macros.
>> v3:
>> Added SoC file and board file as per Alistair comments.
>> v2:
>> Added SPI controller so that u-boot loads kernel from spi flash.
>> v1:
>> Initial patch set with timer and sysreg
>>
>> Thanks,
>> Sundeep
>>
>> Subbaraya Sundeep (5):
>> msf2: Add Smartfusion2 System timer
>> msf2: Microsemi Smartfusion2 System Register block.
>> msf2: Add Smartfusion2 SPI controller
>> msf2: Add Smartfusion2 SoC.
>> msf2: Add Emcraft's Smartfusion2 SOM kit.
>>
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/Makefile.objs | 2 +
>> hw/arm/msf2-soc.c | 201 +++++++++++++++++++++
>> hw/arm/msf2-som.c | 89 ++++++++++
>> hw/misc/Makefile.objs | 1 +
>> hw/misc/msf2-sysreg.c | 161 +++++++++++++++++
>> hw/ssi/Makefile.objs | 1 +
>> hw/ssi/mss-spi.c | 378 ++++++++++++++++++++++++++++++
>> ++++++++++
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/mss-timer.c | 249 ++++++++++++++++++++++++++
>> include/hw/arm/msf2-soc.h | 69 ++++++++
>> include/hw/misc/msf2-sysreg.h | 80 +++++++++
>> include/hw/ssi/mss-spi.h | 104 +++++++++++
>> include/hw/timer/mss-timer.h | 80 +++++++++
>> 14 files changed, 1417 insertions(+)
>> create mode 100644 hw/arm/msf2-soc.c
>> create mode 100644 hw/arm/msf2-som.c
>> create mode 100644 hw/misc/msf2-sysreg.c
>> create mode 100644 hw/ssi/mss-spi.c
>> create mode 100644 hw/timer/mss-timer.c
>> create mode 100644 include/hw/arm/msf2-soc.h
>> create mode 100644 include/hw/misc/msf2-sysreg.h
>> create mode 100644 include/hw/ssi/mss-spi.h
>> create mode 100644 include/hw/timer/mss-timer.h
>>
>>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-05-17 9:39 ` sundeep subbaraya
@ 2017-05-29 5:28 ` sundeep subbaraya
2017-05-31 5:36 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-05-29 5:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
Any update on this? I will wait for your comments too
and send next iteration fixing Alistair comments.
Thanks,
Sundeep
On Wed, May 17, 2017 at 3:09 PM, sundeep subbaraya <sundeep.lkml@gmail.com>
wrote:
> Hi Philippe,
>
> On Wed, May 17, 2017 at 9:57 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
> wrote:
>
>> Hi Sundeep,
>>
>> This patchset is way cleaner!
>> I had a fast look and I like it, I'll try to make some time soon to
>> review details and test it.
>
>
> Thank you
>
>>
>
>
>> Is your work interested on U-Boot or more focused in Linux kernel?
>>
>
> I am interested more in kernel. I had to look into u-boot for first time
> for Qemu only.
> I worked only on FPGAs(load kernel with debugger) till now so never got a
> chance to look into u-boot.
>
>>
>> If you compile QEMU with libfdt support you can use the -dtb option to
>> pass the blob to the kernel directly, bypassing the bootloader.
>>
>> Yeah for armv7m I could not find any thing like that in tree.
>
>
>> If you need a bootloader you may give a look at coreboot which supports
>> dts well, see how Vladimir Serbinenko used Linux's dt to boot a QEMU
>> Versatile Express board:
>> https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-Feb
>> ruary/040899.html
>>
>> Cool. I will look into it.
>
> Thanks,
> Sundeep
>
>
>> Regards,
>>
>> Phil.
>>
>>
>> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>>
>>> Hi Qemu-devel,
>>>
>>> I am trying to add Smartfusion2 SoC.
>>> SoC is from Microsemi and System on Module(SOM)
>>> board is from Emcraft systems. Smartfusion2 has hardened
>>> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
>>> At the moment only system timer, sysreg and SPI
>>> controller are modelled.
>>>
>>> Testing:
>>> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \
>>> -kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw
>>>
>>> Binaries u-boot.bin and spi.bin are at:
>>> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>>>
>>> U-boot is from Emcraft with modified
>>> - SPI driver not to use PDMA.
>>> - ugly hack to pass dtb to kernel in r1.
>>> @
>>> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>>>
>>> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
>>> driver added by myself @
>>> https://github.com/Subbaraya-Sundeep/linux.git
>>>
>>> v5
>>> As per Philippe comments:
>>> Added abort in Sysreg if guest tries to remap memory
>>> other than default mapping.
>>> Use of CONFIG_MSF2 in Makefile for soc.c
>>> Fixed incorrect logic in timer model.
>>> Renamed msf2-timer.c -> mss-timer.c
>>> msf2-spi.c -> mss-spi.c also type names
>>> Renamed function msf2_init->emcraft_sf2_init in msf2-som.c
>>> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
>>> properties to soc.
>>> Pass soc part-name,memory size and clock rate properties from
>>> som.
>>> v4:
>>> Fixed build failure by using PRIx macros.
>>> v3:
>>> Added SoC file and board file as per Alistair comments.
>>> v2:
>>> Added SPI controller so that u-boot loads kernel from spi flash.
>>> v1:
>>> Initial patch set with timer and sysreg
>>>
>>> Thanks,
>>> Sundeep
>>>
>>> Subbaraya Sundeep (5):
>>> msf2: Add Smartfusion2 System timer
>>> msf2: Microsemi Smartfusion2 System Register block.
>>> msf2: Add Smartfusion2 SPI controller
>>> msf2: Add Smartfusion2 SoC.
>>> msf2: Add Emcraft's Smartfusion2 SOM kit.
>>>
>>> default-configs/arm-softmmu.mak | 1 +
>>> hw/arm/Makefile.objs | 2 +
>>> hw/arm/msf2-soc.c | 201 +++++++++++++++++++++
>>> hw/arm/msf2-som.c | 89 ++++++++++
>>> hw/misc/Makefile.objs | 1 +
>>> hw/misc/msf2-sysreg.c | 161 +++++++++++++++++
>>> hw/ssi/Makefile.objs | 1 +
>>> hw/ssi/mss-spi.c | 378 ++++++++++++++++++++++++++++++
>>> ++++++++++
>>> hw/timer/Makefile.objs | 1 +
>>> hw/timer/mss-timer.c | 249 ++++++++++++++++++++++++++
>>> include/hw/arm/msf2-soc.h | 69 ++++++++
>>> include/hw/misc/msf2-sysreg.h | 80 +++++++++
>>> include/hw/ssi/mss-spi.h | 104 +++++++++++
>>> include/hw/timer/mss-timer.h | 80 +++++++++
>>> 14 files changed, 1417 insertions(+)
>>> create mode 100644 hw/arm/msf2-soc.c
>>> create mode 100644 hw/arm/msf2-som.c
>>> create mode 100644 hw/misc/msf2-sysreg.c
>>> create mode 100644 hw/ssi/mss-spi.c
>>> create mode 100644 hw/timer/mss-timer.c
>>> create mode 100644 include/hw/arm/msf2-soc.h
>>> create mode 100644 include/hw/misc/msf2-sysreg.h
>>> create mode 100644 include/hw/ssi/mss-spi.h
>>> create mode 100644 include/hw/timer/mss-timer.h
>>>
>>>
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-05-29 5:28 ` sundeep subbaraya
@ 2017-05-31 5:36 ` Philippe Mathieu-Daudé
2017-06-09 7:21 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-05-31 5:36 UTC (permalink / raw)
To: sundeep subbaraya
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Sundeep,
On 05/29/2017 02:28 AM, sundeep subbaraya wrote:
> Hi Philippe,
>
> Any update on this? I will wait for your comments too
> and send next iteration fixing Alistair comments.
Sorry I'm supposed to be in holidays ;)
>
> Thanks,
> Sundeep
>
> On Wed, May 17, 2017 at 3:09 PM, sundeep subbaraya
> <sundeep.lkml@gmail.com <mailto:sundeep.lkml@gmail.com>> wrote:
>
> Hi Philippe,
>
> On Wed, May 17, 2017 at 9:57 AM, Philippe Mathieu-Daudé
> <f4bug@amsat.org <mailto:f4bug@amsat.org>> wrote:
>
> Hi Sundeep,
>
> This patchset is way cleaner!
> I had a fast look and I like it, I'll try to make some time soon
> to review details and test it.
>
>
> Thank you
>
>
>
>
> Is your work interested on U-Boot or more focused in Linux kernel?
>
>
> I am interested more in kernel. I had to look into u-boot for first
> time for Qemu only.
> I worked only on FPGAs(load kernel with debugger) till now so never
> got a chance to look into u-boot.
>
>
> If you compile QEMU with libfdt support you can use the -dtb
> option to pass the blob to the kernel directly, bypassing the
> bootloader.
>
> Yeah for armv7m I could not find any thing like that in tree.
>
>
> If you need a bootloader you may give a look at coreboot which
> supports dts well, see how Vladimir Serbinenko used Linux's dt
> to boot a QEMU Versatile Express board:
> https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-February/040899.html
> <https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-February/040899.html>
>
> Cool. I will look into it.
>
> Thanks,
> Sundeep
>
>
> Regards,
>
> Phil.
>
>
> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>
> Hi Qemu-devel,
>
> I am trying to add Smartfusion2 SoC.
> SoC is from Microsemi and System on Module(SOM)
> board is from Emcraft systems. Smartfusion2 has hardened
> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
> At the moment only system timer, sysreg and SPI
> controller are modelled.
>
> Testing:
> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial
> mon:stdio \
> -kernel u-boot.bin -display none -drive
> file=spi.bin,if=mtd,format=raw
I'm not sure the timer is working correctly, U-Boot loops with this pattern:
msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
msf2_sysreg_write: addr: 0x00000048 data: 0x00000000
msf2_sysreg_read: addr: 0x00000048 data: 0x00000000
msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
>
> Binaries u-boot.bin and spi.bin are at:
you can compress spi.bin!
can you share u-boot.elf with debug symbols too?
Regards,
Phil.
> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
> <https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git>
>
> U-boot is from Emcraft with modified
> - SPI driver not to use PDMA.
> - ugly hack to pass dtb to kernel in r1.
> @
> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
> <https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git>
>
> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
> driver added by myself @
> https://github.com/Subbaraya-Sundeep/linux.git
> <https://github.com/Subbaraya-Sundeep/linux.git>
>
> v5
> As per Philippe comments:
> Added abort in Sysreg if guest tries to remap memory
> other than default mapping.
> Use of CONFIG_MSF2 in Makefile for soc.c
> Fixed incorrect logic in timer model.
> Renamed msf2-timer.c -> mss-timer.c
> msf2-spi.c -> mss-spi.c also type names
> Renamed function msf2_init->emcraft_sf2_init in
> msf2-som.c
> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
> properties to soc.
> Pass soc part-name,memory size and clock rate
> properties from som.
> v4:
> Fixed build failure by using PRIx macros.
> v3:
> Added SoC file and board file as per Alistair comments.
> v2:
> Added SPI controller so that u-boot loads kernel from
> spi flash.
> v1:
> Initial patch set with timer and sysreg
>
> Thanks,
> Sundeep
>
> Subbaraya Sundeep (5):
> msf2: Add Smartfusion2 System timer
> msf2: Microsemi Smartfusion2 System Register block.
> msf2: Add Smartfusion2 SPI controller
> msf2: Add Smartfusion2 SoC.
> msf2: Add Emcraft's Smartfusion2 SOM kit.
>
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 2 +
> hw/arm/msf2-soc.c | 201 +++++++++++++++++++++
> hw/arm/msf2-som.c | 89 ++++++++++
> hw/misc/Makefile.objs | 1 +
> hw/misc/msf2-sysreg.c | 161 +++++++++++++++++
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/mss-spi.c | 378
> ++++++++++++++++++++++++++++++++++++++++
> hw/timer/Makefile.objs | 1 +
> hw/timer/mss-timer.c | 249
> ++++++++++++++++++++++++++
> include/hw/arm/msf2-soc.h | 69 ++++++++
> include/hw/misc/msf2-sysreg.h | 80 +++++++++
> include/hw/ssi/mss-spi.h | 104 +++++++++++
> include/hw/timer/mss-timer.h | 80 +++++++++
> 14 files changed, 1417 insertions(+)
> create mode 100644 hw/arm/msf2-soc.c
> create mode 100644 hw/arm/msf2-som.c
> create mode 100644 hw/misc/msf2-sysreg.c
> create mode 100644 hw/ssi/mss-spi.c
> create mode 100644 hw/timer/mss-timer.c
> create mode 100644 include/hw/arm/msf2-soc.h
> create mode 100644 include/hw/misc/msf2-sysreg.h
> create mode 100644 include/hw/ssi/mss-spi.h
> create mode 100644 include/hw/timer/mss-timer.h
>
>
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-05-31 5:36 ` Philippe Mathieu-Daudé
@ 2017-06-09 7:21 ` sundeep subbaraya
2017-06-26 16:11 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-09 7:21 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Wed, May 31, 2017 at 11:06 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
wrote:
> Hi Sundeep,
>
> On 05/29/2017 02:28 AM, sundeep subbaraya wrote:
>
>> Hi Philippe,
>>
>> Any update on this? I will wait for your comments too
>> and send next iteration fixing Alistair comments.
>>
>
> Sorry I'm supposed to be in holidays ;)
>
Ohh sorry currently am in vacation :)
>
>
>> Thanks,
>> Sundeep
>>
>> On Wed, May 17, 2017 at 3:09 PM, sundeep subbaraya
>> <sundeep.lkml@gmail.com <mailto:sundeep.lkml@gmail.com>> wrote:
>>
>> Hi Philippe,
>>
>> On Wed, May 17, 2017 at 9:57 AM, Philippe Mathieu-Daudé
>> <f4bug@amsat.org <mailto:f4bug@amsat.org>> wrote:
>>
>> Hi Sundeep,
>>
>> This patchset is way cleaner!
>> I had a fast look and I like it, I'll try to make some time soon
>> to review details and test it.
>>
>>
>> Thank you
>>
>>
>>
>>
>> Is your work interested on U-Boot or more focused in Linux kernel?
>>
>>
>> I am interested more in kernel. I had to look into u-boot for first
>> time for Qemu only.
>> I worked only on FPGAs(load kernel with debugger) till now so never
>> got a chance to look into u-boot.
>>
>>
>> If you compile QEMU with libfdt support you can use the -dtb
>> option to pass the blob to the kernel directly, bypassing the
>> bootloader.
>>
>> Yeah for armv7m I could not find any thing like that in tree.
>>
>>
>> If you need a bootloader you may give a look at coreboot which
>> supports dts well, see how Vladimir Serbinenko used Linux's dt
>> to boot a QEMU Versatile Express board:
>> https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-
>> February/040899.html
>> <https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-
>> February/040899.html>
>>
>> Cool. I will look into it.
>>
>> Thanks,
>> Sundeep
>>
>>
>> Regards,
>>
>> Phil.
>>
>>
>> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>>
>> Hi Qemu-devel,
>>
>> I am trying to add Smartfusion2 SoC.
>> SoC is from Microsemi and System on Module(SOM)
>> board is from Emcraft systems. Smartfusion2 has hardened
>> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
>> At the moment only system timer, sysreg and SPI
>> controller are modelled.
>>
>> Testing:
>> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial
>> mon:stdio \
>> -kernel u-boot.bin -display none -drive
>> file=spi.bin,if=mtd,format=raw
>>
>
> I'm not sure the timer is working correctly, U-Boot loops with this
> pattern:
>
> msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
> msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
> msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
> msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
> msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
> msf2_sysreg_write: addr: 0x00000048 data: 0x00000000
> msf2_sysreg_read: addr: 0x00000048 data: 0x00000000
> msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
> msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
> msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
>
>
>> Binaries u-boot.bin and spi.bin are at:
>>
>
> you can compress spi.bin!
>
> can you share u-boot.elf with debug symbols too?
>
Sure. I have tested binaries before pushing. Did you compile the u-boot
again?
Please wait for a few days I will check and provide once am back.
Thanks,
Sundeep
>
> Regards,
>
> Phil.
>
> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>>
>> <https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git>
>>
>> U-boot is from Emcraft with modified
>> - SPI driver not to use PDMA.
>> - ugly hack to pass dtb to kernel in r1.
>> @
>> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>> <https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git>
>>
>> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
>> driver added by myself @
>> https://github.com/Subbaraya-Sundeep/linux.git
>> <https://github.com/Subbaraya-Sundeep/linux.git>
>>
>> v5
>> As per Philippe comments:
>> Added abort in Sysreg if guest tries to remap memory
>> other than default mapping.
>> Use of CONFIG_MSF2 in Makefile for soc.c
>> Fixed incorrect logic in timer model.
>> Renamed msf2-timer.c -> mss-timer.c
>> msf2-spi.c -> mss-spi.c also type names
>> Renamed function msf2_init->emcraft_sf2_init in
>> msf2-som.c
>> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
>> properties to soc.
>> Pass soc part-name,memory size and clock rate
>> properties from som.
>> v4:
>> Fixed build failure by using PRIx macros.
>> v3:
>> Added SoC file and board file as per Alistair comments.
>> v2:
>> Added SPI controller so that u-boot loads kernel from
>> spi flash.
>> v1:
>> Initial patch set with timer and sysreg
>>
>> Thanks,
>> Sundeep
>>
>> Subbaraya Sundeep (5):
>> msf2: Add Smartfusion2 System timer
>> msf2: Microsemi Smartfusion2 System Register block.
>> msf2: Add Smartfusion2 SPI controller
>> msf2: Add Smartfusion2 SoC.
>> msf2: Add Emcraft's Smartfusion2 SOM kit.
>>
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/Makefile.objs | 2 +
>> hw/arm/msf2-soc.c | 201 +++++++++++++++++++++
>> hw/arm/msf2-som.c | 89 ++++++++++
>> hw/misc/Makefile.objs | 1 +
>> hw/misc/msf2-sysreg.c | 161 +++++++++++++++++
>> hw/ssi/Makefile.objs | 1 +
>> hw/ssi/mss-spi.c | 378
>> ++++++++++++++++++++++++++++++++++++++++
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/mss-timer.c | 249
>> ++++++++++++++++++++++++++
>> include/hw/arm/msf2-soc.h | 69 ++++++++
>> include/hw/misc/msf2-sysreg.h | 80 +++++++++
>> include/hw/ssi/mss-spi.h | 104 +++++++++++
>> include/hw/timer/mss-timer.h | 80 +++++++++
>> 14 files changed, 1417 insertions(+)
>> create mode 100644 hw/arm/msf2-soc.c
>> create mode 100644 hw/arm/msf2-som.c
>> create mode 100644 hw/misc/msf2-sysreg.c
>> create mode 100644 hw/ssi/mss-spi.c
>> create mode 100644 hw/timer/mss-timer.c
>> create mode 100644 include/hw/arm/msf2-soc.h
>> create mode 100644 include/hw/misc/msf2-sysreg.h
>> create mode 100644 include/hw/ssi/mss-spi.h
>> create mode 100644 include/hw/timer/mss-timer.h
>>
>>
>>
>>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-06-09 7:21 ` sundeep subbaraya
@ 2017-06-26 16:11 ` sundeep subbaraya
2017-07-02 17:39 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-06-26 16:11 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Fri, Jun 9, 2017 at 12:51 PM, sundeep subbaraya <sundeep.lkml@gmail.com>
wrote:
> Hi Philippe,
>
> On Wed, May 31, 2017 at 11:06 AM, Philippe Mathieu-Daudé <f4bug@amsat.org>
> wrote:
>
>> Hi Sundeep,
>>
>> On 05/29/2017 02:28 AM, sundeep subbaraya wrote:
>>
>>> Hi Philippe,
>>>
>>> Any update on this? I will wait for your comments too
>>> and send next iteration fixing Alistair comments.
>>>
>>
>> Sorry I'm supposed to be in holidays ;)
>>
>
> Ohh sorry currently am in vacation :)
>
>>
>>
>>> Thanks,
>>> Sundeep
>>>
>>> On Wed, May 17, 2017 at 3:09 PM, sundeep subbaraya
>>> <sundeep.lkml@gmail.com <mailto:sundeep.lkml@gmail.com>> wrote:
>>>
>>> Hi Philippe,
>>>
>>> On Wed, May 17, 2017 at 9:57 AM, Philippe Mathieu-Daudé
>>> <f4bug@amsat.org <mailto:f4bug@amsat.org>> wrote:
>>>
>>> Hi Sundeep,
>>>
>>> This patchset is way cleaner!
>>> I had a fast look and I like it, I'll try to make some time soon
>>> to review details and test it.
>>>
>>>
>>> Thank you
>>>
>>>
>>>
>>>
>>> Is your work interested on U-Boot or more focused in Linux
>>> kernel?
>>>
>>>
>>> I am interested more in kernel. I had to look into u-boot for first
>>> time for Qemu only.
>>> I worked only on FPGAs(load kernel with debugger) till now so never
>>> got a chance to look into u-boot.
>>>
>>>
>>> If you compile QEMU with libfdt support you can use the -dtb
>>> option to pass the blob to the kernel directly, bypassing the
>>> bootloader.
>>>
>>> Yeah for armv7m I could not find any thing like that in tree.
>>>
>>>
>>> If you need a bootloader you may give a look at coreboot which
>>> supports dts well, see how Vladimir Serbinenko used Linux's dt
>>> to boot a QEMU Versatile Express board:
>>> https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-Feb
>>> ruary/040899.html
>>> <https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-Fe
>>> bruary/040899.html>
>>>
>>> Cool. I will look into it.
>>>
>>> Thanks,
>>> Sundeep
>>>
>>>
>>> Regards,
>>>
>>> Phil.
>>>
>>>
>>> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>>>
>>> Hi Qemu-devel,
>>>
>>> I am trying to add Smartfusion2 SoC.
>>> SoC is from Microsemi and System on Module(SOM)
>>> board is from Emcraft systems. Smartfusion2 has hardened
>>> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
>>> At the moment only system timer, sysreg and SPI
>>> controller are modelled.
>>>
>>> Testing:
>>> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial
>>> mon:stdio \
>>> -kernel u-boot.bin -display none -drive
>>> file=spi.bin,if=mtd,format=raw
>>>
>>
>> I'm not sure the timer is working correctly, U-Boot loops with this
>> pattern:
>>
>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000000
>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000000
>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
>>
>> I checked the images and Linux is booting. But as you mentioned I changed
u-boot
for boot delay and have seen this issue. Actually it is taking too long for
a second.
Smartfusion2 timer is working fine(Linux) whereas u-boot is using Systick
for auto-boot
timer. I did not understand quite correctly about ARM Systick in Qemu. How
do we
specify frequency of the Systick timer? How Systick is configured to use
CPU frequency
since qemu cpu speed is not constant? How frequency has to be specified for
using external clock as Systick input?
Please help me understand this.
Thanks,
Sundeep
>
>>> Binaries u-boot.bin and spi.bin are at:
>>>
>>
>> you can compress spi.bin!
>>
>> can you share u-boot.elf with debug symbols too?
>>
>
> Sure. I have tested binaries before pushing. Did you compile the u-boot
> again?
> Please wait for a few days I will check and provide once am back.
>
> Thanks,
> Sundeep
>
>>
>> Regards,
>>
>> Phil.
>>
>> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>>>
>>> <https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>>> >
>>>
>>> U-boot is from Emcraft with modified
>>> - SPI driver not to use PDMA.
>>> - ugly hack to pass dtb to kernel in r1.
>>> @
>>> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>>> <https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git>
>>>
>>> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
>>> driver added by myself @
>>> https://github.com/Subbaraya-Sundeep/linux.git
>>> <https://github.com/Subbaraya-Sundeep/linux.git>
>>>
>>> v5
>>> As per Philippe comments:
>>> Added abort in Sysreg if guest tries to remap memory
>>> other than default mapping.
>>> Use of CONFIG_MSF2 in Makefile for soc.c
>>> Fixed incorrect logic in timer model.
>>> Renamed msf2-timer.c -> mss-timer.c
>>> msf2-spi.c -> mss-spi.c also type names
>>> Renamed function msf2_init->emcraft_sf2_init in
>>> msf2-som.c
>>> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1
>>> properties to soc.
>>> Pass soc part-name,memory size and clock rate
>>> properties from som.
>>> v4:
>>> Fixed build failure by using PRIx macros.
>>> v3:
>>> Added SoC file and board file as per Alistair comments.
>>> v2:
>>> Added SPI controller so that u-boot loads kernel from
>>> spi flash.
>>> v1:
>>> Initial patch set with timer and sysreg
>>>
>>> Thanks,
>>> Sundeep
>>>
>>> Subbaraya Sundeep (5):
>>> msf2: Add Smartfusion2 System timer
>>> msf2: Microsemi Smartfusion2 System Register block.
>>> msf2: Add Smartfusion2 SPI controller
>>> msf2: Add Smartfusion2 SoC.
>>> msf2: Add Emcraft's Smartfusion2 SOM kit.
>>>
>>> default-configs/arm-softmmu.mak | 1 +
>>> hw/arm/Makefile.objs | 2 +
>>> hw/arm/msf2-soc.c | 201 +++++++++++++++++++++
>>> hw/arm/msf2-som.c | 89 ++++++++++
>>> hw/misc/Makefile.objs | 1 +
>>> hw/misc/msf2-sysreg.c | 161 +++++++++++++++++
>>> hw/ssi/Makefile.objs | 1 +
>>> hw/ssi/mss-spi.c | 378
>>> ++++++++++++++++++++++++++++++++++++++++
>>> hw/timer/Makefile.objs | 1 +
>>> hw/timer/mss-timer.c | 249
>>> ++++++++++++++++++++++++++
>>> include/hw/arm/msf2-soc.h | 69 ++++++++
>>> include/hw/misc/msf2-sysreg.h | 80 +++++++++
>>> include/hw/ssi/mss-spi.h | 104 +++++++++++
>>> include/hw/timer/mss-timer.h | 80 +++++++++
>>> 14 files changed, 1417 insertions(+)
>>> create mode 100644 hw/arm/msf2-soc.c
>>> create mode 100644 hw/arm/msf2-som.c
>>> create mode 100644 hw/misc/msf2-sysreg.c
>>> create mode 100644 hw/ssi/mss-spi.c
>>> create mode 100644 hw/timer/mss-timer.c
>>> create mode 100644 include/hw/arm/msf2-soc.h
>>> create mode 100644 include/hw/misc/msf2-sysreg.h
>>> create mode 100644 include/hw/ssi/mss-spi.h
>>> create mode 100644 include/hw/timer/mss-timer.h
>>>
>>>
>>>
>>>
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-06-26 16:11 ` sundeep subbaraya
@ 2017-07-02 17:39 ` sundeep subbaraya
2017-07-02 21:00 ` Peter Maydell
0 siblings, 1 reply; 35+ messages in thread
From: sundeep subbaraya @ 2017-07-02 17:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: QEMU Developers, qemu-arm, Peter Maydell, Peter Crosthwaite,
Alistair Francis
Hi Philippe,
On Mon, Jun 26, 2017 at 9:41 PM, sundeep subbaraya <sundeep.lkml@gmail.com>
wrote:
> Hi Philippe,
>
> On Fri, Jun 9, 2017 at 12:51 PM, sundeep subbaraya <sundeep.lkml@gmail.com
> > wrote:
>
>> Hi Philippe,
>>
>> On Wed, May 31, 2017 at 11:06 AM, Philippe Mathieu-Daudé <f4bug@amsat.org
>> > wrote:
>>
>>> Hi Sundeep,
>>>
>>> On 05/29/2017 02:28 AM, sundeep subbaraya wrote:
>>>
>>>> Hi Philippe,
>>>>
>>>> Any update on this? I will wait for your comments too
>>>> and send next iteration fixing Alistair comments.
>>>>
>>>
>>> Sorry I'm supposed to be in holidays ;)
>>>
>>
>> Ohh sorry currently am in vacation :)
>>
>>>
>>>
>>>> Thanks,
>>>> Sundeep
>>>>
>>>> On Wed, May 17, 2017 at 3:09 PM, sundeep subbaraya
>>>> <sundeep.lkml@gmail.com <mailto:sundeep.lkml@gmail.com>> wrote:
>>>>
>>>> Hi Philippe,
>>>>
>>>> On Wed, May 17, 2017 at 9:57 AM, Philippe Mathieu-Daudé
>>>> <f4bug@amsat.org <mailto:f4bug@amsat.org>> wrote:
>>>>
>>>> Hi Sundeep,
>>>>
>>>> This patchset is way cleaner!
>>>> I had a fast look and I like it, I'll try to make some time soon
>>>> to review details and test it.
>>>>
>>>>
>>>> Thank you
>>>>
>>>>
>>>>
>>>>
>>>> Is your work interested on U-Boot or more focused in Linux
>>>> kernel?
>>>>
>>>>
>>>> I am interested more in kernel. I had to look into u-boot for first
>>>> time for Qemu only.
>>>> I worked only on FPGAs(load kernel with debugger) till now so never
>>>> got a chance to look into u-boot.
>>>>
>>>>
>>>> If you compile QEMU with libfdt support you can use the -dtb
>>>> option to pass the blob to the kernel directly, bypassing the
>>>> bootloader.
>>>>
>>>> Yeah for armv7m I could not find any thing like that in tree.
>>>>
>>>>
>>>> If you need a bootloader you may give a look at coreboot which
>>>> supports dts well, see how Vladimir Serbinenko used Linux's dt
>>>> to boot a QEMU Versatile Express board:
>>>> https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-Feb
>>>> ruary/040899.html
>>>> <https://mail.coreboot.org/pipermail/coreboot-gerrit/2016-Fe
>>>> bruary/040899.html>
>>>>
>>>> Cool. I will look into it.
>>>>
>>>> Thanks,
>>>> Sundeep
>>>>
>>>>
>>>> Regards,
>>>>
>>>> Phil.
>>>>
>>>>
>>>> On 05/16/2017 12:38 PM, Subbaraya Sundeep wrote:
>>>>
>>>> Hi Qemu-devel,
>>>>
>>>> I am trying to add Smartfusion2 SoC.
>>>> SoC is from Microsemi and System on Module(SOM)
>>>> board is from Emcraft systems. Smartfusion2 has hardened
>>>> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
>>>> At the moment only system timer, sysreg and SPI
>>>> controller are modelled.
>>>>
>>>> Testing:
>>>> ./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial
>>>> mon:stdio \
>>>> -kernel u-boot.bin -display none -drive
>>>> file=spi.bin,if=mtd,format=raw
>>>>
>>>
>>> I'm not sure the timer is working correctly, U-Boot loops with this
>>> pattern:
>>>
>>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
>>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
>>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000220
>>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
>>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
>>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000000
>>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000000
>>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000020
>>> msf2_sysreg_read: addr: 0x00000048 data: 0x00000020
>>> msf2_sysreg_write: addr: 0x00000048 data: 0x00000220
>>>
>>> I checked the images and Linux is booting. But as you mentioned I
> changed u-boot
> for boot delay and have seen this issue. Actually it is taking too long
> for a second.
> Smartfusion2 timer is working fine(Linux) whereas u-boot is using Systick
> for auto-boot
> timer. I did not understand quite correctly about ARM Systick in Qemu. How
> do we
> specify frequency of the Systick timer? How Systick is configured to use
> CPU frequency
> since qemu cpu speed is not constant? How frequency has to be specified
> for
> using external clock as Systick input?
>
I figured out that systick uses cpu clock as clock source and
system_clock_scale
need to be set in msf2-soc.c. There is a bug in u-boot where it uses cpu
clock as
systick input but configures systick in external clock mode. I have tested
the modified
u-boot on real hardware too and it works fine. I am calculating
system_clock_scale
as below:
If CPU clock is X MHz then system_clock_scale = (1 / X) * 1000
Tested with different frequencies and they are yielding same results.
Please correct me if am wrong. I will send next iteration of patches.
Thanks,
Sundeep
>
> Please help me understand this.
>
> Thanks,
> Sundeep
>
>
>>
>>>> Binaries u-boot.bin and spi.bin are at:
>>>>
>>>
>>> you can compress spi.bin!
>>>
>>> can you share u-boot.elf with debug symbols too?
>>>
>>
>> Sure. I have tested binaries before pushing. Did you compile the u-boot
>> again?
>> Please wait for a few days I will check and provide once am back.
>>
>> Thanks,
>> Sundeep
>>
>>>
>>> Regards,
>>>
>>> Phil.
>>>
>>> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
>>>>
>>>> <https://github.com/Subbaraya-
>>>> Sundeep/qemu-test-binaries.git>
>>>>
>>>> U-boot is from Emcraft with modified
>>>> - SPI driver not to use PDMA.
>>>> - ugly hack to pass dtb to kernel in r1.
>>>> @
>>>> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>>>> <https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git
>>>> >
>>>>
>>>> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
>>>> driver added by myself @
>>>> https://github.com/Subbaraya-Sundeep/linux.git
>>>> <https://github.com/Subbaraya-Sundeep/linux.git>
>>>>
>>>> v5
>>>> As per Philippe comments:
>>>> Added abort in Sysreg if guest tries to remap memory
>>>> other than default mapping.
>>>> Use of CONFIG_MSF2 in Makefile for soc.c
>>>> Fixed incorrect logic in timer model.
>>>> Renamed msf2-timer.c -> mss-timer.c
>>>> msf2-spi.c -> mss-spi.c also type names
>>>> Renamed function msf2_init->emcraft_sf2_init in
>>>> msf2-som.c
>>>> Added part-name,eNVM-size,eSRAM-size,pclk0 and
>>>> pclk1
>>>> properties to soc.
>>>> Pass soc part-name,memory size and clock rate
>>>> properties from som.
>>>> v4:
>>>> Fixed build failure by using PRIx macros.
>>>> v3:
>>>> Added SoC file and board file as per Alistair comments.
>>>> v2:
>>>> Added SPI controller so that u-boot loads kernel from
>>>> spi flash.
>>>> v1:
>>>> Initial patch set with timer and sysreg
>>>>
>>>> Thanks,
>>>> Sundeep
>>>>
>>>> Subbaraya Sundeep (5):
>>>> msf2: Add Smartfusion2 System timer
>>>> msf2: Microsemi Smartfusion2 System Register block.
>>>> msf2: Add Smartfusion2 SPI controller
>>>> msf2: Add Smartfusion2 SoC.
>>>> msf2: Add Emcraft's Smartfusion2 SOM kit.
>>>>
>>>> default-configs/arm-softmmu.mak | 1 +
>>>> hw/arm/Makefile.objs | 2 +
>>>> hw/arm/msf2-soc.c | 201 +++++++++++++++++++++
>>>> hw/arm/msf2-som.c | 89 ++++++++++
>>>> hw/misc/Makefile.objs | 1 +
>>>> hw/misc/msf2-sysreg.c | 161 +++++++++++++++++
>>>> hw/ssi/Makefile.objs | 1 +
>>>> hw/ssi/mss-spi.c | 378
>>>> ++++++++++++++++++++++++++++++++++++++++
>>>> hw/timer/Makefile.objs | 1 +
>>>> hw/timer/mss-timer.c | 249
>>>> ++++++++++++++++++++++++++
>>>> include/hw/arm/msf2-soc.h | 69 ++++++++
>>>> include/hw/misc/msf2-sysreg.h | 80 +++++++++
>>>> include/hw/ssi/mss-spi.h | 104 +++++++++++
>>>> include/hw/timer/mss-timer.h | 80 +++++++++
>>>> 14 files changed, 1417 insertions(+)
>>>> create mode 100644 hw/arm/msf2-soc.c
>>>> create mode 100644 hw/arm/msf2-som.c
>>>> create mode 100644 hw/misc/msf2-sysreg.c
>>>> create mode 100644 hw/ssi/mss-spi.c
>>>> create mode 100644 hw/timer/mss-timer.c
>>>> create mode 100644 include/hw/arm/msf2-soc.h
>>>> create mode 100644 include/hw/misc/msf2-sysreg.h
>>>> create mode 100644 include/hw/ssi/mss-spi.h
>>>> create mode 100644 include/hw/timer/mss-timer.h
>>>>
>>>>
>>>>
>>>>
>>
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-07-02 17:39 ` sundeep subbaraya
@ 2017-07-02 21:00 ` Peter Maydell
2017-07-03 4:46 ` sundeep subbaraya
0 siblings, 1 reply; 35+ messages in thread
From: Peter Maydell @ 2017-07-02 21:00 UTC (permalink / raw)
To: sundeep subbaraya
Cc: Philippe Mathieu-Daudé,
QEMU Developers, qemu-arm, Peter Crosthwaite, Alistair Francis
On 2 July 2017 at 18:39, sundeep subbaraya <sundeep.lkml@gmail.com> wrote:
> I figured out that systick uses cpu clock as clock source and
> system_clock_scale
> need to be set in msf2-soc.c. There is a bug in u-boot where it uses cpu
> clock as
> systick input but configures systick in external clock mode. I have tested
> the modified
> u-boot on real hardware too and it works fine. I am calculating
> system_clock_scale
> as below:
> If CPU clock is X MHz then system_clock_scale = (1 / X) * 1000
>
> Tested with different frequencies and they are yielding same results.
If you calculate it like that you'll probably get rounding
errors. Better is
system_clock_scale = NANOSECONDS_PER_SECOND / freq_in_hz;
(Our systick implementation hardwires the external clock
frequency at 1MHz, but this is not really correct, it
depends on the SoC.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [Qemu devel v5 PATCH 0/5] Add support for Smartfusion2 SoC
2017-07-02 21:00 ` Peter Maydell
@ 2017-07-03 4:46 ` sundeep subbaraya
0 siblings, 0 replies; 35+ messages in thread
From: sundeep subbaraya @ 2017-07-03 4:46 UTC (permalink / raw)
To: Peter Maydell
Cc: Philippe Mathieu-Daudé,
QEMU Developers, qemu-arm, Peter Crosthwaite, Alistair Francis
Hi Peter,
On Mon, Jul 3, 2017 at 2:30 AM, Peter Maydell <peter.maydell@linaro.org>
wrote:
> On 2 July 2017 at 18:39, sundeep subbaraya <sundeep.lkml@gmail.com> wrote:
> > I figured out that systick uses cpu clock as clock source and
> > system_clock_scale
> > need to be set in msf2-soc.c. There is a bug in u-boot where it uses cpu
> > clock as
> > systick input but configures systick in external clock mode. I have
> tested
> > the modified
> > u-boot on real hardware too and it works fine. I am calculating
> > system_clock_scale
> > as below:
> > If CPU clock is X MHz then system_clock_scale = (1 / X) * 1000
> >
> > Tested with different frequencies and they are yielding same results.
>
> If you calculate it like that you'll probably get rounding
> errors. Better is
> system_clock_scale = NANOSECONDS_PER_SECOND / freq_in_hz;
>
> (Our systick implementation hardwires the external clock
> frequency at 1MHz, but this is not really correct, it
> depends on the SoC.)
>
Ok. Modified as per your comment.
Thanks,
Sundeep
>
> thanks
> -- PMM
>
^ permalink raw reply [flat|nested] 35+ messages in thread