* [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC
@ 2017-04-28 16:51 Subbaraya Sundeep
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Subbaraya Sundeep @ 2017-04-28 16:51 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, Subbaraya Sundeep
Hi Qemu-devel,
I am trying to add Smartfusion2 SoC.
SoC is from Microsemi and System on Module(SOM)
board is from Emcraft systems. Smartfusion2 has hardened
Microcontroller(Cortex-M3)based Sub System and FPGA fabric.
At the moment only system timer, sysreg and SPI
controller are modelled.
Testing:
./arm-softmmu/qemu-system-arm -M smartfusion2-som -serial mon:stdio \
-kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw
U-boot is from Emcraft with modified SPI driver not to use PDMA.
Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource
driver added by myself @
https://github.com/Subbaraya-Sundeep/linux.git
Baremetal elfs from Microsemi Softconsole IDE are also working.
Changes from v2:
Added SoC file and board file.
Changes from v1:
Added SPI controller.
Thanks,
Sundeep
Subbaraya Sundeep (5):
msf2: Add Smartfusion2 System timer
msf2: Microsemi Smartfusion2 System Register block.
msf2: Add Smartfusion2 SPI controller
msf2: Add Smartfusion2 SoC.
msf2: Add Emcraft's Smartfusion2 SOM kit.
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 3 +-
hw/arm/msf2_soc.c | 194 +++++++++++++++++++++
hw/arm/msf2_som.c | 68 ++++++++
hw/misc/Makefile.objs | 1 +
hw/misc/msf2_sysreg.c | 127 ++++++++++++++
hw/ssi/Makefile.objs | 1 +
hw/ssi/msf2_spi.c | 373 ++++++++++++++++++++++++++++++++++++++++
hw/timer/Makefile.objs | 1 +
hw/timer/msf2_timer.c | 250 +++++++++++++++++++++++++++
include/hw/arm/msf2_soc.h | 62 +++++++
include/hw/misc/msf2_sysreg.h | 77 +++++++++
include/hw/ssi/msf2_spi.h | 102 +++++++++++
include/hw/timer/msf2_timer.h | 82 +++++++++
14 files changed, 1341 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/msf2_soc.c
create mode 100644 hw/arm/msf2_som.c
create mode 100644 hw/misc/msf2_sysreg.c
create mode 100644 hw/ssi/msf2_spi.c
create mode 100644 hw/timer/msf2_timer.c
create mode 100644 include/hw/arm/msf2_soc.h
create mode 100644 include/hw/misc/msf2_sysreg.h
create mode 100644 include/hw/ssi/msf2_spi.h
create mode 100644 include/hw/timer/msf2_timer.h
--
2.5.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer
2017-04-28 16:51 [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
@ 2017-04-28 16:51 ` Subbaraya Sundeep
2017-05-02 21:55 ` Alistair Francis
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Subbaraya Sundeep @ 2017-04-28 16:51 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, Subbaraya Sundeep
Modelled System Timer in Microsemi's Smartfusion2 Soc.
Timer has two 32bit down counters and two interrupts.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/timer/Makefile.objs | 1 +
hw/timer/msf2_timer.c | 250 ++++++++++++++++++++++++++++++++++++++++++
include/hw/timer/msf2_timer.h | 82 ++++++++++++++
3 files changed, 333 insertions(+)
create mode 100644 hw/timer/msf2_timer.c
create mode 100644 include/hw/timer/msf2_timer.h
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index dd6f27e..0bdf1e1 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
+common-obj-$(CONFIG_MSF2) += msf2_timer.o
diff --git a/hw/timer/msf2_timer.c b/hw/timer/msf2_timer.c
new file mode 100644
index 0000000..d1dbde5
--- /dev/null
+++ b/hw/timer/msf2_timer.c
@@ -0,0 +1,250 @@
+/*
+ * Timer block model of Microsemi SmartFusion2.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/timer/msf2_timer.h"
+#include "hw/sysbus.h"
+#include "qemu/log.h"
+#include "qemu/main-loop.h"
+
+#ifndef MSF2_TIMER_ERR_DEBUG
+#define MSF2_TIMER_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSF2_TIMER_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void timer_update_irq(struct Msf2Timer *st)
+{
+ bool isr, ier;
+
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+
+ qemu_set_irq(st->irq, (ier && isr));
+}
+
+static void timer_update(struct Msf2Timer *st)
+{
+ uint64_t count;
+
+ DB_PRINT("timer=%d\n", st->nr);
+
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
+ ptimer_stop(st->ptimer);
+ return;
+ }
+
+ count = st->regs[R_TIM_LOADVAL];
+ ptimer_set_limit(st->ptimer, count, 1);
+ ptimer_run(st->ptimer, 1);
+}
+
+static uint64_t
+timer_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ MSF2TimerState *t = opaque;
+ struct Msf2Timer *st;
+ uint32_t r = 0;
+ unsigned int timer = 0;
+ int isr;
+ int ier;
+
+ addr >>= 2;
+ /*
+ * Two independent timers has same base address.
+ * Based on addr passed figure out which timer is being used.
+ */
+ if (addr >= R_TIM1_MAX) {
+ timer = 1;
+ addr -= R_TIM1_MAX;
+ }
+
+ st = &t->timers[timer];
+
+ switch (addr) {
+ case R_TIM_VAL:
+ r = ptimer_get_count(st->ptimer);
+ DB_PRINT("msf2_timer t=%d read counter=%x\n", timer, r);
+ break;
+
+ case R_TIM_MIS:
+ isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
+ ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
+ r = ier && isr;
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(st->regs)) {
+ r = st->regs[addr];
+ }
+ break;
+ }
+ DB_PRINT("timer=%d %lu=%x\n", timer, addr * 4, r);
+ return r;
+}
+
+static void
+timer_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ MSF2TimerState *t = opaque;
+ struct Msf2Timer *st;
+ unsigned int timer = 0;
+ uint32_t value = val64;
+
+ addr >>= 2;
+ /*
+ * Two independent timers has same base address.
+ * Based on addr passed figure out which timer is being used.
+ */
+ if (addr >= R_TIM1_MAX) {
+ timer = 1;
+ addr -= R_TIM1_MAX;
+ }
+
+ st = &t->timers[timer];
+
+ DB_PRINT("addr=%lu val=%x (timer=%d)\n", addr * 4, value, timer);
+
+ switch (addr) {
+ case R_TIM_CTRL:
+ st->regs[R_TIM_CTRL] = value;
+ timer_update(st);
+ break;
+
+ case R_TIM_RIS:
+ if (value & TIMER_RIS_ACK) {
+ st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
+ }
+ break;
+
+ case R_TIM_LOADVAL:
+ st->regs[R_TIM_LOADVAL] = value;
+ if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
+ timer_update(st);
+ }
+ break;
+
+ case R_TIM_BGLOADVAL:
+ st->regs[R_TIM_BGLOADVAL] = value;
+ st->regs[R_TIM_LOADVAL] = value;
+ break;
+
+ case R_TIM_VAL:
+ case R_TIM_MIS:
+ break;
+
+ case R_TIM_MODE:
+ if (value & TIMER_MODE) {
+ DB_PRINT("64-bit mode not supported\n");
+ }
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(st->regs)) {
+ st->regs[addr] = value;
+ }
+ break;
+ }
+ timer_update_irq(st);
+}
+
+static const MemoryRegionOps timer_ops = {
+ .read = timer_read,
+ .write = timer_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void timer_hit(void *opaque)
+{
+ struct Msf2Timer *st = opaque;
+
+ DB_PRINT("%d\n", st->nr);
+ st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
+
+ if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
+ timer_update(st);
+ }
+ timer_update_irq(st);
+}
+
+static void msf2_timer_init(Object *obj)
+{
+ MSF2TimerState *t = MSF2_TIMER(obj);
+ unsigned int i;
+
+ /* Init all the ptimers. */
+ t->timers = g_malloc0((sizeof t->timers[0]) * NUM_TIMERS);
+ for (i = 0; i < NUM_TIMERS; i++) {
+ struct Msf2Timer *st = &t->timers[i];
+
+ st->nr = i;
+ st->bh = qemu_bh_new(timer_hit, st);
+ st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
+ ptimer_set_freq(st->ptimer, t->freq_hz);
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
+ }
+
+ memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSF2_TIMER,
+ R_TIM_MAX * 4);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
+}
+
+static Property msf2_timer_properties[] = {
+ DEFINE_PROP_UINT32("clock-frequency", MSF2TimerState, freq_hz,
+ 83 * 1000000),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void msf2_timer_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->props = msf2_timer_properties;
+}
+
+static const TypeInfo msf2_timer_info = {
+ .name = TYPE_MSF2_TIMER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSF2TimerState),
+ .instance_init = msf2_timer_init,
+ .class_init = msf2_timer_class_init,
+};
+
+static void msf2_timer_register_types(void)
+{
+ type_register_static(&msf2_timer_info);
+}
+
+type_init(msf2_timer_register_types)
diff --git a/include/hw/timer/msf2_timer.h b/include/hw/timer/msf2_timer.h
new file mode 100644
index 0000000..93d9fb3
--- /dev/null
+++ b/include/hw/timer/msf2_timer.h
@@ -0,0 +1,82 @@
+/*
+ * Microsemi SmartFusion2 Timer.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSF2_TIMER_H
+#define HW_MSF2_TIMER_H
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+
+#define TYPE_MSF2_TIMER "msf2-timer"
+#define MSF2_TIMER(obj) OBJECT_CHECK(MSF2TimerState, \
+ (obj), TYPE_MSF2_TIMER)
+
+/*
+ * There are two 32-bit down counting timers.
+ * Timers 1 and 2 can be concatenated into a single 64-bit Timer
+ * that operates either in Periodic mode or in One-shot mode.
+ * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
+ * In 64-bit mode, writing to the 32-bit registers has no effect.
+ * Similarly, in 32-bit mode, writing to the 64-bit mode registers
+ * has no effect. Only two 32-bit timers are supported currently.
+ */
+#define NUM_TIMERS 2
+
+#define R_TIM_VAL 0
+#define R_TIM_LOADVAL 1
+#define R_TIM_BGLOADVAL 2
+#define R_TIM_CTRL 3
+#define R_TIM_RIS 4
+#define R_TIM_MIS 5
+#define R_TIM1_MAX 6
+
+#define R_TIM_MODE 21
+#define R_TIM_MAX 22 /* including 64-bit timer registers */
+
+#define TIMER_CTRL_ENBL (1 << 0)
+#define TIMER_CTRL_ONESHOT (1 << 1)
+#define TIMER_CTRL_INTR (1 << 2)
+#define TIMER_RIS_ACK (1 << 0)
+#define TIMER_RST_CLR (1 << 6)
+#define TIMER_MODE (1 << 0)
+
+struct Msf2Timer {
+ QEMUBH *bh;
+ ptimer_state *ptimer;
+ int nr; /* for debug. */
+
+ uint32_t regs[R_TIM_MAX];
+ qemu_irq irq;
+};
+
+typedef struct MSF2TimerState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+ uint32_t freq_hz;
+ struct Msf2Timer *timers;
+} MSF2TimerState;
+
+#endif /* HW_MSF2_TIMER_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [Qemu-devel RFC v3 2/5] msf2: Microsemi Smartfusion2 System Register block.
2017-04-28 16:51 [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
@ 2017-04-28 16:51 ` Subbaraya Sundeep
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
` (3 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Subbaraya Sundeep @ 2017-04-28 16:51 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, Subbaraya Sundeep
Added Sytem register block of Smartfusion2.
This block has PLL registers which are accessed by guest.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/msf2_sysreg.c | 127 ++++++++++++++++++++++++++++++++++++++++++
include/hw/misc/msf2_sysreg.h | 77 +++++++++++++++++++++++++
3 files changed, 205 insertions(+)
create mode 100644 hw/misc/msf2_sysreg.c
create mode 100644 include/hw/misc/msf2_sysreg.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index c8b4893..aee53df 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -56,3 +56,4 @@ obj-$(CONFIG_EDU) += edu.o
obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
obj-$(CONFIG_AUX) += auxbus.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
+obj-$(CONFIG_MSF2) += msf2_sysreg.o
diff --git a/hw/misc/msf2_sysreg.c b/hw/misc/msf2_sysreg.c
new file mode 100644
index 0000000..6386953
--- /dev/null
+++ b/hw/misc/msf2_sysreg.c
@@ -0,0 +1,127 @@
+/*
+ * System Register block model of Microsemi SmartFusion2.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/msf2_sysreg.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+
+#ifndef MSF2_SYSREG_ERR_DEBUG
+#define MSF2_SYSREG_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSF2_SYSREG_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void msf2_sysreg_reset(DeviceState *d)
+{
+ MSF2SysregState *s = MSF2_SYSREG(d);
+
+ DB_PRINT("RESET\n");
+
+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x02420041;
+ s->regs[MSSDDR_FACC1_CR] = 0x0A482124;
+ s->regs[MSSDDR_PLL_STATUS] = 0x3;
+}
+
+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ MSF2SysregState *s = opaque;
+ offset /= 4;
+ uint32_t ret = 0;
+
+ if (offset < ARRAY_SIZE(s->regs)) {
+ ret = s->regs[offset];
+ DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n",
+ offset * 4, ret);
+ } else {
+ DB_PRINT("addr: %08" HWADDR_PRIx " not valid\n", offset * 4);
+ }
+
+ return ret;
+}
+
+static void msf2_sysreg_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ MSF2SysregState *s = (MSF2SysregState *)opaque;
+ offset /= 4;
+
+ DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
+
+ switch (offset) {
+ case MSSDDR_PLL_STATUS:
+ break;
+
+ default:
+ if (offset < ARRAY_SIZE(s->regs)) {
+ s->regs[offset] = val;
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps sysreg_ops = {
+ .read = msf2_sysreg_read,
+ .write = msf2_sysreg_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void msf2_sysreg_init(Object *obj)
+{
+ MSF2SysregState *s = MSF2_SYSREG(obj);
+
+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,
+ MSF2_SYSREG_MMIO_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+}
+
+static const VMStateDescription vmstate_msf2_sysreg = {
+ .name = TYPE_MSF2_SYSREG,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_NUM_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_msf2_sysreg;
+ dc->reset = msf2_sysreg_reset;
+}
+
+static const TypeInfo msf2_sysreg_info = {
+ .name = TYPE_MSF2_SYSREG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .class_init = msf2_sysreg_class_init,
+ .instance_size = sizeof(MSF2SysregState),
+ .instance_init = msf2_sysreg_init,
+};
+
+static void msf2_sysreg_register_types(void)
+{
+ type_register_static(&msf2_sysreg_info);
+}
+
+type_init(msf2_sysreg_register_types)
diff --git a/include/hw/misc/msf2_sysreg.h b/include/hw/misc/msf2_sysreg.h
new file mode 100644
index 0000000..03c5773
--- /dev/null
+++ b/include/hw/misc/msf2_sysreg.h
@@ -0,0 +1,77 @@
+/*
+ * Microsemi SmartFusion2 SYSREG
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSF2_SYSREG_H
+#define HW_MSF2_SYSREG_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+
+enum {
+ ESRAM_CR = 0x00 / 4,
+ ESRAM_MAX_LAT,
+ DDR_CR,
+ ENVM_CR,
+ ENVM_REMAP_BASE_CR,
+ ENVM_REMAP_FAB_CR,
+ CC_CR,
+ CC_REGION_CR,
+ CC_LOCK_BASE_ADDR_CR,
+ CC_FLUSH_INDX_CR,
+ DDRB_BUF_TIMER_CR,
+ DDRB_NB_ADDR_CR,
+ DDRB_NB_SIZE_CR,
+ DDRB_CR,
+
+ SOFT_RESET_CR = 0x48 / 4,
+ M3_CR,
+
+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,
+
+ MDDR_CR = 0x60 / 4,
+
+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,
+ MSSDDR_PLL_STATUS_HIGH_CR,
+ MSSDDR_FACC1_CR,
+ MSSDDR_FACC2_CR,
+
+ MSSDDR_PLL_STATUS = 0x150 / 4,
+
+};
+
+#define MSF2_SYSREG_MMIO_SIZE 0x300
+#define MSF2_SYSREG_NUM_REGS (MSF2_SYSREG_MMIO_SIZE / 4)
+
+#define TYPE_MSF2_SYSREG "msf2-sysreg"
+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)
+
+typedef struct MSF2SysregState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+
+ uint32_t regs[MSF2_SYSREG_NUM_REGS];
+} MSF2SysregState;
+
+#endif /* HW_MSF2_SYSREG_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller
2017-04-28 16:51 [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
@ 2017-04-28 16:51 ` Subbaraya Sundeep
2017-05-02 5:02 ` sundeep subbaraya
2017-05-03 23:39 ` Alistair Francis
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
` (2 subsequent siblings)
5 siblings, 2 replies; 16+ messages in thread
From: Subbaraya Sundeep @ 2017-04-28 16:51 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, Subbaraya Sundeep
Modelled Microsemi's Smartfusion2 SPI controller.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
Hi Peter and Alistair,
I created two SPI controllers as per SoC spec
in hw/arm/msf2_soc.c. I am assuming there has to be two
busses spi0 and spi1 one for each controller. In board file
(hw/arm/msf2_som.c) attached SPI flash to SPI0 controller.
I am not able to understand(from hw/ssi/xilinx_spips.c)
how to create two busses in hw/ssi/msf2_spi.c.
Please help me here. Below is the output of info qtree:
(qemu) info qtree
bus: main-system-bus
type System
dev: msf2-soc, id ""
cpu-model = "cortex-m3"
dev: msf2-spi, id ""
gpio-out "sysbus-irq" 2
mmio 0000000040011000/0000000000000040
bus: spi0
type SSI
dev: msf2-spi, id ""
gpio-out "sysbus-irq" 2
mmio 0000000040001000/0000000000000040
bus: spi0
type SSI
dev: s25sl12801, id ""
gpio-in "ssi-gpio-cs" 1
nonvolatile-cfg = 36863 (0x8fff)
spansion-cr1nv = 0 (0x0)
spansion-cr2nv = 1 (0x1)
spansion-cr3nv = 2 (0x2)
spansion-cr4nv = 16 (0x10)
drive = "mtd0"
Thanks,
Sundeep
hw/ssi/Makefile.objs | 1 +
hw/ssi/msf2_spi.c | 373 ++++++++++++++++++++++++++++++++++++++++++++++
include/hw/ssi/msf2_spi.h | 102 +++++++++++++
3 files changed, 476 insertions(+)
create mode 100644 hw/ssi/msf2_spi.c
create mode 100644 include/hw/ssi/msf2_spi.h
diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
index 487add2..86445d7 100644
--- a/hw/ssi/Makefile.objs
+++ b/hw/ssi/Makefile.objs
@@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
+common-obj-$(CONFIG_MSF2) += msf2_spi.o
obj-$(CONFIG_OMAP) += omap_spi.o
obj-$(CONFIG_IMX) += imx_spi.o
diff --git a/hw/ssi/msf2_spi.c b/hw/ssi/msf2_spi.c
new file mode 100644
index 0000000..e7ffa21
--- /dev/null
+++ b/hw/ssi/msf2_spi.c
@@ -0,0 +1,373 @@
+/*
+ * SPI controller model of Microsemi SmartFusion2.
+ *
+ * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/ssi/msf2_spi.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+
+#ifndef MSF2_SPI_ERR_DEBUG
+#define MSF2_SPI_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+ if (MSF2_SPI_ERR_DEBUG >= lvl) { \
+ qemu_log("%s: " fmt, __func__, ## args); \
+ } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void txfifo_reset(MSF2SpiState *s)
+{
+ fifo32_reset(&s->tx_fifo);
+
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
+ s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
+}
+
+static void rxfifo_reset(MSF2SpiState *s)
+{
+ fifo32_reset(&s->rx_fifo);
+
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+}
+
+static void set_fifodepth(MSF2SpiState *s)
+{
+ int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
+
+ if (0 <= size && size <= 8) {
+ s->fifo_depth = 32;
+ }
+ if (9 <= size && size <= 16) {
+ s->fifo_depth = 16;
+ }
+ if (17 <= size && size <= 32) {
+ s->fifo_depth = 8;
+ }
+}
+
+static void msf2_spi_do_reset(MSF2SpiState *s)
+{
+ memset(s->regs, 0, sizeof s->regs);
+ s->regs[R_SPI_CONTROL] = 0x80000102;
+ s->regs[R_SPI_DFSIZE] = 0x4;
+ s->regs[R_SPI_STATUS] = 0x2440;
+ s->regs[R_SPI_CLKGEN] = 0x7;
+ s->regs[R_SPI_STAT8] = 0x7;
+ s->regs[R_SPI_RIS] = 0x0;
+
+ s->fifo_depth = 4;
+ s->frame_count = 1;
+ s->enabled = false;
+
+ rxfifo_reset(s);
+ txfifo_reset(s);
+}
+
+static void update_mis(MSF2SpiState *s)
+{
+ uint32_t reg = s->regs[R_SPI_CONTROL];
+ uint32_t tmp;
+
+ /*
+ * form the Control register interrupt enable bits
+ * same as RIS, MIS and Interrupt clear registers for simplicity
+ */
+ tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
+ ((reg & C_INTTXDATA) >> 5);
+ s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
+}
+
+static void spi_update_irq(MSF2SpiState *s)
+{
+ int irq;
+
+ update_mis(s);
+ irq = !!(s->regs[R_SPI_MIS]);
+
+ qemu_set_irq(s->irq, irq);
+}
+
+static void msf2_spi_reset(DeviceState *d)
+{
+ msf2_spi_do_reset(MSF2_SPI(d));
+}
+
+static uint64_t
+spi_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ MSF2SpiState *s = opaque;
+ uint32_t r = 0;
+
+ addr >>= 2;
+ switch (addr) {
+ case R_SPI_RX:
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
+ s->regs[R_SPI_STATUS] &= ~RXCHOVRF;
+ r = fifo32_pop(&s->rx_fifo);
+ if (fifo32_is_empty(&s->rx_fifo)) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
+ }
+ break;
+
+ case R_SPI_MIS:
+ update_mis(s);
+ r = s->regs[R_SPI_MIS];
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ r = s->regs[addr];
+ }
+ break;
+ }
+
+ DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
+ spi_update_irq(s);
+ return r;
+}
+
+static void assert_cs(MSF2SpiState *s)
+{
+ qemu_set_irq(s->cs_line, 0);
+}
+
+static void deassert_cs(MSF2SpiState *s)
+{
+ qemu_set_irq(s->cs_line, 1);
+}
+
+static void spi_flush_txfifo(MSF2SpiState *s)
+{
+ uint32_t tx;
+ uint32_t rx;
+ bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
+
+ /*
+ * Chip Select(CS) is automatically controlled by this controller.
+ * If SPS bit is set in Control register then CS is asserted
+ * until all the frames set in frame count of Control register are
+ * transferred. If SPS is not set then CS pulses between frames.
+ * Note that Slave Select register specifies which of the CS line
+ * has to be controlled automatically by controller. Bits SS[7:1] are for
+ * masters in FPGA fabric since we model only Microcontroller subsystem
+ * of Smartfusion2 we control only one CS(SS[0]) line.
+ */
+ while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
+ assert_cs(s);
+
+ s->regs[R_SPI_STATUS] &= ~TXDONE;
+ s->regs[R_SPI_STATUS] &= ~RXRDY;
+
+ tx = fifo32_pop(&s->tx_fifo);
+ DB_PRINT("data tx:%x\n", tx);
+ rx = ssi_transfer(s->spi, tx);
+ DB_PRINT("data rx:%x\n", rx);
+
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= RXCHOVRF;
+ s->regs[R_SPI_RIS] |= RXCHOVRF;
+ } else {
+ fifo32_push(&s->rx_fifo, rx);
+ s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
+ if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
+ }
+ if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
+ }
+ }
+ s->frame_count--;
+ if (!sps) {
+ deassert_cs(s);
+ assert_cs(s);
+ }
+ }
+
+ if (!sps) {
+ deassert_cs(s);
+ }
+
+ if (!s->frame_count) {
+ s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
+ FMCOUNT_SHIFT;
+ if (sps) {
+ deassert_cs(s);
+ }
+ s->regs[R_SPI_RIS] |= TXDONE;
+ s->regs[R_SPI_RIS] |= RXRDY;
+ s->regs[R_SPI_STATUS] |= TXDONE;
+ s->regs[R_SPI_STATUS] |= RXRDY;
+ }
+}
+
+static void spi_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ MSF2SpiState *s = opaque;
+ uint32_t value = val64;
+
+ DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
+ addr >>= 2;
+
+ switch (addr) {
+ case R_SPI_TX:
+ /* adding to already full FIFO */
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+ break;
+ }
+ s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
+ fifo32_push(&s->tx_fifo, value);
+ if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
+ }
+ if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
+ s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
+ }
+ if (s->enabled) {
+ spi_flush_txfifo(s);
+ }
+ break;
+
+ case R_SPI_CONTROL:
+ s->regs[R_SPI_CONTROL] = value;
+ if (value & C_BIGFIFO) {
+ set_fifodepth(s);
+ } else {
+ s->fifo_depth = 4;
+ }
+ if (value & C_ENABLE) {
+ s->enabled = true;
+ } else {
+ s->enabled = false;
+ }
+ s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
+ if (value & C_RESET) {
+ msf2_spi_do_reset(s);
+ }
+ break;
+
+ case R_SPI_DFSIZE:
+ if (s->enabled) {
+ break;
+ }
+ s->regs[R_SPI_DFSIZE] = value;
+ break;
+
+ case R_SPI_INTCLR:
+ s->regs[R_SPI_INTCLR] = value;
+ if (value & TXDONE) {
+ s->regs[R_SPI_RIS] &= ~TXDONE;
+ }
+ if (value & RXRDY) {
+ s->regs[R_SPI_RIS] &= ~RXRDY;
+ }
+ if (value & RXCHOVRF) {
+ s->regs[R_SPI_RIS] &= ~RXCHOVRF;
+ }
+ break;
+
+ case R_SPI_MIS:
+ case R_SPI_STATUS:
+ case R_SPI_RIS:
+ break;
+
+ default:
+ if (addr < ARRAY_SIZE(s->regs)) {
+ s->regs[addr] = value;
+ }
+ break;
+ }
+
+ spi_update_irq(s);
+}
+
+static const MemoryRegionOps spi_ops = {
+ .read = spi_read,
+ .write = spi_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+};
+
+static void msf2_spi_realize(DeviceState *dev, Error **errp)
+{
+ MSF2SpiState *s = MSF2_SPI(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ DB_PRINT("\n");
+
+ s->spi = ssi_create_bus(dev, "spi0");
+
+ sysbus_init_irq(sbd, &s->irq);
+ ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
+ sysbus_init_irq(sbd, &s->cs_line);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
+ TYPE_MSF2_SPI, R_SPI_MAX * 4);
+ sysbus_init_mmio(sbd, &s->mmio);
+
+ fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
+ fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
+}
+
+static const VMStateDescription vmstate_msf2_spi = {
+ .name = TYPE_MSF2_SPI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_FIFO32(tx_fifo, MSF2SpiState),
+ VMSTATE_FIFO32(rx_fifo, MSF2SpiState),
+ VMSTATE_UINT32_ARRAY(regs, MSF2SpiState, R_SPI_MAX),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void msf2_spi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = msf2_spi_realize;
+ dc->reset = msf2_spi_reset;
+ dc->vmsd = &vmstate_msf2_spi;
+}
+
+static const TypeInfo msf2_spi_info = {
+ .name = TYPE_MSF2_SPI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSF2SpiState),
+ .class_init = msf2_spi_class_init,
+};
+
+static void msf2_spi_register_types(void)
+{
+ type_register_static(&msf2_spi_info);
+}
+
+type_init(msf2_spi_register_types)
diff --git a/include/hw/ssi/msf2_spi.h b/include/hw/ssi/msf2_spi.h
new file mode 100644
index 0000000..7f266c2
--- /dev/null
+++ b/include/hw/ssi/msf2_spi.h
@@ -0,0 +1,102 @@
+/*
+ * Microsemi SmartFusion2 SPI
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_MSF2_SPI_H
+#define HW_MSF2_SPI_H
+
+#include "hw/sysbus.h"
+#include "hw/hw.h"
+#include "hw/ssi/ssi.h"
+#include "qemu/fifo32.h"
+
+#define FIFO_CAPACITY 32
+#define FIFO_CAPACITY 32
+
+#define R_SPI_CONTROL 0
+#define R_SPI_DFSIZE 1
+#define R_SPI_STATUS 2
+#define R_SPI_INTCLR 3
+#define R_SPI_RX 4
+#define R_SPI_TX 5
+#define R_SPI_CLKGEN 6
+#define R_SPI_SS 7
+#define R_SPI_MIS 8
+#define R_SPI_RIS 9
+#define R_SPI_STAT8 15
+#define R_SPI_MAX 16
+
+#define S_RXFIFOFUL (1 << 4)
+#define S_RXFIFOFULNXT (1 << 5)
+#define S_RXFIFOEMP (1 << 6)
+#define S_RXFIFOEMPNXT (1 << 7)
+#define S_TXFIFOFUL (1 << 8)
+#define S_TXFIFOFULNXT (1 << 9)
+#define S_TXFIFOEMP (1 << 10)
+#define S_TXFIFOEMPNXT (1 << 11)
+#define S_FRAMESTART (1 << 12)
+#define S_SSEL (1 << 13)
+#define S_ACTIVE (1 << 14)
+
+#define C_ENABLE (1 << 0)
+#define C_MODE (1 << 1)
+#define C_INTRXDATA (1 << 4)
+#define C_INTTXDATA (1 << 5)
+#define C_INTRXOVRFLO (1 << 6)
+#define C_SPS (1 << 26)
+#define C_BIGFIFO (1 << 29)
+#define C_RESET (1 << 31)
+
+#define FRAMESZ_MASK 0x1F
+#define FMCOUNT_MASK 0x00FFFF00
+#define FMCOUNT_SHIFT 8
+
+#define TXDONE (1 << 0)
+#define RXRDY (1 << 1)
+#define RXCHOVRF (1 << 2)
+
+#define TYPE_MSF2_SPI "msf2-spi"
+#define MSF2_SPI(obj) OBJECT_CHECK(MSF2SpiState, (obj), TYPE_MSF2_SPI)
+
+typedef struct MSF2SpiState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ qemu_irq irq;
+
+ qemu_irq cs_line;
+
+ SSIBus *spi;
+
+ Fifo32 rx_fifo;
+ Fifo32 tx_fifo;
+
+ int fifo_depth;
+ uint32_t frame_count;
+ bool enabled;
+
+ uint32_t regs[R_SPI_MAX];
+} MSF2SpiState;
+
+#endif /* HW_MSF2_SPI_H */
--
2.5.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC.
2017-04-28 16:51 [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (2 preceding siblings ...)
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
@ 2017-04-28 16:51 ` Subbaraya Sundeep
2017-05-04 22:21 ` Alistair Francis
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
2017-04-28 17:20 ` [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC no-reply
5 siblings, 1 reply; 16+ messages in thread
From: Subbaraya Sundeep @ 2017-04-28 16:51 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, Subbaraya Sundeep
Smartfusion2 SoC has hardened Microcontroller subsystem
and flash based FPGA fabric. This patch adds support for
Microcontroller subsystem in the SoC.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/Makefile.objs | 2 +-
hw/arm/msf2_soc.c | 194 ++++++++++++++++++++++++++++++++++++++++
include/hw/arm/msf2_soc.h | 62 +++++++++++++
4 files changed, 258 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/msf2_soc.c
create mode 100644 include/hw/arm/msf2_soc.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 78d7af0..7062512 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -122,3 +122,4 @@ CONFIG_ACPI=y
CONFIG_SMBIOS=y
CONFIG_ASPEED_SOC=y
CONFIG_GPIO_KEY=y
+CONFIG_MSF2=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 4c5c4ee..cce2759 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -1,7 +1,7 @@
obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
obj-$(CONFIG_DIGIC) += digic_boards.o
obj-y += integratorcp.o mainstone.o musicpal.o nseries.o
-obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
+obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o msf2_soc.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
obj-$(CONFIG_ACPI) += virt-acpi-build.o
obj-y += netduino2.o
diff --git a/hw/arm/msf2_soc.c b/hw/arm/msf2_soc.c
new file mode 100644
index 0000000..a470872
--- /dev/null
+++ b/hw/arm/msf2_soc.c
@@ -0,0 +1,194 @@
+/*
+ * SmartFusion2 SoC emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "qemu-common.h"
+#include "hw/arm/arm.h"
+#include "exec/address-spaces.h"
+#include "hw/char/serial.h"
+#include "hw/boards.h"
+#include "sysemu/block-backend.h"
+#include "hw/arm/msf2_soc.h"
+
+#define MSF2_TIMER_BASE 0x40004000
+#define MSF2_SYSREG_BASE 0x40038000
+
+#define MSF2_TIMER_IRQ0 14
+#define MSF2_TIMER_IRQ1 15
+
+static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
+static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
+
+static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
+static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
+
+static void msf2_soc_initfn(Object *obj)
+{
+ MSF2State *s = MSF2_SOC(obj);
+ int i;
+
+ object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
+ qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
+
+ object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
+ qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
+
+ object_initialize(&s->timer, sizeof(s->timer), TYPE_MSF2_TIMER);
+ qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
+
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
+ object_initialize(&s->spi[i], sizeof(s->spi[i]),
+ TYPE_MSF2_SPI);
+ qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
+ }
+}
+
+static void msf2_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ MSF2State *s = MSF2_SOC(dev_soc);
+ DeviceState *dev, *armv7m;
+ SysBusDevice *busdev;
+ Error *err = NULL;
+ int i;
+
+ MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *nvm = g_new(MemoryRegion, 1);
+ MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
+ MemoryRegion *sram = g_new(MemoryRegion, 1);
+ MemoryRegion *ddr = g_new(MemoryRegion, 1);
+
+ memory_region_init_ram(nvm, NULL, "MSF2.envm", ENVM_SIZE,
+ &error_fatal);
+ memory_region_init_alias(nvm_alias, NULL, "MSF2.flash.alias",
+ nvm, 0, ENVM_SIZE);
+ vmstate_register_ram_global(nvm);
+
+ memory_region_set_readonly(nvm, true);
+ memory_region_set_readonly(nvm_alias, true);
+
+ memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
+ memory_region_add_subregion(system_memory, 0, nvm_alias);
+
+ memory_region_init_ram(ddr, NULL, "MSF2.ddr", DDR_SIZE,
+ &error_fatal);
+ vmstate_register_ram_global(ddr);
+ memory_region_add_subregion(system_memory, DDR_BASE_ADDRESS, ddr);
+
+ memory_region_init_ram(sram, NULL, "MSF2.sram", SRAM_SIZE,
+ &error_fatal);
+ vmstate_register_ram_global(sram);
+ memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
+
+ armv7m = DEVICE(&s->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 96);
+ qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
+ object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
+ "memory", &error_abort);
+ object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ for (i = 0; i < MSF2_NUM_UARTS; i++) {
+ if (serial_hds[i]) {
+ serial_mm_init(get_system_memory(), uart_addr[i], 2,
+ qdev_get_gpio_in(armv7m, uart_irq[i]),
+ 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
+ }
+ }
+
+ dev = DEVICE(&s->timer);
+ qdev_prop_set_uint32(dev, "clock-frequency", 83 * 1000000);
+ object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
+ sysbus_connect_irq(busdev, 1,
+ qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
+
+ dev = DEVICE(&s->sysreg);
+ object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ busdev = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
+
+ for (i = 0; i < MSF2_NUM_SPIS; i++) {
+ gchar *bus_name = g_strdup_printf("spi%d", i);
+
+ object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
+ if (err != NULL) {
+ g_free(bus_name);
+ error_propagate(errp, err);
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+ qdev_get_gpio_in(armv7m, spi_irq[i]));
+
+ /* Alias controller SPI bus to the SoC itself */
+ object_property_add_alias(OBJECT(s), bus_name,
+ OBJECT(&s->spi[i]), "spi0",
+ &error_abort);
+ g_free(bus_name);
+ }
+}
+
+static Property msf2_soc_properties[] = {
+ DEFINE_PROP_STRING("cpu-model", MSF2State, cpu_model),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void msf2_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = msf2_soc_realize;
+ dc->props = msf2_soc_properties;
+}
+
+static const TypeInfo msf2_soc_info = {
+ .name = TYPE_MSF2_SOC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MSF2State),
+ .instance_init = msf2_soc_initfn,
+ .class_init = msf2_soc_class_init,
+};
+
+static void msf2_soc_types(void)
+{
+ type_register_static(&msf2_soc_info);
+}
+
+type_init(msf2_soc_types)
diff --git a/include/hw/arm/msf2_soc.h b/include/hw/arm/msf2_soc.h
new file mode 100644
index 0000000..1184d9a
--- /dev/null
+++ b/include/hw/arm/msf2_soc.h
@@ -0,0 +1,62 @@
+/*
+ * Microsemi Smartfusion2 SoC
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_ARM_MSF2_SOC_H
+#define HW_ARM_MSF2_SOC_H
+
+#include "hw/misc/msf2_sysreg.h"
+#include "hw/timer/msf2_timer.h"
+#include "hw/ssi/msf2_spi.h"
+#include "hw/arm/armv7m.h"
+
+#define TYPE_MSF2_SOC "msf2-soc"
+#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
+
+#define MSF2_NUM_SPIS 2
+#define MSF2_NUM_UARTS 2
+
+#define ENVM_BASE_ADDRESS 0x60000000
+#define ENVM_SIZE (128 * 1024)
+
+#define DDR_BASE_ADDRESS 0xA0000000
+#define DDR_SIZE (64 * 1024 * 1024)
+
+#define SRAM_BASE_ADDRESS 0x20000000
+#define SRAM_SIZE (64 * 1024)
+
+typedef struct MSF2State {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ char *cpu_model;
+
+ ARMv7MState armv7m;
+
+ MSF2SysregState sysreg;
+ MSF2TimerState timer;
+ MSF2SpiState spi[MSF2_NUM_SPIS];
+} MSF2State;
+
+#endif
--
2.5.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [Qemu-devel RFC v3 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit.
2017-04-28 16:51 [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (3 preceding siblings ...)
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
@ 2017-04-28 16:51 ` Subbaraya Sundeep
2017-04-28 17:20 ` [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC no-reply
5 siblings, 0 replies; 16+ messages in thread
From: Subbaraya Sundeep @ 2017-04-28 16:51 UTC (permalink / raw)
To: qemu-devel, qemu-arm
Cc: peter.maydell, crosthwaite.peter, alistair23, Subbaraya Sundeep
Emulated Emcraft's Smartfusion2 System On Module starter
kit.
Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
---
hw/arm/Makefile.objs | 1 +
hw/arm/msf2_som.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+)
create mode 100644 hw/arm/msf2_som.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index cce2759..d0b7093 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,6 +5,7 @@ obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o msf2_soc.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
obj-$(CONFIG_ACPI) += virt-acpi-build.o
obj-y += netduino2.o
+obj-y += msf2_som.o
obj-y += sysbus-fdt.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
diff --git a/hw/arm/msf2_som.c b/hw/arm/msf2_som.c
new file mode 100644
index 0000000..c41edd5
--- /dev/null
+++ b/hw/arm/msf2_som.c
@@ -0,0 +1,68 @@
+/*
+ * SmartFusion2 SOM starter kit(from Emcraft) emulation.
+ *
+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/boards.h"
+#include "hw/arm/msf2_soc.h"
+#include "hw/arm/arm.h"
+
+static void msf2_init(MachineState *machine)
+{
+ DeviceState *dev;
+ DeviceState *spi_flash;
+ MSF2State *soc;
+ DriveInfo *dinfo = drive_get_next(IF_MTD);
+ qemu_irq cs_line;
+ SSIBus *spi_bus;
+
+ dev = qdev_create(NULL, TYPE_MSF2_SOC);
+ qdev_prop_set_string(dev, "cpu-model", "cortex-m3");
+ object_property_set_bool(OBJECT(dev), true, "realized", &error_fatal);
+
+ soc = MSF2_SOC(dev);
+
+ /* Attach SPI flash to SPI0 controller */
+ spi_bus = (SSIBus *)qdev_get_child_bus(dev, "spi0");
+ spi_flash = ssi_create_slave_no_init(spi_bus, "s25sl12801");
+ qdev_prop_set_uint8(spi_flash, "spansion-cr2nv", 1);
+ if (dinfo) {
+ qdev_prop_set_drive(spi_flash, "drive", blk_by_legacy_dinfo(dinfo),
+ &error_fatal);
+ }
+ qdev_init_nofail(spi_flash);
+ cs_line = qdev_get_gpio_in_named(spi_flash, SSI_GPIO_CS, 0);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&soc->spi[0]), 1, cs_line);
+
+ armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,
+ ENVM_SIZE);
+}
+
+static void msf2_machine_init(MachineClass *mc)
+{
+ mc->desc = "SmartFusion2 SOM kit from Emcraft";
+ mc->init = msf2_init;
+}
+
+DEFINE_MACHINE("smartfusion2-som", msf2_machine_init)
--
2.5.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC
2017-04-28 16:51 [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
` (4 preceding siblings ...)
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
@ 2017-04-28 17:20 ` no-reply
5 siblings, 0 replies; 16+ messages in thread
From: no-reply @ 2017-04-28 17:20 UTC (permalink / raw)
To: sundeep.lkml
Cc: famz, qemu-devel, qemu-arm, peter.maydell, alistair23, crosthwaite.peter
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com
Subject: [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
make docker-test-quick@centos6
make docker-test-mingw@fedora
make docker-test-build@min-glib
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com -> patchew/1493398313-6673-1-git-send-email-sundeep.lkml@gmail.com
- [tag update] patchew/20170425103049.4073-1-quintela@redhat.com -> patchew/20170425103049.4073-1-quintela@redhat.com
- [tag update] patchew/20170427120006.20564-1-rth@twiddle.net -> patchew/20170427120006.20564-1-rth@twiddle.net
Switched to a new branch 'test'
cf0f888 msf2: Add Emcraft's Smartfusion2 SOM kit.
3b2bcbc msf2: Add Smartfusion2 SoC.
20212c0 msf2: Add Smartfusion2 SPI controller
f077366 msf2: Microsemi Smartfusion2 System Register block.
45363b4 msf2: Add Smartfusion2 System timer
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-tjgugl52/src/dtc'...
Submodule path 'dtc': checked out '558cd81bdd432769b59bff01240c44f82cfb1a9d'
BUILD centos6
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-tjgugl52/src'
ARCHIVE qemu.tgz
ARCHIVE dtc.tgz
COPY RUNNER
RUN test-quick in qemu:centos6
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
ccache-3.1.6-2.el6.x86_64
epel-release-6-8.noarch
gcc-4.4.7-17.el6.x86_64
git-1.7.1-4.el6_7.1.x86_64
glib2-devel-2.28.8-5.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
make-3.81-23.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
tar-1.23-15.el6_8.x86_64
zlib-devel-1.2.3-29.el6.x86_64
Environment variables:
PACKAGES=libfdt-devel ccache tar git make gcc g++ zlib-devel glib2-devel SDL-devel pixman-devel epel-release
HOSTNAME=0e4385092ea7
TERM=xterm
MAKEFLAGS= -j8
HISTSIZE=1000
J=8
USER=root
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
MAIL=/var/spool/mail/root
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
LANG=en_US.UTF-8
TARGET_LIST=
HISTCONTROL=ignoredups
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
LOGNAME=root
LESSOPEN=||/usr/bin/lesspipe.sh %s
FEATURES= dtc
DEBUG=
G_BROKEN_FILENAMES=1
CCACHE_HASHDIR=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install
grep: scripts/tracetool/backend/*.py: No such file or directory
No C++ compiler available; disabling C++ specific optional code
Install prefix /var/tmp/qemu-build/install
BIOS directory /var/tmp/qemu-build/install/share/qemu
binary directory /var/tmp/qemu-build/install/bin
library directory /var/tmp/qemu-build/install/lib
module directory /var/tmp/qemu-build/install/lib/qemu
libexec directory /var/tmp/qemu-build/install/libexec
include directory /var/tmp/qemu-build/install/include
config directory /var/tmp/qemu-build/install/etc
local state directory /var/tmp/qemu-build/install/var
Manual directory /var/tmp/qemu-build/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /tmp/qemu-test/src
C compiler cc
Host C compiler cc
C++ compiler
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all
LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
tcg debug enabled no
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
pixman system
SDL support yes (1.2.14)
GTK support no
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support no
GNUTLS rnd no
libgcrypt no
libgcrypt kdf no
nettle no
nettle kdf no
libtasn1 no
curses support no
virgl support no
curl support no
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
VNC support yes
VNC SASL support no
VNC JPEG support no
VNC PNG support no
xen support no
brlapi support no
bluez support no
Documentation no
PIE yes
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
RDMA support no
TCG interpreter no
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support no
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
Trace backends log
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough yes
QOM debugging yes
lzo support no
snappy support no
bzip2 support no
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
mkdir -p dtc/libfdt
mkdir -p dtc/tests
GEN x86_64-softmmu/config-devices.mak.tmp
GEN aarch64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN x86_64-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN qmp-marshal.c
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.h
GEN qmp-introspect.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN backends/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN backends/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/srcpos.c
BISON dtc-parser.tab.c
make[1]: bison: Command not found
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
make[1]: flex: Command not found
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
CHK version_gen.h
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
BISON dtc-parser.tab.c
LEX dtc-lexer.lex.c
make[1]: bison: Command not found
make[1]: flex: Command not found
UPD version_gen.h
DEP /tmp/qemu-test/src/dtc/util.c
LEX convert-dtsv0-lexer.lex.c
BISON dtc-parser.tab.c
make[1]: flex: Command not found
LEX dtc-lexer.lex.c
make[1]: bison: Command not found
make[1]: flex: Command not found
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
BISON dtc-parser.tab.c
LEX dtc-lexer.lex.c
make[1]: bison: Command not found
make[1]: flex: Command not found
CC tests/qemu-iotests/socket_scm_helper.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qmp-introspect.o
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qint.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qfloat.o
CC qobject/qbool.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-posix.o
CC util/compatfd.o
CC util/event_notifier-posix.o
CC util/mmap-alloc.o
CC util/qemu-openpty.o
CC util/oslib-posix.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/coroutine-ucontext.o
CC util/qemu-coroutine-sleep.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/qdist.o
CC util/qht.o
CC util/systemd.o
CC util/range.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC backends/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/usb/trace.o
CC hw/misc/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/xen/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/i386/trace.o
CC target/arm/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/qmp_pc_dimm_device_list.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC block.o
CC blockjob.o
CC qemu-io-cmds.o
CC block/raw-format.o
CC block/qcow.o
CC replication.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qed.o
CC block/qed-gencb.o
CC block/qed-table.o
CC block/qed-l2-cache.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/quorum.o
CC block/vhdx-log.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-posix.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/sheepdog.o
CC block/nbd-client.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/backup.o
CC block/replication.o
CC block/write-threshold.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-glib.o
CC crypto/hmac.o
CC crypto/aes.o
CC crypto/hmac-glib.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/secret.o
CC crypto/random-platform.o
CC crypto/pbkdf.o
CC crypto/ivgen.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC crypto/block.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-websock.o
CC io/channel-watch.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
GEN qemu-img-cmds.h
CC qemu-io.o
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC page_cache.o
CC accel.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC audio/audio.o
CC cpus-common.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/rng-random.o
CC backends/msmouse.o
CC backends/wctablet.o
CC backends/testdev.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC disas/arm.o
CC block/stream.o
CC disas/i386.o
CC fsdev/qemu-fsdev-dummy.o
CC fsdev/qemu-fsdev-throttle.o
CC fsdev/qemu-fsdev-opts.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/vmgenid.o
CC hw/acpi/nvdimm.o
CC hw/acpi/aml-build.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/ipmi.o
CC hw/audio/sb16.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/hda-codec.o
CC hw/audio/intel-hda.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi02.o
CC hw/block/pflash_cfi01.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/char/parallel.o
CC hw/char/ipoctal232.o
CC hw/bt/hci-csr.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/cadence_uart.o
CC hw/char/imx_serial.o
CC hw/char/debugcon.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ads7846.o
CC hw/display/ssd0323.o
CC hw/display/ssd0303.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/framebuffer.o
CC hw/display/exynos4210_fimd.o
CC hw/display/tc6393xb.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-host.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/unimp.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/net/pcnet-pci.o
CC hw/net/eepro100.o
CC hw/net/ne2000.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_rx_pkt.o
CC hw/net/net_tx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/smc91c111.o
CC hw/net/vmxnet3.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
CC hw/net/allwinner_emac.o
CC hw/net/cadence_gem.o
CC hw/net/imx_fec.o
CC hw/net/stellaris_enet.o
CC hw/net/ftgmac100.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/nvram/eeprom93xx.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/chrp_nvram.o
CC hw/nvram/fw_cfg.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-host/pam.o
CC hw/pci-host/versatile.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_port.o
CC hw/pci/pcie_aer.o
CC hw/pcmcia/pcmcia.o
CC hw/pci/pci-stub.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/megasas.o
CC hw/scsi/mptendian.o
CC hw/scsi/mptconfig.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/smbios/smbios-stub.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/ssi/msf2_spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/pl031.o
CC hw/timer/twl92230.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/msf2_timer.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_passthrough.o
CC hw/tpm/tpm_util.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-hid.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/dev-mtp.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/watchdog/watchdog.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_aspeed.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/colo.o
CC migration/colo-comm.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/qemu-file.o
CC migration/qemu-file-channel.o
CC migration/postcopy-ram.o
CC migration/xbzrle.o
CC migration/qjson.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/l2tpv3.o
CC net/tap.o
CC net/tap-linux.o
CC net/vhost-user.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
/tmp/qemu-test/src/replay/replay-internal.c: In function ‘replay_put_array’:
/tmp/qemu-test/src/replay/replay-internal.c:65: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
CC replay/replay-net.o
CC replay/replay-audio.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/ip6_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/tcp_input.o
CC slirp/socket.o
CC slirp/tcp_output.o
/tmp/qemu-test/src/slirp/tcp_input.c: In function ‘tcp_input’:
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_p’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_len’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_tos’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_id’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_off’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_ttl’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_sum’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_src.s_addr’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: ‘save_ip.ip_dst.s_addr’ may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:220: warning: ‘save_ip6.ip_nh’ may be used uninitialized in this function
CC slirp/tcp_subr.o
CC slirp/udp.o
CC slirp/tcp_timer.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC ui/keymaps.o
CC slirp/ncsi.o
CC ui/console.o
CC ui/qemu-pixman.o
CC ui/cursor.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/input-linux.o
CC ui/sdl.o
CC ui/sdl_zoom.o
CC ui/x_keymap.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-ws.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-jobs.o
CC chardev/char.o
CC chardev/char-fd.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-null.o
CC chardev/char-parallel.o
CC chardev/char-pipe.o
CC chardev/char-pty.o
CC chardev/char-ringbuf.o
CC chardev/char-serial.o
CC chardev/char-socket.o
CC chardev/char-stdio.o
CC chardev/char-udp.o
LINK tests/qemu-iotests/socket_scm_helper
CC qga/commands.o
CC qga/guest-agent-command-state.o
CC qga/commands-posix.o
CC qga/main.o
CC qga/channel-posix.o
CC qga/qapi-generated/qga-qapi-types.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
AR libqemuutil.a
AR libqemustub.a
CC qemu-img.o
CC optionrom/linuxboot_dma.o
AS optionrom/multiboot.o
AS optionrom/linuxboot.o
cc: unrecognized option '-no-integrated-as'
cc: unrecognized option '-no-integrated-as'
BUILD optionrom/linuxboot_dma.img
AS optionrom/kvmvapic.o
BUILD optionrom/linuxboot_dma.raw
BUILD optionrom/multiboot.img
BUILD optionrom/linuxboot.img
BUILD optionrom/multiboot.raw
BUILD optionrom/linuxboot.raw
BUILD optionrom/kvmvapic.img
BUILD optionrom/kvmvapic.raw
SIGN optionrom/linuxboot_dma.bin
SIGN optionrom/kvmvapic.bin
SIGN optionrom/linuxboot.bin
SIGN optionrom/multiboot.bin
LINK qemu-ga
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
LINK qemu-img
LINK qemu-io
LINK qemu-bridge-helper
GEN x86_64-softmmu/hmp-commands.h
GEN x86_64-softmmu/hmp-commands-info.h
GEN x86_64-softmmu/config-target.h
GEN aarch64-softmmu/hmp-commands.h
GEN aarch64-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/config-target.h
CC x86_64-softmmu/exec.o
CC x86_64-softmmu/cpu-exec-common.o
CC x86_64-softmmu/cpu-exec.o
CC x86_64-softmmu/translate-common.o
CC x86_64-softmmu/translate-all.o
CC x86_64-softmmu/tcg/tcg.o
CC x86_64-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/tcg/optimize.o
CC x86_64-softmmu/tcg/tcg-common.o
CC x86_64-softmmu/fpu/softfloat.o
CC x86_64-softmmu/disas.o
CC x86_64-softmmu/tcg-runtime.o
CC x86_64-softmmu/hax-stub.o
CC x86_64-softmmu/arch_init.o
CC x86_64-softmmu/cpus.o
CC x86_64-softmmu/monitor.o
CC x86_64-softmmu/gdbstub.o
CC x86_64-softmmu/balloon.o
CC x86_64-softmmu/numa.o
CC x86_64-softmmu/ioport.o
CC x86_64-softmmu/qtest.o
CC x86_64-softmmu/bootdevice.o
CC x86_64-softmmu/kvm-all.o
CC x86_64-softmmu/memory.o
CC x86_64-softmmu/cputlb.o
CC x86_64-softmmu/memory_mapping.o
CC x86_64-softmmu/dump.o
CC x86_64-softmmu/migration/ram.o
CC x86_64-softmmu/migration/savevm.o
CC aarch64-softmmu/exec.o
CC aarch64-softmmu/translate-all.o
CC x86_64-softmmu/hw/block/virtio-blk.o
CC aarch64-softmmu/translate-common.o
CC aarch64-softmmu/cpu-exec.o
CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
CC aarch64-softmmu/cpu-exec-common.o
CC aarch64-softmmu/tcg/tcg.o
CC x86_64-softmmu/hw/char/virtio-serial-bus.o
CC aarch64-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/tcg/optimize.o
CC aarch64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/fpu/softfloat.o
CC x86_64-softmmu/hw/core/nmi.o
CC x86_64-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/disas.o
CC x86_64-softmmu/hw/core/null-machine.o
CC aarch64-softmmu/tcg-runtime.o
CC aarch64-softmmu/hax-stub.o
GEN aarch64-softmmu/gdbstub-xml.c
CC x86_64-softmmu/hw/cpu/core.o
CC x86_64-softmmu/hw/display/vga.o
CC aarch64-softmmu/kvm-stub.o
CC x86_64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/arch_init.o
CC x86_64-softmmu/hw/display/virtio-gpu-3d.o
CC aarch64-softmmu/cpus.o
CC x86_64-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/monitor.o
CC x86_64-softmmu/hw/display/virtio-vga.o
CC x86_64-softmmu/hw/intc/apic.o
CC aarch64-softmmu/gdbstub.o
CC x86_64-softmmu/hw/intc/apic_common.o
CC x86_64-softmmu/hw/intc/ioapic.o
CC aarch64-softmmu/balloon.o
CC x86_64-softmmu/hw/isa/lpc_ich9.o
CC aarch64-softmmu/ioport.o
CC x86_64-softmmu/hw/misc/vmport.o
CC x86_64-softmmu/hw/misc/ivshmem.o
CC aarch64-softmmu/numa.o
CC x86_64-softmmu/hw/misc/pvpanic.o
CC x86_64-softmmu/hw/misc/edu.o
CC aarch64-softmmu/qtest.o
CC aarch64-softmmu/bootdevice.o
CC x86_64-softmmu/hw/misc/hyperv_testdev.o
CC x86_64-softmmu/hw/net/virtio-net.o
CC x86_64-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/memory.o
CC x86_64-softmmu/hw/scsi/virtio-scsi.o
CC aarch64-softmmu/memory_mapping.o
CC aarch64-softmmu/cputlb.o
CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC x86_64-softmmu/hw/scsi/vhost-scsi.o
CC aarch64-softmmu/dump.o
CC x86_64-softmmu/hw/timer/mc146818rtc.o
CC aarch64-softmmu/migration/ram.o
CC aarch64-softmmu/migration/savevm.o
CC x86_64-softmmu/hw/vfio/common.o
CC x86_64-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
CC aarch64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/hw/vfio/pci-quirks.o
CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
CC aarch64-softmmu/hw/char/exynos4210_uart.o
CC aarch64-softmmu/hw/char/omap_uart.o
CC aarch64-softmmu/hw/char/digic-uart.o
CC x86_64-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
CC x86_64-softmmu/hw/vfio/spapr.o
CC x86_64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/char/bcm2835_aux.o
CC x86_64-softmmu/hw/virtio/virtio-balloon.o
CC aarch64-softmmu/hw/core/nmi.o
CC aarch64-softmmu/hw/char/virtio-serial-bus.o
CC x86_64-softmmu/hw/virtio/vhost.o
CC aarch64-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/hw/core/null-machine.o
CC aarch64-softmmu/hw/cpu/arm11mpcore.o
CC aarch64-softmmu/hw/cpu/realview_mpcore.o
CC aarch64-softmmu/hw/cpu/a9mpcore.o
CC x86_64-softmmu/hw/virtio/vhost-backend.o
CC x86_64-softmmu/hw/virtio/vhost-user.o
CC x86_64-softmmu/hw/virtio/vhost-vsock.o
CC aarch64-softmmu/hw/cpu/a15mpcore.o
CC aarch64-softmmu/hw/cpu/core.o
CC x86_64-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-softmmu/hw/display/omap_dss.o
CC aarch64-softmmu/hw/display/omap_lcdc.o
CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
CC x86_64-softmmu/hw/virtio/virtio-crypto-pci.o
CC x86_64-softmmu/hw/i386/multiboot.o
CC aarch64-softmmu/hw/display/bcm2835_fb.o
CC aarch64-softmmu/hw/display/vga.o
CC x86_64-softmmu/hw/i386/pc.o
CC aarch64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/hw/display/dpcd.o
CC aarch64-softmmu/hw/display/xlnx_dp.o
CC x86_64-softmmu/hw/i386/pc_piix.o
CC x86_64-softmmu/hw/i386/pc_q35.o
CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
CC aarch64-softmmu/hw/dma/omap_dma.o
CC aarch64-softmmu/hw/dma/soc_dma.o
/tmp/qemu-test/src/hw/i386/pc_piix.c: In function ‘igd_passthrough_isa_bridge_create’:
/tmp/qemu-test/src/hw/i386/pc_piix.c:1055: warning: ‘pch_rev_id’ may be used uninitialized in this function
CC x86_64-softmmu/hw/i386/pc_sysfw.o
CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
CC aarch64-softmmu/hw/dma/bcm2835_dma.o
CC x86_64-softmmu/hw/i386/x86-iommu.o
CC x86_64-softmmu/hw/i386/intel_iommu.o
CC x86_64-softmmu/hw/i386/amd_iommu.o
CC aarch64-softmmu/hw/gpio/omap_gpio.o
CC x86_64-softmmu/hw/i386/kvmvapic.o
CC x86_64-softmmu/hw/i386/acpi-build.o
CC aarch64-softmmu/hw/gpio/imx_gpio.o
CC x86_64-softmmu/hw/i386/pci-assign-load-rom.o
/tmp/qemu-test/src/hw/i386/acpi-build.c: In function ‘build_append_pci_bus_devices’:
/tmp/qemu-test/src/hw/i386/acpi-build.c:496: warning: ‘notify_method’ may be used uninitialized in this function
CC x86_64-softmmu/hw/i386/kvm/clock.o
CC aarch64-softmmu/hw/gpio/bcm2835_gpio.o
CC aarch64-softmmu/hw/i2c/omap_i2c.o
CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
CC x86_64-softmmu/hw/i386/kvm/apic.o
CC aarch64-softmmu/hw/input/tsc210x.o
CC aarch64-softmmu/hw/intc/armv7m_nvic.o
CC aarch64-softmmu/hw/intc/exynos4210_gic.o
CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
CC aarch64-softmmu/hw/intc/omap_intc.o
CC aarch64-softmmu/hw/intc/bcm2835_ic.o
CC aarch64-softmmu/hw/intc/bcm2836_control.o
CC x86_64-softmmu/hw/i386/kvm/i8259.o
CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
CC aarch64-softmmu/hw/intc/aspeed_vic.o
CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
CC aarch64-softmmu/hw/misc/ivshmem.o
CC aarch64-softmmu/hw/misc/arm_sysctl.o
CC aarch64-softmmu/hw/misc/cbus.o
CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
CC aarch64-softmmu/hw/misc/exynos4210_clk.o
CC aarch64-softmmu/hw/misc/imx_ccm.o
CC aarch64-softmmu/hw/misc/imx31_ccm.o
CC aarch64-softmmu/hw/misc/imx25_ccm.o
CC aarch64-softmmu/hw/misc/imx6_ccm.o
CC aarch64-softmmu/hw/misc/imx6_src.o
CC aarch64-softmmu/hw/misc/mst_fpga.o
CC aarch64-softmmu/hw/misc/omap_clk.o
CC aarch64-softmmu/hw/misc/omap_gpmc.o
CC aarch64-softmmu/hw/misc/omap_l4.o
CC x86_64-softmmu/hw/i386/kvm/ioapic.o
CC x86_64-softmmu/hw/i386/kvm/i8254.o
CC x86_64-softmmu/hw/i386/kvm/pci-assign.o
CC aarch64-softmmu/hw/misc/omap_sdrc.o
CC aarch64-softmmu/hw/misc/omap_tap.o
CC aarch64-softmmu/hw/misc/bcm2835_mbox.o
CC aarch64-softmmu/hw/misc/bcm2835_property.o
CC x86_64-softmmu/target/i386/translate.o
CC aarch64-softmmu/hw/misc/bcm2835_rng.o
CC x86_64-softmmu/target/i386/helper.o
CC aarch64-softmmu/hw/misc/zynq_slcr.o
CC aarch64-softmmu/hw/misc/zynq-xadc.o
CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o
CC aarch64-softmmu/hw/misc/edu.o
CC aarch64-softmmu/hw/misc/auxbus.o
CC aarch64-softmmu/hw/misc/aspeed_scu.o
CC aarch64-softmmu/hw/misc/aspeed_sdmc.o
CC aarch64-softmmu/hw/misc/msf2_sysreg.o
CC aarch64-softmmu/hw/net/virtio-net.o
CC aarch64-softmmu/hw/net/vhost_net.o
CC aarch64-softmmu/hw/pcmcia/pxa2xx.o
CC aarch64-softmmu/hw/scsi/virtio-scsi.o
CC x86_64-softmmu/target/i386/cpu.o
CC x86_64-softmmu/target/i386/bpt_helper.o
CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC x86_64-softmmu/target/i386/excp_helper.o
CC x86_64-softmmu/target/i386/fpu_helper.o
CC x86_64-softmmu/target/i386/cc_helper.o
CC x86_64-softmmu/target/i386/int_helper.o
CC x86_64-softmmu/target/i386/svm_helper.o
CC x86_64-softmmu/target/i386/smm_helper.o
CC x86_64-softmmu/target/i386/misc_helper.o
CC aarch64-softmmu/hw/scsi/vhost-scsi.o
CC x86_64-softmmu/target/i386/mem_helper.o
CC x86_64-softmmu/target/i386/seg_helper.o
CC x86_64-softmmu/target/i386/mpx_helper.o
CC x86_64-softmmu/target/i386/gdbstub.o
CC x86_64-softmmu/target/i386/machine.o
CC aarch64-softmmu/hw/sd/omap_mmc.o
CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o
CC aarch64-softmmu/hw/sd/bcm2835_sdhost.o
CC aarch64-softmmu/hw/ssi/omap_spi.o
CC aarch64-softmmu/hw/ssi/imx_spi.o
CC x86_64-softmmu/target/i386/arch_memory_mapping.o
CC x86_64-softmmu/target/i386/arch_dump.o
CC aarch64-softmmu/hw/timer/exynos4210_mct.o
CC x86_64-softmmu/target/i386/monitor.o
CC aarch64-softmmu/hw/timer/exynos4210_pwm.o
CC x86_64-softmmu/target/i386/kvm.o
CC aarch64-softmmu/hw/timer/exynos4210_rtc.o
CC aarch64-softmmu/hw/timer/omap_gptimer.o
CC aarch64-softmmu/hw/timer/omap_synctimer.o
CC aarch64-softmmu/hw/timer/pxa2xx_timer.o
CC aarch64-softmmu/hw/timer/digic-timer.o
CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o
CC x86_64-softmmu/target/i386/hyperv.o
CC aarch64-softmmu/hw/usb/tusb6010.o
CC aarch64-softmmu/hw/vfio/common.o
CC aarch64-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/vfio/pci-quirks.o
CC aarch64-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/vfio/calxeda-xgmac.o
CC aarch64-softmmu/hw/vfio/amd-xgbe.o
CC aarch64-softmmu/hw/vfio/spapr.o
CC aarch64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/virtio/virtio-balloon.o
CC aarch64-softmmu/hw/virtio/vhost.o
CC aarch64-softmmu/hw/virtio/vhost-backend.o
GEN trace/generated-helpers.c
CC x86_64-softmmu/trace/control-target.o
CC aarch64-softmmu/hw/virtio/vhost-user.o
CC aarch64-softmmu/hw/virtio/vhost-vsock.o
CC aarch64-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-softmmu/hw/virtio/virtio-crypto-pci.o
CC aarch64-softmmu/hw/arm/boot.o
CC aarch64-softmmu/hw/arm/collie.o
CC aarch64-softmmu/hw/arm/exynos4_boards.o
CC aarch64-softmmu/hw/arm/gumstix.o
CC aarch64-softmmu/hw/arm/highbank.o
CC aarch64-softmmu/hw/arm/digic_boards.o
CC aarch64-softmmu/hw/arm/integratorcp.o
CC aarch64-softmmu/hw/arm/mainstone.o
CC aarch64-softmmu/hw/arm/musicpal.o
CC aarch64-softmmu/hw/arm/nseries.o
CC aarch64-softmmu/hw/arm/omap_sx1.o
CC aarch64-softmmu/hw/arm/palm.o
CC aarch64-softmmu/hw/arm/realview.o
CC aarch64-softmmu/hw/arm/spitz.o
CC aarch64-softmmu/hw/arm/stellaris.o
CC aarch64-softmmu/hw/arm/msf2_soc.o
CC aarch64-softmmu/hw/arm/tosa.o
CC aarch64-softmmu/hw/arm/versatilepb.o
CC aarch64-softmmu/hw/arm/vexpress.o
CC aarch64-softmmu/hw/arm/virt.o
CC aarch64-softmmu/hw/arm/xilinx_zynq.o
CC aarch64-softmmu/hw/arm/z2.o
CC aarch64-softmmu/hw/arm/virt-acpi-build.o
CC aarch64-softmmu/hw/arm/netduino2.o
CC aarch64-softmmu/hw/arm/msf2_som.o
CC aarch64-softmmu/hw/arm/armv7m.o
CC aarch64-softmmu/hw/arm/exynos4210.o
CC aarch64-softmmu/hw/arm/sysbus-fdt.o
CC aarch64-softmmu/hw/arm/pxa2xx.o
CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o
CC aarch64-softmmu/hw/arm/digic.o
CC aarch64-softmmu/hw/arm/pxa2xx_pic.o
CC aarch64-softmmu/hw/arm/omap1.o
CC aarch64-softmmu/hw/arm/omap2.o
CC aarch64-softmmu/hw/arm/strongarm.o
CC aarch64-softmmu/hw/arm/allwinner-a10.o
CC aarch64-softmmu/hw/arm/cubieboard.o
CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o
CC aarch64-softmmu/hw/arm/bcm2836.o
CC aarch64-softmmu/hw/arm/raspi.o
CC aarch64-softmmu/hw/arm/stm32f205_soc.o
CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o
CC aarch64-softmmu/hw/arm/xlnx-ep108.o
CC aarch64-softmmu/hw/arm/fsl-imx25.o
CC aarch64-softmmu/hw/arm/imx25_pdk.o
CC aarch64-softmmu/hw/arm/fsl-imx31.o
CC aarch64-softmmu/hw/arm/kzm.o
CC aarch64-softmmu/hw/arm/fsl-imx6.o
CC aarch64-softmmu/hw/arm/sabrelite.o
CC aarch64-softmmu/hw/arm/aspeed_soc.o
CC aarch64-softmmu/target/arm/arm-semi.o
CC aarch64-softmmu/hw/arm/aspeed.o
CC aarch64-softmmu/target/arm/machine.o
CC aarch64-softmmu/target/arm/psci.o
CC aarch64-softmmu/target/arm/arch_dump.o
CC aarch64-softmmu/target/arm/monitor.o
CC aarch64-softmmu/target/arm/kvm-stub.o
CC aarch64-softmmu/target/arm/translate.o
CC aarch64-softmmu/target/arm/op_helper.o
CC aarch64-softmmu/target/arm/helper.o
CC aarch64-softmmu/target/arm/cpu.o
CC aarch64-softmmu/target/arm/neon_helper.o
CC aarch64-softmmu/target/arm/iwmmxt_helper.o
CC x86_64-softmmu/trace/generated-helpers.o
CC aarch64-softmmu/target/arm/gdbstub.o
LINK x86_64-softmmu/qemu-system-x86_64
CC aarch64-softmmu/target/arm/cpu64.o
CC aarch64-softmmu/target/arm/translate-a64.o
CC aarch64-softmmu/target/arm/helper-a64.o
CC aarch64-softmmu/target/arm/gdbstub64.o
CC aarch64-softmmu/target/arm/crypto_helper.o
CC aarch64-softmmu/target/arm/arm-powerctl.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/trace/control-target.o
CC aarch64-softmmu/gdbstub-xml.o
CC aarch64-softmmu/trace/generated-helpers.o
/tmp/qemu-test/src/target/arm/translate-a64.c: In function ‘handle_shri_with_rndacc’:
/tmp/qemu-test/src/target/arm/translate-a64.c:6359: warning: ‘tcg_src_hi’ may be used uninitialized in this function
/tmp/qemu-test/src/target/arm/translate-a64.c: In function ‘disas_simd_scalar_two_reg_misc’:
/tmp/qemu-test/src/target/arm/translate-a64.c:8086: warning: ‘rmode’ may be used uninitialized in this function
LINK aarch64-softmmu/qemu-system-aarch64
LEX convert-dtsv0-lexer.lex.c
make[1]: flex: Command not found
BISON dtc-parser.tab.c
make[1]: bison: Command not found
LEX dtc-lexer.lex.c
make[1]: flex: Command not found
TEST tests/qapi-schema/alternate-any.out
TEST tests/qapi-schema/alternate-array.out
TEST tests/qapi-schema/alternate-base.out
TEST tests/qapi-schema/alternate-clash.out
TEST tests/qapi-schema/alternate-conflict-dict.out
TEST tests/qapi-schema/alternate-conflict-string.out
TEST tests/qapi-schema/alternate-nested.out
TEST tests/qapi-schema/alternate-empty.out
TEST tests/qapi-schema/alternate-unknown.out
TEST tests/qapi-schema/args-alternate.out
TEST tests/qapi-schema/args-any.out
TEST tests/qapi-schema/args-array-empty.out
TEST tests/qapi-schema/args-array-unknown.out
TEST tests/qapi-schema/args-bad-boxed.out
TEST tests/qapi-schema/args-boxed-anon.out
TEST tests/qapi-schema/args-boxed-empty.out
TEST tests/qapi-schema/args-boxed-string.out
TEST tests/qapi-schema/args-int.out
TEST tests/qapi-schema/args-invalid.out
TEST tests/qapi-schema/args-member-array-bad.out
TEST tests/qapi-schema/args-member-case.out
TEST tests/qapi-schema/args-member-unknown.out
TEST tests/qapi-schema/args-name-clash.out
TEST tests/qapi-schema/args-union.out
TEST tests/qapi-schema/args-unknown.out
TEST tests/qapi-schema/bad-base.out
TEST tests/qapi-schema/bad-data.out
TEST tests/qapi-schema/bad-ident.out
TEST tests/qapi-schema/bad-type-bool.out
TEST tests/qapi-schema/bad-type-dict.out
TEST tests/qapi-schema/bad-type-int.out
TEST tests/qapi-schema/base-cycle-direct.out
TEST tests/qapi-schema/base-cycle-indirect.out
TEST tests/qapi-schema/command-int.out
TEST tests/qapi-schema/comments.out
TEST tests/qapi-schema/doc-bad-alternate-member.out
TEST tests/qapi-schema/doc-bad-symbol.out
TEST tests/qapi-schema/doc-bad-union-member.out
TEST tests/qapi-schema/doc-bad-command-arg.out
TEST tests/qapi-schema/doc-before-include.out
TEST tests/qapi-schema/doc-before-pragma.out
TEST tests/qapi-schema/doc-duplicated-arg.out
TEST tests/qapi-schema/doc-duplicated-return.out
TEST tests/qapi-schema/doc-duplicated-since.out
TEST tests/qapi-schema/doc-empty-arg.out
TEST tests/qapi-schema/doc-empty-section.out
TEST tests/qapi-schema/doc-empty-symbol.out
TEST tests/qapi-schema/doc-good.out
TEST tests/qapi-schema/doc-interleaved-section.out
TEST tests/qapi-schema/doc-invalid-end.out
TEST tests/qapi-schema/doc-invalid-end2.out
TEST tests/qapi-schema/doc-invalid-return.out
TEST tests/qapi-schema/doc-invalid-section.out
TEST tests/qapi-schema/doc-invalid-start.out
TEST tests/qapi-schema/doc-missing.out
TEST tests/qapi-schema/doc-missing-colon.out
TEST tests/qapi-schema/doc-missing-expr.out
TEST tests/qapi-schema/doc-missing-space.out
TEST tests/qapi-schema/doc-no-symbol.out
TEST tests/qapi-schema/double-data.out
TEST tests/qapi-schema/double-type.out
TEST tests/qapi-schema/duplicate-key.out
TEST tests/qapi-schema/empty.out
TEST tests/qapi-schema/enum-bad-name.out
TEST tests/qapi-schema/enum-bad-prefix.out
TEST tests/qapi-schema/enum-clash-member.out
TEST tests/qapi-schema/enum-dict-member.out
TEST tests/qapi-schema/enum-int-member.out
TEST tests/qapi-schema/enum-missing-data.out
TEST tests/qapi-schema/enum-wrong-data.out
TEST tests/qapi-schema/enum-member-case.out
TEST tests/qapi-schema/escape-outside-string.out
TEST tests/qapi-schema/escape-too-big.out
TEST tests/qapi-schema/escape-too-short.out
TEST tests/qapi-schema/event-boxed-empty.out
TEST tests/qapi-schema/event-case.out
TEST tests/qapi-schema/event-nest-struct.out
TEST tests/qapi-schema/flat-union-array-branch.out
TEST tests/qapi-schema/flat-union-bad-base.out
TEST tests/qapi-schema/flat-union-bad-discriminator.out
TEST tests/qapi-schema/flat-union-base-any.out
TEST tests/qapi-schema/flat-union-base-union.out
TEST tests/qapi-schema/flat-union-clash-member.out
TEST tests/qapi-schema/flat-union-empty.out
TEST tests/qapi-schema/flat-union-incomplete-branch.out
TEST tests/qapi-schema/flat-union-inline.out
TEST tests/qapi-schema/flat-union-int-branch.out
TEST tests/qapi-schema/flat-union-invalid-branch-key.out
TEST tests/qapi-schema/flat-union-invalid-discriminator.out
TEST tests/qapi-schema/flat-union-no-base.out
TEST tests/qapi-schema/flat-union-optional-discriminator.out
TEST tests/qapi-schema/flat-union-string-discriminator.out
TEST tests/qapi-schema/funny-char.out
TEST tests/qapi-schema/ident-with-escape.out
TEST tests/qapi-schema/include-before-err.out
TEST tests/qapi-schema/include-cycle.out
TEST tests/qapi-schema/include-extra-junk.out
TEST tests/qapi-schema/include-format-err.out
TEST tests/qapi-schema/include-nested-err.out
TEST tests/qapi-schema/include-non-file.out
TEST tests/qapi-schema/include-relpath.out
TEST tests/qapi-schema/include-no-file.out
TEST tests/qapi-schema/include-repetition.out
TEST tests/qapi-schema/include-self-cycle.out
TEST tests/qapi-schema/include-simple.out
TEST tests/qapi-schema/indented-expr.out
TEST tests/qapi-schema/leading-comma-list.out
TEST tests/qapi-schema/leading-comma-object.out
TEST tests/qapi-schema/missing-colon.out
TEST tests/qapi-schema/missing-comma-list.out
TEST tests/qapi-schema/missing-comma-object.out
TEST tests/qapi-schema/missing-type.out
TEST tests/qapi-schema/nested-struct-data.out
TEST tests/qapi-schema/non-objects.out
TEST tests/qapi-schema/pragma-doc-required-crap.out
TEST tests/qapi-schema/pragma-extra-junk.out
TEST tests/qapi-schema/pragma-name-case-whitelist-crap.out
TEST tests/qapi-schema/pragma-non-dict.out
TEST tests/qapi-schema/pragma-returns-whitelist-crap.out
TEST tests/qapi-schema/qapi-schema-test.out
TEST tests/qapi-schema/quoted-structural-chars.out
TEST tests/qapi-schema/redefined-builtin.out
TEST tests/qapi-schema/redefined-command.out
TEST tests/qapi-schema/redefined-event.out
TEST tests/qapi-schema/redefined-type.out
TEST tests/qapi-schema/reserved-command-q.out
TEST tests/qapi-schema/reserved-enum-q.out
TEST tests/qapi-schema/reserved-member-has.out
TEST tests/qapi-schema/reserved-member-q.out
TEST tests/qapi-schema/reserved-member-u.out
TEST tests/qapi-schema/reserved-member-underscore.out
TEST tests/qapi-schema/reserved-type-kind.out
TEST tests/qapi-schema/reserved-type-list.out
TEST tests/qapi-schema/returns-alternate.out
TEST tests/qapi-schema/returns-array-bad.out
TEST tests/qapi-schema/returns-dict.out
TEST tests/qapi-schema/returns-unknown.out
TEST tests/qapi-schema/returns-whitelist.out
TEST tests/qapi-schema/struct-base-clash-deep.out
TEST tests/qapi-schema/struct-data-invalid.out
TEST tests/qapi-schema/struct-base-clash.out
TEST tests/qapi-schema/struct-member-invalid.out
TEST tests/qapi-schema/trailing-comma-list.out
TEST tests/qapi-schema/trailing-comma-object.out
TEST tests/qapi-schema/type-bypass-bad-gen.out
TEST tests/qapi-schema/unclosed-list.out
TEST tests/qapi-schema/unclosed-object.out
TEST tests/qapi-schema/unclosed-string.out
TEST tests/qapi-schema/unicode-str.out
TEST tests/qapi-schema/union-base-empty.out
TEST tests/qapi-schema/union-base-no-discriminator.out
TEST tests/qapi-schema/union-branch-case.out
TEST tests/qapi-schema/union-clash-branches.out
TEST tests/qapi-schema/union-empty.out
TEST tests/qapi-schema/union-invalid-base.out
TEST tests/qapi-schema/union-optional-branch.out
TEST tests/qapi-schema/union-unknown.out
TEST tests/qapi-schema/unknown-escape.out
TEST tests/qapi-schema/unknown-expr-key.out
GEN tests/qapi-schema/doc-good.test.texi
CC tests/check-qdict.o
CC tests/test-char.o
CC tests/check-qfloat.o
CC tests/check-qint.o
CC tests/check-qstring.o
CC tests/check-qlist.o
CC tests/check-qnull.o
CC tests/check-qjson.o
CC tests/test-qobject-output-visitor.o
GEN tests/test-qapi-visit.c
GEN tests/test-qapi-types.c
GEN tests/test-qapi-event.c
GEN tests/test-qmp-introspect.c
CC tests/test-clone-visitor.o
CC tests/test-qobject-input-visitor.o
CC tests/test-qmp-commands.o
GEN tests/test-qmp-marshal.c
CC tests/test-string-input-visitor.o
CC tests/test-string-output-visitor.o
CC tests/test-qmp-event.o
CC tests/test-opts-visitor.o
CC tests/test-coroutine.o
CC tests/iothread.o
CC tests/test-visitor-serialization.o
CC tests/test-iov.o
CC tests/test-aio.o
CC tests/test-aio-multithread.o
CC tests/test-throttle.o
CC tests/test-thread-pool.o
CC tests/test-hbitmap.o
CC tests/test-blockjob-txn.o
CC tests/test-blockjob.o
CC tests/test-x86-cpuid.o
CC tests/test-xbzrle.o
CC tests/test-vmstate.o
CC tests/test-cutils.o
CC tests/test-shift128.o
CC tests/test-mul64.o
CC tests/test-int128.o
CC tests/rcutorture.o
CC tests/test-rcu-list.o
CC tests/test-qdist.o
CC tests/test-qht.o
CC tests/test-qht-par.o
CC tests/qht-bench.o
/tmp/qemu-test/src/tests/test-int128.c:180: warning: ‘__noclone__’ attribute directive ignored
CC tests/test-bitops.o
CC tests/test-bitcnt.o
CC tests/check-qom-interface.o
CC tests/check-qom-proplist.o
CC tests/test-qemu-opts.o
CC tests/test-keyval.o
CC tests/test-write-threshold.o
CC tests/test-crypto-hash.o
CC tests/test-crypto-hmac.o
CC tests/test-crypto-cipher.o
CC tests/test-crypto-secret.o
CC tests/test-qga.o
CC tests/libqtest.o
CC tests/test-timed-average.o
CC tests/test-io-task.o
CC tests/test-io-channel-socket.o
CC tests/io-channel-helpers.o
CC tests/test-io-channel-file.o
CC tests/test-io-channel-command.o
CC tests/test-io-channel-buffer.o
CC tests/test-base64.o
CC tests/test-crypto-ivgen.o
CC tests/test-crypto-afsplit.o
CC tests/test-crypto-xts.o
CC tests/test-crypto-block.o
CC tests/test-logging.o
CC tests/test-replication.o
CC tests/test-bufferiszero.o
CC tests/test-uuid.o
CC tests/ptimer-test.o
CC tests/ptimer-test-stubs.o
CC tests/test-qapi-util.o
CC tests/vhost-user-test.o
CC tests/libqos/pci.o
CC tests/libqos/fw_cfg.o
CC tests/libqos/malloc.o
CC tests/libqos/i2c.o
CC tests/libqos/libqos.o
CC tests/libqos/malloc-spapr.o
CC tests/libqos/libqos-spapr.o
CC tests/libqos/rtas.o
CC tests/libqos/pci-spapr.o
CC tests/libqos/pci-pc.o
CC tests/libqos/malloc-pc.o
CC tests/libqos/libqos-pc.o
CC tests/libqos/ahci.o
CC tests/libqos/virtio.o
CC tests/libqos/virtio-pci.o
CC tests/libqos/virtio-mmio.o
CC tests/libqos/malloc-generic.o
CC tests/endianness-test.o
CC tests/fdc-test.o
CC tests/ide-test.o
CC tests/ahci-test.o
CC tests/hd-geo-test.o
CC tests/boot-order-test.o
CC tests/boot-sector.o
CC tests/bios-tables-test.o
CC tests/acpi-utils.o
/tmp/qemu-test/src/tests/ide-test.c: In function ‘cdrom_pio_impl’:
/tmp/qemu-test/src/tests/ide-test.c:803: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
/tmp/qemu-test/src/tests/ide-test.c: In function ‘test_cdrom_dma’:
/tmp/qemu-test/src/tests/ide-test.c:899: warning: ignoring return value of ‘fwrite’, declared with attribute warn_unused_result
CC tests/boot-serial-test.o
CC tests/pxe-test.o
CC tests/rtc-test.o
CC tests/ipmi-kcs-test.o
CC tests/ipmi-bt-test.o
CC tests/i440fx-test.o
CC tests/fw_cfg-test.o
CC tests/drive_del-test.o
CC tests/wdt_ib700-test.o
CC tests/tco-test.o
CC tests/e1000-test.o
CC tests/e1000e-test.o
CC tests/rtl8139-test.o
CC tests/pcnet-test.o
CC tests/eepro100-test.o
CC tests/ne2000-test.o
CC tests/nvme-test.o
CC tests/ac97-test.o
CC tests/es1370-test.o
CC tests/virtio-net-test.o
CC tests/virtio-balloon-test.o
CC tests/virtio-blk-test.o
CC tests/virtio-rng-test.o
CC tests/virtio-scsi-test.o
CC tests/virtio-serial-test.o
CC tests/virtio-console-test.o
CC tests/tpci200-test.o
CC tests/ipoctal232-test.o
CC tests/display-vga-test.o
CC tests/intel-hda-test.o
CC tests/ivshmem-test.o
CC tests/vmxnet3-test.o
CC tests/pvpanic-test.o
CC tests/i82801b11-test.o
CC tests/ioh3420-test.o
CC tests/usb-hcd-ohci-test.o
CC tests/libqos/usb.o
CC tests/usb-hcd-uhci-test.o
CC tests/usb-hcd-ehci-test.o
CC tests/usb-hcd-xhci-test.o
CC tests/pc-cpu-test.o
CC tests/q35-test.o
CC tests/test-netfilter.o
CC tests/test-filter-mirror.o
CC tests/test-filter-redirector.o
CC tests/postcopy-test.o
CC tests/test-x86-cpuid-compat.o
CC tests/qmp-test.o
CC tests/device-introspect-test.o
CC tests/qom-test.o
CC tests/test-hmp.o
LINK tests/check-qdict
LINK tests/test-char
LINK tests/check-qfloat
LINK tests/check-qint
LINK tests/check-qstring
LINK tests/check-qlist
LINK tests/check-qnull
LINK tests/check-qjson
CC tests/test-qapi-visit.o
CC tests/test-qapi-types.o
CC tests/test-qapi-event.o
CC tests/test-qmp-introspect.o
CC tests/test-qmp-marshal.o
LINK tests/test-coroutine
LINK tests/test-visitor-serialization
LINK tests/test-iov
LINK tests/test-aio
LINK tests/test-aio-multithread
LINK tests/test-throttle
LINK tests/test-thread-pool
LINK tests/test-hbitmap
LINK tests/test-blockjob
LINK tests/test-blockjob-txn
LINK tests/test-x86-cpuid
LINK tests/test-xbzrle
LINK tests/test-vmstate
LINK tests/test-cutils
LINK tests/test-shift128
LINK tests/test-mul64
LINK tests/test-int128
LINK tests/rcutorture
LINK tests/test-rcu-list
LINK tests/test-qdist
LINK tests/test-qht
LINK tests/qht-bench
LINK tests/test-bitops
LINK tests/test-bitcnt
LINK tests/check-qom-interface
LINK tests/check-qom-proplist
LINK tests/test-qemu-opts
LINK tests/test-keyval
LINK tests/test-write-threshold
LINK tests/test-crypto-hash
LINK tests/test-crypto-hmac
LINK tests/test-crypto-cipher
LINK tests/test-crypto-secret
LINK tests/test-qga
LINK tests/test-timed-average
LINK tests/test-io-task
LINK tests/test-io-channel-socket
LINK tests/test-io-channel-file
LINK tests/test-io-channel-command
LINK tests/test-io-channel-buffer
LINK tests/test-base64
LINK tests/test-crypto-ivgen
LINK tests/test-crypto-afsplit
LINK tests/test-crypto-xts
LINK tests/test-crypto-block
LINK tests/test-logging
LINK tests/test-replication
LINK tests/test-bufferiszero
LINK tests/test-uuid
LINK tests/ptimer-test
LINK tests/test-qapi-util
LINK tests/vhost-user-test
LINK tests/endianness-test
LINK tests/fdc-test
LINK tests/ide-test
LINK tests/ahci-test
LINK tests/hd-geo-test
LINK tests/boot-order-test
LINK tests/bios-tables-test
LINK tests/boot-serial-test
LINK tests/pxe-test
LINK tests/rtc-test
LINK tests/ipmi-kcs-test
LINK tests/ipmi-bt-test
LINK tests/i440fx-test
LINK tests/fw_cfg-test
LINK tests/drive_del-test
LINK tests/wdt_ib700-test
LINK tests/tco-test
LINK tests/e1000-test
LINK tests/e1000e-test
LINK tests/rtl8139-test
LINK tests/pcnet-test
LINK tests/eepro100-test
LINK tests/ne2000-test
LINK tests/nvme-test
LINK tests/ac97-test
LINK tests/es1370-test
LINK tests/virtio-net-test
LINK tests/virtio-balloon-test
LINK tests/virtio-blk-test
LINK tests/virtio-rng-test
LINK tests/virtio-scsi-test
LINK tests/virtio-serial-test
LINK tests/virtio-console-test
LINK tests/tpci200-test
LINK tests/ipoctal232-test
LINK tests/display-vga-test
LINK tests/intel-hda-test
LINK tests/ivshmem-test
LINK tests/vmxnet3-test
LINK tests/pvpanic-test
LINK tests/i82801b11-test
LINK tests/ioh3420-test
LINK tests/usb-hcd-ohci-test
LINK tests/usb-hcd-uhci-test
LINK tests/usb-hcd-ehci-test
LINK tests/usb-hcd-xhci-test
LINK tests/pc-cpu-test
LINK tests/q35-test
LINK tests/test-netfilter
LINK tests/test-filter-mirror
LINK tests/test-filter-redirector
LINK tests/postcopy-test
LINK tests/test-x86-cpuid-compat
LINK tests/qmp-test
LINK tests/device-introspect-test
LINK tests/qom-test
LINK tests/test-hmp
GTESTER tests/check-qdict
GTESTER tests/test-char
GTESTER tests/check-qfloat
GTESTER tests/check-qint
GTESTER tests/check-qstring
GTESTER tests/check-qlist
GTESTER tests/check-qnull
GTESTER tests/check-qjson
LINK tests/test-qobject-output-visitor
LINK tests/test-clone-visitor
LINK tests/test-qobject-input-visitor
LINK tests/test-qmp-commands
LINK tests/test-string-input-visitor
LINK tests/test-string-output-visitor
LINK tests/test-qmp-event
LINK tests/test-opts-visitor
GTESTER tests/test-coroutine
GTESTER tests/test-visitor-serialization
GTESTER tests/test-iov
GTESTER tests/test-aio-multithread
GTESTER tests/test-aio
GTESTER tests/test-throttle
GTESTER tests/test-thread-pool
GTESTER tests/test-hbitmap
GTESTER tests/test-blockjob
GTESTER tests/test-blockjob-txn
GTESTER tests/test-x86-cpuid
GTESTER tests/test-xbzrle
GTESTER tests/test-vmstate
Failed to load simple/primitive:b_1
Failed to load simple/primitive:i64_2
Failed to load simple/primitive:i32_1
Failed to load simple/primitive:i32_1
Failed to load test/with_tmp:a
Failed to load test/tmp_child_parent:f
Failed to load test/tmp_child:parent
Failed to load test/with_tmp:tmp
Failed to load test/tmp_child:diff
Failed to load test/with_tmp:tmp
Failed to load test/tmp_child:diff
Failed to load test/with_tmp:tmp
GTESTER tests/test-cutils
GTESTER tests/test-shift128
GTESTER tests/test-mul64
GTESTER tests/test-int128
GTESTER tests/rcutorture
GTESTER tests/test-rcu-list
GTESTER tests/test-qdist
GTESTER tests/test-qht
LINK tests/test-qht-par
GTESTER tests/test-bitops
GTESTER tests/test-bitcnt
GTESTER tests/check-qom-interface
GTESTER tests/check-qom-proplist
GTESTER tests/test-qemu-opts
GTESTER tests/test-keyval
GTESTER tests/test-write-threshold
GTESTER tests/test-crypto-hash
GTESTER tests/test-crypto-hmac
GTESTER tests/test-crypto-cipher
GTESTER tests/test-crypto-secret
GTESTER tests/test-qga
GTESTER tests/test-timed-average
GTESTER tests/test-io-task
GTESTER tests/test-io-channel-socket
GTESTER tests/test-io-channel-file
GTESTER tests/test-io-channel-command
GTESTER tests/test-io-channel-buffer
GTESTER tests/test-base64
GTESTER tests/test-crypto-ivgen
GTESTER tests/test-crypto-afsplit
GTESTER tests/test-crypto-xts
GTESTER tests/test-crypto-block
GTESTER tests/test-logging
GTESTER tests/test-replication
GTESTER tests/test-bufferiszero
GTESTER tests/test-uuid
GTESTER tests/ptimer-test
GTESTER tests/test-qapi-util
GTESTER check-qtest-x86_64
GTESTER check-qtest-aarch64
GTESTER tests/test-qobject-output-visitor
GTESTER tests/test-clone-visitor
GTESTER tests/test-qobject-input-visitor
GTESTER tests/test-qmp-commands
GTESTER tests/test-string-input-visitor
GTESTER tests/test-string-output-visitor
GTESTER tests/test-qmp-event
GTESTER tests/test-opts-visitor
GTESTER tests/test-qht-par
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
Could not access KVM kernel module: No such file or directory
failed to initialize KVM: No such file or directory
Back to tcg accelerator.
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-tjgugl52/src'
BUILD fedora
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-tjgugl52/src'
ARCHIVE qemu.tgz
ARCHIVE dtc.tgz
COPY RUNNER
RUN test-mingw in qemu:fedora
Packages installed:
PyYAML-3.11-13.fc25.x86_64
SDL-devel-1.2.15-21.fc24.x86_64
bc-1.06.95-16.fc24.x86_64
bison-3.0.4-4.fc24.x86_64
ccache-3.3.4-1.fc25.x86_64
clang-3.9.1-2.fc25.x86_64
findutils-4.6.0-8.fc25.x86_64
flex-2.6.0-3.fc25.x86_64
gcc-6.3.1-1.fc25.x86_64
gcc-c++-6.3.1-1.fc25.x86_64
git-2.9.3-2.fc25.x86_64
glib2-devel-2.50.3-1.fc25.x86_64
libfdt-devel-1.4.2-1.fc25.x86_64
make-4.1-5.fc24.x86_64
mingw32-SDL-1.2.15-7.fc24.noarch
mingw32-bzip2-1.0.6-7.fc24.noarch
mingw32-curl-7.47.0-1.fc24.noarch
mingw32-glib2-2.50.1-1.fc25.noarch
mingw32-gmp-6.1.1-1.fc25.noarch
mingw32-gnutls-3.5.5-2.fc25.noarch
mingw32-gtk2-2.24.31-2.fc25.noarch
mingw32-gtk3-3.22.2-1.fc25.noarch
mingw32-libjpeg-turbo-1.5.1-1.fc25.noarch
mingw32-libpng-1.6.27-1.fc25.noarch
mingw32-libssh2-1.4.3-5.fc24.noarch
mingw32-libtasn1-4.9-1.fc25.noarch
mingw32-nettle-3.3-1.fc25.noarch
mingw32-pixman-0.34.0-1.fc25.noarch
mingw32-pkg-config-0.28-6.fc24.x86_64
mingw64-SDL-1.2.15-7.fc24.noarch
mingw64-bzip2-1.0.6-7.fc24.noarch
mingw64-curl-7.47.0-1.fc24.noarch
mingw64-glib2-2.50.1-1.fc25.noarch
mingw64-gmp-6.1.1-1.fc25.noarch
mingw64-gnutls-3.5.5-2.fc25.noarch
mingw64-gtk2-2.24.31-2.fc25.noarch
mingw64-gtk3-3.22.2-1.fc25.noarch
mingw64-libjpeg-turbo-1.5.1-1.fc25.noarch
mingw64-libpng-1.6.27-1.fc25.noarch
mingw64-libssh2-1.4.3-5.fc24.noarch
mingw64-libtasn1-4.9-1.fc25.noarch
mingw64-nettle-3.3-1.fc25.noarch
mingw64-pixman-0.34.0-1.fc25.noarch
mingw64-pkg-config-0.28-6.fc24.x86_64
package python2 is not installed
perl-5.24.1-385.fc25.x86_64
pixman-devel-0.34.0-2.fc24.x86_64
sparse-0.5.0-10.fc25.x86_64
tar-1.29-3.fc25.x86_64
which-2.21-1.fc25.x86_64
zlib-devel-1.2.8-10.fc24.x86_64
Environment variables:
FBR=f25
PACKAGES=ccache git tar PyYAML sparse flex bison python2 glib2-devel pixman-devel zlib-devel SDL-devel libfdt-devel gcc gcc-c++ clang make perl which bc findutils mingw32-pixman mingw32-glib2 mingw32-gmp mingw32-SDL mingw32-pkg-config mingw32-gtk2 mingw32-gtk3 mingw32-gnutls mingw32-nettle mingw32-libtasn1 mingw32-libjpeg-turbo mingw32-libpng mingw32-curl mingw32-libssh2 mingw32-bzip2 mingw64-pixman mingw64-glib2 mingw64-gmp mingw64-SDL mingw64-pkg-config mingw64-gtk2 mingw64-gtk3 mingw64-gnutls mingw64-nettle mingw64-libtasn1 mingw64-libjpeg-turbo mingw64-libpng mingw64-curl mingw64-libssh2 mingw64-bzip2
HOSTNAME=
TERM=xterm
MAKEFLAGS= -j8
HISTSIZE=1000
J=8
USER=root
LS_COLORS=rs=0:di=01;34:ln=01;36:mh=00:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:mi=01;05;37;41:su=37;41:sg=30;43:ca=30;41:tw=30;42:ow=34;42:st=37;44:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arc=01;31:*.arj=01;31:*.taz=01;31:*.lha=01;31:*.lz4=01;31:*.lzh=01;31:*.lzma=01;31:*.tlz=01;31:*.txz=01;31:*.tzo=01;31:*.t7z=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.dz=01;31:*.gz=01;31:*.lrz=01;31:*.lz=01;31:*.lzo=01;31:*.xz=01;31:*.bz2=01;31:*.bz=01;31:*.tbz=01;31:*.tbz2=01;31:*.tz=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.war=01;31:*.ear=01;31:*.sar=01;31:*.rar=01;31:*.alz=01;31:*.ace=01;31:*.zoo=01;31:*.cpio=01;31:*.7z=01;31:*.rz=01;31:*.cab=01;31:*.jpg=01;35:*.jpeg=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.png=01;35:*.svg=01;35:*.svgz=01;35:*.mng=01;35:*.pcx=01;35:*.mov=01;35:*.mpg=01;35:*.mpeg=01;35:*.m2v=01;35:*.mkv=01;35:*.webm=01;35:*.ogm=01;35:*.mp4=01;35:*.m4v=01;35:*.mp4v=01;35:*.vob=01;35:*.qt=01;35:*.nuv=01;35:*.wmv=01;35:*.asf=01;35:*.rm=01;35:*.rmvb=01;35:*.flc=01;35:*.avi=01;35:*.fli=01;35:*.flv=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:*.yuv=01;35:*.cgm=01;35:*.emf=01;35:*.ogv=01;35:*.ogx=01;35:*.aac=01;36:*.au=01;36:*.flac=01;36:*.m4a=01;36:*.mid=01;36:*.midi=01;36:*.mka=01;36:*.mp3=01;36:*.mpc=01;36:*.ogg=01;36:*.ra=01;36:*.wav=01;36:*.oga=01;36:*.opus=01;36:*.spx=01;36:*.xspf=01;36:
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
MAIL=/var/spool/mail/root
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
TARGET_LIST=
HISTCONTROL=ignoredups
FGC=f25
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
DISTTAG=f25docker
LOGNAME=root
LESSOPEN=||/usr/bin/lesspipe.sh %s
FEATURES=mingw clang pyyaml dtc
DEBUG=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/var/tmp/qemu-build/install --cross-prefix=x86_64-w64-mingw32- --enable-trace-backends=simple --enable-debug --enable-gnutls --enable-nettle --enable-curl --enable-vnc --enable-bzip2 --enable-guest-agent --with-sdlabi=1.2 --with-gtkabi=2.0
grep: scripts/tracetool/backend/*.py: No such file or directory
Install prefix /var/tmp/qemu-build/install
BIOS directory /var/tmp/qemu-build/install
binary directory /var/tmp/qemu-build/install
library directory /var/tmp/qemu-build/install/lib
module directory /var/tmp/qemu-build/install/lib
libexec directory /var/tmp/qemu-build/install/libexec
include directory /var/tmp/qemu-build/install/include
config directory /var/tmp/qemu-build/install
local state directory queried at runtime
Windows SDK no
Source path /tmp/qemu-test/src
C compiler x86_64-w64-mingw32-gcc
Host C compiler cc
C++ compiler x86_64-w64-mingw32-g++
Objective-C compiler clang
ARFLAGS rv
CFLAGS -g
QEMU_CFLAGS -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -mms-bitfields -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/glib-2.0 -I/usr/x86_64-w64-mingw32/sys-root/mingw/lib/glib-2.0/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -m64 -mcx16 -mthreads -D__USE_MINGW_ANSI_STDIO=1 -DWIN32_LEAN_AND_MEAN -DWINVER=0x501 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/p11-kit-1 -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include -I/usr/x86_64-w64-mingw32/sys-root/mingw/include/libpng16
LDFLAGS -Wl,--nxcompat -Wl,--no-seh -Wl,--dynamicbase -Wl,--warn-common -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
tcg debug enabled yes
gprof enabled no
sparse enabled no
strip binaries no
profiler no
static build no
pixman system
SDL support yes (1.2.15)
GTK support yes (2.24.31)
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (3.3)
nettle kdf yes
libtasn1 yes
curses support no
virgl support no
curl support yes
mingw32 support yes
Audio drivers dsound
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
VNC support yes
VNC SASL support no
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support no
bluez support no
Documentation no
PIE no
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support no
Install blobs yes
KVM support no
HAX support yes
RDMA support no
TCG interpreter no
fdt support yes
preadv support no
fdatasync no
madvise no
posix_madvise no
libcap-ng support no
vhost-net support no
vhost-scsi support no
vhost-vsock support no
Trace backends simple
Trace output file trace-<pid>
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb no
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info yes
QGA MSI support no
seccomp support no
coroutine backend win32
coroutine pool yes
debug stack usage no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support yes
TPM passthrough no
QOM debugging yes
lzo support no
snappy support no
bzip2 support yes
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization yes
replication support yes
VxHS block device no
mkdir -p dtc/libfdt
mkdir -p dtc/tests
GEN aarch64-softmmu/config-devices.mak.tmp
GEN x86_64-softmmu/config-devices.mak.tmp
GEN qemu-options.def
GEN config-host.h
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN x86_64-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN qmp-marshal.c
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.h
GEN qmp-introspect.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN backends/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN trace-root.c
GEN qapi/trace.h
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN backends/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
LEX convert-dtsv0-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/srcpos.c
BISON dtc-parser.tab.c
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
DEP convert-dtsv0-lexer.lex.c
DEP dtc-parser.tab.c
DEP dtc-lexer.lex.c
CHK version_gen.h
UPD version_gen.h
DEP /tmp/qemu-test/src/dtc/util.c
CC libfdt/fdt_ro.o
CC libfdt/fdt.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
x86_64-w64-mingw32-ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
RC version.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qapi-types.c
CC qapi-types.o
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qmp-introspect.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qint.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qfloat.o
CC qobject/qbool.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-parser.o
CC qobject/json-streamer.o
CC trace/simple.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-win32.o
CC util/event_notifier-win32.o
CC util/oslib-win32.o
CC util/qemu-thread-win32.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/throttle.o
CC util/uuid.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-win32.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC util/systemd.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC backends/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/usb/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/xen/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/get-vm-name.o
CC stubs/gdbstub.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/fd-register.o
CC stubs/qmp_pc_dimm_device_list.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
GEN qemu-img-cmds.h
CC block.o
CC blockjob.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/vpc.o
CC block/bochs.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qed.o
CC block/qed-gencb.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-check.o
CC block/qed-cluster.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-win32.o
CC block/win32-aio.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/crypto.o
CC block/replication.o
CC block/backup.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC block/curl.o
CC block/ssh.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-nettle.o
CC crypto/hmac.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/hmac-nettle.o
CC crypto/cipher.o
CC crypto/tlscredsanon.o
CC crypto/tlscreds.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/secret.o
CC crypto/random-gnutls.o
CC crypto/pbkdf.o
CC crypto/pbkdf-nettle.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-command.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/qom-qobject.o
CC qom/container.o
CC qom/object_interfaces.o
CC qemu-io.o
CC blockdev.o
CC blockdev-nbd.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-win32.o
CC accel.o
CC bt-host.o
CC page_cache.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/dsoundaudio.o
CC audio/audio_win_int.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/msmouse.o
CC backends/wctablet.o
CC backends/testdev.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC block/stream.o
CC disas/arm.o
CC disas/i386.o
CXX disas/arm-a64.o
CXX disas/libvixl/vixl/utils.o
CXX disas/libvixl/vixl/compiler-intrinsics.o
CXX disas/libvixl/vixl/a64/instructions-a64.o
CXX disas/libvixl/vixl/a64/decoder-a64.o
CXX disas/libvixl/vixl/a64/disasm-a64.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/tco.o
CC hw/acpi/ich9.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/ecc.o
CC hw/block/pflash_cfi02.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/cadence_uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/qdev-properties-system.o
CC hw/core/loader.o
CC hw/core/register.o
CC hw/core/platform-bus.o
CC hw/core/or-irq.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/tc6393xb.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/unimp.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/ftgmac100.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-host/pam.o
CC hw/pci-host/versatile.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/ssi/msf2_spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/pl031.o
CC hw/timer/twl92230.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/msf2_timer.o
CC hw/tpm/tpm_tis.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_aspeed.o
CC migration/migration.o
CC hw/watchdog/wdt_ib700.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/qemu-file.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/slirp.o
CC net/tap-win32.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC replay/replay-net.o
CC replay/replay-audio.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip_input.o
CC slirp/ip6_output.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_output.o
CC slirp/tcp_input.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC slirp/ncsi.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/sdl.o
CC ui/sdl_zoom.o
/tmp/qemu-test/src/hw/timer/msf2_timer.c: In function 'timer_read':
/tmp/qemu-test/src/hw/timer/msf2_timer.c:37:18: error: format '%lu' expects argument of type 'long unsigned int', but argument 4 has type 'hwaddr {aka long long unsigned int}' [-Werror=format=]
qemu_log("%s: " fmt, __func__, ## args); \
^
/tmp/qemu-test/src/hw/timer/msf2_timer.c:41:32: note: in expansion of macro 'DB_PRINT_L'
#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
^~~~~~~~~~
/tmp/qemu-test/src/hw/timer/msf2_timer.c:109:5: note: in expansion of macro 'DB_PRINT'
DB_PRINT("timer=%d %lu=%x\n", timer, addr * 4, r);
^~~~~~~~
/tmp/qemu-test/src/hw/timer/msf2_timer.c: In function 'timer_write':
/tmp/qemu-test/src/hw/timer/msf2_timer.c:37:18: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'hwaddr {aka long long unsigned int}' [-Werror=format=]
qemu_log("%s: " fmt, __func__, ## args); \
^
/tmp/qemu-test/src/hw/timer/msf2_timer.c:41:32: note: in expansion of macro 'DB_PRINT_L'
#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
^~~~~~~~~~
/tmp/qemu-test/src/hw/timer/msf2_timer.c:134:5: note: in expansion of macro 'DB_PRINT'
DB_PRINT("addr=%lu val=%x (timer=%d)\n", addr * 4, value, timer);
^~~~~~~~
cc1: all warnings being treated as errors
/tmp/qemu-test/src/rules.mak:69: recipe for target 'hw/timer/msf2_timer.o' failed
make: *** [hw/timer/msf2_timer.o] Error 1
make: *** Waiting for unfinished jobs....
CC ui/x_keymap.o
CC ui/vnc.o
tests/docker/Makefile.include:118: recipe for target 'docker-run' failed
make[1]: *** [docker-run] Error 2
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-tjgugl52/src'
tests/docker/Makefile.include:149: recipe for target 'docker-run-test-mingw@fedora' failed
make: *** [docker-run-test-mingw@fedora] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
@ 2017-05-02 5:02 ` sundeep subbaraya
2017-05-03 23:39 ` Alistair Francis
1 sibling, 0 replies; 16+ messages in thread
From: sundeep subbaraya @ 2017-05-02 5:02 UTC (permalink / raw)
To: QEMU Developers, qemu-arm
Cc: Peter Maydell, Peter Crosthwaite, Alistair Francis, Subbaraya Sundeep
Hi,
Gentle Reminder.
Thanks,
Sundeep
On Fri, Apr 28, 2017 at 10:21 PM, Subbaraya Sundeep
<sundeep.lkml@gmail.com> wrote:
> Modelled Microsemi's Smartfusion2 SPI controller.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> Hi Peter and Alistair,
>
> I created two SPI controllers as per SoC spec
> in hw/arm/msf2_soc.c. I am assuming there has to be two
> busses spi0 and spi1 one for each controller. In board file
> (hw/arm/msf2_som.c) attached SPI flash to SPI0 controller.
> I am not able to understand(from hw/ssi/xilinx_spips.c)
> how to create two busses in hw/ssi/msf2_spi.c.
> Please help me here. Below is the output of info qtree:
>
> (qemu) info qtree
> bus: main-system-bus
> type System
> dev: msf2-soc, id ""
> cpu-model = "cortex-m3"
> dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040011000/0000000000000040
> bus: spi0
> type SSI
> dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040001000/0000000000000040
> bus: spi0
> type SSI
> dev: s25sl12801, id ""
> gpio-in "ssi-gpio-cs" 1
> nonvolatile-cfg = 36863 (0x8fff)
> spansion-cr1nv = 0 (0x0)
> spansion-cr2nv = 1 (0x1)
> spansion-cr3nv = 2 (0x2)
> spansion-cr4nv = 16 (0x10)
> drive = "mtd0"
>
> Thanks,
> Sundeep
>
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/msf2_spi.c | 373 ++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ssi/msf2_spi.h | 102 +++++++++++++
> 3 files changed, 476 insertions(+)
> create mode 100644 hw/ssi/msf2_spi.c
> create mode 100644 include/hw/ssi/msf2_spi.h
>
> diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
> index 487add2..86445d7 100644
> --- a/hw/ssi/Makefile.objs
> +++ b/hw/ssi/Makefile.objs
> @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
> common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
> +common-obj-$(CONFIG_MSF2) += msf2_spi.o
>
> obj-$(CONFIG_OMAP) += omap_spi.o
> obj-$(CONFIG_IMX) += imx_spi.o
> diff --git a/hw/ssi/msf2_spi.c b/hw/ssi/msf2_spi.c
> new file mode 100644
> index 0000000..e7ffa21
> --- /dev/null
> +++ b/hw/ssi/msf2_spi.c
> @@ -0,0 +1,373 @@
> +/*
> + * SPI controller model of Microsemi SmartFusion2.
> + *
> + * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/ssi/msf2_spi.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/log.h"
> +
> +#ifndef MSF2_SPI_ERR_DEBUG
> +#define MSF2_SPI_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSF2_SPI_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt, __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void txfifo_reset(MSF2SpiState *s)
> +{
> + fifo32_reset(&s->tx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
> +}
> +
> +static void rxfifo_reset(MSF2SpiState *s)
> +{
> + fifo32_reset(&s->rx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> +}
> +
> +static void set_fifodepth(MSF2SpiState *s)
> +{
> + int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
> +
> + if (0 <= size && size <= 8) {
> + s->fifo_depth = 32;
> + }
> + if (9 <= size && size <= 16) {
> + s->fifo_depth = 16;
> + }
> + if (17 <= size && size <= 32) {
> + s->fifo_depth = 8;
> + }
> +}
> +
> +static void msf2_spi_do_reset(MSF2SpiState *s)
> +{
> + memset(s->regs, 0, sizeof s->regs);
> + s->regs[R_SPI_CONTROL] = 0x80000102;
> + s->regs[R_SPI_DFSIZE] = 0x4;
> + s->regs[R_SPI_STATUS] = 0x2440;
> + s->regs[R_SPI_CLKGEN] = 0x7;
> + s->regs[R_SPI_STAT8] = 0x7;
> + s->regs[R_SPI_RIS] = 0x0;
> +
> + s->fifo_depth = 4;
> + s->frame_count = 1;
> + s->enabled = false;
> +
> + rxfifo_reset(s);
> + txfifo_reset(s);
> +}
> +
> +static void update_mis(MSF2SpiState *s)
> +{
> + uint32_t reg = s->regs[R_SPI_CONTROL];
> + uint32_t tmp;
> +
> + /*
> + * form the Control register interrupt enable bits
> + * same as RIS, MIS and Interrupt clear registers for simplicity
> + */
> + tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
> + ((reg & C_INTTXDATA) >> 5);
> + s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
> +}
> +
> +static void spi_update_irq(MSF2SpiState *s)
> +{
> + int irq;
> +
> + update_mis(s);
> + irq = !!(s->regs[R_SPI_MIS]);
> +
> + qemu_set_irq(s->irq, irq);
> +}
> +
> +static void msf2_spi_reset(DeviceState *d)
> +{
> + msf2_spi_do_reset(MSF2_SPI(d));
> +}
> +
> +static uint64_t
> +spi_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + MSF2SpiState *s = opaque;
> + uint32_t r = 0;
> +
> + addr >>= 2;
> + switch (addr) {
> + case R_SPI_RX:
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] &= ~RXCHOVRF;
> + r = fifo32_pop(&s->rx_fifo);
> + if (fifo32_is_empty(&s->rx_fifo)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + update_mis(s);
> + r = s->regs[R_SPI_MIS];
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + r = s->regs[addr];
> + }
> + break;
> + }
> +
> + DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
> + spi_update_irq(s);
> + return r;
> +}
> +
> +static void assert_cs(MSF2SpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 0);
> +}
> +
> +static void deassert_cs(MSF2SpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 1);
> +}
> +
> +static void spi_flush_txfifo(MSF2SpiState *s)
> +{
> + uint32_t tx;
> + uint32_t rx;
> + bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
> +
> + /*
> + * Chip Select(CS) is automatically controlled by this controller.
> + * If SPS bit is set in Control register then CS is asserted
> + * until all the frames set in frame count of Control register are
> + * transferred. If SPS is not set then CS pulses between frames.
> + * Note that Slave Select register specifies which of the CS line
> + * has to be controlled automatically by controller. Bits SS[7:1] are for
> + * masters in FPGA fabric since we model only Microcontroller subsystem
> + * of Smartfusion2 we control only one CS(SS[0]) line.
> + */
> + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
> + assert_cs(s);
> +
> + s->regs[R_SPI_STATUS] &= ~TXDONE;
> + s->regs[R_SPI_STATUS] &= ~RXRDY;
> +
> + tx = fifo32_pop(&s->tx_fifo);
> + DB_PRINT("data tx:%x\n", tx);
> + rx = ssi_transfer(s->spi, tx);
> + DB_PRINT("data rx:%x\n", rx);
> +
> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= RXCHOVRF;
> + s->regs[R_SPI_RIS] |= RXCHOVRF;
> + } else {
> + fifo32_push(&s->rx_fifo, rx);
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
> + if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
> + }
> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
> + }
> + }
> + s->frame_count--;
> + if (!sps) {
> + deassert_cs(s);
> + assert_cs(s);
> + }
> + }
> +
> + if (!sps) {
> + deassert_cs(s);
> + }
> +
> + if (!s->frame_count) {
> + s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
> + FMCOUNT_SHIFT;
> + if (sps) {
> + deassert_cs(s);
> + }
> + s->regs[R_SPI_RIS] |= TXDONE;
> + s->regs[R_SPI_RIS] |= RXRDY;
> + s->regs[R_SPI_STATUS] |= TXDONE;
> + s->regs[R_SPI_STATUS] |= RXRDY;
> + }
> +}
> +
> +static void spi_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + MSF2SpiState *s = opaque;
> + uint32_t value = val64;
> +
> + DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
> + addr >>= 2;
> +
> + switch (addr) {
> + case R_SPI_TX:
> + /* adding to already full FIFO */
> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + break;
> + }
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
> + fifo32_push(&s->tx_fifo, value);
> + if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
> + }
> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
> + }
> + if (s->enabled) {
> + spi_flush_txfifo(s);
> + }
> + break;
> +
> + case R_SPI_CONTROL:
> + s->regs[R_SPI_CONTROL] = value;
> + if (value & C_BIGFIFO) {
> + set_fifodepth(s);
> + } else {
> + s->fifo_depth = 4;
> + }
> + if (value & C_ENABLE) {
> + s->enabled = true;
> + } else {
> + s->enabled = false;
> + }
> + s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
> + if (value & C_RESET) {
> + msf2_spi_do_reset(s);
> + }
> + break;
> +
> + case R_SPI_DFSIZE:
> + if (s->enabled) {
> + break;
> + }
> + s->regs[R_SPI_DFSIZE] = value;
> + break;
> +
> + case R_SPI_INTCLR:
> + s->regs[R_SPI_INTCLR] = value;
> + if (value & TXDONE) {
> + s->regs[R_SPI_RIS] &= ~TXDONE;
> + }
> + if (value & RXRDY) {
> + s->regs[R_SPI_RIS] &= ~RXRDY;
> + }
> + if (value & RXCHOVRF) {
> + s->regs[R_SPI_RIS] &= ~RXCHOVRF;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + case R_SPI_STATUS:
> + case R_SPI_RIS:
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + s->regs[addr] = value;
> + }
> + break;
> + }
> +
> + spi_update_irq(s);
> +}
> +
> +static const MemoryRegionOps spi_ops = {
> + .read = spi_read,
> + .write = spi_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> +};
> +
> +static void msf2_spi_realize(DeviceState *dev, Error **errp)
> +{
> + MSF2SpiState *s = MSF2_SPI(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + DB_PRINT("\n");
> +
> + s->spi = ssi_create_bus(dev, "spi0");
> +
> + sysbus_init_irq(sbd, &s->irq);
> + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
> + sysbus_init_irq(sbd, &s->cs_line);
> +
> + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
> + TYPE_MSF2_SPI, R_SPI_MAX * 4);
> + sysbus_init_mmio(sbd, &s->mmio);
> +
> + fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
> + fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
> +}
> +
> +static const VMStateDescription vmstate_msf2_spi = {
> + .name = TYPE_MSF2_SPI,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_FIFO32(tx_fifo, MSF2SpiState),
> + VMSTATE_FIFO32(rx_fifo, MSF2SpiState),
> + VMSTATE_UINT32_ARRAY(regs, MSF2SpiState, R_SPI_MAX),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void msf2_spi_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = msf2_spi_realize;
> + dc->reset = msf2_spi_reset;
> + dc->vmsd = &vmstate_msf2_spi;
> +}
> +
> +static const TypeInfo msf2_spi_info = {
> + .name = TYPE_MSF2_SPI,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSF2SpiState),
> + .class_init = msf2_spi_class_init,
> +};
> +
> +static void msf2_spi_register_types(void)
> +{
> + type_register_static(&msf2_spi_info);
> +}
> +
> +type_init(msf2_spi_register_types)
> diff --git a/include/hw/ssi/msf2_spi.h b/include/hw/ssi/msf2_spi.h
> new file mode 100644
> index 0000000..7f266c2
> --- /dev/null
> +++ b/include/hw/ssi/msf2_spi.h
> @@ -0,0 +1,102 @@
> +/*
> + * Microsemi SmartFusion2 SPI
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MSF2_SPI_H
> +#define HW_MSF2_SPI_H
> +
> +#include "hw/sysbus.h"
> +#include "hw/hw.h"
> +#include "hw/ssi/ssi.h"
> +#include "qemu/fifo32.h"
> +
> +#define FIFO_CAPACITY 32
> +#define FIFO_CAPACITY 32
> +
> +#define R_SPI_CONTROL 0
> +#define R_SPI_DFSIZE 1
> +#define R_SPI_STATUS 2
> +#define R_SPI_INTCLR 3
> +#define R_SPI_RX 4
> +#define R_SPI_TX 5
> +#define R_SPI_CLKGEN 6
> +#define R_SPI_SS 7
> +#define R_SPI_MIS 8
> +#define R_SPI_RIS 9
> +#define R_SPI_STAT8 15
> +#define R_SPI_MAX 16
> +
> +#define S_RXFIFOFUL (1 << 4)
> +#define S_RXFIFOFULNXT (1 << 5)
> +#define S_RXFIFOEMP (1 << 6)
> +#define S_RXFIFOEMPNXT (1 << 7)
> +#define S_TXFIFOFUL (1 << 8)
> +#define S_TXFIFOFULNXT (1 << 9)
> +#define S_TXFIFOEMP (1 << 10)
> +#define S_TXFIFOEMPNXT (1 << 11)
> +#define S_FRAMESTART (1 << 12)
> +#define S_SSEL (1 << 13)
> +#define S_ACTIVE (1 << 14)
> +
> +#define C_ENABLE (1 << 0)
> +#define C_MODE (1 << 1)
> +#define C_INTRXDATA (1 << 4)
> +#define C_INTTXDATA (1 << 5)
> +#define C_INTRXOVRFLO (1 << 6)
> +#define C_SPS (1 << 26)
> +#define C_BIGFIFO (1 << 29)
> +#define C_RESET (1 << 31)
> +
> +#define FRAMESZ_MASK 0x1F
> +#define FMCOUNT_MASK 0x00FFFF00
> +#define FMCOUNT_SHIFT 8
> +
> +#define TXDONE (1 << 0)
> +#define RXRDY (1 << 1)
> +#define RXCHOVRF (1 << 2)
> +
> +#define TYPE_MSF2_SPI "msf2-spi"
> +#define MSF2_SPI(obj) OBJECT_CHECK(MSF2SpiState, (obj), TYPE_MSF2_SPI)
> +
> +typedef struct MSF2SpiState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> +
> + qemu_irq irq;
> +
> + qemu_irq cs_line;
> +
> + SSIBus *spi;
> +
> + Fifo32 rx_fifo;
> + Fifo32 tx_fifo;
> +
> + int fifo_depth;
> + uint32_t frame_count;
> + bool enabled;
> +
> + uint32_t regs[R_SPI_MAX];
> +} MSF2SpiState;
> +
> +#endif /* HW_MSF2_SPI_H */
> --
> 2.5.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
@ 2017-05-02 21:55 ` Alistair Francis
2017-05-03 5:11 ` sundeep subbaraya
0 siblings, 1 reply; 16+ messages in thread
From: Alistair Francis @ 2017-05-02 21:55 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
<sundeep.lkml@gmail.com> wrote:
> Modelled System Timer in Microsemi's Smartfusion2 Soc.
> Timer has two 32bit down counters and two interrupts.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> hw/timer/Makefile.objs | 1 +
> hw/timer/msf2_timer.c | 250 ++++++++++++++++++++++++++++++++++++++++++
> include/hw/timer/msf2_timer.h | 82 ++++++++++++++
> 3 files changed, 333 insertions(+)
> create mode 100644 hw/timer/msf2_timer.c
> create mode 100644 include/hw/timer/msf2_timer.h
>
> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> index dd6f27e..0bdf1e1 100644
> --- a/hw/timer/Makefile.objs
> +++ b/hw/timer/Makefile.objs
> @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
>
> common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
> +common-obj-$(CONFIG_MSF2) += msf2_timer.o
> diff --git a/hw/timer/msf2_timer.c b/hw/timer/msf2_timer.c
> new file mode 100644
> index 0000000..d1dbde5
> --- /dev/null
> +++ b/hw/timer/msf2_timer.c
Hey Sundeep,
File names should use '-' instead of '_'.
> @@ -0,0 +1,250 @@
> +/*
> + * Timer block model of Microsemi SmartFusion2.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/timer/msf2_timer.h"
> +#include "hw/sysbus.h"
> +#include "qemu/log.h"
> +#include "qemu/main-loop.h"
Do you need to include the main-loop.h? This doesn't look right.
> +
> +#ifndef MSF2_TIMER_ERR_DEBUG
> +#define MSF2_TIMER_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSF2_TIMER_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt, __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void timer_update_irq(struct Msf2Timer *st)
> +{
> + bool isr, ier;
> +
> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
> +
> + qemu_set_irq(st->irq, (ier && isr));
> +}
> +
> +static void timer_update(struct Msf2Timer *st)
> +{
> + uint64_t count;
> +
> + DB_PRINT("timer=%d\n", st->nr);
Maybe make this a little more explict. Something like "Updating timer: %d"?
> +
> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
> + ptimer_stop(st->ptimer);
> + return;
> + }
> +
> + count = st->regs[R_TIM_LOADVAL];
> + ptimer_set_limit(st->ptimer, count, 1);
> + ptimer_run(st->ptimer, 1);
> +}
> +
> +static uint64_t
> +timer_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + MSF2TimerState *t = opaque;
> + struct Msf2Timer *st;
> + uint32_t r = 0;
Call the ret instead of r and it should be a uint64_t.
> + unsigned int timer = 0;
Isn't the timer normally an int? Try to use the same type throughout the code.
> + int isr;
> + int ier;
> +
> + addr >>= 2;
> + /*
> + * Two independent timers has same base address.
> + * Based on addr passed figure out which timer is being used.
> + */
> + if (addr >= R_TIM1_MAX) {
> + timer = 1;
> + addr -= R_TIM1_MAX;
> + }
> +
> + st = &t->timers[timer];
> +
> + switch (addr) {
> + case R_TIM_VAL:
> + r = ptimer_get_count(st->ptimer);
> + DB_PRINT("msf2_timer t=%d read counter=%x\n", timer, r);
Put a 0x in front of hex values.
Also %x isn't the correct type for uint64_t, it's something similar to PRIx.
> + break;
> +
> + case R_TIM_MIS:
> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
> + r = ier && isr;
This should be a bitwise AND.
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(st->regs)) {
> + r = st->regs[addr];
> + }
If the write is outside the array you should print a guest error.
> + break;
> + }
> + DB_PRINT("timer=%d %lu=%x\n", timer, addr * 4, r);
> + return r;
> +}
> +
> +static void
> +timer_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + MSF2TimerState *t = opaque;
> + struct Msf2Timer *st;
> + unsigned int timer = 0;
> + uint32_t value = val64;
> +
> + addr >>= 2;
> + /*
> + * Two independent timers has same base address.
> + * Based on addr passed figure out which timer is being used.
> + */
> + if (addr >= R_TIM1_MAX) {
> + timer = 1;
> + addr -= R_TIM1_MAX;
> + }
> +
> + st = &t->timers[timer];
> +
> + DB_PRINT("addr=%lu val=%x (timer=%d)\n", addr * 4, value, timer);
> +
> + switch (addr) {
> + case R_TIM_CTRL:
> + st->regs[R_TIM_CTRL] = value;
> + timer_update(st);
> + break;
> +
> + case R_TIM_RIS:
> + if (value & TIMER_RIS_ACK) {
> + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
> + }
> + break;
> +
> + case R_TIM_LOADVAL:
> + st->regs[R_TIM_LOADVAL] = value;
> + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
> + timer_update(st);
> + }
> + break;
> +
> + case R_TIM_BGLOADVAL:
> + st->regs[R_TIM_BGLOADVAL] = value;
> + st->regs[R_TIM_LOADVAL] = value;
> + break;
> +
> + case R_TIM_VAL:
> + case R_TIM_MIS:
> + break;
> +
> + case R_TIM_MODE:
> + if (value & TIMER_MODE) {
> + DB_PRINT("64-bit mode not supported\n");
There is an unimp mask for qemu_log() which you should use here.
> + }
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(st->regs)) {
> + st->regs[addr] = value;
> + }
> + break;
> + }
> + timer_update_irq(st);
> +}
> +
> +static const MemoryRegionOps timer_ops = {
> + .read = timer_read,
> + .write = timer_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> +};
> +
> +static void timer_hit(void *opaque)
> +{
> + struct Msf2Timer *st = opaque;
> +
> + DB_PRINT("%d\n", st->nr);
Maybe make this clearer.
> + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
> +
> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
> + timer_update(st);
> + }
> + timer_update_irq(st);
> +}
> +
> +static void msf2_timer_init(Object *obj)
> +{
> + MSF2TimerState *t = MSF2_TIMER(obj);
> + unsigned int i;
int i;
> +
> + /* Init all the ptimers. */
> + t->timers = g_malloc0((sizeof t->timers[0]) * NUM_TIMERS);
> + for (i = 0; i < NUM_TIMERS; i++) {
> + struct Msf2Timer *st = &t->timers[i];
> +
> + st->nr = i;
> + st->bh = qemu_bh_new(timer_hit, st);
> + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
> + ptimer_set_freq(st->ptimer, t->freq_hz);
> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
> + }
> +
> + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSF2_TIMER,
> + R_TIM_MAX * 4);
> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
> +}
> +
> +static Property msf2_timer_properties[] = {
> + DEFINE_PROP_UINT32("clock-frequency", MSF2TimerState, freq_hz,
> + 83 * 1000000),
This value should be a macro.
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void msf2_timer_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->props = msf2_timer_properties;
> +}
> +
> +static const TypeInfo msf2_timer_info = {
> + .name = TYPE_MSF2_TIMER,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSF2TimerState),
> + .instance_init = msf2_timer_init,
> + .class_init = msf2_timer_class_init,
> +};
> +
> +static void msf2_timer_register_types(void)
> +{
> + type_register_static(&msf2_timer_info);
> +}
> +
> +type_init(msf2_timer_register_types)
> diff --git a/include/hw/timer/msf2_timer.h b/include/hw/timer/msf2_timer.h
> new file mode 100644
> index 0000000..93d9fb3
> --- /dev/null
> +++ b/include/hw/timer/msf2_timer.h
> @@ -0,0 +1,82 @@
> +/*
> + * Microsemi SmartFusion2 Timer.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_MSF2_TIMER_H
> +#define HW_MSF2_TIMER_H
> +
> +#include "hw/sysbus.h"
> +#include "hw/ptimer.h"
> +#include "sysemu/sysemu.h"
I think osdep should be included in header files as well.
> +
> +#define TYPE_MSF2_TIMER "msf2-timer"
> +#define MSF2_TIMER(obj) OBJECT_CHECK(MSF2TimerState, \
> + (obj), TYPE_MSF2_TIMER)
> +
> +/*
> + * There are two 32-bit down counting timers.
> + * Timers 1 and 2 can be concatenated into a single 64-bit Timer
> + * that operates either in Periodic mode or in One-shot mode.
> + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
> + * In 64-bit mode, writing to the 32-bit registers has no effect.
> + * Similarly, in 32-bit mode, writing to the 64-bit mode registers
> + * has no effect. Only two 32-bit timers are supported currently.
> + */
> +#define NUM_TIMERS 2
> +
> +#define R_TIM_VAL 0
> +#define R_TIM_LOADVAL 1
> +#define R_TIM_BGLOADVAL 2
> +#define R_TIM_CTRL 3
> +#define R_TIM_RIS 4
> +#define R_TIM_MIS 5
> +#define R_TIM1_MAX 6
> +
> +#define R_TIM_MODE 21
> +#define R_TIM_MAX 22 /* including 64-bit timer registers */
> +
> +#define TIMER_CTRL_ENBL (1 << 0)
> +#define TIMER_CTRL_ONESHOT (1 << 1)
> +#define TIMER_CTRL_INTR (1 << 2)
> +#define TIMER_RIS_ACK (1 << 0)
> +#define TIMER_RST_CLR (1 << 6)
> +#define TIMER_MODE (1 << 0)
> +
> +struct Msf2Timer {
> + QEMUBH *bh;
> + ptimer_state *ptimer;
> + int nr; /* for debug. */
What is this used for?
Thanks,
Alistair
> +
> + uint32_t regs[R_TIM_MAX];
> + qemu_irq irq;
> +};
> +
> +typedef struct MSF2TimerState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion mmio;
> + uint32_t freq_hz;
> + struct Msf2Timer *timers;
> +} MSF2TimerState;
> +
> +#endif /* HW_MSF2_TIMER_H */
> --
> 2.5.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer
2017-05-02 21:55 ` Alistair Francis
@ 2017-05-03 5:11 ` sundeep subbaraya
2017-05-03 23:32 ` Alistair Francis
0 siblings, 1 reply; 16+ messages in thread
From: sundeep subbaraya @ 2017-05-03 5:11 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
Hi Alistair,
On Wed, May 3, 2017 at 3:25 AM, Alistair Francis <alistair23@gmail.com> wrote:
> On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
> <sundeep.lkml@gmail.com> wrote:
>> Modelled System Timer in Microsemi's Smartfusion2 Soc.
>> Timer has two 32bit down counters and two interrupts.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> ---
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/msf2_timer.c | 250 ++++++++++++++++++++++++++++++++++++++++++
>> include/hw/timer/msf2_timer.h | 82 ++++++++++++++
>> 3 files changed, 333 insertions(+)
>> create mode 100644 hw/timer/msf2_timer.c
>> create mode 100644 include/hw/timer/msf2_timer.h
>>
>> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
>> index dd6f27e..0bdf1e1 100644
>> --- a/hw/timer/Makefile.objs
>> +++ b/hw/timer/Makefile.objs
>> @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
>> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
>>
>> common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
>> +common-obj-$(CONFIG_MSF2) += msf2_timer.o
>> diff --git a/hw/timer/msf2_timer.c b/hw/timer/msf2_timer.c
>> new file mode 100644
>> index 0000000..d1dbde5
>> --- /dev/null
>> +++ b/hw/timer/msf2_timer.c
>
> Hey Sundeep,
>
> File names should use '-' instead of '_'.
Ok will change.
>
>> @@ -0,0 +1,250 @@
>> +/*
>> + * Timer block model of Microsemi SmartFusion2.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/timer/msf2_timer.h"
>> +#include "hw/sysbus.h"
>> +#include "qemu/log.h"
>> +#include "qemu/main-loop.h"
>
> Do you need to include the main-loop.h? This doesn't look right.
>
Ok I will remove it.
>> +
>> +#ifndef MSF2_TIMER_ERR_DEBUG
>> +#define MSF2_TIMER_ERR_DEBUG 0
>> +#endif
>> +
>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>> + if (MSF2_TIMER_ERR_DEBUG >= lvl) { \
>> + qemu_log("%s: " fmt, __func__, ## args); \
>> + } \
>> +} while (0);
>> +
>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>> +
>> +static void timer_update_irq(struct Msf2Timer *st)
>> +{
>> + bool isr, ier;
>> +
>> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
>> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
>> +
>> + qemu_set_irq(st->irq, (ier && isr));
>> +}
>> +
>> +static void timer_update(struct Msf2Timer *st)
>> +{
>> + uint64_t count;
>> +
>> + DB_PRINT("timer=%d\n", st->nr);
>
> Maybe make this a little more explict. Something like "Updating timer: %d"?
>
Yeah will change that.
>> +
>> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
>> + ptimer_stop(st->ptimer);
>> + return;
>> + }
>> +
>> + count = st->regs[R_TIM_LOADVAL];
>> + ptimer_set_limit(st->ptimer, count, 1);
>> + ptimer_run(st->ptimer, 1);
>> +}
>> +
>> +static uint64_t
>> +timer_read(void *opaque, hwaddr addr, unsigned int size)
>> +{
>> + MSF2TimerState *t = opaque;
>> + struct Msf2Timer *st;
>> + uint32_t r = 0;
>
> Call the ret instead of r and it should be a uint64_t.
>
I will change to ret. I guess uint32_t is fine because same is used
for returning values in 32 bit registers.
>> + unsigned int timer = 0;
>
> Isn't the timer normally an int? Try to use the same type throughout the code.
>
Ok will use int.
>> + int isr;
>> + int ier;
>> +
>> + addr >>= 2;
>> + /*
>> + * Two independent timers has same base address.
>> + * Based on addr passed figure out which timer is being used.
>> + */
>> + if (addr >= R_TIM1_MAX) {
>> + timer = 1;
>> + addr -= R_TIM1_MAX;
>> + }
>> +
>> + st = &t->timers[timer];
>> +
>> + switch (addr) {
>> + case R_TIM_VAL:
>> + r = ptimer_get_count(st->ptimer);
>> + DB_PRINT("msf2_timer t=%d read counter=%x\n", timer, r);
>
> Put a 0x in front of hex values.
>
Ok
> Also %x isn't the correct type for uint64_t, it's something similar to PRIx.
>
Yeah build test reported these errors. I will fix them.
>> + break;
>> +
>> + case R_TIM_MIS:
>> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
>> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
>> + r = ier && isr;
>
> This should be a bitwise AND.
>
Ok
>> + break;
>> +
>> + default:
>> + if (addr < ARRAY_SIZE(st->regs)) {
>> + r = st->regs[addr];
>> + }
>
> If the write is outside the array you should print a guest error.
>
Ok
>> + break;
>> + }
>> + DB_PRINT("timer=%d %lu=%x\n", timer, addr * 4, r);
>> + return r;
>> +}
>> +
>> +static void
>> +timer_write(void *opaque, hwaddr addr,
>> + uint64_t val64, unsigned int size)
>> +{
>> + MSF2TimerState *t = opaque;
>> + struct Msf2Timer *st;
>> + unsigned int timer = 0;
>> + uint32_t value = val64;
>> +
>> + addr >>= 2;
>> + /*
>> + * Two independent timers has same base address.
>> + * Based on addr passed figure out which timer is being used.
>> + */
>> + if (addr >= R_TIM1_MAX) {
>> + timer = 1;
>> + addr -= R_TIM1_MAX;
>> + }
>> +
>> + st = &t->timers[timer];
>> +
>> + DB_PRINT("addr=%lu val=%x (timer=%d)\n", addr * 4, value, timer);
>> +
>> + switch (addr) {
>> + case R_TIM_CTRL:
>> + st->regs[R_TIM_CTRL] = value;
>> + timer_update(st);
>> + break;
>> +
>> + case R_TIM_RIS:
>> + if (value & TIMER_RIS_ACK) {
>> + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
>> + }
>> + break;
>> +
>> + case R_TIM_LOADVAL:
>> + st->regs[R_TIM_LOADVAL] = value;
>> + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
>> + timer_update(st);
>> + }
>> + break;
>> +
>> + case R_TIM_BGLOADVAL:
>> + st->regs[R_TIM_BGLOADVAL] = value;
>> + st->regs[R_TIM_LOADVAL] = value;
>> + break;
>> +
>> + case R_TIM_VAL:
>> + case R_TIM_MIS:
>> + break;
>> +
>> + case R_TIM_MODE:
>> + if (value & TIMER_MODE) {
>> + DB_PRINT("64-bit mode not supported\n");
>
> There is an unimp mask for qemu_log() which you should use here.
>
I see. I will change it.
>> + }
>> + break;
>> +
>> + default:
>> + if (addr < ARRAY_SIZE(st->regs)) {
>> + st->regs[addr] = value;
>> + }
>> + break;
>> + }
>> + timer_update_irq(st);
>> +}
>> +
>> +static const MemoryRegionOps timer_ops = {
>> + .read = timer_read,
>> + .write = timer_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4
>> + }
>> +};
>> +
>> +static void timer_hit(void *opaque)
>> +{
>> + struct Msf2Timer *st = opaque;
>> +
>> + DB_PRINT("%d\n", st->nr);
>
> Maybe make this clearer.
>
Ok
>> + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
>> +
>> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
>> + timer_update(st);
>> + }
>> + timer_update_irq(st);
>> +}
>> +
>> +static void msf2_timer_init(Object *obj)
>> +{
>> + MSF2TimerState *t = MSF2_TIMER(obj);
>> + unsigned int i;
>
> int i;
>
Ok
>> +
>> + /* Init all the ptimers. */
>> + t->timers = g_malloc0((sizeof t->timers[0]) * NUM_TIMERS);
>> + for (i = 0; i < NUM_TIMERS; i++) {
>> + struct Msf2Timer *st = &t->timers[i];
>> +
>> + st->nr = i;
>> + st->bh = qemu_bh_new(timer_hit, st);
>> + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
>> + ptimer_set_freq(st->ptimer, t->freq_hz);
>> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
>> + }
>> +
>> + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSF2_TIMER,
>> + R_TIM_MAX * 4);
>> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
>> +}
>> +
>> +static Property msf2_timer_properties[] = {
>> + DEFINE_PROP_UINT32("clock-frequency", MSF2TimerState, freq_hz,
>> + 83 * 1000000),
>
> This value should be a macro.
>
Yes will add in header file.
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void msf2_timer_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->props = msf2_timer_properties;
>> +}
>> +
>> +static const TypeInfo msf2_timer_info = {
>> + .name = TYPE_MSF2_TIMER,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(MSF2TimerState),
>> + .instance_init = msf2_timer_init,
>> + .class_init = msf2_timer_class_init,
>> +};
>> +
>> +static void msf2_timer_register_types(void)
>> +{
>> + type_register_static(&msf2_timer_info);
>> +}
>> +
>> +type_init(msf2_timer_register_types)
>> diff --git a/include/hw/timer/msf2_timer.h b/include/hw/timer/msf2_timer.h
>> new file mode 100644
>> index 0000000..93d9fb3
>> --- /dev/null
>> +++ b/include/hw/timer/msf2_timer.h
>> @@ -0,0 +1,82 @@
>> +/*
>> + * Microsemi SmartFusion2 Timer.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_MSF2_TIMER_H
>> +#define HW_MSF2_TIMER_H
>> +
>> +#include "hw/sysbus.h"
>> +#include "hw/ptimer.h"
>> +#include "sysemu/sysemu.h"
>
> I think osdep should be included in header files as well.
>
Ok will add.
>> +
>> +#define TYPE_MSF2_TIMER "msf2-timer"
>> +#define MSF2_TIMER(obj) OBJECT_CHECK(MSF2TimerState, \
>> + (obj), TYPE_MSF2_TIMER)
>> +
>> +/*
>> + * There are two 32-bit down counting timers.
>> + * Timers 1 and 2 can be concatenated into a single 64-bit Timer
>> + * that operates either in Periodic mode or in One-shot mode.
>> + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
>> + * In 64-bit mode, writing to the 32-bit registers has no effect.
>> + * Similarly, in 32-bit mode, writing to the 64-bit mode registers
>> + * has no effect. Only two 32-bit timers are supported currently.
>> + */
>> +#define NUM_TIMERS 2
>> +
>> +#define R_TIM_VAL 0
>> +#define R_TIM_LOADVAL 1
>> +#define R_TIM_BGLOADVAL 2
>> +#define R_TIM_CTRL 3
>> +#define R_TIM_RIS 4
>> +#define R_TIM_MIS 5
>> +#define R_TIM1_MAX 6
>> +
>> +#define R_TIM_MODE 21
>> +#define R_TIM_MAX 22 /* including 64-bit timer registers */
>> +
>> +#define TIMER_CTRL_ENBL (1 << 0)
>> +#define TIMER_CTRL_ONESHOT (1 << 1)
>> +#define TIMER_CTRL_INTR (1 << 2)
>> +#define TIMER_RIS_ACK (1 << 0)
>> +#define TIMER_RST_CLR (1 << 6)
>> +#define TIMER_MODE (1 << 0)
>> +
>> +struct Msf2Timer {
>> + QEMUBH *bh;
>> + ptimer_state *ptimer;
>> + int nr; /* for debug. */
>
> What is this used for?
>
Just for debugging which timer is being handled.
Also can you please answer my query on SPI controller model patch.
Thanks,
Sundeep
> Thanks,
>
> Alistair
>
>> +
>> + uint32_t regs[R_TIM_MAX];
>> + qemu_irq irq;
>> +};
>> +
>> +typedef struct MSF2TimerState {
>> + SysBusDevice parent_obj;
>> +
>> + MemoryRegion mmio;
>> + uint32_t freq_hz;
>> + struct Msf2Timer *timers;
>> +} MSF2TimerState;
>> +
>> +#endif /* HW_MSF2_TIMER_H */
>> --
>> 2.5.0
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer
2017-05-03 5:11 ` sundeep subbaraya
@ 2017-05-03 23:32 ` Alistair Francis
0 siblings, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2017-05-03 23:32 UTC (permalink / raw)
To: sundeep subbaraya
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
On Tue, May 2, 2017 at 10:11 PM, sundeep subbaraya
<sundeep.lkml@gmail.com> wrote:
> Hi Alistair,
>
> On Wed, May 3, 2017 at 3:25 AM, Alistair Francis <alistair23@gmail.com> wrote:
>> On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
>> <sundeep.lkml@gmail.com> wrote:
>>> Modelled System Timer in Microsemi's Smartfusion2 Soc.
>>> Timer has two 32bit down counters and two interrupts.
>>>
>>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> ---
>>> hw/timer/Makefile.objs | 1 +
>>> hw/timer/msf2_timer.c | 250 ++++++++++++++++++++++++++++++++++++++++++
>>> include/hw/timer/msf2_timer.h | 82 ++++++++++++++
>>> 3 files changed, 333 insertions(+)
>>> create mode 100644 hw/timer/msf2_timer.c
>>> create mode 100644 include/hw/timer/msf2_timer.h
>>>
>>> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
>>> index dd6f27e..0bdf1e1 100644
>>> --- a/hw/timer/Makefile.objs
>>> +++ b/hw/timer/Makefile.objs
>>> @@ -41,3 +41,4 @@ common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
>>> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
>>>
>>> common-obj-$(CONFIG_SUN4V_RTC) += sun4v-rtc.o
>>> +common-obj-$(CONFIG_MSF2) += msf2_timer.o
>>> diff --git a/hw/timer/msf2_timer.c b/hw/timer/msf2_timer.c
>>> new file mode 100644
>>> index 0000000..d1dbde5
>>> --- /dev/null
>>> +++ b/hw/timer/msf2_timer.c
>>
>> Hey Sundeep,
>>
>> File names should use '-' instead of '_'.
>
> Ok will change.
>>
>>> @@ -0,0 +1,250 @@
>>> +/*
>>> + * Timer block model of Microsemi SmartFusion2.
>>> + *
>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>.
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>> + * of this software and associated documentation files (the "Software"), to deal
>>> + * in the Software without restriction, including without limitation the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +
>>> +#include "qemu/osdep.h"
>>> +#include "hw/timer/msf2_timer.h"
>>> +#include "hw/sysbus.h"
>>> +#include "qemu/log.h"
>>> +#include "qemu/main-loop.h"
>>
>> Do you need to include the main-loop.h? This doesn't look right.
>>
> Ok I will remove it.
>
>>> +
>>> +#ifndef MSF2_TIMER_ERR_DEBUG
>>> +#define MSF2_TIMER_ERR_DEBUG 0
>>> +#endif
>>> +
>>> +#define DB_PRINT_L(lvl, fmt, args...) do { \
>>> + if (MSF2_TIMER_ERR_DEBUG >= lvl) { \
>>> + qemu_log("%s: " fmt, __func__, ## args); \
>>> + } \
>>> +} while (0);
>>> +
>>> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
>>> +
>>> +static void timer_update_irq(struct Msf2Timer *st)
>>> +{
>>> + bool isr, ier;
>>> +
>>> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
>>> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
>>> +
>>> + qemu_set_irq(st->irq, (ier && isr));
>>> +}
>>> +
>>> +static void timer_update(struct Msf2Timer *st)
>>> +{
>>> + uint64_t count;
>>> +
>>> + DB_PRINT("timer=%d\n", st->nr);
>>
>> Maybe make this a little more explict. Something like "Updating timer: %d"?
>>
> Yeah will change that.
>>> +
>>> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) {
>>> + ptimer_stop(st->ptimer);
>>> + return;
>>> + }
>>> +
>>> + count = st->regs[R_TIM_LOADVAL];
>>> + ptimer_set_limit(st->ptimer, count, 1);
>>> + ptimer_run(st->ptimer, 1);
>>> +}
>>> +
>>> +static uint64_t
>>> +timer_read(void *opaque, hwaddr addr, unsigned int size)
>>> +{
>>> + MSF2TimerState *t = opaque;
>>> + struct Msf2Timer *st;
>>> + uint32_t r = 0;
>>
>> Call the ret instead of r and it should be a uint64_t.
>>
> I will change to ret. I guess uint32_t is fine because same is used
> for returning values in 32 bit registers.
>
>>> + unsigned int timer = 0;
>>
>> Isn't the timer normally an int? Try to use the same type throughout the code.
>>
> Ok will use int.
>
>>> + int isr;
>>> + int ier;
>>> +
>>> + addr >>= 2;
>>> + /*
>>> + * Two independent timers has same base address.
>>> + * Based on addr passed figure out which timer is being used.
>>> + */
>>> + if (addr >= R_TIM1_MAX) {
>>> + timer = 1;
>>> + addr -= R_TIM1_MAX;
>>> + }
>>> +
>>> + st = &t->timers[timer];
>>> +
>>> + switch (addr) {
>>> + case R_TIM_VAL:
>>> + r = ptimer_get_count(st->ptimer);
>>> + DB_PRINT("msf2_timer t=%d read counter=%x\n", timer, r);
>>
>> Put a 0x in front of hex values.
>>
> Ok
>> Also %x isn't the correct type for uint64_t, it's something similar to PRIx.
>>
> Yeah build test reported these errors. I will fix them.
>
>>> + break;
>>> +
>>> + case R_TIM_MIS:
>>> + isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK);
>>> + ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR);
>>> + r = ier && isr;
>>
>> This should be a bitwise AND.
>>
> Ok
>>> + break;
>>> +
>>> + default:
>>> + if (addr < ARRAY_SIZE(st->regs)) {
>>> + r = st->regs[addr];
>>> + }
>>
>> If the write is outside the array you should print a guest error.
>>
> Ok
>>> + break;
>>> + }
>>> + DB_PRINT("timer=%d %lu=%x\n", timer, addr * 4, r);
>>> + return r;
>>> +}
>>> +
>>> +static void
>>> +timer_write(void *opaque, hwaddr addr,
>>> + uint64_t val64, unsigned int size)
>>> +{
>>> + MSF2TimerState *t = opaque;
>>> + struct Msf2Timer *st;
>>> + unsigned int timer = 0;
>>> + uint32_t value = val64;
>>> +
>>> + addr >>= 2;
>>> + /*
>>> + * Two independent timers has same base address.
>>> + * Based on addr passed figure out which timer is being used.
>>> + */
>>> + if (addr >= R_TIM1_MAX) {
>>> + timer = 1;
>>> + addr -= R_TIM1_MAX;
>>> + }
>>> +
>>> + st = &t->timers[timer];
>>> +
>>> + DB_PRINT("addr=%lu val=%x (timer=%d)\n", addr * 4, value, timer);
>>> +
>>> + switch (addr) {
>>> + case R_TIM_CTRL:
>>> + st->regs[R_TIM_CTRL] = value;
>>> + timer_update(st);
>>> + break;
>>> +
>>> + case R_TIM_RIS:
>>> + if (value & TIMER_RIS_ACK) {
>>> + st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
>>> + }
>>> + break;
>>> +
>>> + case R_TIM_LOADVAL:
>>> + st->regs[R_TIM_LOADVAL] = value;
>>> + if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
>>> + timer_update(st);
>>> + }
>>> + break;
>>> +
>>> + case R_TIM_BGLOADVAL:
>>> + st->regs[R_TIM_BGLOADVAL] = value;
>>> + st->regs[R_TIM_LOADVAL] = value;
>>> + break;
>>> +
>>> + case R_TIM_VAL:
>>> + case R_TIM_MIS:
>>> + break;
>>> +
>>> + case R_TIM_MODE:
>>> + if (value & TIMER_MODE) {
>>> + DB_PRINT("64-bit mode not supported\n");
>>
>> There is an unimp mask for qemu_log() which you should use here.
>>
> I see. I will change it.
>>> + }
>>> + break;
>>> +
>>> + default:
>>> + if (addr < ARRAY_SIZE(st->regs)) {
>>> + st->regs[addr] = value;
>>> + }
>>> + break;
>>> + }
>>> + timer_update_irq(st);
>>> +}
>>> +
>>> +static const MemoryRegionOps timer_ops = {
>>> + .read = timer_read,
>>> + .write = timer_write,
>>> + .endianness = DEVICE_NATIVE_ENDIAN,
>>> + .valid = {
>>> + .min_access_size = 4,
>>> + .max_access_size = 4
>>> + }
>>> +};
>>> +
>>> +static void timer_hit(void *opaque)
>>> +{
>>> + struct Msf2Timer *st = opaque;
>>> +
>>> + DB_PRINT("%d\n", st->nr);
>>
>> Maybe make this clearer.
>>
> Ok
>>> + st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
>>> +
>>> + if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
>>> + timer_update(st);
>>> + }
>>> + timer_update_irq(st);
>>> +}
>>> +
>>> +static void msf2_timer_init(Object *obj)
>>> +{
>>> + MSF2TimerState *t = MSF2_TIMER(obj);
>>> + unsigned int i;
>>
>> int i;
>>
> Ok
>>> +
>>> + /* Init all the ptimers. */
>>> + t->timers = g_malloc0((sizeof t->timers[0]) * NUM_TIMERS);
>>> + for (i = 0; i < NUM_TIMERS; i++) {
>>> + struct Msf2Timer *st = &t->timers[i];
>>> +
>>> + st->nr = i;
>>> + st->bh = qemu_bh_new(timer_hit, st);
>>> + st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT);
>>> + ptimer_set_freq(st->ptimer, t->freq_hz);
>>> + sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq);
>>> + }
>>> +
>>> + memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSF2_TIMER,
>>> + R_TIM_MAX * 4);
>>> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio);
>>> +}
>>> +
>>> +static Property msf2_timer_properties[] = {
>>> + DEFINE_PROP_UINT32("clock-frequency", MSF2TimerState, freq_hz,
>>> + 83 * 1000000),
>>
>> This value should be a macro.
>>
> Yes will add in header file.
>
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>> +
>>> +static void msf2_timer_class_init(ObjectClass *klass, void *data)
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>> +
>>> + dc->props = msf2_timer_properties;
>>> +}
>>> +
>>> +static const TypeInfo msf2_timer_info = {
>>> + .name = TYPE_MSF2_TIMER,
>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>> + .instance_size = sizeof(MSF2TimerState),
>>> + .instance_init = msf2_timer_init,
>>> + .class_init = msf2_timer_class_init,
>>> +};
>>> +
>>> +static void msf2_timer_register_types(void)
>>> +{
>>> + type_register_static(&msf2_timer_info);
>>> +}
>>> +
>>> +type_init(msf2_timer_register_types)
>>> diff --git a/include/hw/timer/msf2_timer.h b/include/hw/timer/msf2_timer.h
>>> new file mode 100644
>>> index 0000000..93d9fb3
>>> --- /dev/null
>>> +++ b/include/hw/timer/msf2_timer.h
>>> @@ -0,0 +1,82 @@
>>> +/*
>>> + * Microsemi SmartFusion2 Timer.
>>> + *
>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>> + * of this software and associated documentation files (the "Software"), to deal
>>> + * in the Software without restriction, including without limitation the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +
>>> +#ifndef HW_MSF2_TIMER_H
>>> +#define HW_MSF2_TIMER_H
>>> +
>>> +#include "hw/sysbus.h"
>>> +#include "hw/ptimer.h"
>>> +#include "sysemu/sysemu.h"
>>
>> I think osdep should be included in header files as well.
>>
> Ok will add.
>>> +
>>> +#define TYPE_MSF2_TIMER "msf2-timer"
>>> +#define MSF2_TIMER(obj) OBJECT_CHECK(MSF2TimerState, \
>>> + (obj), TYPE_MSF2_TIMER)
>>> +
>>> +/*
>>> + * There are two 32-bit down counting timers.
>>> + * Timers 1 and 2 can be concatenated into a single 64-bit Timer
>>> + * that operates either in Periodic mode or in One-shot mode.
>>> + * Writing 1 to the TIM64_MODE register bit 0 sets the Timers in 64-bit mode.
>>> + * In 64-bit mode, writing to the 32-bit registers has no effect.
>>> + * Similarly, in 32-bit mode, writing to the 64-bit mode registers
>>> + * has no effect. Only two 32-bit timers are supported currently.
>>> + */
>>> +#define NUM_TIMERS 2
>>> +
>>> +#define R_TIM_VAL 0
>>> +#define R_TIM_LOADVAL 1
>>> +#define R_TIM_BGLOADVAL 2
>>> +#define R_TIM_CTRL 3
>>> +#define R_TIM_RIS 4
>>> +#define R_TIM_MIS 5
>>> +#define R_TIM1_MAX 6
>>> +
>>> +#define R_TIM_MODE 21
>>> +#define R_TIM_MAX 22 /* including 64-bit timer registers */
>>> +
>>> +#define TIMER_CTRL_ENBL (1 << 0)
>>> +#define TIMER_CTRL_ONESHOT (1 << 1)
>>> +#define TIMER_CTRL_INTR (1 << 2)
>>> +#define TIMER_RIS_ACK (1 << 0)
>>> +#define TIMER_RST_CLR (1 << 6)
>>> +#define TIMER_MODE (1 << 0)
>>> +
>>> +struct Msf2Timer {
>>> + QEMUBH *bh;
>>> + ptimer_state *ptimer;
>>> + int nr; /* for debug. */
>>
>> What is this used for?
>>
> Just for debugging which timer is being handled.
It's probably best to just pass that information into the function
instead of having it in the struct.
> Also can you please answer my query on SPI controller model patch.
Ok, will do.
Thanks,
Alistair
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
2017-05-02 5:02 ` sundeep subbaraya
@ 2017-05-03 23:39 ` Alistair Francis
1 sibling, 0 replies; 16+ messages in thread
From: Alistair Francis @ 2017-05-03 23:39 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
(_On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
<sundeep.lkml@gmail.com> wrote:
> Modelled Microsemi's Smartfusion2 SPI controller.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> Hi Peter and Alistair,
>
> I created two SPI controllers as per SoC spec
> in hw/arm/msf2_soc.c. I am assuming there has to be two
> busses spi0 and spi1 one for each controller. In board file
> (hw/arm/msf2_som.c) attached SPI flash to SPI0 controller.
> I am not able to understand(from hw/ssi/xilinx_spips.c)
> how to create two busses in hw/ssi/msf2_spi.c.
> Please help me here. Below is the output of info qtree:
>
> (qemu) info qtree
> bus: main-system-bus
> type System
> dev: msf2-soc, id ""
> cpu-model = "cortex-m3"
> dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040011000/0000000000000040
> bus: spi0
> type SSI
> dev: msf2-spi, id ""
> gpio-out "sysbus-irq" 2
> mmio 0000000040001000/0000000000000040
> bus: spi0
> type SSI
> dev: s25sl12801, id ""
> gpio-in "ssi-gpio-cs" 1
> nonvolatile-cfg = 36863 (0x8fff)
> spansion-cr1nv = 0 (0x0)
> spansion-cr2nv = 1 (0x1)
> spansion-cr3nv = 2 (0x2)
> spansion-cr4nv = 16 (0x10)
> drive = "mtd0"
Hey Sundeep,
This looks like you have created two SPI devices with one bus each.
What you want (I think) is one SPI device with two busses.
>
> Thanks,
> Sundeep
>
> hw/ssi/Makefile.objs | 1 +
> hw/ssi/msf2_spi.c | 373 ++++++++++++++++++++++++++++++++++++++++++++++
> include/hw/ssi/msf2_spi.h | 102 +++++++++++++
> 3 files changed, 476 insertions(+)
> create mode 100644 hw/ssi/msf2_spi.c
> create mode 100644 include/hw/ssi/msf2_spi.h
>
> diff --git a/hw/ssi/Makefile.objs b/hw/ssi/Makefile.objs
> index 487add2..86445d7 100644
> --- a/hw/ssi/Makefile.objs
> +++ b/hw/ssi/Makefile.objs
> @@ -4,6 +4,7 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
> common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
> common-obj-$(CONFIG_ASPEED_SOC) += aspeed_smc.o
> common-obj-$(CONFIG_STM32F2XX_SPI) += stm32f2xx_spi.o
> +common-obj-$(CONFIG_MSF2) += msf2_spi.o
>
> obj-$(CONFIG_OMAP) += omap_spi.o
> obj-$(CONFIG_IMX) += imx_spi.o
> diff --git a/hw/ssi/msf2_spi.c b/hw/ssi/msf2_spi.c
> new file mode 100644
> index 0000000..e7ffa21
> --- /dev/null
> +++ b/hw/ssi/msf2_spi.c
> @@ -0,0 +1,373 @@
> +/*
> + * SPI controller model of Microsemi SmartFusion2.
> + *
> + * Copyright (C) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/ssi/msf2_spi.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/log.h"
> +
> +#ifndef MSF2_SPI_ERR_DEBUG
> +#define MSF2_SPI_ERR_DEBUG 0
> +#endif
> +
> +#define DB_PRINT_L(lvl, fmt, args...) do { \
> + if (MSF2_SPI_ERR_DEBUG >= lvl) { \
> + qemu_log("%s: " fmt, __func__, ## args); \
> + } \
> +} while (0);
> +
> +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
> +
> +static void txfifo_reset(MSF2SpiState *s)
> +{
> + fifo32_reset(&s->tx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_TXFIFOEMP;
> +}
> +
> +static void rxfifo_reset(MSF2SpiState *s)
> +{
> + fifo32_reset(&s->rx_fifo);
> +
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> +}
> +
> +static void set_fifodepth(MSF2SpiState *s)
> +{
> + int size = s->regs[R_SPI_DFSIZE] & FRAMESZ_MASK;
> +
> + if (0 <= size && size <= 8) {
> + s->fifo_depth = 32;
> + }
> + if (9 <= size && size <= 16) {
> + s->fifo_depth = 16;
> + }
> + if (17 <= size && size <= 32) {
> + s->fifo_depth = 8;
> + }
> +}
> +
> +static void msf2_spi_do_reset(MSF2SpiState *s)
> +{
> + memset(s->regs, 0, sizeof s->regs);
> + s->regs[R_SPI_CONTROL] = 0x80000102;
> + s->regs[R_SPI_DFSIZE] = 0x4;
> + s->regs[R_SPI_STATUS] = 0x2440;
> + s->regs[R_SPI_CLKGEN] = 0x7;
> + s->regs[R_SPI_STAT8] = 0x7;
> + s->regs[R_SPI_RIS] = 0x0;
> +
> + s->fifo_depth = 4;
> + s->frame_count = 1;
> + s->enabled = false;
> +
> + rxfifo_reset(s);
> + txfifo_reset(s);
> +}
> +
> +static void update_mis(MSF2SpiState *s)
> +{
> + uint32_t reg = s->regs[R_SPI_CONTROL];
> + uint32_t tmp;
> +
> + /*
> + * form the Control register interrupt enable bits
> + * same as RIS, MIS and Interrupt clear registers for simplicity
> + */
> + tmp = ((reg & C_INTRXOVRFLO) >> 4) | ((reg & C_INTRXDATA) >> 3) |
> + ((reg & C_INTTXDATA) >> 5);
> + s->regs[R_SPI_MIS] |= tmp & s->regs[R_SPI_RIS];
> +}
> +
> +static void spi_update_irq(MSF2SpiState *s)
> +{
> + int irq;
> +
> + update_mis(s);
> + irq = !!(s->regs[R_SPI_MIS]);
> +
> + qemu_set_irq(s->irq, irq);
> +}
> +
> +static void msf2_spi_reset(DeviceState *d)
> +{
> + msf2_spi_do_reset(MSF2_SPI(d));
> +}
> +
> +static uint64_t
> +spi_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> + MSF2SpiState *s = opaque;
> + uint32_t r = 0;
> +
> + addr >>= 2;
> + switch (addr) {
> + case R_SPI_RX:
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOFUL;
> + s->regs[R_SPI_STATUS] &= ~RXCHOVRF;
> + r = fifo32_pop(&s->rx_fifo);
> + if (fifo32_is_empty(&s->rx_fifo)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOEMP;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + update_mis(s);
> + r = s->regs[R_SPI_MIS];
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + r = s->regs[addr];
> + }
> + break;
> + }
> +
> + DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
> + spi_update_irq(s);
> + return r;
> +}
> +
> +static void assert_cs(MSF2SpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 0);
> +}
> +
> +static void deassert_cs(MSF2SpiState *s)
> +{
> + qemu_set_irq(s->cs_line, 1);
> +}
> +
> +static void spi_flush_txfifo(MSF2SpiState *s)
> +{
> + uint32_t tx;
> + uint32_t rx;
> + bool sps = !!(s->regs[R_SPI_CONTROL] & C_SPS);
> +
> + /*
> + * Chip Select(CS) is automatically controlled by this controller.
> + * If SPS bit is set in Control register then CS is asserted
> + * until all the frames set in frame count of Control register are
> + * transferred. If SPS is not set then CS pulses between frames.
> + * Note that Slave Select register specifies which of the CS line
> + * has to be controlled automatically by controller. Bits SS[7:1] are for
> + * masters in FPGA fabric since we model only Microcontroller subsystem
> + * of Smartfusion2 we control only one CS(SS[0]) line.
> + */
> + while (!fifo32_is_empty(&s->tx_fifo) && s->frame_count) {
> + assert_cs(s);
> +
> + s->regs[R_SPI_STATUS] &= ~TXDONE;
> + s->regs[R_SPI_STATUS] &= ~RXRDY;
> +
> + tx = fifo32_pop(&s->tx_fifo);
> + DB_PRINT("data tx:%x\n", tx);
> + rx = ssi_transfer(s->spi, tx);
> + DB_PRINT("data rx:%x\n", rx);
> +
> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= RXCHOVRF;
> + s->regs[R_SPI_RIS] |= RXCHOVRF;
> + } else {
> + fifo32_push(&s->rx_fifo, rx);
> + s->regs[R_SPI_STATUS] &= ~S_RXFIFOEMP;
> + if (fifo32_num_used(&s->rx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFULNXT;
> + }
> + if (fifo32_num_used(&s->rx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_RXFIFOFUL;
> + }
> + }
> + s->frame_count--;
> + if (!sps) {
> + deassert_cs(s);
> + assert_cs(s);
> + }
> + }
> +
> + if (!sps) {
> + deassert_cs(s);
> + }
> +
> + if (!s->frame_count) {
> + s->frame_count = (s->regs[R_SPI_CONTROL] & FMCOUNT_MASK) >>
> + FMCOUNT_SHIFT;
> + if (sps) {
> + deassert_cs(s);
> + }
> + s->regs[R_SPI_RIS] |= TXDONE;
> + s->regs[R_SPI_RIS] |= RXRDY;
> + s->regs[R_SPI_STATUS] |= TXDONE;
> + s->regs[R_SPI_STATUS] |= RXRDY;
> + }
> +}
> +
> +static void spi_write(void *opaque, hwaddr addr,
> + uint64_t val64, unsigned int size)
> +{
> + MSF2SpiState *s = opaque;
> + uint32_t value = val64;
> +
> + DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
> + addr >>= 2;
> +
> + switch (addr) {
> + case R_SPI_TX:
> + /* adding to already full FIFO */
> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + break;
> + }
> + s->regs[R_SPI_STATUS] &= ~S_TXFIFOEMP;
> + fifo32_push(&s->tx_fifo, value);
> + if (fifo32_num_used(&s->tx_fifo) == (s->fifo_depth - 1)) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFULNXT;
> + }
> + if (fifo32_num_used(&s->tx_fifo) == s->fifo_depth) {
> + s->regs[R_SPI_STATUS] |= S_TXFIFOFUL;
> + }
> + if (s->enabled) {
> + spi_flush_txfifo(s);
> + }
> + break;
> +
> + case R_SPI_CONTROL:
> + s->regs[R_SPI_CONTROL] = value;
> + if (value & C_BIGFIFO) {
> + set_fifodepth(s);
> + } else {
> + s->fifo_depth = 4;
> + }
> + if (value & C_ENABLE) {
> + s->enabled = true;
> + } else {
> + s->enabled = false;
> + }
> + s->frame_count = (value & FMCOUNT_MASK) >> FMCOUNT_SHIFT;
> + if (value & C_RESET) {
> + msf2_spi_do_reset(s);
> + }
> + break;
> +
> + case R_SPI_DFSIZE:
> + if (s->enabled) {
> + break;
> + }
> + s->regs[R_SPI_DFSIZE] = value;
> + break;
> +
> + case R_SPI_INTCLR:
> + s->regs[R_SPI_INTCLR] = value;
> + if (value & TXDONE) {
> + s->regs[R_SPI_RIS] &= ~TXDONE;
> + }
> + if (value & RXRDY) {
> + s->regs[R_SPI_RIS] &= ~RXRDY;
> + }
> + if (value & RXCHOVRF) {
> + s->regs[R_SPI_RIS] &= ~RXCHOVRF;
> + }
> + break;
> +
> + case R_SPI_MIS:
> + case R_SPI_STATUS:
> + case R_SPI_RIS:
> + break;
> +
> + default:
> + if (addr < ARRAY_SIZE(s->regs)) {
> + s->regs[addr] = value;
> + }
> + break;
> + }
> +
> + spi_update_irq(s);
> +}
> +
> +static const MemoryRegionOps spi_ops = {
> + .read = spi_read,
> + .write = spi_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> +};
> +
> +static void msf2_spi_realize(DeviceState *dev, Error **errp)
> +{
> + MSF2SpiState *s = MSF2_SPI(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + DB_PRINT("\n");
> +
> + s->spi = ssi_create_bus(dev, "spi0");
You want to create a seperate spi bus "spi1" here as well.
Then the parent can call qdev_get_child_bus() to get the bus. In the
ZynqMP example we have to make an alias to pass it from the SoC to the
board.
Thanks,
Alistair
> +
> + sysbus_init_irq(sbd, &s->irq);
> + ssi_auto_connect_slaves(dev, &s->cs_line, s->spi);
> + sysbus_init_irq(sbd, &s->cs_line);
> +
> + memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
> + TYPE_MSF2_SPI, R_SPI_MAX * 4);
> + sysbus_init_mmio(sbd, &s->mmio);
> +
> + fifo32_create(&s->tx_fifo, FIFO_CAPACITY);
> + fifo32_create(&s->rx_fifo, FIFO_CAPACITY);
> +}
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC.
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
@ 2017-05-04 22:21 ` Alistair Francis
2017-05-05 16:14 ` sundeep subbaraya
0 siblings, 1 reply; 16+ messages in thread
From: Alistair Francis @ 2017-05-04 22:21 UTC (permalink / raw)
To: Subbaraya Sundeep
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
<sundeep.lkml@gmail.com> wrote:
> Smartfusion2 SoC has hardened Microcontroller subsystem
> and flash based FPGA fabric. This patch adds support for
> Microcontroller subsystem in the SoC.
>
> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
> ---
> default-configs/arm-softmmu.mak | 1 +
> hw/arm/Makefile.objs | 2 +-
> hw/arm/msf2_soc.c | 194 ++++++++++++++++++++++++++++++++++++++++
> include/hw/arm/msf2_soc.h | 62 +++++++++++++
> 4 files changed, 258 insertions(+), 1 deletion(-)
> create mode 100644 hw/arm/msf2_soc.c
> create mode 100644 include/hw/arm/msf2_soc.h
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index 78d7af0..7062512 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -122,3 +122,4 @@ CONFIG_ACPI=y
> CONFIG_SMBIOS=y
> CONFIG_ASPEED_SOC=y
> CONFIG_GPIO_KEY=y
> +CONFIG_MSF2=y
> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
> index 4c5c4ee..cce2759 100644
> --- a/hw/arm/Makefile.objs
> +++ b/hw/arm/Makefile.objs
> @@ -1,7 +1,7 @@
> obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
> obj-$(CONFIG_DIGIC) += digic_boards.o
> obj-y += integratorcp.o mainstone.o musicpal.o nseries.o
> -obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
> +obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o msf2_soc.o
> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
> obj-$(CONFIG_ACPI) += virt-acpi-build.o
> obj-y += netduino2.o
> diff --git a/hw/arm/msf2_soc.c b/hw/arm/msf2_soc.c
> new file mode 100644
> index 0000000..a470872
> --- /dev/null
> +++ b/hw/arm/msf2_soc.c
> @@ -0,0 +1,194 @@
> +/*
> + * SmartFusion2 SoC emulation.
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "qemu-common.h"
> +#include "hw/arm/arm.h"
> +#include "exec/address-spaces.h"
> +#include "hw/char/serial.h"
> +#include "hw/boards.h"
> +#include "sysemu/block-backend.h"
> +#include "hw/arm/msf2_soc.h"
> +
> +#define MSF2_TIMER_BASE 0x40004000
> +#define MSF2_SYSREG_BASE 0x40038000
> +
> +#define MSF2_TIMER_IRQ0 14
> +#define MSF2_TIMER_IRQ1 15
> +
> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
Hey Sundeep,
>From your other patch it sounds like this should just be a single SPI
device with to busses, so this will have to be re-worked.
> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
> +
> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
> +
> +static void msf2_soc_initfn(Object *obj)
> +{
> + MSF2State *s = MSF2_SOC(obj);
> + int i;
> +
> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
> +
> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
> +
> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSF2_TIMER);
> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
> + TYPE_MSF2_SPI);
> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
> + }
> +}
> +
> +static void msf2_soc_realize(DeviceState *dev_soc, Error **errp)
> +{
> + MSF2State *s = MSF2_SOC(dev_soc);
> + DeviceState *dev, *armv7m;
> + SysBusDevice *busdev;
> + Error *err = NULL;
> + int i;
> +
> + MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
> + MemoryRegion *sram = g_new(MemoryRegion, 1);
> + MemoryRegion *ddr = g_new(MemoryRegion, 1);
> +
> + memory_region_init_ram(nvm, NULL, "MSF2.envm", ENVM_SIZE,
> + &error_fatal);
> + memory_region_init_alias(nvm_alias, NULL, "MSF2.flash.alias",
> + nvm, 0, ENVM_SIZE);
> + vmstate_register_ram_global(nvm);
> +
> + memory_region_set_readonly(nvm, true);
> + memory_region_set_readonly(nvm_alias, true);
> +
> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
> + memory_region_add_subregion(system_memory, 0, nvm_alias);
> +
> + memory_region_init_ram(ddr, NULL, "MSF2.ddr", DDR_SIZE,
> + &error_fatal);
> + vmstate_register_ram_global(ddr);
> + memory_region_add_subregion(system_memory, DDR_BASE_ADDRESS, ddr);
> +
> + memory_region_init_ram(sram, NULL, "MSF2.sram", SRAM_SIZE,
> + &error_fatal);
> + vmstate_register_ram_global(sram);
> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
> +
> + armv7m = DEVICE(&s->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 96);
> + qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
> + "memory", &error_abort);
> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> +
> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
> + if (serial_hds[i]) {
> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
> + qdev_get_gpio_in(armv7m, uart_irq[i]),
> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
> + }
> + }
> +
> + dev = DEVICE(&s->timer);
> + qdev_prop_set_uint32(dev, "clock-frequency", 83 * 1000000);
Macro for the frequency.
> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
> + sysbus_connect_irq(busdev, 0,
> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
> + sysbus_connect_irq(busdev, 1,
> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
> +
> + dev = DEVICE(&s->sysreg);
> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
> +
> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
> + gchar *bus_name = g_strdup_printf("spi%d", i);
> +
> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
> + if (err != NULL) {
> + g_free(bus_name);
> + error_propagate(errp, err);
> + return;
> + }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
> + qdev_get_gpio_in(armv7m, spi_irq[i]));
> +
> + /* Alias controller SPI bus to the SoC itself */
> + object_property_add_alias(OBJECT(s), bus_name,
> + OBJECT(&s->spi[i]), "spi0",
> + &error_abort);
> + g_free(bus_name);
> + }
> +}
> +
> +static Property msf2_soc_properties[] = {
> + DEFINE_PROP_STRING("cpu-model", MSF2State, cpu_model),
Does this actually change?
This looks pretty good, just a few things to fix up.
Thanks,
Alistair
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void msf2_soc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->realize = msf2_soc_realize;
> + dc->props = msf2_soc_properties;
> +}
> +
> +static const TypeInfo msf2_soc_info = {
> + .name = TYPE_MSF2_SOC,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MSF2State),
> + .instance_init = msf2_soc_initfn,
> + .class_init = msf2_soc_class_init,
> +};
> +
> +static void msf2_soc_types(void)
> +{
> + type_register_static(&msf2_soc_info);
> +}
> +
> +type_init(msf2_soc_types)
> diff --git a/include/hw/arm/msf2_soc.h b/include/hw/arm/msf2_soc.h
> new file mode 100644
> index 0000000..1184d9a
> --- /dev/null
> +++ b/include/hw/arm/msf2_soc.h
> @@ -0,0 +1,62 @@
> +/*
> + * Microsemi Smartfusion2 SoC
> + *
> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_ARM_MSF2_SOC_H
> +#define HW_ARM_MSF2_SOC_H
> +
> +#include "hw/misc/msf2_sysreg.h"
> +#include "hw/timer/msf2_timer.h"
> +#include "hw/ssi/msf2_spi.h"
> +#include "hw/arm/armv7m.h"
> +
> +#define TYPE_MSF2_SOC "msf2-soc"
> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
> +
> +#define MSF2_NUM_SPIS 2
> +#define MSF2_NUM_UARTS 2
> +
> +#define ENVM_BASE_ADDRESS 0x60000000
> +#define ENVM_SIZE (128 * 1024)
> +
> +#define DDR_BASE_ADDRESS 0xA0000000
> +#define DDR_SIZE (64 * 1024 * 1024)
> +
> +#define SRAM_BASE_ADDRESS 0x20000000
> +#define SRAM_SIZE (64 * 1024)
> +
> +typedef struct MSF2State {
> + /*< private >*/
> + SysBusDevice parent_obj;
> + /*< public >*/
> +
> + char *cpu_model;
> +
> + ARMv7MState armv7m;
> +
> + MSF2SysregState sysreg;
> + MSF2TimerState timer;
> + MSF2SpiState spi[MSF2_NUM_SPIS];
> +} MSF2State;
> +
> +#endif
> --
> 2.5.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC.
2017-05-04 22:21 ` Alistair Francis
@ 2017-05-05 16:14 ` sundeep subbaraya
2017-05-05 23:53 ` Alistair Francis
0 siblings, 1 reply; 16+ messages in thread
From: sundeep subbaraya @ 2017-05-05 16:14 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
Hi Alistair,
On Fri, May 5, 2017 at 3:51 AM, Alistair Francis <alistair23@gmail.com> wrote:
> On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
> <sundeep.lkml@gmail.com> wrote:
>> Smartfusion2 SoC has hardened Microcontroller subsystem
>> and flash based FPGA fabric. This patch adds support for
>> Microcontroller subsystem in the SoC.
>>
>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> ---
>> default-configs/arm-softmmu.mak | 1 +
>> hw/arm/Makefile.objs | 2 +-
>> hw/arm/msf2_soc.c | 194 ++++++++++++++++++++++++++++++++++++++++
>> include/hw/arm/msf2_soc.h | 62 +++++++++++++
>> 4 files changed, 258 insertions(+), 1 deletion(-)
>> create mode 100644 hw/arm/msf2_soc.c
>> create mode 100644 include/hw/arm/msf2_soc.h
>>
>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
>> index 78d7af0..7062512 100644
>> --- a/default-configs/arm-softmmu.mak
>> +++ b/default-configs/arm-softmmu.mak
>> @@ -122,3 +122,4 @@ CONFIG_ACPI=y
>> CONFIG_SMBIOS=y
>> CONFIG_ASPEED_SOC=y
>> CONFIG_GPIO_KEY=y
>> +CONFIG_MSF2=y
>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>> index 4c5c4ee..cce2759 100644
>> --- a/hw/arm/Makefile.objs
>> +++ b/hw/arm/Makefile.objs
>> @@ -1,7 +1,7 @@
>> obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
>> obj-$(CONFIG_DIGIC) += digic_boards.o
>> obj-y += integratorcp.o mainstone.o musicpal.o nseries.o
>> -obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
>> +obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o msf2_soc.o
>> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
>> obj-$(CONFIG_ACPI) += virt-acpi-build.o
>> obj-y += netduino2.o
>> diff --git a/hw/arm/msf2_soc.c b/hw/arm/msf2_soc.c
>> new file mode 100644
>> index 0000000..a470872
>> --- /dev/null
>> +++ b/hw/arm/msf2_soc.c
>> @@ -0,0 +1,194 @@
>> +/*
>> + * SmartFusion2 SoC emulation.
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "qapi/error.h"
>> +#include "qemu-common.h"
>> +#include "hw/arm/arm.h"
>> +#include "exec/address-spaces.h"
>> +#include "hw/char/serial.h"
>> +#include "hw/boards.h"
>> +#include "sysemu/block-backend.h"
>> +#include "hw/arm/msf2_soc.h"
>> +
>> +#define MSF2_TIMER_BASE 0x40004000
>> +#define MSF2_SYSREG_BASE 0x40038000
>> +
>> +#define MSF2_TIMER_IRQ0 14
>> +#define MSF2_TIMER_IRQ1 15
>> +
>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
>
> Hey Sundeep,
>
> From your other patch it sounds like this should just be a single SPI
> device with to busses, so this will have to be re-worked.
>
I may be entirely wrong please correct me. I assumed this SoC and Board file
are analogous to dtsi and dts in linux. So SoC file will instantiate
all the controllers
like SPI0 and SPI1 present in SoC whereas board file will attach slaves present
on board (like EEPROM, SPI flashes etc.,). Hence in board file I
attached flash to
SPI0. I was expecting one bus for each controller eg:
SPI0:
bus: spi0
device: flash (Chip select 0)
device: other device (Chip select 1)
SPI1:
bus: spi1
device: other device (Chip select 0) (if attached in board file)
But this is not the case because am not able to create spi1 bus in
controller model
(hw/ssi/msf2_spi.c). How would model know about which
controller(SPI0/1) is currently
accessed and use corresponding bus(spi0/spi1) to transfer to slave devices?
If am wrong I will remove SPI1 from SoC.
>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
>> +
>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>> +
>> +static void msf2_soc_initfn(Object *obj)
>> +{
>> + MSF2State *s = MSF2_SOC(obj);
>> + int i;
>> +
>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>> +
>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>> +
>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSF2_TIMER);
>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>> +
>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>> + TYPE_MSF2_SPI);
>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>> + }
>> +}
>> +
>> +static void msf2_soc_realize(DeviceState *dev_soc, Error **errp)
>> +{
>> + MSF2State *s = MSF2_SOC(dev_soc);
>> + DeviceState *dev, *armv7m;
>> + SysBusDevice *busdev;
>> + Error *err = NULL;
>> + int i;
>> +
>> + MemoryRegion *system_memory = get_system_memory();
>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>> + MemoryRegion *ddr = g_new(MemoryRegion, 1);
>> +
>> + memory_region_init_ram(nvm, NULL, "MSF2.envm", ENVM_SIZE,
>> + &error_fatal);
>> + memory_region_init_alias(nvm_alias, NULL, "MSF2.flash.alias",
>> + nvm, 0, ENVM_SIZE);
>> + vmstate_register_ram_global(nvm);
>> +
>> + memory_region_set_readonly(nvm, true);
>> + memory_region_set_readonly(nvm_alias, true);
>> +
>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
>> + memory_region_add_subregion(system_memory, 0, nvm_alias);
>> +
>> + memory_region_init_ram(ddr, NULL, "MSF2.ddr", DDR_SIZE,
>> + &error_fatal);
>> + vmstate_register_ram_global(ddr);
>> + memory_region_add_subregion(system_memory, DDR_BASE_ADDRESS, ddr);
>> +
>> + memory_region_init_ram(sram, NULL, "MSF2.sram", SRAM_SIZE,
>> + &error_fatal);
>> + vmstate_register_ram_global(sram);
>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
>> +
>> + armv7m = DEVICE(&s->armv7m);
>> + qdev_prop_set_uint32(armv7m, "num-irq", 96);
>> + qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
>> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
>> + "memory", &error_abort);
>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> +
>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>> + if (serial_hds[i]) {
>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>> + qdev_get_gpio_in(armv7m, uart_irq[i]),
>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
>> + }
>> + }
>> +
>> + dev = DEVICE(&s->timer);
>> + qdev_prop_set_uint32(dev, "clock-frequency", 83 * 1000000);
>
> Macro for the frequency.
>
Yeah will change.
>> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> + busdev = SYS_BUS_DEVICE(dev);
>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>> + sysbus_connect_irq(busdev, 0,
>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
>> + sysbus_connect_irq(busdev, 1,
>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
>> +
>> + dev = DEVICE(&s->sysreg);
>> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
>> + if (err != NULL) {
>> + error_propagate(errp, err);
>> + return;
>> + }
>> + busdev = SYS_BUS_DEVICE(dev);
>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>> +
>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>> + gchar *bus_name = g_strdup_printf("spi%d", i);
>> +
>> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
>> + if (err != NULL) {
>> + g_free(bus_name);
>> + error_propagate(errp, err);
>> + return;
>> + }
>> +
>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>> + qdev_get_gpio_in(armv7m, spi_irq[i]));
>> +
>> + /* Alias controller SPI bus to the SoC itself */
>> + object_property_add_alias(OBJECT(s), bus_name,
>> + OBJECT(&s->spi[i]), "spi0",
>> + &error_abort);
>> + g_free(bus_name);
>> + }
>> +}
>> +
>> +static Property msf2_soc_properties[] = {
>> + DEFINE_PROP_STRING("cpu-model", MSF2State, cpu_model),
>
> Does this actually change?
>
No. I will remove the property.
> This looks pretty good, just a few things to fix up.
>
Thank you,
Sundeep
> Thanks,
>
> Alistair
>
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void msf2_soc_class_init(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> +
>> + dc->realize = msf2_soc_realize;
>> + dc->props = msf2_soc_properties;
>> +}
>> +
>> +static const TypeInfo msf2_soc_info = {
>> + .name = TYPE_MSF2_SOC,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(MSF2State),
>> + .instance_init = msf2_soc_initfn,
>> + .class_init = msf2_soc_class_init,
>> +};
>> +
>> +static void msf2_soc_types(void)
>> +{
>> + type_register_static(&msf2_soc_info);
>> +}
>> +
>> +type_init(msf2_soc_types)
>> diff --git a/include/hw/arm/msf2_soc.h b/include/hw/arm/msf2_soc.h
>> new file mode 100644
>> index 0000000..1184d9a
>> --- /dev/null
>> +++ b/include/hw/arm/msf2_soc.h
>> @@ -0,0 +1,62 @@
>> +/*
>> + * Microsemi Smartfusion2 SoC
>> + *
>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +
>> +#ifndef HW_ARM_MSF2_SOC_H
>> +#define HW_ARM_MSF2_SOC_H
>> +
>> +#include "hw/misc/msf2_sysreg.h"
>> +#include "hw/timer/msf2_timer.h"
>> +#include "hw/ssi/msf2_spi.h"
>> +#include "hw/arm/armv7m.h"
>> +
>> +#define TYPE_MSF2_SOC "msf2-soc"
>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>> +
>> +#define MSF2_NUM_SPIS 2
>> +#define MSF2_NUM_UARTS 2
>> +
>> +#define ENVM_BASE_ADDRESS 0x60000000
>> +#define ENVM_SIZE (128 * 1024)
>> +
>> +#define DDR_BASE_ADDRESS 0xA0000000
>> +#define DDR_SIZE (64 * 1024 * 1024)
>> +
>> +#define SRAM_BASE_ADDRESS 0x20000000
>> +#define SRAM_SIZE (64 * 1024)
>> +
>> +typedef struct MSF2State {
>> + /*< private >*/
>> + SysBusDevice parent_obj;
>> + /*< public >*/
>> +
>> + char *cpu_model;
>> +
>> + ARMv7MState armv7m;
>> +
>> + MSF2SysregState sysreg;
>> + MSF2TimerState timer;
>> + MSF2SpiState spi[MSF2_NUM_SPIS];
>> +} MSF2State;
>> +
>> +#endif
>> --
>> 2.5.0
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC.
2017-05-05 16:14 ` sundeep subbaraya
@ 2017-05-05 23:53 ` Alistair Francis
2017-05-06 8:49 ` sundeep subbaraya
0 siblings, 1 reply; 16+ messages in thread
From: Alistair Francis @ 2017-05-05 23:53 UTC (permalink / raw)
To: sundeep subbaraya
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
On Fri, May 5, 2017 at 9:14 AM, sundeep subbaraya
<sundeep.lkml@gmail.com> wrote:
> Hi Alistair,
>
> On Fri, May 5, 2017 at 3:51 AM, Alistair Francis <alistair23@gmail.com> wrote:
>> On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
>> <sundeep.lkml@gmail.com> wrote:
>>> Smartfusion2 SoC has hardened Microcontroller subsystem
>>> and flash based FPGA fabric. This patch adds support for
>>> Microcontroller subsystem in the SoC.
>>>
>>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> ---
>>> default-configs/arm-softmmu.mak | 1 +
>>> hw/arm/Makefile.objs | 2 +-
>>> hw/arm/msf2_soc.c | 194 ++++++++++++++++++++++++++++++++++++++++
>>> include/hw/arm/msf2_soc.h | 62 +++++++++++++
>>> 4 files changed, 258 insertions(+), 1 deletion(-)
>>> create mode 100644 hw/arm/msf2_soc.c
>>> create mode 100644 include/hw/arm/msf2_soc.h
>>>
>>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
>>> index 78d7af0..7062512 100644
>>> --- a/default-configs/arm-softmmu.mak
>>> +++ b/default-configs/arm-softmmu.mak
>>> @@ -122,3 +122,4 @@ CONFIG_ACPI=y
>>> CONFIG_SMBIOS=y
>>> CONFIG_ASPEED_SOC=y
>>> CONFIG_GPIO_KEY=y
>>> +CONFIG_MSF2=y
>>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>>> index 4c5c4ee..cce2759 100644
>>> --- a/hw/arm/Makefile.objs
>>> +++ b/hw/arm/Makefile.objs
>>> @@ -1,7 +1,7 @@
>>> obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
>>> obj-$(CONFIG_DIGIC) += digic_boards.o
>>> obj-y += integratorcp.o mainstone.o musicpal.o nseries.o
>>> -obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
>>> +obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o msf2_soc.o
>>> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
>>> obj-$(CONFIG_ACPI) += virt-acpi-build.o
>>> obj-y += netduino2.o
>>> diff --git a/hw/arm/msf2_soc.c b/hw/arm/msf2_soc.c
>>> new file mode 100644
>>> index 0000000..a470872
>>> --- /dev/null
>>> +++ b/hw/arm/msf2_soc.c
>>> @@ -0,0 +1,194 @@
>>> +/*
>>> + * SmartFusion2 SoC emulation.
>>> + *
>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>> + * of this software and associated documentation files (the "Software"), to deal
>>> + * in the Software without restriction, including without limitation the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +
>>> +#include "qemu/osdep.h"
>>> +#include "qapi/error.h"
>>> +#include "qemu-common.h"
>>> +#include "hw/arm/arm.h"
>>> +#include "exec/address-spaces.h"
>>> +#include "hw/char/serial.h"
>>> +#include "hw/boards.h"
>>> +#include "sysemu/block-backend.h"
>>> +#include "hw/arm/msf2_soc.h"
>>> +
>>> +#define MSF2_TIMER_BASE 0x40004000
>>> +#define MSF2_SYSREG_BASE 0x40038000
>>> +
>>> +#define MSF2_TIMER_IRQ0 14
>>> +#define MSF2_TIMER_IRQ1 15
>>> +
>>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
>>
>> Hey Sundeep,
>>
>> From your other patch it sounds like this should just be a single SPI
>> device with to busses, so this will have to be re-worked.
>>
> I may be entirely wrong please correct me. I assumed this SoC and Board file
> are analogous to dtsi and dts in linux. So SoC file will instantiate
> all the controllers
> like SPI0 and SPI1 present in SoC whereas board file will attach slaves present
> on board (like EEPROM, SPI flashes etc.,). Hence in board file I
> attached flash to
> SPI0. I was expecting one bus for each controller eg:
> SPI0:
> bus: spi0
> device: flash (Chip select 0)
> device: other device (Chip select 1)
> SPI1:
> bus: spi1
> device: other device (Chip select 0) (if attached in board file)
That's pretty much each. The SoC should create everything that is on
the SoC. So the SoC should create the SPI controller (which will
create the SPI buses) but not connect anything to them.
Then it's up to the board/machine to connect the SPI devices to the SPI buses.
>
> But this is not the case because am not able to create spi1 bus in
> controller model
> (hw/ssi/msf2_spi.c). How would model know about which
> controller(SPI0/1) is currently
> accessed and use corresponding bus(spi0/spi1) to transfer to slave devices?
I don't know anything about the board, but it sounds like you need to
be able to create the spi1 bus in a single SPI device right?
Otherwise you can do what the ZynqMP board does and create multiple
spi devices and alias spi0,spi1... to the spi0 bus of each device.
Thanks,
Alistair
> If am wrong I will remove SPI1 from SoC.
>
>>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
>>> +
>>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>>> +
>>> +static void msf2_soc_initfn(Object *obj)
>>> +{
>>> + MSF2State *s = MSF2_SOC(obj);
>>> + int i;
>>> +
>>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>>> +
>>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>>> +
>>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSF2_TIMER);
>>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>>> +
>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>> + TYPE_MSF2_SPI);
>>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>> + }
>>> +}
>>> +
>>> +static void msf2_soc_realize(DeviceState *dev_soc, Error **errp)
>>> +{
>>> + MSF2State *s = MSF2_SOC(dev_soc);
>>> + DeviceState *dev, *armv7m;
>>> + SysBusDevice *busdev;
>>> + Error *err = NULL;
>>> + int i;
>>> +
>>> + MemoryRegion *system_memory = get_system_memory();
>>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>>> + MemoryRegion *ddr = g_new(MemoryRegion, 1);
>>> +
>>> + memory_region_init_ram(nvm, NULL, "MSF2.envm", ENVM_SIZE,
>>> + &error_fatal);
>>> + memory_region_init_alias(nvm_alias, NULL, "MSF2.flash.alias",
>>> + nvm, 0, ENVM_SIZE);
>>> + vmstate_register_ram_global(nvm);
>>> +
>>> + memory_region_set_readonly(nvm, true);
>>> + memory_region_set_readonly(nvm_alias, true);
>>> +
>>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
>>> + memory_region_add_subregion(system_memory, 0, nvm_alias);
>>> +
>>> + memory_region_init_ram(ddr, NULL, "MSF2.ddr", DDR_SIZE,
>>> + &error_fatal);
>>> + vmstate_register_ram_global(ddr);
>>> + memory_region_add_subregion(system_memory, DDR_BASE_ADDRESS, ddr);
>>> +
>>> + memory_region_init_ram(sram, NULL, "MSF2.sram", SRAM_SIZE,
>>> + &error_fatal);
>>> + vmstate_register_ram_global(sram);
>>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
>>> +
>>> + armv7m = DEVICE(&s->armv7m);
>>> + qdev_prop_set_uint32(armv7m, "num-irq", 96);
>>> + qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
>>> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
>>> + "memory", &error_abort);
>>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
>>> + if (err != NULL) {
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> +
>>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>>> + if (serial_hds[i]) {
>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),
>>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
>>> + }
>>> + }
>>> +
>>> + dev = DEVICE(&s->timer);
>>> + qdev_prop_set_uint32(dev, "clock-frequency", 83 * 1000000);
>>
>> Macro for the frequency.
>>
> Yeah will change.
>
>>> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
>>> + if (err != NULL) {
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> + busdev = SYS_BUS_DEVICE(dev);
>>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>>> + sysbus_connect_irq(busdev, 0,
>>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
>>> + sysbus_connect_irq(busdev, 1,
>>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
>>> +
>>> + dev = DEVICE(&s->sysreg);
>>> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
>>> + if (err != NULL) {
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> + busdev = SYS_BUS_DEVICE(dev);
>>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>>> +
>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>> + gchar *bus_name = g_strdup_printf("spi%d", i);
>>> +
>>> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
>>> + if (err != NULL) {
>>> + g_free(bus_name);
>>> + error_propagate(errp, err);
>>> + return;
>>> + }
>>> +
>>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>> + qdev_get_gpio_in(armv7m, spi_irq[i]));
>>> +
>>> + /* Alias controller SPI bus to the SoC itself */
>>> + object_property_add_alias(OBJECT(s), bus_name,
>>> + OBJECT(&s->spi[i]), "spi0",
>>> + &error_abort);
>>> + g_free(bus_name);
>>> + }
>>> +}
>>> +
>>> +static Property msf2_soc_properties[] = {
>>> + DEFINE_PROP_STRING("cpu-model", MSF2State, cpu_model),
>>
>> Does this actually change?
>>
> No. I will remove the property.
>
>> This looks pretty good, just a few things to fix up.
>>
>
> Thank you,
> Sundeep
>
>> Thanks,
>>
>> Alistair
>>
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>> +
>>> +static void msf2_soc_class_init(ObjectClass *klass, void *data)
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>> +
>>> + dc->realize = msf2_soc_realize;
>>> + dc->props = msf2_soc_properties;
>>> +}
>>> +
>>> +static const TypeInfo msf2_soc_info = {
>>> + .name = TYPE_MSF2_SOC,
>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>> + .instance_size = sizeof(MSF2State),
>>> + .instance_init = msf2_soc_initfn,
>>> + .class_init = msf2_soc_class_init,
>>> +};
>>> +
>>> +static void msf2_soc_types(void)
>>> +{
>>> + type_register_static(&msf2_soc_info);
>>> +}
>>> +
>>> +type_init(msf2_soc_types)
>>> diff --git a/include/hw/arm/msf2_soc.h b/include/hw/arm/msf2_soc.h
>>> new file mode 100644
>>> index 0000000..1184d9a
>>> --- /dev/null
>>> +++ b/include/hw/arm/msf2_soc.h
>>> @@ -0,0 +1,62 @@
>>> +/*
>>> + * Microsemi Smartfusion2 SoC
>>> + *
>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>> + * of this software and associated documentation files (the "Software"), to deal
>>> + * in the Software without restriction, including without limitation the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +
>>> +#ifndef HW_ARM_MSF2_SOC_H
>>> +#define HW_ARM_MSF2_SOC_H
>>> +
>>> +#include "hw/misc/msf2_sysreg.h"
>>> +#include "hw/timer/msf2_timer.h"
>>> +#include "hw/ssi/msf2_spi.h"
>>> +#include "hw/arm/armv7m.h"
>>> +
>>> +#define TYPE_MSF2_SOC "msf2-soc"
>>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>>> +
>>> +#define MSF2_NUM_SPIS 2
>>> +#define MSF2_NUM_UARTS 2
>>> +
>>> +#define ENVM_BASE_ADDRESS 0x60000000
>>> +#define ENVM_SIZE (128 * 1024)
>>> +
>>> +#define DDR_BASE_ADDRESS 0xA0000000
>>> +#define DDR_SIZE (64 * 1024 * 1024)
>>> +
>>> +#define SRAM_BASE_ADDRESS 0x20000000
>>> +#define SRAM_SIZE (64 * 1024)
>>> +
>>> +typedef struct MSF2State {
>>> + /*< private >*/
>>> + SysBusDevice parent_obj;
>>> + /*< public >*/
>>> +
>>> + char *cpu_model;
>>> +
>>> + ARMv7MState armv7m;
>>> +
>>> + MSF2SysregState sysreg;
>>> + MSF2TimerState timer;
>>> + MSF2SpiState spi[MSF2_NUM_SPIS];
>>> +} MSF2State;
>>> +
>>> +#endif
>>> --
>>> 2.5.0
>>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC.
2017-05-05 23:53 ` Alistair Francis
@ 2017-05-06 8:49 ` sundeep subbaraya
0 siblings, 0 replies; 16+ messages in thread
From: sundeep subbaraya @ 2017-05-06 8:49 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, qemu-arm, Peter Maydell,
Peter Crosthwaite
Hi Alistair,
On Sat, May 6, 2017 at 5:23 AM, Alistair Francis <alistair23@gmail.com> wrote:
> On Fri, May 5, 2017 at 9:14 AM, sundeep subbaraya
> <sundeep.lkml@gmail.com> wrote:
>> Hi Alistair,
>>
>> On Fri, May 5, 2017 at 3:51 AM, Alistair Francis <alistair23@gmail.com> wrote:
>>> On Fri, Apr 28, 2017 at 9:51 AM, Subbaraya Sundeep
>>> <sundeep.lkml@gmail.com> wrote:
>>>> Smartfusion2 SoC has hardened Microcontroller subsystem
>>>> and flash based FPGA fabric. This patch adds support for
>>>> Microcontroller subsystem in the SoC.
>>>>
>>>> Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>>> ---
>>>> default-configs/arm-softmmu.mak | 1 +
>>>> hw/arm/Makefile.objs | 2 +-
>>>> hw/arm/msf2_soc.c | 194 ++++++++++++++++++++++++++++++++++++++++
>>>> include/hw/arm/msf2_soc.h | 62 +++++++++++++
>>>> 4 files changed, 258 insertions(+), 1 deletion(-)
>>>> create mode 100644 hw/arm/msf2_soc.c
>>>> create mode 100644 include/hw/arm/msf2_soc.h
>>>>
>>>> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
>>>> index 78d7af0..7062512 100644
>>>> --- a/default-configs/arm-softmmu.mak
>>>> +++ b/default-configs/arm-softmmu.mak
>>>> @@ -122,3 +122,4 @@ CONFIG_ACPI=y
>>>> CONFIG_SMBIOS=y
>>>> CONFIG_ASPEED_SOC=y
>>>> CONFIG_GPIO_KEY=y
>>>> +CONFIG_MSF2=y
>>>> diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
>>>> index 4c5c4ee..cce2759 100644
>>>> --- a/hw/arm/Makefile.objs
>>>> +++ b/hw/arm/Makefile.objs
>>>> @@ -1,7 +1,7 @@
>>>> obj-y += boot.o collie.o exynos4_boards.o gumstix.o highbank.o
>>>> obj-$(CONFIG_DIGIC) += digic_boards.o
>>>> obj-y += integratorcp.o mainstone.o musicpal.o nseries.o
>>>> -obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
>>>> +obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o msf2_soc.o
>>>> obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
>>>> obj-$(CONFIG_ACPI) += virt-acpi-build.o
>>>> obj-y += netduino2.o
>>>> diff --git a/hw/arm/msf2_soc.c b/hw/arm/msf2_soc.c
>>>> new file mode 100644
>>>> index 0000000..a470872
>>>> --- /dev/null
>>>> +++ b/hw/arm/msf2_soc.c
>>>> @@ -0,0 +1,194 @@
>>>> +/*
>>>> + * SmartFusion2 SoC emulation.
>>>> + *
>>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>>> + * of this software and associated documentation files (the "Software"), to deal
>>>> + * in the Software without restriction, including without limitation the rights
>>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>>> + * copies of the Software, and to permit persons to whom the Software is
>>>> + * furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>>> + * THE SOFTWARE.
>>>> + */
>>>> +
>>>> +#include "qemu/osdep.h"
>>>> +#include "qapi/error.h"
>>>> +#include "qemu-common.h"
>>>> +#include "hw/arm/arm.h"
>>>> +#include "exec/address-spaces.h"
>>>> +#include "hw/char/serial.h"
>>>> +#include "hw/boards.h"
>>>> +#include "sysemu/block-backend.h"
>>>> +#include "hw/arm/msf2_soc.h"
>>>> +
>>>> +#define MSF2_TIMER_BASE 0x40004000
>>>> +#define MSF2_SYSREG_BASE 0x40038000
>>>> +
>>>> +#define MSF2_TIMER_IRQ0 14
>>>> +#define MSF2_TIMER_IRQ1 15
>>>> +
>>>> +static const uint32_t spi_addr[MSF2_NUM_SPIS] = { 0x40001000 , 0x40011000 };
>>>
>>> Hey Sundeep,
>>>
>>> From your other patch it sounds like this should just be a single SPI
>>> device with to busses, so this will have to be re-worked.
>>>
>> I may be entirely wrong please correct me. I assumed this SoC and Board file
>> are analogous to dtsi and dts in linux. So SoC file will instantiate
>> all the controllers
>> like SPI0 and SPI1 present in SoC whereas board file will attach slaves present
>> on board (like EEPROM, SPI flashes etc.,). Hence in board file I
>> attached flash to
>> SPI0. I was expecting one bus for each controller eg:
>> SPI0:
>> bus: spi0
>> device: flash (Chip select 0)
>> device: other device (Chip select 1)
>> SPI1:
>> bus: spi1
>> device: other device (Chip select 0) (if attached in board file)
>
> That's pretty much each. The SoC should create everything that is on
> the SoC. So the SoC should create the SPI controller (which will
> create the SPI buses) but not connect anything to them.
>
> Then it's up to the board/machine to connect the SPI devices to the SPI buses.
>
>>
>> But this is not the case because am not able to create spi1 bus in
>> controller model
>> (hw/ssi/msf2_spi.c). How would model know about which
>> controller(SPI0/1) is currently
>> accessed and use corresponding bus(spi0/spi1) to transfer to slave devices?
>
> I don't know anything about the board, but it sounds like you need to
> be able to create the spi1 bus in a single SPI device right?
>
> Otherwise you can do what the ZynqMP board does and create multiple
> spi devices and alias spi0,spi1... to the spi0 bus of each device.
>
Now I understood. spi0, spi1 are aliases and are used to retrieve which
controller to attach slaves to in board file. But bus name will always be
spi0 only. Other SoCs use bus names like ssi/spi.
AFAIK for I2C, bus name will use incrementing index for each controller.
Thats not the case for SPI.
I tested other controller also by attaching another SPI flash to it and it works
prefect. Below is the output:
bus: main-system-bus
type System
dev: msf2-soc, id ""
cpu-model = "cortex-m3"
dev: msf2-spi, id ""
gpio-out "sysbus-irq" 2
mmio 0000000040011000/0000000000000040
bus: spi0
type SSI
dev: s25sl12800, id ""
gpio-in "ssi-gpio-cs" 1
nonvolatile-cfg = 36863 (0x8fff)
spansion-cr1nv = 0 (0x0)
spansion-cr2nv = 1 (0x1)
spansion-cr3nv = 2 (0x2)
spansion-cr4nv = 16 (0x10)
drive = "mtd1"
dev: msf2-spi, id ""
gpio-out "sysbus-irq" 2
mmio 0000000040001000/0000000000000040
bus: spi0
type SSI
dev: s25sl12801, id ""
gpio-in "ssi-gpio-cs" 1
nonvolatile-cfg = 36863 (0x8fff)
spansion-cr1nv = 0 (0x0)
spansion-cr2nv = 1 (0x1)
spansion-cr3nv = 2 (0x2)
spansion-cr4nv = 16 (0x10)
drive = "mtd0"
I will fix other comments and send the patch.
Thank you,
Sundeep
> Thanks,
>
> Alistair
>
>> If am wrong I will remove SPI1 from SoC.
>>
>>>> +static const uint32_t uart_addr[MSF2_NUM_UARTS] = { 0x40000000 , 0x40010000 };
>>>> +
>>>> +static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 };
>>>> +static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };
>>>> +
>>>> +static void msf2_soc_initfn(Object *obj)
>>>> +{
>>>> + MSF2State *s = MSF2_SOC(obj);
>>>> + int i;
>>>> +
>>>> + object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
>>>> + qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
>>>> +
>>>> + object_initialize(&s->sysreg, sizeof(s->sysreg), TYPE_MSF2_SYSREG);
>>>> + qdev_set_parent_bus(DEVICE(&s->sysreg), sysbus_get_default());
>>>> +
>>>> + object_initialize(&s->timer, sizeof(s->timer), TYPE_MSF2_TIMER);
>>>> + qdev_set_parent_bus(DEVICE(&s->timer), sysbus_get_default());
>>>> +
>>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>>> + object_initialize(&s->spi[i], sizeof(s->spi[i]),
>>>> + TYPE_MSF2_SPI);
>>>> + qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
>>>> + }
>>>> +}
>>>> +
>>>> +static void msf2_soc_realize(DeviceState *dev_soc, Error **errp)
>>>> +{
>>>> + MSF2State *s = MSF2_SOC(dev_soc);
>>>> + DeviceState *dev, *armv7m;
>>>> + SysBusDevice *busdev;
>>>> + Error *err = NULL;
>>>> + int i;
>>>> +
>>>> + MemoryRegion *system_memory = get_system_memory();
>>>> + MemoryRegion *nvm = g_new(MemoryRegion, 1);
>>>> + MemoryRegion *nvm_alias = g_new(MemoryRegion, 1);
>>>> + MemoryRegion *sram = g_new(MemoryRegion, 1);
>>>> + MemoryRegion *ddr = g_new(MemoryRegion, 1);
>>>> +
>>>> + memory_region_init_ram(nvm, NULL, "MSF2.envm", ENVM_SIZE,
>>>> + &error_fatal);
>>>> + memory_region_init_alias(nvm_alias, NULL, "MSF2.flash.alias",
>>>> + nvm, 0, ENVM_SIZE);
>>>> + vmstate_register_ram_global(nvm);
>>>> +
>>>> + memory_region_set_readonly(nvm, true);
>>>> + memory_region_set_readonly(nvm_alias, true);
>>>> +
>>>> + memory_region_add_subregion(system_memory, ENVM_BASE_ADDRESS, nvm);
>>>> + memory_region_add_subregion(system_memory, 0, nvm_alias);
>>>> +
>>>> + memory_region_init_ram(ddr, NULL, "MSF2.ddr", DDR_SIZE,
>>>> + &error_fatal);
>>>> + vmstate_register_ram_global(ddr);
>>>> + memory_region_add_subregion(system_memory, DDR_BASE_ADDRESS, ddr);
>>>> +
>>>> + memory_region_init_ram(sram, NULL, "MSF2.sram", SRAM_SIZE,
>>>> + &error_fatal);
>>>> + vmstate_register_ram_global(sram);
>>>> + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
>>>> +
>>>> + armv7m = DEVICE(&s->armv7m);
>>>> + qdev_prop_set_uint32(armv7m, "num-irq", 96);
>>>> + qdev_prop_set_string(armv7m, "cpu-model", s->cpu_model);
>>>> + object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
>>>> + "memory", &error_abort);
>>>> + object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
>>>> + if (err != NULL) {
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> +
>>>> + for (i = 0; i < MSF2_NUM_UARTS; i++) {
>>>> + if (serial_hds[i]) {
>>>> + serial_mm_init(get_system_memory(), uart_addr[i], 2,
>>>> + qdev_get_gpio_in(armv7m, uart_irq[i]),
>>>> + 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN);
>>>> + }
>>>> + }
>>>> +
>>>> + dev = DEVICE(&s->timer);
>>>> + qdev_prop_set_uint32(dev, "clock-frequency", 83 * 1000000);
>>>
>>> Macro for the frequency.
>>>
>> Yeah will change.
>>
>>>> + object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
>>>> + if (err != NULL) {
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> + busdev = SYS_BUS_DEVICE(dev);
>>>> + sysbus_mmio_map(busdev, 0, MSF2_TIMER_BASE);
>>>> + sysbus_connect_irq(busdev, 0,
>>>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ0));
>>>> + sysbus_connect_irq(busdev, 1,
>>>> + qdev_get_gpio_in(armv7m, MSF2_TIMER_IRQ1));
>>>> +
>>>> + dev = DEVICE(&s->sysreg);
>>>> + object_property_set_bool(OBJECT(&s->sysreg), true, "realized", &err);
>>>> + if (err != NULL) {
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> + busdev = SYS_BUS_DEVICE(dev);
>>>> + sysbus_mmio_map(busdev, 0, MSF2_SYSREG_BASE);
>>>> +
>>>> + for (i = 0; i < MSF2_NUM_SPIS; i++) {
>>>> + gchar *bus_name = g_strdup_printf("spi%d", i);
>>>> +
>>>> + object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
>>>> + if (err != NULL) {
>>>> + g_free(bus_name);
>>>> + error_propagate(errp, err);
>>>> + return;
>>>> + }
>>>> +
>>>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
>>>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
>>>> + qdev_get_gpio_in(armv7m, spi_irq[i]));
>>>> +
>>>> + /* Alias controller SPI bus to the SoC itself */
>>>> + object_property_add_alias(OBJECT(s), bus_name,
>>>> + OBJECT(&s->spi[i]), "spi0",
>>>> + &error_abort);
>>>> + g_free(bus_name);
>>>> + }
>>>> +}
>>>> +
>>>> +static Property msf2_soc_properties[] = {
>>>> + DEFINE_PROP_STRING("cpu-model", MSF2State, cpu_model),
>>>
>>> Does this actually change?
>>>
>> No. I will remove the property.
>>
>>> This looks pretty good, just a few things to fix up.
>>>
>>
>> Thank you,
>> Sundeep
>>
>>> Thanks,
>>>
>>> Alistair
>>>
>>>> + DEFINE_PROP_END_OF_LIST(),
>>>> +};
>>>> +
>>>> +static void msf2_soc_class_init(ObjectClass *klass, void *data)
>>>> +{
>>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>>> +
>>>> + dc->realize = msf2_soc_realize;
>>>> + dc->props = msf2_soc_properties;
>>>> +}
>>>> +
>>>> +static const TypeInfo msf2_soc_info = {
>>>> + .name = TYPE_MSF2_SOC,
>>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>>> + .instance_size = sizeof(MSF2State),
>>>> + .instance_init = msf2_soc_initfn,
>>>> + .class_init = msf2_soc_class_init,
>>>> +};
>>>> +
>>>> +static void msf2_soc_types(void)
>>>> +{
>>>> + type_register_static(&msf2_soc_info);
>>>> +}
>>>> +
>>>> +type_init(msf2_soc_types)
>>>> diff --git a/include/hw/arm/msf2_soc.h b/include/hw/arm/msf2_soc.h
>>>> new file mode 100644
>>>> index 0000000..1184d9a
>>>> --- /dev/null
>>>> +++ b/include/hw/arm/msf2_soc.h
>>>> @@ -0,0 +1,62 @@
>>>> +/*
>>>> + * Microsemi Smartfusion2 SoC
>>>> + *
>>>> + * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>>> + * of this software and associated documentation files (the "Software"), to deal
>>>> + * in the Software without restriction, including without limitation the rights
>>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>>> + * copies of the Software, and to permit persons to whom the Software is
>>>> + * furnished to do so, subject to the following conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>>> + * THE SOFTWARE.
>>>> + */
>>>> +
>>>> +#ifndef HW_ARM_MSF2_SOC_H
>>>> +#define HW_ARM_MSF2_SOC_H
>>>> +
>>>> +#include "hw/misc/msf2_sysreg.h"
>>>> +#include "hw/timer/msf2_timer.h"
>>>> +#include "hw/ssi/msf2_spi.h"
>>>> +#include "hw/arm/armv7m.h"
>>>> +
>>>> +#define TYPE_MSF2_SOC "msf2-soc"
>>>> +#define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC)
>>>> +
>>>> +#define MSF2_NUM_SPIS 2
>>>> +#define MSF2_NUM_UARTS 2
>>>> +
>>>> +#define ENVM_BASE_ADDRESS 0x60000000
>>>> +#define ENVM_SIZE (128 * 1024)
>>>> +
>>>> +#define DDR_BASE_ADDRESS 0xA0000000
>>>> +#define DDR_SIZE (64 * 1024 * 1024)
>>>> +
>>>> +#define SRAM_BASE_ADDRESS 0x20000000
>>>> +#define SRAM_SIZE (64 * 1024)
>>>> +
>>>> +typedef struct MSF2State {
>>>> + /*< private >*/
>>>> + SysBusDevice parent_obj;
>>>> + /*< public >*/
>>>> +
>>>> + char *cpu_model;
>>>> +
>>>> + ARMv7MState armv7m;
>>>> +
>>>> + MSF2SysregState sysreg;
>>>> + MSF2TimerState timer;
>>>> + MSF2SpiState spi[MSF2_NUM_SPIS];
>>>> +} MSF2State;
>>>> +
>>>> +#endif
>>>> --
>>>> 2.5.0
>>>>
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-05-06 8:49 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-28 16:51 [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC Subbaraya Sundeep
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 1/5] msf2: Add Smartfusion2 System timer Subbaraya Sundeep
2017-05-02 21:55 ` Alistair Francis
2017-05-03 5:11 ` sundeep subbaraya
2017-05-03 23:32 ` Alistair Francis
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 2/5] msf2: Microsemi Smartfusion2 System Register block Subbaraya Sundeep
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 3/5] msf2: Add Smartfusion2 SPI controller Subbaraya Sundeep
2017-05-02 5:02 ` sundeep subbaraya
2017-05-03 23:39 ` Alistair Francis
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 4/5] msf2: Add Smartfusion2 SoC Subbaraya Sundeep
2017-05-04 22:21 ` Alistair Francis
2017-05-05 16:14 ` sundeep subbaraya
2017-05-05 23:53 ` Alistair Francis
2017-05-06 8:49 ` sundeep subbaraya
2017-04-28 16:51 ` [Qemu-devel] [Qemu-devel RFC v3 5/5] msf2: Add Emcraft's Smartfusion2 SOM kit Subbaraya Sundeep
2017-04-28 17:20 ` [Qemu-devel] [Qemu-devel RFC v3 0/5] Add support for Smartfusion2 SoC no-reply
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