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From: Jim Mattson <jmattson@google.com>
To: Wanpeng Li <kernellwp@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
	kvm list <kvm@vger.kernel.org>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Sean Christopherson <seanjc@google.com>,
	Vitaly Kuznetsov <vkuznets@redhat.com>,
	Wanpeng Li <wanpengli@tencent.com>,
	Joerg Roedel <joro@8bytes.org>
Subject: Re: [PATCH 2/2] KVM: LAPIC: reset TMCCT during vCPU reset
Date: Thu, 3 Jun 2021 05:27:46 -0700	[thread overview]
Message-ID: <CALMp9eSK-_xOp=WdRbOOHaHHMHuJkPhG+7h4M+_+=4d-GCNzwA@mail.gmail.com> (raw)
In-Reply-To: <1622710841-76604-2-git-send-email-wanpengli@tencent.com>

On Thu, Jun 3, 2021 at 2:01 AM Wanpeng Li <kernellwp@gmail.com> wrote:
>
> From: Wanpeng Li <wanpengli@tencent.com>
>
> The value of current counter register after reset is 0 for both Intel
> and AMD, let's do it in kvm.
>
> Signed-off-by: Wanpeng Li <wanpengli@tencent.com>

How did we miss that?

Reviewed-by: Jim Mattson <jmattson@google.com>

  reply	other threads:[~2021-06-03 12:29 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-03  9:00 [PATCH 1/2] KVM: LAPIC: write 0 to TMICT should also cancel vmx-preemption timer Wanpeng Li
2021-06-03  9:00 ` [PATCH 2/2] KVM: LAPIC: reset TMCCT during vCPU reset Wanpeng Li
2021-06-03 12:27   ` Jim Mattson [this message]
2021-06-03 15:34     ` Sean Christopherson
2021-06-08  0:31       ` Wanpeng Li
2021-06-03 15:20 ` [PATCH 1/2] KVM: LAPIC: write 0 to TMICT should also cancel vmx-preemption timer Sean Christopherson
2021-06-04  0:36   ` Wanpeng Li
2021-06-04 15:37     ` Sean Christopherson
2021-06-08  0:30       ` Wanpeng Li
2021-06-03 23:02 ` David Matlack
2021-06-04  0:32   ` Wanpeng Li
2021-06-04 15:59     ` David Matlack

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