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From: Jim Mattson <jmattson@google.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Aaron Lewis <aaronlewis@google.com>,
	Babu Moger <Babu.Moger@amd.com>,
	Yang Weijiang <weijiang.yang@intel.com>,
	Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
	kvm list <kvm@vger.kernel.org>, Luwei Kang <luwei.kang@intel.com>
Subject: Re: [Patch 3/6] kvm: svm: Add support for XSAVES on AMD
Date: Wed, 9 Oct 2019 14:58:05 -0700	[thread overview]
Message-ID: <CALMp9eTW56TDny5MehuW-wS8dHWwfVEdzEvZQkOfVumEwcMWAA@mail.gmail.com> (raw)
In-Reply-To: <9335c3c7-e2dd-cb2d-454a-c41143c94b63@redhat.com>

On Wed, Oct 9, 2019 at 2:40 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 09/10/19 23:29, Jim Mattson wrote:
> > On Wed, Oct 9, 2019 at 12:02 AM Paolo Bonzini <pbonzini@redhat.com> wrote:
> >>
> >> On 09/10/19 02:41, Aaron Lewis wrote:
> >>> -             /*
> >>> -              * The only supported bit as of Skylake is bit 8, but
> >>> -              * it is not supported on KVM.
> >>> -              */
> >>> -             if (data != 0)
> >>> -                     return 1;
> >>
> >> This comment is actually not true anymore; Intel supports PT (bit 8) on
> >> Cascade Lake, so it could be changed to something like
> >>
> >>         /*
> >>          * We do support PT (bit 8) if kvm_x86_ops->pt_supported(), but
> >>          * guests will have to configure it using WRMSR rather than
> >>          * XSAVES.
> >>          */
> >>
> >> Paolo
> >
> > Isn't it necessary for the host to set IA32_XSS to a superset of the
> > guest IA32_XSS for proper host-level context-switching?
>
> Yes, this is why we cannot allow the guest to set bit 8.  But the
> comment is obsolete:
>
> 1) of course Skylake is not the newest model
>
> 2) processor tracing was not supported at all when the comment was
> written; but on CascadeLake, guest PT is now supported---just not the
> processor tracing XSAVES component.

I think we're on the same page. I was just confused by your wording;
it sounded like you were saying that KVM supported bit 8.

How about:

/*
 * We do support PT if kvm_x86_ops->pt_supported(), but we do not
 * support IA32_XSS[bit 8]. Guests will have to use WRMSR rather than
 * XSAVES/XRSTORS to save/restore PT MSRs.
 */

  reply	other threads:[~2019-10-09 21:58 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-09  0:41 [Patch 1/6] KVM: VMX: Remove unneeded check for X86_FEATURE_XSAVE Aaron Lewis
2019-10-09  0:41 ` [Patch 2/6] KVM: VMX: Use wrmsr for switching between guest and host IA32_XSS Aaron Lewis
2019-10-09  4:49   ` Yang Weijiang
2019-10-09  6:30   ` Paolo Bonzini
2019-10-09 12:34     ` Vitaly Kuznetsov
2019-10-09  6:31   ` Sebastian Andrzej Siewior
2019-10-09  0:41 ` [Patch 3/6] kvm: svm: Add support for XSAVES on AMD Aaron Lewis
2019-10-09  6:44   ` Sebastian Andrzej Siewior
2019-10-10 14:42     ` Aaron Lewis
2019-10-10 16:04       ` Paolo Bonzini
2019-10-09  7:01   ` Paolo Bonzini
2019-10-09 21:29     ` Jim Mattson
2019-10-09 21:40       ` Paolo Bonzini
2019-10-09 21:58         ` Jim Mattson [this message]
2019-10-09 22:49           ` Paolo Bonzini
2019-10-10  0:42             ` Kang, Luwei
2019-10-09  0:41 ` [Patch 4/6] kvm: svm: Enumerate XSAVES in guest CPUID when it is available to the guest Aaron Lewis
2019-10-09  1:42   ` Yang Weijiang
2019-10-09  6:32     ` Paolo Bonzini
2019-10-09 23:35       ` Jim Mattson
2019-10-09  0:41 ` [Patch 5/6] kvm: x86: Add IA32_XSS to the emulated_msrs list Aaron Lewis
2019-10-09  0:41 ` [Patch 6/6] kvm: tests: Add test to verify MSR_IA32_XSS Aaron Lewis
2019-10-09  6:30   ` Paolo Bonzini
2019-10-09 23:44     ` Jim Mattson
2019-10-10 16:01       ` Paolo Bonzini

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