From: Rob Herring <robherring2@gmail.com> To: Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com> Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>, Ian Campbell <ijc+devicetree@hellion.org.uk>, Kumar Gala <galak@codeaurora.org>, Michal Simek <michal.simek@xilinx.com>, Vinod Koul <vinod.koul@intel.com>, Dan Williams <dan.j.williams@intel.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Punnaiah Choudary <kpc528@gmail.com>, punnaiah choudary kalluri <kalluripunnaiahchoudary@gmail.com>, dmaengine@vger.kernel.org, Punnaiah Choudary Kalluri <punnaia@xilinx.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation Date: Mon, 24 Aug 2015 13:53:38 -0500 [thread overview] Message-ID: <CAL_Jsq+261JzSorbgEyQ4BFCHbsFsBaJQnpWJX-G=SX3yhqZJw@mail.gmail.com> (raw) In-Reply-To: <1438831173-8761-1-git-send-email-punnaia@xilinx.com> On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com> wrote: > Device-tree binding documentation for Xilinx zynqmp dma engine used in > Zynq UltraScale+ MPSoC. > > Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> > --- > Changes in v4: > - None > Changes in v3: > - None > Changes in v2: > - None > --- > .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 ++++++++++++++++++++ > 1 files changed, 61 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > new file mode 100644 > index 0000000..e4f92b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > @@ -0,0 +1,61 @@ > +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, > +memory to device and device to memory transfers. It also has flow > +control and rate control support for slave/peripheral dma access. > + > +Required properties: > +- compatible: Should be "xlnx,zynqmp-dma-1.0" > +- #dma-cells: Should be <1>, a single cell holding a line request number > +- reg: Memory map for module access > +- interrupt-parent: Interrupt controller the interrupt is routed through > +- interrupts: Should contain DMA channel interrupt > +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64 > + > +Optional properties: > +- xlnx,include-sg: Indicates the controller to operate in simple or scatter > + gather dma mode > +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for > + source AXI transaction > +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data > +- xlnx,src-issue: Number of AXI outstanding transactions on source side > +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the > + descriptor read are marked Non-coherent > +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the > + source descriptor payload are marked Non-coherent > +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the > + dst descriptor payload are marked Non-coherent Do you really need 3? dma-coherent property doesn't work for you? Not that it should dictate the binding, but the kernel doesn't support a device needing both coherent and non-coherent DMA ops. > +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch > +- xlnx,src-axi-qos: AXI QOS bits to be used for data read > +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write > +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. > +- xlnx,desc-axi-cache: AXI cache bits to be used for data read > +- xlnx,desc-axi-cache: AXI cache bits to be used for data write These signals are generally part of the coherent or not setting. This allows for potentially invalid combinations. Plus you have a copy/paste error. > +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values > + i.e 1,2,4,8 and 16 > +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values > + i.e 1,2,4,8 and 16 > + > +Example: > +++++++++ > +fpd_dma_chan1: dma@FD500000 { > + compatible = "xlnx,zynqmp-dma-1.0"; > + reg = <0x0 0xFD500000 0x1000>; > + #dma_cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <0 117 4>; > + xlnx,bus-width = <128>; > + xlnx,include-sg; > + xlnx,overfetch; > + xlnx,ratectrl = <0>; > + xlnx,src-issue = <16>; > + xlnx,desc-axi-cohrnt; > + xlnx,src-axi-cohrnt; > + xlnx,dst-axi-cohrnt; > + xlnx,desc-axi-qos = <0>; > + xlnx,desc-axi-cache = <0>; > + xlnx,src-axi-qos = <0>; > + xlnx,src-axi-cache = <2>; > + xlnx,dst-axi-qos = <0>; > + xlnx,dst-axi-cache = <2>; > + xlnx,src-burst-len = <4>; > + xlnx,dst-burst-len = <4>; > +}; > -- > 1.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: robherring2@gmail.com (Rob Herring) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation Date: Mon, 24 Aug 2015 13:53:38 -0500 [thread overview] Message-ID: <CAL_Jsq+261JzSorbgEyQ4BFCHbsFsBaJQnpWJX-G=SX3yhqZJw@mail.gmail.com> (raw) In-Reply-To: <1438831173-8761-1-git-send-email-punnaia@xilinx.com> On Wed, Aug 5, 2015 at 10:19 PM, Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com> wrote: > Device-tree binding documentation for Xilinx zynqmp dma engine used in > Zynq UltraScale+ MPSoC. > > Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> > --- > Changes in v4: > - None > Changes in v3: > - None > Changes in v2: > - None > --- > .../devicetree/bindings/dma/xilinx/zynqmp_dma.txt | 61 ++++++++++++++++++++ > 1 files changed, 61 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > > diff --git a/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > new file mode 100644 > index 0000000..e4f92b9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt > @@ -0,0 +1,61 @@ > +Xilinx ZynqMP DMA engine, it does support memory to memory transfers, > +memory to device and device to memory transfers. It also has flow > +control and rate control support for slave/peripheral dma access. > + > +Required properties: > +- compatible: Should be "xlnx,zynqmp-dma-1.0" > +- #dma-cells: Should be <1>, a single cell holding a line request number > +- reg: Memory map for module access > +- interrupt-parent: Interrupt controller the interrupt is routed through > +- interrupts: Should contain DMA channel interrupt > +- xlnx,bus-width: AXI buswidth in bits. Should contain 128 or 64 > + > +Optional properties: > +- xlnx,include-sg: Indicates the controller to operate in simple or scatter > + gather dma mode > +- xlnx,ratectrl: Scheduling interval in terms of clock cycles for > + source AXI transaction > +- xlnx,overfetch: Tells whether the channel is allowed to over fetch the data > +- xlnx,src-issue: Number of AXI outstanding transactions on source side > +- xlnx,desc-axi-cohrnt: Tells whether the AXI transactions generated for the > + descriptor read are marked Non-coherent > +- xlnx,src-axi-cohrnt: Tells whether the AXI transactions generated for the > + source descriptor payload are marked Non-coherent > +- xlnx,dst-axi-cohrnt: Tells whether the AXI transactions generated for the > + dst descriptor payload are marked Non-coherent Do you really need 3? dma-coherent property doesn't work for you? Not that it should dictate the binding, but the kernel doesn't support a device needing both coherent and non-coherent DMA ops. > +- xlnx,desc-axi-qos: AXI QOS bits to be used for descriptor fetch > +- xlnx,src-axi-qos: AXI QOS bits to be used for data read > +- xlnx,dst-axi-qos: AXI QOS bits to be used for data write > +- xlnx,desc-axi-cache: AXI cache bits to be used for descriptor fetch. > +- xlnx,desc-axi-cache: AXI cache bits to be used for data read > +- xlnx,desc-axi-cache: AXI cache bits to be used for data write These signals are generally part of the coherent or not setting. This allows for potentially invalid combinations. Plus you have a copy/paste error. > +- xlnx,src-burst-len: AXI length for data read. Support only power of 2 values > + i.e 1,2,4,8 and 16 > +- xlnx,dst-burst-len: AXI length for data write. Support only power of 2 values > + i.e 1,2,4,8 and 16 > + > +Example: > +++++++++ > +fpd_dma_chan1: dma at FD500000 { > + compatible = "xlnx,zynqmp-dma-1.0"; > + reg = <0x0 0xFD500000 0x1000>; > + #dma_cells = <1>; > + interrupt-parent = <&gic>; > + interrupts = <0 117 4>; > + xlnx,bus-width = <128>; > + xlnx,include-sg; > + xlnx,overfetch; > + xlnx,ratectrl = <0>; > + xlnx,src-issue = <16>; > + xlnx,desc-axi-cohrnt; > + xlnx,src-axi-cohrnt; > + xlnx,dst-axi-cohrnt; > + xlnx,desc-axi-qos = <0>; > + xlnx,desc-axi-cache = <0>; > + xlnx,src-axi-qos = <0>; > + xlnx,src-axi-cache = <2>; > + xlnx,dst-axi-qos = <0>; > + xlnx,dst-axi-cache = <2>; > + xlnx,src-burst-len = <4>; > + xlnx,dst-burst-len = <4>; > +}; > -- > 1.7.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel at lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2015-08-24 18:54 UTC|newest] Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-08-06 3:19 [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation Punnaiah Choudary Kalluri 2015-08-06 3:19 ` Punnaiah Choudary Kalluri 2015-08-06 3:19 ` Punnaiah Choudary Kalluri 2015-08-06 3:19 ` [PATCH v4 2/2] dma: Add Xilinx zynqmp dma engine driver support Punnaiah Choudary Kalluri 2015-08-06 3:19 ` Punnaiah Choudary Kalluri 2015-08-06 3:19 ` Punnaiah Choudary Kalluri 2015-08-20 6:13 ` Vinod Koul 2015-08-20 6:13 ` Vinod Koul 2015-08-20 6:31 ` punnaiah choudary kalluri 2015-08-20 6:31 ` punnaiah choudary kalluri 2015-08-20 6:31 ` punnaiah choudary kalluri 2015-08-23 14:08 ` Vinod Koul 2015-08-23 14:08 ` Vinod Koul 2015-08-23 14:08 ` Vinod Koul 2015-08-23 14:54 ` punnaiah choudary kalluri 2015-08-23 14:54 ` punnaiah choudary kalluri 2015-08-20 5:52 ` [PATCH v4 1/2] Documentation: dt: Add Xilinx zynqmp dma device tree binding documentation Vinod Koul 2015-08-20 5:52 ` Vinod Koul 2015-08-20 5:52 ` Vinod Koul 2015-08-20 6:11 ` punnaiah choudary kalluri 2015-08-20 6:11 ` punnaiah choudary kalluri 2015-08-20 6:18 ` Vinod Koul 2015-08-20 6:18 ` Vinod Koul 2015-08-20 6:18 ` Vinod Koul 2015-08-20 6:20 ` Michal Simek 2015-08-20 6:20 ` Michal Simek 2015-08-20 6:20 ` Michal Simek 2015-08-21 8:29 ` Moritz Fischer 2015-08-21 16:42 ` Moritz Fischer 2015-08-21 16:42 ` Moritz Fischer 2015-08-21 16:42 ` Moritz Fischer 2015-08-22 10:47 ` punnaiah choudary kalluri 2015-08-22 10:47 ` punnaiah choudary kalluri 2015-08-22 10:47 ` punnaiah choudary kalluri 2015-08-24 13:47 ` Lars-Peter Clausen 2015-08-24 13:47 ` Lars-Peter Clausen 2015-08-24 13:47 ` Lars-Peter Clausen 2015-08-24 18:39 ` punnaiah choudary kalluri 2015-08-24 18:39 ` punnaiah choudary kalluri 2015-08-24 18:39 ` punnaiah choudary kalluri 2015-08-24 18:53 ` Rob Herring [this message] 2015-08-24 18:53 ` Rob Herring 2015-08-24 18:53 ` Rob Herring 2015-08-25 6:46 ` punnaiah choudary kalluri 2015-08-25 6:46 ` punnaiah choudary kalluri 2015-08-25 6:46 ` punnaiah choudary kalluri 2015-08-31 3:37 ` punnaiah choudary kalluri 2015-08-31 3:37 ` punnaiah choudary kalluri 2015-08-31 3:37 ` punnaiah choudary kalluri
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