* [PATCH 0/2] mmc: Add support for the ASPEED SD controller @ 2019-07-10 14:16 ` Andrew Jeffery 0 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-10 14:16 UTC (permalink / raw) To: linux-mmc Cc: Andrew Jeffery, ulf.hansson, robh+dt, mark.rutland, joel, adrian.hunter, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, ryanchen.aspeed Hello, This short series introduce devicetree bindings and a driver for the ASPEED SD controller. Please review! Andrew Andrew Jeffery (2): dt-bindings: mmc: Document Aspeed SD controller mmc: Add support for the ASPEED SD controller .../bindings/mmc/sdhci-of-aspeed.yaml | 91 ++++++ drivers/mmc/host/Kconfig | 12 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-aspeed.c | 307 ++++++++++++++++++ 4 files changed, 411 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml create mode 100644 drivers/mmc/host/sdhci-of-aspeed.c -- 2.20.1 ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/2] mmc: Add support for the ASPEED SD controller @ 2019-07-10 14:16 ` Andrew Jeffery 0 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-10 14:16 UTC (permalink / raw) To: linux-mmc Cc: mark.rutland, devicetree, ulf.hansson, linux-aspeed, Andrew Jeffery, ryanchen.aspeed, adrian.hunter, linux-kernel, robh+dt, joel, linux-arm-kernel Hello, This short series introduce devicetree bindings and a driver for the ASPEED SD controller. Please review! Andrew Andrew Jeffery (2): dt-bindings: mmc: Document Aspeed SD controller mmc: Add support for the ASPEED SD controller .../bindings/mmc/sdhci-of-aspeed.yaml | 91 ++++++ drivers/mmc/host/Kconfig | 12 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-aspeed.c | 307 ++++++++++++++++++ 4 files changed, 411 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml create mode 100644 drivers/mmc/host/sdhci-of-aspeed.c -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller 2019-07-10 14:16 ` Andrew Jeffery @ 2019-07-10 14:16 ` Andrew Jeffery -1 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-10 14:16 UTC (permalink / raw) To: linux-mmc Cc: Andrew Jeffery, ulf.hansson, robh+dt, mark.rutland, joel, adrian.hunter, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, ryanchen.aspeed The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if only a single slot is enabled. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml new file mode 100644 index 000000000000..e98a2ac4d46d --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED SD/SDIO/eMMC Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + - Ryan Chen <ryanchen.aspeed@gmail.com> + +description: |+ + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if + only a single slot is enabled. + + The two slots are supported by a common configuration area. As the SDHCIs for + the slots are dependent on the common configuration area, they are described + as child nodes. + +properties: + compatible: + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] + reg: + description: Common configuration registers + ranges: true + clocks: + maxItems: 1 + description: The SD/SDIO controller clock gate + sdhci: + type: object + properties: + compatible: + allOf: + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] + - const: sdhci + reg: + description: The SDHCI registers + clocks: + maxItems: 1 + description: The SD bus clock + slot: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1] + interrupts: + maxItems: 1 + description: The SD interrupt shared between both slots + required: + - compatible + - reg + - clocks + - slot + - interrupts + +required: + - compatible + - reg + - ranges + - clocks + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + sdc@1e740000 { + compatible = "aspeed,ast2500-sdc"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + + sdhci0: sdhci@1e740100 { + compatible = "aspeed,ast2500-sdhci", "sdhci"; + reg = <0x1e740100 0x100>; + slot = <0>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + }; + + sdhci1: sdhci@1e740200 { + compatible = "aspeed,ast2500-sdhci", "sdhci"; + reg = <0x1e740200 0x100>; + slot = <1>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + }; + }; -- 2.20.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller @ 2019-07-10 14:16 ` Andrew Jeffery 0 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-10 14:16 UTC (permalink / raw) To: linux-mmc Cc: mark.rutland, devicetree, ulf.hansson, linux-aspeed, Andrew Jeffery, ryanchen.aspeed, adrian.hunter, linux-kernel, robh+dt, joel, linux-arm-kernel The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if only a single slot is enabled. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml new file mode 100644 index 000000000000..e98a2ac4d46d --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED SD/SDIO/eMMC Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + - Ryan Chen <ryanchen.aspeed@gmail.com> + +description: |+ + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if + only a single slot is enabled. + + The two slots are supported by a common configuration area. As the SDHCIs for + the slots are dependent on the common configuration area, they are described + as child nodes. + +properties: + compatible: + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] + reg: + description: Common configuration registers + ranges: true + clocks: + maxItems: 1 + description: The SD/SDIO controller clock gate + sdhci: + type: object + properties: + compatible: + allOf: + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] + - const: sdhci + reg: + description: The SDHCI registers + clocks: + maxItems: 1 + description: The SD bus clock + slot: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1] + interrupts: + maxItems: 1 + description: The SD interrupt shared between both slots + required: + - compatible + - reg + - clocks + - slot + - interrupts + +required: + - compatible + - reg + - ranges + - clocks + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + sdc@1e740000 { + compatible = "aspeed,ast2500-sdc"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + + sdhci0: sdhci@1e740100 { + compatible = "aspeed,ast2500-sdhci", "sdhci"; + reg = <0x1e740100 0x100>; + slot = <0>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + }; + + sdhci1: sdhci@1e740200 { + compatible = "aspeed,ast2500-sdhci", "sdhci"; + reg = <0x1e740200 0x100>; + slot = <1>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + }; + }; -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller 2019-07-10 14:16 ` Andrew Jeffery (?) @ 2019-07-10 15:49 ` Rob Herring -1 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-10 15:49 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-mmc, Ulf Hansson, Mark Rutland, Joel Stanley, Adrian Hunter, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-aspeed, linux-kernel, ryanchen.aspeed On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > data bus if only a single slot is enabled. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ aspeed,sdhci.yaml > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > new file mode 100644 > index 000000000000..e98a2ac4d46d > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ASPEED SD/SDIO/eMMC Controller > + > +maintainers: > + - Andrew Jeffery <andrew@aj.id.au> > + - Ryan Chen <ryanchen.aspeed@gmail.com> > + > +description: |+ > + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO > + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if > + only a single slot is enabled. > + > + The two slots are supported by a common configuration area. As the SDHCIs for > + the slots are dependent on the common configuration area, they are described > + as child nodes. > + > +properties: > + compatible: > + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] > + reg: > + description: Common configuration registers This should have a 'maxItems: 1'. Same for the child reg. > + ranges: true > + clocks: > + maxItems: 1 > + description: The SD/SDIO controller clock gate > + sdhci: This needs to be a pattern (under patternProperties) as these have unit-addresses. > + type: object > + properties: > + compatible: > + allOf: > + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] > + - const: sdhci This condition can never be true. What you need is s/allOf/items/. However, 'sdhci' is not really a useful compatible because every implementation has quirks, so I'd drop it. > + reg: > + description: The SDHCI registers > + clocks: > + maxItems: 1 > + description: The SD bus clock > + slot: > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [0, 1] Is this really needed? Offset 0x100 is slot 0 and offset 0x200 is slot 1. Does that ever change? > + interrupts: > + maxItems: 1 > + description: The SD interrupt shared between both slots > + required: > + - compatible > + - reg > + - clocks > + - slot > + - interrupts > + > +required: > + - compatible > + - reg > + - ranges > + - clocks #address-cells and #size-cells are required too. You should also add 'additionalProperties: false' here so other random properties can't be present. > + > +examples: > + - | > + #include <dt-bindings/clock/aspeed-clock.h> > + sdc@1e740000 { > + compatible = "aspeed,ast2500-sdc"; > + reg = <0x1e740000 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; It's preferred to limit the range here and then the child addresses are 0x100 and 0x200. > + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; > + > + sdhci0: sdhci@1e740100 { > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > + reg = <0x1e740100 0x100>; > + slot = <0>; > + interrupts = <26>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + }; > + > + sdhci1: sdhci@1e740200 { > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > + reg = <0x1e740200 0x100>; > + slot = <1>; > + interrupts = <26>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + }; > + }; > -- > 2.20.1 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller @ 2019-07-10 15:49 ` Rob Herring 0 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-10 15:49 UTC (permalink / raw) To: Andrew Jeffery Cc: Mark Rutland, devicetree, Ulf Hansson, linux-aspeed, ryanchen.aspeed, linux-mmc, Adrian Hunter, linux-kernel, Joel Stanley, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > data bus if only a single slot is enabled. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ aspeed,sdhci.yaml > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > new file mode 100644 > index 000000000000..e98a2ac4d46d > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ASPEED SD/SDIO/eMMC Controller > + > +maintainers: > + - Andrew Jeffery <andrew@aj.id.au> > + - Ryan Chen <ryanchen.aspeed@gmail.com> > + > +description: |+ > + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO > + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if > + only a single slot is enabled. > + > + The two slots are supported by a common configuration area. As the SDHCIs for > + the slots are dependent on the common configuration area, they are described > + as child nodes. > + > +properties: > + compatible: > + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] > + reg: > + description: Common configuration registers This should have a 'maxItems: 1'. Same for the child reg. > + ranges: true > + clocks: > + maxItems: 1 > + description: The SD/SDIO controller clock gate > + sdhci: This needs to be a pattern (under patternProperties) as these have unit-addresses. > + type: object > + properties: > + compatible: > + allOf: > + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] > + - const: sdhci This condition can never be true. What you need is s/allOf/items/. However, 'sdhci' is not really a useful compatible because every implementation has quirks, so I'd drop it. > + reg: > + description: The SDHCI registers > + clocks: > + maxItems: 1 > + description: The SD bus clock > + slot: > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [0, 1] Is this really needed? Offset 0x100 is slot 0 and offset 0x200 is slot 1. Does that ever change? > + interrupts: > + maxItems: 1 > + description: The SD interrupt shared between both slots > + required: > + - compatible > + - reg > + - clocks > + - slot > + - interrupts > + > +required: > + - compatible > + - reg > + - ranges > + - clocks #address-cells and #size-cells are required too. You should also add 'additionalProperties: false' here so other random properties can't be present. > + > +examples: > + - | > + #include <dt-bindings/clock/aspeed-clock.h> > + sdc@1e740000 { > + compatible = "aspeed,ast2500-sdc"; > + reg = <0x1e740000 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; It's preferred to limit the range here and then the child addresses are 0x100 and 0x200. > + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; > + > + sdhci0: sdhci@1e740100 { > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > + reg = <0x1e740100 0x100>; > + slot = <0>; > + interrupts = <26>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + }; > + > + sdhci1: sdhci@1e740200 { > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > + reg = <0x1e740200 0x100>; > + slot = <1>; > + interrupts = <26>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + }; > + }; > -- > 2.20.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller @ 2019-07-10 15:49 ` Rob Herring 0 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-10 15:49 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-mmc, Ulf Hansson, Mark Rutland, Joel Stanley, Adrian Hunter, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-aspeed, linux-kernel, ryanchen.aspeed On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > data bus if only a single slot is enabled. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > --- > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ aspeed,sdhci.yaml > 1 file changed, 91 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > new file mode 100644 > index 000000000000..e98a2ac4d46d > --- /dev/null > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > @@ -0,0 +1,91 @@ > +# SPDX-License-Identifier: GPL-2.0-or-later The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ASPEED SD/SDIO/eMMC Controller > + > +maintainers: > + - Andrew Jeffery <andrew@aj.id.au> > + - Ryan Chen <ryanchen.aspeed@gmail.com> > + > +description: |+ > + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO > + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if > + only a single slot is enabled. > + > + The two slots are supported by a common configuration area. As the SDHCIs for > + the slots are dependent on the common configuration area, they are described > + as child nodes. > + > +properties: > + compatible: > + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] > + reg: > + description: Common configuration registers This should have a 'maxItems: 1'. Same for the child reg. > + ranges: true > + clocks: > + maxItems: 1 > + description: The SD/SDIO controller clock gate > + sdhci: This needs to be a pattern (under patternProperties) as these have unit-addresses. > + type: object > + properties: > + compatible: > + allOf: > + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] > + - const: sdhci This condition can never be true. What you need is s/allOf/items/. However, 'sdhci' is not really a useful compatible because every implementation has quirks, so I'd drop it. > + reg: > + description: The SDHCI registers > + clocks: > + maxItems: 1 > + description: The SD bus clock > + slot: > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [0, 1] Is this really needed? Offset 0x100 is slot 0 and offset 0x200 is slot 1. Does that ever change? > + interrupts: > + maxItems: 1 > + description: The SD interrupt shared between both slots > + required: > + - compatible > + - reg > + - clocks > + - slot > + - interrupts > + > +required: > + - compatible > + - reg > + - ranges > + - clocks #address-cells and #size-cells are required too. You should also add 'additionalProperties: false' here so other random properties can't be present. > + > +examples: > + - | > + #include <dt-bindings/clock/aspeed-clock.h> > + sdc@1e740000 { > + compatible = "aspeed,ast2500-sdc"; > + reg = <0x1e740000 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; It's preferred to limit the range here and then the child addresses are 0x100 and 0x200. > + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; > + > + sdhci0: sdhci@1e740100 { > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > + reg = <0x1e740100 0x100>; > + slot = <0>; > + interrupts = <26>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + }; > + > + sdhci1: sdhci@1e740200 { > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > + reg = <0x1e740200 0x100>; > + slot = <1>; > + interrupts = <26>; > + sdhci,auto-cmd12; > + clocks = <&syscon ASPEED_CLK_SDIO>; > + }; > + }; > -- > 2.20.1 > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller 2019-07-10 15:49 ` Rob Herring (?) @ 2019-07-11 0:56 ` Andrew Jeffery -1 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-11 0:56 UTC (permalink / raw) To: Rob Herring Cc: linux-mmc, Ulf Hansson, Mark Rutland, Joel Stanley, Adrian Hunter, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-aspeed, linux-kernel, Ryan Chen On Thu, 11 Jul 2019, at 01:20, Rob Herring wrote: > On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > > data bus if only a single slot is enabled. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ > > aspeed,sdhci.yaml Ack. Previously I had separate documents for different compatibles, wasn't sure how to tackle name one document covering multiple compatibles. > > > 1 file changed, 91 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > new file mode 100644 > > index 000000000000..e98a2ac4d46d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > @@ -0,0 +1,91 @@ > > +# SPDX-License-Identifier: GPL-2.0-or-later > > The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. I should poke people internally again, I had asked, just haven't got a clear answer. What was the justification for the preference (just so I can pass that on)? > > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: ASPEED SD/SDIO/eMMC Controller > > + > > +maintainers: > > + - Andrew Jeffery <andrew@aj.id.au> > > + - Ryan Chen <ryanchen.aspeed@gmail.com> > > + > > +description: |+ > > + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO > > + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if > > + only a single slot is enabled. > > + > > + The two slots are supported by a common configuration area. As the SDHCIs for > > + the slots are dependent on the common configuration area, they are described > > + as child nodes. > > + > > +properties: > > + compatible: > > + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] > > + reg: > > + description: Common configuration registers > > This should have a 'maxItems: 1'. Same for the child reg. Ack. > > > + ranges: true > > + clocks: > > + maxItems: 1 > > + description: The SD/SDIO controller clock gate > > + sdhci: > > This needs to be a pattern (under patternProperties) as these have > unit-addresses. Ah, I didn't think about that. > > > + type: object > > + properties: > > + compatible: > > + allOf: > > + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] > > + - const: sdhci > > This condition can never be true. What you need is s/allOf/items/. > However, 'sdhci' is not really a useful compatible because every > implementation has quirks, so I'd drop it. Yeah, I was tossing up whether to include "sdhci". I'll drop it as you suggest. Pity the shorthand doesn't work how I expected. Might explain some of the behaviour I was seeing with the bindings make targets though. > > > + reg: > > + description: The SDHCI registers > > + clocks: > > + maxItems: 1 > > + description: The SD bus clock > > + slot: > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + - enum: [0, 1] > > Is this really needed? Offset 0x100 is slot 0 and offset 0x200 is slot > 1. Does that ever change? It doesn't in the SoCs at hand, but the downstream impact (driver implementation) is that you need to derive the slot index from the address and I was trying to avoid that. The slot index influences some bit index calculations. > > > + interrupts: > > + maxItems: 1 > > + description: The SD interrupt shared between both slots > > + required: > > + - compatible > > + - reg > > + - clocks > > + - slot > > + - interrupts > > + > > +required: > > + - compatible > > + - reg > > + - ranges > > + - clocks > > #address-cells and #size-cells are required too. Ack. > > You should also add 'additionalProperties: false' here so other random > properties can't be present. Ah yes. Will fix. > > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/aspeed-clock.h> > > + sdc@1e740000 { > > + compatible = "aspeed,ast2500-sdc"; > > + reg = <0x1e740000 0x100>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > It's preferred to limit the range here and then the child addresses > are 0x100 and 0x200. Okay. Was just trying to dodge mental arithmetic where I could, but if that's the preference then I'll fix it up. Thanks for the review! Andrew > > > + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; > > + > > + sdhci0: sdhci@1e740100 { > > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > > + reg = <0x1e740100 0x100>; > > + slot = <0>; > > + interrupts = <26>; > > + sdhci,auto-cmd12; > > + clocks = <&syscon ASPEED_CLK_SDIO>; > > + }; > > + > > + sdhci1: sdhci@1e740200 { > > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > > + reg = <0x1e740200 0x100>; > > + slot = <1>; > > + interrupts = <26>; > > + sdhci,auto-cmd12; > > + clocks = <&syscon ASPEED_CLK_SDIO>; > > + }; > > + }; > > -- > > 2.20.1 > > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller @ 2019-07-11 0:56 ` Andrew Jeffery 0 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-11 0:56 UTC (permalink / raw) To: Rob Herring Cc: Mark Rutland, devicetree, Ulf Hansson, linux-aspeed, Ryan Chen, linux-mmc, Adrian Hunter, linux-kernel, Joel Stanley, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Thu, 11 Jul 2019, at 01:20, Rob Herring wrote: > On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > > data bus if only a single slot is enabled. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ > > aspeed,sdhci.yaml Ack. Previously I had separate documents for different compatibles, wasn't sure how to tackle name one document covering multiple compatibles. > > > 1 file changed, 91 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > new file mode 100644 > > index 000000000000..e98a2ac4d46d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > @@ -0,0 +1,91 @@ > > +# SPDX-License-Identifier: GPL-2.0-or-later > > The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. I should poke people internally again, I had asked, just haven't got a clear answer. What was the justification for the preference (just so I can pass that on)? > > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: ASPEED SD/SDIO/eMMC Controller > > + > > +maintainers: > > + - Andrew Jeffery <andrew@aj.id.au> > > + - Ryan Chen <ryanchen.aspeed@gmail.com> > > + > > +description: |+ > > + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO > > + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if > > + only a single slot is enabled. > > + > > + The two slots are supported by a common configuration area. As the SDHCIs for > > + the slots are dependent on the common configuration area, they are described > > + as child nodes. > > + > > +properties: > > + compatible: > > + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] > > + reg: > > + description: Common configuration registers > > This should have a 'maxItems: 1'. Same for the child reg. Ack. > > > + ranges: true > > + clocks: > > + maxItems: 1 > > + description: The SD/SDIO controller clock gate > > + sdhci: > > This needs to be a pattern (under patternProperties) as these have > unit-addresses. Ah, I didn't think about that. > > > + type: object > > + properties: > > + compatible: > > + allOf: > > + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] > > + - const: sdhci > > This condition can never be true. What you need is s/allOf/items/. > However, 'sdhci' is not really a useful compatible because every > implementation has quirks, so I'd drop it. Yeah, I was tossing up whether to include "sdhci". I'll drop it as you suggest. Pity the shorthand doesn't work how I expected. Might explain some of the behaviour I was seeing with the bindings make targets though. > > > + reg: > > + description: The SDHCI registers > > + clocks: > > + maxItems: 1 > > + description: The SD bus clock > > + slot: > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + - enum: [0, 1] > > Is this really needed? Offset 0x100 is slot 0 and offset 0x200 is slot > 1. Does that ever change? It doesn't in the SoCs at hand, but the downstream impact (driver implementation) is that you need to derive the slot index from the address and I was trying to avoid that. The slot index influences some bit index calculations. > > > + interrupts: > > + maxItems: 1 > > + description: The SD interrupt shared between both slots > > + required: > > + - compatible > > + - reg > > + - clocks > > + - slot > > + - interrupts > > + > > +required: > > + - compatible > > + - reg > > + - ranges > > + - clocks > > #address-cells and #size-cells are required too. Ack. > > You should also add 'additionalProperties: false' here so other random > properties can't be present. Ah yes. Will fix. > > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/aspeed-clock.h> > > + sdc@1e740000 { > > + compatible = "aspeed,ast2500-sdc"; > > + reg = <0x1e740000 0x100>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > It's preferred to limit the range here and then the child addresses > are 0x100 and 0x200. Okay. Was just trying to dodge mental arithmetic where I could, but if that's the preference then I'll fix it up. Thanks for the review! Andrew > > > + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; > > + > > + sdhci0: sdhci@1e740100 { > > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > > + reg = <0x1e740100 0x100>; > > + slot = <0>; > > + interrupts = <26>; > > + sdhci,auto-cmd12; > > + clocks = <&syscon ASPEED_CLK_SDIO>; > > + }; > > + > > + sdhci1: sdhci@1e740200 { > > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > > + reg = <0x1e740200 0x100>; > > + slot = <1>; > > + interrupts = <26>; > > + sdhci,auto-cmd12; > > + clocks = <&syscon ASPEED_CLK_SDIO>; > > + }; > > + }; > > -- > > 2.20.1 > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller @ 2019-07-11 0:56 ` Andrew Jeffery 0 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-11 0:56 UTC (permalink / raw) To: Rob Herring Cc: linux-mmc, Ulf Hansson, Mark Rutland, Joel Stanley, Adrian Hunter, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-aspeed, linux-kernel, Ryan Chen On Thu, 11 Jul 2019, at 01:20, Rob Herring wrote: > On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > > data bus if only a single slot is enabled. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > --- > > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ > > aspeed,sdhci.yaml Ack. Previously I had separate documents for different compatibles, wasn't sure how to tackle name one document covering multiple compatibles. > > > 1 file changed, 91 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > new file mode 100644 > > index 000000000000..e98a2ac4d46d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > @@ -0,0 +1,91 @@ > > +# SPDX-License-Identifier: GPL-2.0-or-later > > The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. I should poke people internally again, I had asked, just haven't got a clear answer. What was the justification for the preference (just so I can pass that on)? > > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mmc/sdhci-of-aspeed.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: ASPEED SD/SDIO/eMMC Controller > > + > > +maintainers: > > + - Andrew Jeffery <andrew@aj.id.au> > > + - Ryan Chen <ryanchen.aspeed@gmail.com> > > + > > +description: |+ > > + The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the SDIO > > + Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if > > + only a single slot is enabled. > > + > > + The two slots are supported by a common configuration area. As the SDHCIs for > > + the slots are dependent on the common configuration area, they are described > > + as child nodes. > > + > > +properties: > > + compatible: > > + enum: [ aspeed,ast2400-sdc, aspeed,ast2500-sdc ] > > + reg: > > + description: Common configuration registers > > This should have a 'maxItems: 1'. Same for the child reg. Ack. > > > + ranges: true > > + clocks: > > + maxItems: 1 > > + description: The SD/SDIO controller clock gate > > + sdhci: > > This needs to be a pattern (under patternProperties) as these have > unit-addresses. Ah, I didn't think about that. > > > + type: object > > + properties: > > + compatible: > > + allOf: > > + - enum: [ aspeed,ast2400-sdhci, aspeed,ast2500-sdhci ] > > + - const: sdhci > > This condition can never be true. What you need is s/allOf/items/. > However, 'sdhci' is not really a useful compatible because every > implementation has quirks, so I'd drop it. Yeah, I was tossing up whether to include "sdhci". I'll drop it as you suggest. Pity the shorthand doesn't work how I expected. Might explain some of the behaviour I was seeing with the bindings make targets though. > > > + reg: > > + description: The SDHCI registers > > + clocks: > > + maxItems: 1 > > + description: The SD bus clock > > + slot: > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + - enum: [0, 1] > > Is this really needed? Offset 0x100 is slot 0 and offset 0x200 is slot > 1. Does that ever change? It doesn't in the SoCs at hand, but the downstream impact (driver implementation) is that you need to derive the slot index from the address and I was trying to avoid that. The slot index influences some bit index calculations. > > > + interrupts: > > + maxItems: 1 > > + description: The SD interrupt shared between both slots > > + required: > > + - compatible > > + - reg > > + - clocks > > + - slot > > + - interrupts > > + > > +required: > > + - compatible > > + - reg > > + - ranges > > + - clocks > > #address-cells and #size-cells are required too. Ack. > > You should also add 'additionalProperties: false' here so other random > properties can't be present. Ah yes. Will fix. > > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/aspeed-clock.h> > > + sdc@1e740000 { > > + compatible = "aspeed,ast2500-sdc"; > > + reg = <0x1e740000 0x100>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > > It's preferred to limit the range here and then the child addresses > are 0x100 and 0x200. Okay. Was just trying to dodge mental arithmetic where I could, but if that's the preference then I'll fix it up. Thanks for the review! Andrew > > > + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; > > + > > + sdhci0: sdhci@1e740100 { > > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > > + reg = <0x1e740100 0x100>; > > + slot = <0>; > > + interrupts = <26>; > > + sdhci,auto-cmd12; > > + clocks = <&syscon ASPEED_CLK_SDIO>; > > + }; > > + > > + sdhci1: sdhci@1e740200 { > > + compatible = "aspeed,ast2500-sdhci", "sdhci"; > > + reg = <0x1e740200 0x100>; > > + slot = <1>; > > + interrupts = <26>; > > + sdhci,auto-cmd12; > > + clocks = <&syscon ASPEED_CLK_SDIO>; > > + }; > > + }; > > -- > > 2.20.1 > > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller 2019-07-11 0:56 ` Andrew Jeffery (?) @ 2019-07-11 13:44 ` Rob Herring -1 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-11 13:44 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-mmc, Ulf Hansson, Mark Rutland, Joel Stanley, Adrian Hunter, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-aspeed, linux-kernel, Ryan Chen On Wed, Jul 10, 2019 at 6:56 PM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > On Thu, 11 Jul 2019, at 01:20, Rob Herring wrote: > > On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > > > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > > > data bus if only a single slot is enabled. > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > --- > > > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ > > > > aspeed,sdhci.yaml > > Ack. Previously I had separate documents for different compatibles, wasn't sure > how to tackle name one document covering multiple compatibles. > > > > > > 1 file changed, 91 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > new file mode 100644 > > > index 000000000000..e98a2ac4d46d > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > @@ -0,0 +1,91 @@ > > > +# SPDX-License-Identifier: GPL-2.0-or-later > > > > The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. > > I should poke people internally again, I had asked, just haven't got a clear > answer. What was the justification for the preference (just so I can pass that > on)? To use schema in non-GPL projects. *BSD, Zephyr, etc. Rob ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller @ 2019-07-11 13:44 ` Rob Herring 0 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-11 13:44 UTC (permalink / raw) To: Andrew Jeffery Cc: Mark Rutland, devicetree, Ulf Hansson, linux-aspeed, Ryan Chen, linux-mmc, Adrian Hunter, linux-kernel, Joel Stanley, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Wed, Jul 10, 2019 at 6:56 PM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > On Thu, 11 Jul 2019, at 01:20, Rob Herring wrote: > > On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > > > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > > > data bus if only a single slot is enabled. > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > --- > > > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ > > > > aspeed,sdhci.yaml > > Ack. Previously I had separate documents for different compatibles, wasn't sure > how to tackle name one document covering multiple compatibles. > > > > > > 1 file changed, 91 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > new file mode 100644 > > > index 000000000000..e98a2ac4d46d > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > @@ -0,0 +1,91 @@ > > > +# SPDX-License-Identifier: GPL-2.0-or-later > > > > The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. > > I should poke people internally again, I had asked, just haven't got a clear > answer. What was the justification for the preference (just so I can pass that > on)? To use schema in non-GPL projects. *BSD, Zephyr, etc. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mmc: Document Aspeed SD controller @ 2019-07-11 13:44 ` Rob Herring 0 siblings, 0 replies; 15+ messages in thread From: Rob Herring @ 2019-07-11 13:44 UTC (permalink / raw) To: Andrew Jeffery Cc: linux-mmc, Ulf Hansson, Mark Rutland, Joel Stanley, Adrian Hunter, devicetree, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, linux-aspeed, linux-kernel, Ryan Chen On Wed, Jul 10, 2019 at 6:56 PM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > On Thu, 11 Jul 2019, at 01:20, Rob Herring wrote: > > On Wed, Jul 10, 2019 at 8:16 AM Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > The ASPEED SD/SDIO/eMMC controller exposes two slots implementing the > > > SDIO Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit > > > data bus if only a single slot is enabled. > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > --- > > > .../bindings/mmc/sdhci-of-aspeed.yaml | 91 +++++++++++++++++++ > > > > aspeed,sdhci.yaml > > Ack. Previously I had separate documents for different compatibles, wasn't sure > how to tackle name one document covering multiple compatibles. > > > > > > 1 file changed, 91 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > new file mode 100644 > > > index 000000000000..e98a2ac4d46d > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/mmc/sdhci-of-aspeed.yaml > > > @@ -0,0 +1,91 @@ > > > +# SPDX-License-Identifier: GPL-2.0-or-later > > > > The preferred license is (GPL-2.0 OR BSD-2-Clause) if that is okay with you. > > I should poke people internally again, I had asked, just haven't got a clear > answer. What was the justification for the preference (just so I can pass that > on)? To use schema in non-GPL projects. *BSD, Zephyr, etc. Rob ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/2] mmc: Add support for the ASPEED SD controller 2019-07-10 14:16 ` Andrew Jeffery @ 2019-07-10 14:16 ` Andrew Jeffery -1 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-10 14:16 UTC (permalink / raw) To: linux-mmc Cc: Andrew Jeffery, ulf.hansson, robh+dt, mark.rutland, joel, adrian.hunter, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, ryanchen.aspeed Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/mmc/host/Kconfig | 12 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-aspeed.c | 307 +++++++++++++++++++++++++++++ 3 files changed, 320 insertions(+) create mode 100644 drivers/mmc/host/sdhci-of-aspeed.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 931770f17087..2bb5e1264b3d 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -154,6 +154,18 @@ config MMC_SDHCI_OF_ARASAN If unsure, say N. +config MMC_SDHCI_OF_ASPEED + tristate "SDHCI OF support for the ASPEED SDHCI controller" + depends on MMC_SDHCI_PLTFM + depends on OF + help + This selects the ASPEED Secure Digital Host Controller Interface. + + If you have a controller with this interface, say Y or M here. You + also need to enable an appropriate bus interface. + + If unsure, say N. + config MMC_SDHCI_OF_AT91 tristate "SDHCI OF support for the Atmel SDMMC controller" depends on MMC_SDHCI_PLTFM diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..390ee162fe71 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o +obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c new file mode 100644 index 000000000000..23fad19787db --- /dev/null +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2019 ASPEED Technology Inc. */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/mmc/host.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#include "sdhci-pltfm.h" + +#define ASPEED_SDC_INFO 0x00 +#define ASPEED_SDC_S1MMC8 BIT(25) +#define ASPEED_SDC_S0MMC8 BIT(24) + +struct aspeed_sdc { + struct clk *clk; + + spinlock_t lock; + void __iomem *regs; +}; + +struct aspeed_sdhci { + struct aspeed_sdc *parent; + u32 width_mask; +}; + +static void aspeed_sdc_bus_width(struct aspeed_sdc *sdc, + struct aspeed_sdhci *sdhci, bool bus8) +{ + u32 info; + + /* Set/clear 8 bit mode */ + spin_lock(&sdc->lock); + info = readl(sdc->regs + ASPEED_SDC_INFO); + if (bus8) + info |= sdhci->width_mask; + else + info &= ~sdhci->width_mask; + writel(info, sdc->regs + ASPEED_SDC_INFO); + spin_unlock(&sdc->lock); +} + +static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + unsigned long timeout; + int div; + u16 clk; + + if (clock == host->clock) + return; + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + goto out; + + for (div = 1; div < 256; div *= 2) { + if ((host->max_clk / div) <= clock) + break; + } + div >>= 1; + + clk = div << SDHCI_DIVIDER_SHIFT; + clk |= SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 20 ms */ + timeout = 20; + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + return; + } + timeout--; + mdelay(1); + } + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + +out: + host->clock = clock; +} + +static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) +{ + struct sdhci_pltfm_host *pltfm_priv; + struct aspeed_sdhci *aspeed_sdhci; + struct aspeed_sdc *aspeed_sdc; + u8 ctrl; + + pltfm_priv = sdhci_priv(host); + aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv); + aspeed_sdc = aspeed_sdhci->parent; + + /* Set/clear 8-bit mode */ + aspeed_sdc_bus_width(aspeed_sdc, aspeed_sdhci, + width == MMC_BUS_WIDTH_8); + + /* Set/clear 1 or 4 bit mode */ + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + if (width == MMC_BUS_WIDTH_4) + ctrl |= SDHCI_CTRL_4BITBUS; + else + ctrl &= ~SDHCI_CTRL_4BITBUS; + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + +static const struct sdhci_ops aspeed_sdhci_ops = { + .set_clock = aspeed_sdhci_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .set_bus_width = aspeed_sdhci_set_bus_width, + .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + +static const struct sdhci_pltfm_data aspeed_sdc_pdata = { + .ops = &aspeed_sdhci_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, +}; + +static int aspeed_sdhci_probe(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct aspeed_sdhci *dev; + struct sdhci_host *host; + u32 slot; + int ret; + + host = sdhci_pltfm_init(pdev, &aspeed_sdc_pdata, sizeof(*dev)); + if (IS_ERR(host)) + return PTR_ERR(host); + + pltfm_host = sdhci_priv(host); + dev = sdhci_pltfm_priv(pltfm_host); + dev->parent = dev_get_drvdata(pdev->dev.parent); + + ret = of_property_read_u32(pdev->dev.of_node, "slot", &slot); + if (ret < 0) + return ret; + else if (slot > 2) + return -EINVAL; + + dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8; + + sdhci_get_of_property(pdev); + + pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pltfm_host->clk)) + return PTR_ERR(pltfm_host->clk); + + ret = clk_prepare_enable(pltfm_host->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable SDIO clock\n"); + goto err_pltfm_free; + } + + ret = mmc_of_parse(host->mmc); + if (ret) + goto err_sdhci_add; + + ret = sdhci_add_host(host); + if (ret) + goto err_sdhci_add; + + return 0; + +err_sdhci_add: + clk_disable_unprepare(pltfm_host->clk); +err_pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int aspeed_sdhci_remove(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; + int dead; + + host = platform_get_drvdata(pdev); + pltfm_host = sdhci_priv(host); + + dead = readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff; + + sdhci_remove_host(host, dead); + + clk_disable_unprepare(pltfm_host->clk); + + sdhci_pltfm_free(pdev); + + return 0; +} + +static const struct of_device_id aspeed_sdhci_of_match[] = { + { .compatible = "aspeed,ast2400-sdhci", }, + { .compatible = "aspeed,ast2500-sdhci", }, + { } +}; + +MODULE_DEVICE_TABLE(of, aspeed_sdhci_of_match); + +static struct platform_driver aspeed_sdhci_driver = { + .driver = { + .name = "sdhci-aspeed", + .of_match_table = aspeed_sdhci_of_match, + }, + .probe = aspeed_sdhci_probe, + .remove = aspeed_sdhci_remove, +}; + +module_platform_driver(aspeed_sdhci_driver); + +static int aspeed_sdc_probe(struct platform_device *pdev) + +{ + struct device_node *parent, *child; + struct aspeed_sdc *sdc; + int ret; + + sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); + if (!sdc) + return -ENOMEM; + + spin_lock_init(&sdc->lock); + + sdc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(sdc->clk)) + return PTR_ERR(sdc->clk); + + ret = clk_prepare_enable(sdc->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable SDCLK\n"); + return ret; + } + + sdc->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sdc->regs)) { + ret = PTR_ERR(sdc->regs); + goto err_clk; + } + + dev_set_drvdata(&pdev->dev, sdc); + + parent = pdev->dev.of_node; + for_each_available_child_of_node(parent, child) { + struct platform_device *cpdev; + + cpdev = of_platform_device_create(child, NULL, &pdev->dev); + if (IS_ERR(cpdev)) { + of_node_put(child); + ret = PTR_ERR(pdev); + goto err_clk; + } + } + + return 0; + +err_clk: + clk_disable_unprepare(sdc->clk); + return ret; +} + +static int aspeed_sdc_remove(struct platform_device *pdev) +{ + struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev); + + clk_disable_unprepare(sdc->clk); + + return 0; +} + +static const struct of_device_id aspeed_sdc_of_match[] = { + { .compatible = "aspeed,ast2400-sdc", .data = &aspeed_sdc_pdata }, + { .compatible = "aspeed,ast2500-sdc", .data = &aspeed_sdc_pdata }, + { } +}; + +MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match); + +static struct platform_driver aspeed_sdc_driver = { + .driver = { + .name = "sdc-aspeed", + .pm = &sdhci_pltfm_pmops, + .of_match_table = aspeed_sdc_of_match, + }, + .probe = aspeed_sdc_probe, + .remove = aspeed_sdc_remove, +}; + +module_platform_driver(aspeed_sdc_driver); + +MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers"); +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>"); +MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>"); +MODULE_LICENSE("GPL v2"); -- 2.20.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] mmc: Add support for the ASPEED SD controller @ 2019-07-10 14:16 ` Andrew Jeffery 0 siblings, 0 replies; 15+ messages in thread From: Andrew Jeffery @ 2019-07-10 14:16 UTC (permalink / raw) To: linux-mmc Cc: mark.rutland, devicetree, ulf.hansson, linux-aspeed, Andrew Jeffery, ryanchen.aspeed, adrian.hunter, linux-kernel, robh+dt, joel, linux-arm-kernel Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> --- drivers/mmc/host/Kconfig | 12 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-of-aspeed.c | 307 +++++++++++++++++++++++++++++ 3 files changed, 320 insertions(+) create mode 100644 drivers/mmc/host/sdhci-of-aspeed.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 931770f17087..2bb5e1264b3d 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -154,6 +154,18 @@ config MMC_SDHCI_OF_ARASAN If unsure, say N. +config MMC_SDHCI_OF_ASPEED + tristate "SDHCI OF support for the ASPEED SDHCI controller" + depends on MMC_SDHCI_PLTFM + depends on OF + help + This selects the ASPEED Secure Digital Host Controller Interface. + + If you have a controller with this interface, say Y or M here. You + also need to enable an appropriate bus interface. + + If unsure, say N. + config MMC_SDHCI_OF_AT91 tristate "SDHCI OF support for the Atmel SDMMC controller" depends on MMC_SDHCI_PLTFM diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..390ee162fe71 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o +obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c new file mode 100644 index 000000000000..23fad19787db --- /dev/null +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2019 ASPEED Technology Inc. */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/mmc/host.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#include "sdhci-pltfm.h" + +#define ASPEED_SDC_INFO 0x00 +#define ASPEED_SDC_S1MMC8 BIT(25) +#define ASPEED_SDC_S0MMC8 BIT(24) + +struct aspeed_sdc { + struct clk *clk; + + spinlock_t lock; + void __iomem *regs; +}; + +struct aspeed_sdhci { + struct aspeed_sdc *parent; + u32 width_mask; +}; + +static void aspeed_sdc_bus_width(struct aspeed_sdc *sdc, + struct aspeed_sdhci *sdhci, bool bus8) +{ + u32 info; + + /* Set/clear 8 bit mode */ + spin_lock(&sdc->lock); + info = readl(sdc->regs + ASPEED_SDC_INFO); + if (bus8) + info |= sdhci->width_mask; + else + info &= ~sdhci->width_mask; + writel(info, sdc->regs + ASPEED_SDC_INFO); + spin_unlock(&sdc->lock); +} + +static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + unsigned long timeout; + int div; + u16 clk; + + if (clock == host->clock) + return; + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + goto out; + + for (div = 1; div < 256; div *= 2) { + if ((host->max_clk / div) <= clock) + break; + } + div >>= 1; + + clk = div << SDHCI_DIVIDER_SHIFT; + clk |= SDHCI_CLOCK_INT_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 20 ms */ + timeout = 20; + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (timeout == 0) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + return; + } + timeout--; + mdelay(1); + } + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + +out: + host->clock = clock; +} + +static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) +{ + struct sdhci_pltfm_host *pltfm_priv; + struct aspeed_sdhci *aspeed_sdhci; + struct aspeed_sdc *aspeed_sdc; + u8 ctrl; + + pltfm_priv = sdhci_priv(host); + aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv); + aspeed_sdc = aspeed_sdhci->parent; + + /* Set/clear 8-bit mode */ + aspeed_sdc_bus_width(aspeed_sdc, aspeed_sdhci, + width == MMC_BUS_WIDTH_8); + + /* Set/clear 1 or 4 bit mode */ + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + if (width == MMC_BUS_WIDTH_4) + ctrl |= SDHCI_CTRL_4BITBUS; + else + ctrl &= ~SDHCI_CTRL_4BITBUS; + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + +static const struct sdhci_ops aspeed_sdhci_ops = { + .set_clock = aspeed_sdhci_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .set_bus_width = aspeed_sdhci_set_bus_width, + .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + +static const struct sdhci_pltfm_data aspeed_sdc_pdata = { + .ops = &aspeed_sdhci_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, +}; + +static int aspeed_sdhci_probe(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct aspeed_sdhci *dev; + struct sdhci_host *host; + u32 slot; + int ret; + + host = sdhci_pltfm_init(pdev, &aspeed_sdc_pdata, sizeof(*dev)); + if (IS_ERR(host)) + return PTR_ERR(host); + + pltfm_host = sdhci_priv(host); + dev = sdhci_pltfm_priv(pltfm_host); + dev->parent = dev_get_drvdata(pdev->dev.parent); + + ret = of_property_read_u32(pdev->dev.of_node, "slot", &slot); + if (ret < 0) + return ret; + else if (slot > 2) + return -EINVAL; + + dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8; + + sdhci_get_of_property(pdev); + + pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pltfm_host->clk)) + return PTR_ERR(pltfm_host->clk); + + ret = clk_prepare_enable(pltfm_host->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable SDIO clock\n"); + goto err_pltfm_free; + } + + ret = mmc_of_parse(host->mmc); + if (ret) + goto err_sdhci_add; + + ret = sdhci_add_host(host); + if (ret) + goto err_sdhci_add; + + return 0; + +err_sdhci_add: + clk_disable_unprepare(pltfm_host->clk); +err_pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int aspeed_sdhci_remove(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; + int dead; + + host = platform_get_drvdata(pdev); + pltfm_host = sdhci_priv(host); + + dead = readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff; + + sdhci_remove_host(host, dead); + + clk_disable_unprepare(pltfm_host->clk); + + sdhci_pltfm_free(pdev); + + return 0; +} + +static const struct of_device_id aspeed_sdhci_of_match[] = { + { .compatible = "aspeed,ast2400-sdhci", }, + { .compatible = "aspeed,ast2500-sdhci", }, + { } +}; + +MODULE_DEVICE_TABLE(of, aspeed_sdhci_of_match); + +static struct platform_driver aspeed_sdhci_driver = { + .driver = { + .name = "sdhci-aspeed", + .of_match_table = aspeed_sdhci_of_match, + }, + .probe = aspeed_sdhci_probe, + .remove = aspeed_sdhci_remove, +}; + +module_platform_driver(aspeed_sdhci_driver); + +static int aspeed_sdc_probe(struct platform_device *pdev) + +{ + struct device_node *parent, *child; + struct aspeed_sdc *sdc; + int ret; + + sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); + if (!sdc) + return -ENOMEM; + + spin_lock_init(&sdc->lock); + + sdc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(sdc->clk)) + return PTR_ERR(sdc->clk); + + ret = clk_prepare_enable(sdc->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable SDCLK\n"); + return ret; + } + + sdc->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sdc->regs)) { + ret = PTR_ERR(sdc->regs); + goto err_clk; + } + + dev_set_drvdata(&pdev->dev, sdc); + + parent = pdev->dev.of_node; + for_each_available_child_of_node(parent, child) { + struct platform_device *cpdev; + + cpdev = of_platform_device_create(child, NULL, &pdev->dev); + if (IS_ERR(cpdev)) { + of_node_put(child); + ret = PTR_ERR(pdev); + goto err_clk; + } + } + + return 0; + +err_clk: + clk_disable_unprepare(sdc->clk); + return ret; +} + +static int aspeed_sdc_remove(struct platform_device *pdev) +{ + struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev); + + clk_disable_unprepare(sdc->clk); + + return 0; +} + +static const struct of_device_id aspeed_sdc_of_match[] = { + { .compatible = "aspeed,ast2400-sdc", .data = &aspeed_sdc_pdata }, + { .compatible = "aspeed,ast2500-sdc", .data = &aspeed_sdc_pdata }, + { } +}; + +MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match); + +static struct platform_driver aspeed_sdc_driver = { + .driver = { + .name = "sdc-aspeed", + .pm = &sdhci_pltfm_pmops, + .of_match_table = aspeed_sdc_of_match, + }, + .probe = aspeed_sdc_probe, + .remove = aspeed_sdc_remove, +}; + +module_platform_driver(aspeed_sdc_driver); + +MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers"); +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>"); +MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>"); +MODULE_LICENSE("GPL v2"); -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2019-07-11 13:44 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-07-10 14:16 [PATCH 0/2] mmc: Add support for the ASPEED SD controller Andrew Jeffery 2019-07-10 14:16 ` Andrew Jeffery 2019-07-10 14:16 ` [PATCH 1/2] dt-bindings: mmc: Document Aspeed " Andrew Jeffery 2019-07-10 14:16 ` Andrew Jeffery 2019-07-10 15:49 ` Rob Herring 2019-07-10 15:49 ` Rob Herring 2019-07-10 15:49 ` Rob Herring 2019-07-11 0:56 ` Andrew Jeffery 2019-07-11 0:56 ` Andrew Jeffery 2019-07-11 0:56 ` Andrew Jeffery 2019-07-11 13:44 ` Rob Herring 2019-07-11 13:44 ` Rob Herring 2019-07-11 13:44 ` Rob Herring 2019-07-10 14:16 ` [PATCH 2/2] mmc: Add support for the ASPEED " Andrew Jeffery 2019-07-10 14:16 ` Andrew Jeffery
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