* [PATCH v6 0/7] ARM generic idle states
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel, linux-pm
Cc: devicetree, Lorenzo Pieralisi, Mark Rutland, Sudeep Holla,
Catalin Marinas, Charles Garcia Tobin, Nicolas Pitre,
Rob Herring, Grant Likely, Peter De Schrijver, Santosh Shilimkar,
Daniel Lezcano, Amit Kucheria, Vincent Guittot, Antti Miettinen,
Stephen Boyd, Kevin Hilman, Sebastian Capella, Tomasz Figa,
Mark Brown, Paul Walmsley, Chander Kashyap, Geoff
This patch is v6 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266488.html
Patchset has been tested on:
- Juno ARM64 platform and Foundation v8 models (based on Trusted Firmware
PSCI implementation available at [1])
# Patches to enable idle states on Juno and Foundation models can be made
available, current dts are not in the mainline kernel
- TC2
- Compile tested on Samsung Exynos
Patch for Exynos CPUidle code depends on patch [2].
[1] https://github.com/ARM-software/arm-trusted-firmware
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/274179.html
Changes in v6:
- Added ARM64 CPU init idle to CPU operations
- Removed power-rank property; sorting depends on the cpu-idle-states phandle
list order now
- Added local-timer-stop flag
- Removed useless TC2 and Exynos DT idle state entry-method bindings
- Removed RTSM dts update
- Updated PSCI suspend parameter and DT bindings
- Updated PSCI parsing code
- Rebased against 3.16-rc6
Changes in v5:
- Added power-rank property to implement state sorting, following a number
of on/off list review comments
- Added timer retained bool property
- Ported TC2 big.LITTLE and Exynos drivers to DT initialization
- Renamed s/OF/dt/ throughout the patch
- Incorporated review comments and list discussions in the idle states
bindings documents
- Rebased against 3.16-rc2
Changes in v4:
- States sorting using exit-latency
- Added cosmetic review comments
- Dropped RFC
- Rebased against 3.15
Changes in v3:
- Streamlined the idle states bindings and added them to the series
http://www.spinics.net/lists/arm-kernel/msg316299.html
- Sorting states through min-residency+exit-latency
- Added debug strings formatting
- Reworded min-residency-us idle state property
- Removed power-domain properties from idle states waiting for code
examples requiring them to be defined
Changes in v2:
- Moved OF parsing code to drivers/cpuidle
- Improved states detection and sorting through linked list
- Split code in generic and ARM64 specific bits
- Moved idle enter function into ARM64 idle driver
- Refactored PSCI idle states register function
- Renamed suspend operations and moved detection to ARM64 idle driver
- Changed the way CPUIDLE_FLAG_TIMER_STOP is handled
- Simplified idle state nodes parsing since according to the latest
bindings idle state nodes are a flat list, not hierarchical anymore
- Used min-residency-us to sort the states, to be further discussed
Idle states on most ARM platforms can be characterized by a set of
parameters that are platform agnostic and describe the HW idle states
features. So far, CPU idle drivers for ARM platforms required the definition
of parameters through static tables, duplicating control data for different
platforms. Moreover, the lack of standardization on firmware interfaces
hampered any standardization effort, resulting in CPU idle drivers for ARM
platforms containing duplicated code and platform specific power down routines.
The introduction of the PSCI firmware interface, and more in general, well
defined suspend back-ends, allows the definition of generic idle states and
the respective kernel infrastructure to support them.
Building on top of DT idle states bindings, that standardize idle states
parameters and corresponding suspend back-ends, this patchset provides code
that parses DT idle states nodes and builds at run-time the control data
infrastructure required by the ARM CPU idle drivers.
Idle states define an entry method (eg PSCI), that requires the respective
ARM64 kernel back-end to be invoked to initialize idle states parameters, so
that when the idle driver executes the back-end specific entry method a table
look-up can be carried out to retrieve the corresponding idle state parameter.
On legacy ARM platforms, the DT idle states are just used to initialize
states data.
Lorenzo Pieralisi (7):
Documentation: arm: define DT idle states bindings
drivers: cpuidle: implement DT based idle states infrastructure
arm64: kernel: introduce cpu_init_idle CPU operation
arm64: add PSCI CPU_SUSPEND based cpu_suspend support
drivers: cpuidle: CPU idle ARM64 driver
drivers: cpuidle: initialize big.LITTLE driver through DT
drivers: cpuidle: initialize Exynos driver through DT
Documentation/devicetree/bindings/arm/cpus.txt | 8 +
.../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
Documentation/devicetree/bindings/arm/psci.txt | 14 +-
arch/arm/boot/dts/exynos4210.dtsi | 11 +
arch/arm/boot/dts/exynos5250.dtsi | 11 +
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 23 +
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/cpuidle.h | 13 +
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/cpuidle.c | 27 +
arch/arm64/kernel/psci.c | 89 +++
drivers/cpuidle/Kconfig | 13 +
drivers/cpuidle/Kconfig.arm | 2 +
drivers/cpuidle/Kconfig.arm64 | 14 +
drivers/cpuidle/Makefile | 5 +
drivers/cpuidle/cpuidle-arm64.c | 128 ++++
drivers/cpuidle/cpuidle-big_little.c | 43 +-
drivers/cpuidle/cpuidle-exynos.c | 37 +-
drivers/cpuidle/dt_idle_states.c | 138 +++++
drivers/cpuidle/dt_idle_states.h | 5 +
20 files changed, 1227 insertions(+), 35 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
create mode 100644 arch/arm64/include/asm/cpuidle.h
create mode 100644 arch/arm64/kernel/cpuidle.c
create mode 100644 drivers/cpuidle/Kconfig.arm64
create mode 100644 drivers/cpuidle/cpuidle-arm64.c
create mode 100644 drivers/cpuidle/dt_idle_states.c
create mode 100644 drivers/cpuidle/dt_idle_states.h
--
1.9.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 0/7] ARM generic idle states
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
This patch is v6 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266488.html
Patchset has been tested on:
- Juno ARM64 platform and Foundation v8 models (based on Trusted Firmware
PSCI implementation available at [1])
# Patches to enable idle states on Juno and Foundation models can be made
available, current dts are not in the mainline kernel
- TC2
- Compile tested on Samsung Exynos
Patch for Exynos CPUidle code depends on patch [2].
[1] https://github.com/ARM-software/arm-trusted-firmware
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/274179.html
Changes in v6:
- Added ARM64 CPU init idle to CPU operations
- Removed power-rank property; sorting depends on the cpu-idle-states phandle
list order now
- Added local-timer-stop flag
- Removed useless TC2 and Exynos DT idle state entry-method bindings
- Removed RTSM dts update
- Updated PSCI suspend parameter and DT bindings
- Updated PSCI parsing code
- Rebased against 3.16-rc6
Changes in v5:
- Added power-rank property to implement state sorting, following a number
of on/off list review comments
- Added timer retained bool property
- Ported TC2 big.LITTLE and Exynos drivers to DT initialization
- Renamed s/OF/dt/ throughout the patch
- Incorporated review comments and list discussions in the idle states
bindings documents
- Rebased against 3.16-rc2
Changes in v4:
- States sorting using exit-latency
- Added cosmetic review comments
- Dropped RFC
- Rebased against 3.15
Changes in v3:
- Streamlined the idle states bindings and added them to the series
http://www.spinics.net/lists/arm-kernel/msg316299.html
- Sorting states through min-residency+exit-latency
- Added debug strings formatting
- Reworded min-residency-us idle state property
- Removed power-domain properties from idle states waiting for code
examples requiring them to be defined
Changes in v2:
- Moved OF parsing code to drivers/cpuidle
- Improved states detection and sorting through linked list
- Split code in generic and ARM64 specific bits
- Moved idle enter function into ARM64 idle driver
- Refactored PSCI idle states register function
- Renamed suspend operations and moved detection to ARM64 idle driver
- Changed the way CPUIDLE_FLAG_TIMER_STOP is handled
- Simplified idle state nodes parsing since according to the latest
bindings idle state nodes are a flat list, not hierarchical anymore
- Used min-residency-us to sort the states, to be further discussed
Idle states on most ARM platforms can be characterized by a set of
parameters that are platform agnostic and describe the HW idle states
features. So far, CPU idle drivers for ARM platforms required the definition
of parameters through static tables, duplicating control data for different
platforms. Moreover, the lack of standardization on firmware interfaces
hampered any standardization effort, resulting in CPU idle drivers for ARM
platforms containing duplicated code and platform specific power down routines.
The introduction of the PSCI firmware interface, and more in general, well
defined suspend back-ends, allows the definition of generic idle states and
the respective kernel infrastructure to support them.
Building on top of DT idle states bindings, that standardize idle states
parameters and corresponding suspend back-ends, this patchset provides code
that parses DT idle states nodes and builds at run-time the control data
infrastructure required by the ARM CPU idle drivers.
Idle states define an entry method (eg PSCI), that requires the respective
ARM64 kernel back-end to be invoked to initialize idle states parameters, so
that when the idle driver executes the back-end specific entry method a table
look-up can be carried out to retrieve the corresponding idle state parameter.
On legacy ARM platforms, the DT idle states are just used to initialize
states data.
Lorenzo Pieralisi (7):
Documentation: arm: define DT idle states bindings
drivers: cpuidle: implement DT based idle states infrastructure
arm64: kernel: introduce cpu_init_idle CPU operation
arm64: add PSCI CPU_SUSPEND based cpu_suspend support
drivers: cpuidle: CPU idle ARM64 driver
drivers: cpuidle: initialize big.LITTLE driver through DT
drivers: cpuidle: initialize Exynos driver through DT
Documentation/devicetree/bindings/arm/cpus.txt | 8 +
.../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
Documentation/devicetree/bindings/arm/psci.txt | 14 +-
arch/arm/boot/dts/exynos4210.dtsi | 11 +
arch/arm/boot/dts/exynos5250.dtsi | 11 +
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 23 +
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/cpuidle.h | 13 +
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/cpuidle.c | 27 +
arch/arm64/kernel/psci.c | 89 +++
drivers/cpuidle/Kconfig | 13 +
drivers/cpuidle/Kconfig.arm | 2 +
drivers/cpuidle/Kconfig.arm64 | 14 +
drivers/cpuidle/Makefile | 5 +
drivers/cpuidle/cpuidle-arm64.c | 128 ++++
drivers/cpuidle/cpuidle-big_little.c | 43 +-
drivers/cpuidle/cpuidle-exynos.c | 37 +-
drivers/cpuidle/dt_idle_states.c | 138 +++++
drivers/cpuidle/dt_idle_states.h | 5 +
20 files changed, 1227 insertions(+), 35 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
create mode 100644 arch/arm64/include/asm/cpuidle.h
create mode 100644 arch/arm64/kernel/cpuidle.c
create mode 100644 drivers/cpuidle/Kconfig.arm64
create mode 100644 drivers/cpuidle/cpuidle-arm64.c
create mode 100644 drivers/cpuidle/dt_idle_states.c
create mode 100644 drivers/cpuidle/dt_idle_states.h
--
1.9.1
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel, linux-pm
Cc: devicetree, Lorenzo Pieralisi, Mark Rutland, Sudeep Holla,
Catalin Marinas, Charles Garcia Tobin, Nicolas Pitre,
Rob Herring, Grant Likely, Peter De Schrijver, Santosh Shilimkar,
Daniel Lezcano, Amit Kucheria, Vincent Guittot, Antti Miettinen,
Stephen Boyd, Kevin Hilman, Sebastian Capella, Tomasz Figa,
Mark Brown, Paul Walmsley, Chander Kashyap, Geoff
ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the state parameters in platform specific static tables
whose size grows as the number of platforms supported in the kernel increases
and hampers device drivers standardization.
Therefore, this patch aims at standardizing idle state device tree bindings
for ARM platforms. Bindings define idle state parameters inclusive of entry
methods and state latencies, to allow operating systems to retrieve the
configuration entries from the device tree and initialize the related power
management drivers, paving the way for common code in the kernel to deal with
idle states and removing the need for static data in current and previous
kernel versions.
ARM64 platforms require the DT to define an entry-method property
for idle states.
On system implementing PSCI as an enable-method to enter low-power
states the PSCI CPU suspend method requires the power_state parameter to
be passed to the PSCI CPU suspend function.
This parameter is specific to a power state and platform specific,
therefore must be provided by firmware to the OS in order to enable
proper call sequence.
Thus, this patch also adds a property in the PSCI bindings that
describes how the PSCI CPU suspend power_state parameter should be
defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 8 +
.../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
Documentation/devicetree/bindings/arm/psci.txt | 14 +-
3 files changed, 700 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1fe72a0..a44d4fd 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
Value type: <phandle>
Definition: Specifies the ACC[2] node associated with this CPU.
+ - cpu-idle-states
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition:
+ # List of phandles to idle state nodes supported
+ by this cpu [3].
Example 1 (dual-cluster big.LITTLE system 32-bit):
@@ -411,3 +417,5 @@ cpus {
--
[1] arm/msm/qcom,saw2.txt
[2] arm/msm/qcom,kpss-acc.txt
+[3] ARM Linux kernel documentation - idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
new file mode 100644
index 0000000..37375c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/idle-states.txt
@@ -0,0 +1,679 @@
+==========================================
+ARM idle states binding description
+==========================================
+
+==========================================
+1 - Introduction
+==========================================
+
+ARM systems contain HW capable of managing power consumption dynamically,
+where cores can be put in different low-power states (ranging from simple
+wfi to power gating) according to OS PM policies. The CPU states representing
+the range of dynamic idle states that a processor can enter at run-time, can be
+specified through device tree bindings representing the parameters required
+to enter/exit specific idle states on a given processor.
+
+According to the Server Base System Architecture document (SBSA, [3]), the
+power states an ARM CPU can be put into are identified by the following list:
+
+- Running
+- Idle_standby
+- Idle_retention
+- Sleep
+- Off
+
+The power states described in the SBSA document define the basic CPU states on
+top of which ARM platforms implement power management schemes that allow an OS
+PM implementation to put the processor in different idle states (which include
+states listed above; "off" state is not an idle state since it does not have
+wake-up capabilities, hence it is not considered in this document).
+
+Idle state parameters (eg entry latency) are platform specific and need to be
+characterized with bindings that provide the required information to OS PM
+code so that it can build the required tables and use them at runtime.
+
+The device tree binding definition for ARM idle states is the subject of this
+document.
+
+===========================================
+2 - idle-states definitions
+===========================================
+
+Idle states are characterized for a specific system through a set of
+timing and energy related properties, that underline the HW behaviour
+triggered upon idle states entry and exit.
+
+The following diagram depicts the CPU execution phases and related timing
+properties required to enter and exit an idle state:
+
+..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
+ | | | | |
+
+ |<------ entry ------->|
+ | latency |
+ |<- exit ->|
+ | latency |
+ |<-------- min-residency -------->|
+ |<------- wakeup-latency ------->|
+
+ Diagram 1: CPU idle state execution phases
+
+EXEC: Normal CPU execution.
+
+PREP: Preparation phase before committing the hardware to idle mode
+ like cache flushing. This is abortable on pending wake-up
+ event conditions. The abort latency is assumed to be negligible
+ (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
+ goes back to EXEC. This phase is optional. If not abortable,
+ this should be included in the ENTRY phase instead.
+
+ENTRY: The hardware is committed to idle mode. This period must run
+ to completion up to IDLE before anything else can happen.
+
+IDLE: This is the actual energy-saving idle period. This may last
+ between 0 and infinite time, until a wake-up event occurs.
+
+EXIT: Period during which the CPU is brought back to operational
+ mode (EXEC).
+
+entry-latency: Worst case latency required to enter the idle state. The
+exit-latency may be guaranteed only after entry-latency has passed.
+
+min-residency: Minimum period, including preparation and entry, for a given
+idle state to be worthwhile energywise.
+
+wakeup-latency: Maximum delay between the signaling of a wake-up event and the
+CPU being able to execute normal code again. If not specified, this is assumed
+to be entry-latency + exit-latency.
+
+These timing parameters can be used by an OS in different circumstances.
+
+An idle CPU requires the expected min-residency time to select the most
+appropriate idle state based on the expected expiry time of the next IRQ
+(ie wake-up) that causes the CPU to return to the EXEC phase.
+
+An operating system scheduler may need to compute the shortest wake-up delay
+for CPUs in the system by detecting how long will it take to get a CPU out
+of an idle state, eg:
+
+wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
+
+In other words, the scheduler can make its scheduling decision by selecting
+(eg waking-up) the CPU with the shortest wake-up latency.
+The wake-up latency must take into account the entry latency if that period
+has not expired. The abortable nature of the PREP period can be ignored
+if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
+the worst case since it depends on the CPU operating conditions, ie caches
+state).
+
+An OS has to reliably probe the wakeup-latency since some devices can enforce
+latency constraints guarantees to work properly, so the OS has to detect the
+worst case wake-up latency it can incur if a CPU is allowed to enter an
+idle state, and possibly to prevent that to guarantee reliable device
+functioning.
+
+The min-residency time parameter deserves further explanation since it is
+expressed in time units but must factor in energy consumption coefficients.
+
+The energy consumption of a cpu when it enters a power state can be roughly
+characterised by the following graph:
+
+ |
+ |
+ |
+ e |
+ n | /---
+ e | /------
+ r | /------
+ g | /-----
+ y | /------
+ | ----
+ | /|
+ | / |
+ | / |
+ | / |
+ | / |
+ | / |
+ |/ |
+ -----|-------+----------------------------------
+ 0| 1 time(ms)
+
+ Graph 1: Energy vs time example
+
+The graph is split in two parts delimited by time 1ms on the X-axis.
+The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
+and denotes the energy costs incurred whilst entering and leaving the idle
+state.
+The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
+shallower slope and essentially represents the energy consumption of the idle
+state.
+
+min-residency is defined for a given idle state as the minimum expected
+residency time for a state (inclusive of preparation and entry) after
+which choosing that state become the most energy efficient option. A good
+way to visualise this, is by taking the same graph above and comparing some
+states energy consumptions plots.
+
+For sake of simplicity, let's consider a system with two idle states IDLE1,
+and IDLE2:
+
+ |
+ |
+ |
+ | /-- IDLE1
+ e | /---
+ n | /----
+ e | /---
+ r | /-----/--------- IDLE2
+ g | /-------/---------
+ y | ------------ /---|
+ | / /---- |
+ | / /--- |
+ | / /---- |
+ | / /--- |
+ | --- |
+ | / |
+ | / |
+ |/ | time
+ ---/----------------------------+------------------------
+ |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
+ |
+ IDLE2-min-residency
+
+ Graph 2: idle states min-residency example
+
+In graph 2 above, that takes into account idle states entry/exit energy
+costs, it is clear that if the idle state residency time (ie time till next
+wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
+choice energywise.
+
+This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
+than IDLE2.
+
+However, the lower power consumption (ie shallower energy curve slope) of idle
+state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
+efficient.
+
+The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
+shallower states in a system with multiple idle states) is defined
+IDLE2-min-residency and corresponds to the time when energy consumption of
+IDLE1 and IDLE2 states breaks even.
+
+The definitions provided in this section underpin the idle states
+properties specification that is the subject of the following sections.
+
+===========================================
+3 - idle-states node
+===========================================
+
+ARM processor idle states are defined within the idle-states node, which is
+a direct child of the cpus node [1] and provides a container where the
+processor idle states, defined as device tree nodes, are listed.
+
+- idle-states node
+
+ Usage: Optional - On ARM systems, it is a container of processor idle
+ states nodes. If the system does not provide CPU
+ power management capabilities or the processor just
+ supports idle_standby an idle-states node is not
+ required.
+
+ Description: idle-states node is a container node, where its
+ subnodes describe the CPU idle states.
+
+ Node name must be "idle-states".
+
+ The idle-states node's parent node must be the cpus node.
+
+ The idle-states node's child nodes can be:
+
+ - one or more state nodes
+
+ Any other configuration is considered invalid.
+
+ An idle-states node defines the following properties:
+
+ - entry-method
+ Value type: <stringlist>
+ Usage and definition depend on ARM architecture version.
+ # On ARM v8 64-bit this property is required and must
+ be one of:
+ - "psci" (see bindings in [2])
+ # On ARM 32-bit systems this property is optional
+
+The nodes describing the idle states (state) can only be defined within the
+idle-states node, any other configuration is considered invalid and therefore
+must be ignored.
+
+===========================================
+4 - state node
+===========================================
+
+A state node represents an idle state description and must be defined as
+follows:
+
+- state node
+
+ Description: must be child of the idle-states node
+
+ The state node name shall follow standard device tree naming
+ rules ([5], 2.2.1 "Node names"), in particular state nodes which
+ are siblings within a single common parent must be given a unique name.
+
+ The idle state entered by executing the wfi instruction (idle_standby
+ SBSA,[3][4]) is considered standard on all ARM platforms and therefore
+ must not be listed.
+
+ With the definitions provided above, the following list represents
+ the valid properties for a state node:
+
+ - compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must be "arm,idle-state".
+
+ - local-timer-stop
+ Usage: See definition
+ Value type: <none>
+ Definition: if present the CPU local timer control logic is
+ lost on state entry, otherwise it is retained.
+
+ - entry-latency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency in
+ microseconds required to enter the idle state.
+ The exit-latency-us duration may be guaranteed
+ only after entry-latency-us has passed.
+
+ - exit-latency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency
+ in microseconds required to exit the idle state.
+
+ - min-residency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing minimum residency duration
+ in microseconds, inclusive of preparation and
+ entry, for this idle state to be considered
+ worthwhile energy wise (refer to section 2 of
+ this document for a complete description).
+
+ - wakeup-latency-us:
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing maximum delay between the
+ signaling of a wake-up event and the CPU being
+ able to execute normal code again. If omitted,
+ this is assumed to be equal to:
+
+ entry-latency-us + exit-latency-us
+
+ It is important to supply this value on systems
+ where the duration of PREP phase (see diagram 1,
+ section 2) is non-neglibigle.
+ In such systems entry-latency-us + exit-latency-us
+ will exceed wakeup-latency-us by this duration.
+
+ In addition to the properties listed above, a state node may require
+ additional properties specifics to the entry-method defined in the
+ idle-states node, please refer to the entry-method bindings
+ documentation for properties definitions.
+
+===========================================
+4 - Examples
+===========================================
+
+Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU5: cpu@10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU6: cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU7: cpu@10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU8: cpu@100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU9: cpu@100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU10: cpu@100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU11: cpu@100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU12: cpu@100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU13: cpu@100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU14: cpu@100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU15: cpu@100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_RETENTION_0_0: cpu-retention-0-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <80>;
+ };
+
+ CLUSTER_RETENTION_0: cluster-retention-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <250>;
+ wakeup-latency-us = <130>;
+ };
+
+ CPU_SLEEP_0_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <250>;
+ exit-latency-us = <500>;
+ min-residency-us = <950>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1100>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+
+ CPU_RETENTION_1_0: cpu-retention-1-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <90>;
+ };
+
+ CLUSTER_RETENTION_1: cluster-retention-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <270>;
+ wakeup-latency-us = <100>;
+ };
+
+ CPU_SLEEP_1_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <70>;
+ exit-latency-us = <100>;
+ min-residency-us = <300>;
+ wakeup-latency-us = <150>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <500>;
+ exit-latency-us = <1200>;
+ min-residency-us = <3500>;
+ wakeup-latency-us = <1300>;
+ };
+ };
+
+};
+
+Example 2 (ARM 32-bit, 8-cpu system, two clusters):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x3>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ idle-states {
+ CPU_SLEEP_0_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <200>;
+ exit-latency-us = <100>;
+ min-residency-us = <400>;
+ wakeup-latency-us = <250>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <500>;
+ exit-latency-us = <1500>;
+ min-residency-us = <2500>;
+ wakeup-latency-us = <1700>;
+ };
+
+ CPU_SLEEP_1_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <500>;
+ min-residency-us = <900>;
+ wakeup-latency-us = <600>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <800>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6500>;
+ wakeup-latency-us = <2300>;
+ };
+ };
+
+};
+
+===========================================
+5 - References
+===========================================
+
+[1] ARM Linux Kernel documentation - CPUs bindings
+ Documentation/devicetree/bindings/arm/cpus.txt
+
+[2] ARM Linux Kernel documentation - PSCI bindings
+ Documentation/devicetree/bindings/arm/psci.txt
+
+[3] ARM Server Base System Architecture (SBSA)
+ http://infocenter.arm.com/help/index.jsp
+
+[4] ARM Architecture Reference Manuals
+ http://infocenter.arm.com/help/index.jsp
+
+[5] ePAPR standard
+ https://www.power.org/documentation/epapr-version-1-1/
diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
index b4a58f3..5aa40ed 100644
--- a/Documentation/devicetree/bindings/arm/psci.txt
+++ b/Documentation/devicetree/bindings/arm/psci.txt
@@ -50,6 +50,16 @@ Main node optional properties:
- migrate : Function ID for MIGRATE operation
+Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
+state nodes, as per bindings in [1]) must specify the following properties:
+
+- arm,psci-suspend-param
+ Usage: Required for state nodes[1] if the corresponding
+ idle-states node entry-method property is set
+ to "psci".
+ Value type: <u32>
+ Definition: power_state parameter to pass to the PSCI
+ suspend call.
Example:
@@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
migrate = <0x95c10003>;
};
-
Case 2: PSCI v0.2 only
psci {
@@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
...
};
+
+[1] Kernel documentation - ARM idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the state parameters in platform specific static tables
whose size grows as the number of platforms supported in the kernel increases
and hampers device drivers standardization.
Therefore, this patch aims at standardizing idle state device tree bindings
for ARM platforms. Bindings define idle state parameters inclusive of entry
methods and state latencies, to allow operating systems to retrieve the
configuration entries from the device tree and initialize the related power
management drivers, paving the way for common code in the kernel to deal with
idle states and removing the need for static data in current and previous
kernel versions.
ARM64 platforms require the DT to define an entry-method property
for idle states.
On system implementing PSCI as an enable-method to enter low-power
states the PSCI CPU suspend method requires the power_state parameter to
be passed to the PSCI CPU suspend function.
This parameter is specific to a power state and platform specific,
therefore must be provided by firmware to the OS in order to enable
proper call sequence.
Thus, this patch also adds a property in the PSCI bindings that
describes how the PSCI CPU suspend power_state parameter should be
defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 8 +
.../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
Documentation/devicetree/bindings/arm/psci.txt | 14 +-
3 files changed, 700 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 1fe72a0..a44d4fd 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
Value type: <phandle>
Definition: Specifies the ACC[2] node associated with this CPU.
+ - cpu-idle-states
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition:
+ # List of phandles to idle state nodes supported
+ by this cpu [3].
Example 1 (dual-cluster big.LITTLE system 32-bit):
@@ -411,3 +417,5 @@ cpus {
--
[1] arm/msm/qcom,saw2.txt
[2] arm/msm/qcom,kpss-acc.txt
+[3] ARM Linux kernel documentation - idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
new file mode 100644
index 0000000..37375c7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/idle-states.txt
@@ -0,0 +1,679 @@
+==========================================
+ARM idle states binding description
+==========================================
+
+==========================================
+1 - Introduction
+==========================================
+
+ARM systems contain HW capable of managing power consumption dynamically,
+where cores can be put in different low-power states (ranging from simple
+wfi to power gating) according to OS PM policies. The CPU states representing
+the range of dynamic idle states that a processor can enter at run-time, can be
+specified through device tree bindings representing the parameters required
+to enter/exit specific idle states on a given processor.
+
+According to the Server Base System Architecture document (SBSA, [3]), the
+power states an ARM CPU can be put into are identified by the following list:
+
+- Running
+- Idle_standby
+- Idle_retention
+- Sleep
+- Off
+
+The power states described in the SBSA document define the basic CPU states on
+top of which ARM platforms implement power management schemes that allow an OS
+PM implementation to put the processor in different idle states (which include
+states listed above; "off" state is not an idle state since it does not have
+wake-up capabilities, hence it is not considered in this document).
+
+Idle state parameters (eg entry latency) are platform specific and need to be
+characterized with bindings that provide the required information to OS PM
+code so that it can build the required tables and use them at runtime.
+
+The device tree binding definition for ARM idle states is the subject of this
+document.
+
+===========================================
+2 - idle-states definitions
+===========================================
+
+Idle states are characterized for a specific system through a set of
+timing and energy related properties, that underline the HW behaviour
+triggered upon idle states entry and exit.
+
+The following diagram depicts the CPU execution phases and related timing
+properties required to enter and exit an idle state:
+
+..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
+ | | | | |
+
+ |<------ entry ------->|
+ | latency |
+ |<- exit ->|
+ | latency |
+ |<-------- min-residency -------->|
+ |<------- wakeup-latency ------->|
+
+ Diagram 1: CPU idle state execution phases
+
+EXEC: Normal CPU execution.
+
+PREP: Preparation phase before committing the hardware to idle mode
+ like cache flushing. This is abortable on pending wake-up
+ event conditions. The abort latency is assumed to be negligible
+ (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
+ goes back to EXEC. This phase is optional. If not abortable,
+ this should be included in the ENTRY phase instead.
+
+ENTRY: The hardware is committed to idle mode. This period must run
+ to completion up to IDLE before anything else can happen.
+
+IDLE: This is the actual energy-saving idle period. This may last
+ between 0 and infinite time, until a wake-up event occurs.
+
+EXIT: Period during which the CPU is brought back to operational
+ mode (EXEC).
+
+entry-latency: Worst case latency required to enter the idle state. The
+exit-latency may be guaranteed only after entry-latency has passed.
+
+min-residency: Minimum period, including preparation and entry, for a given
+idle state to be worthwhile energywise.
+
+wakeup-latency: Maximum delay between the signaling of a wake-up event and the
+CPU being able to execute normal code again. If not specified, this is assumed
+to be entry-latency + exit-latency.
+
+These timing parameters can be used by an OS in different circumstances.
+
+An idle CPU requires the expected min-residency time to select the most
+appropriate idle state based on the expected expiry time of the next IRQ
+(ie wake-up) that causes the CPU to return to the EXEC phase.
+
+An operating system scheduler may need to compute the shortest wake-up delay
+for CPUs in the system by detecting how long will it take to get a CPU out
+of an idle state, eg:
+
+wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
+
+In other words, the scheduler can make its scheduling decision by selecting
+(eg waking-up) the CPU with the shortest wake-up latency.
+The wake-up latency must take into account the entry latency if that period
+has not expired. The abortable nature of the PREP period can be ignored
+if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
+the worst case since it depends on the CPU operating conditions, ie caches
+state).
+
+An OS has to reliably probe the wakeup-latency since some devices can enforce
+latency constraints guarantees to work properly, so the OS has to detect the
+worst case wake-up latency it can incur if a CPU is allowed to enter an
+idle state, and possibly to prevent that to guarantee reliable device
+functioning.
+
+The min-residency time parameter deserves further explanation since it is
+expressed in time units but must factor in energy consumption coefficients.
+
+The energy consumption of a cpu when it enters a power state can be roughly
+characterised by the following graph:
+
+ |
+ |
+ |
+ e |
+ n | /---
+ e | /------
+ r | /------
+ g | /-----
+ y | /------
+ | ----
+ | /|
+ | / |
+ | / |
+ | / |
+ | / |
+ | / |
+ |/ |
+ -----|-------+----------------------------------
+ 0| 1 time(ms)
+
+ Graph 1: Energy vs time example
+
+The graph is split in two parts delimited by time 1ms on the X-axis.
+The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
+and denotes the energy costs incurred whilst entering and leaving the idle
+state.
+The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
+shallower slope and essentially represents the energy consumption of the idle
+state.
+
+min-residency is defined for a given idle state as the minimum expected
+residency time for a state (inclusive of preparation and entry) after
+which choosing that state become the most energy efficient option. A good
+way to visualise this, is by taking the same graph above and comparing some
+states energy consumptions plots.
+
+For sake of simplicity, let's consider a system with two idle states IDLE1,
+and IDLE2:
+
+ |
+ |
+ |
+ | /-- IDLE1
+ e | /---
+ n | /----
+ e | /---
+ r | /-----/--------- IDLE2
+ g | /-------/---------
+ y | ------------ /---|
+ | / /---- |
+ | / /--- |
+ | / /---- |
+ | / /--- |
+ | --- |
+ | / |
+ | / |
+ |/ | time
+ ---/----------------------------+------------------------
+ |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
+ |
+ IDLE2-min-residency
+
+ Graph 2: idle states min-residency example
+
+In graph 2 above, that takes into account idle states entry/exit energy
+costs, it is clear that if the idle state residency time (ie time till next
+wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
+choice energywise.
+
+This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
+than IDLE2.
+
+However, the lower power consumption (ie shallower energy curve slope) of idle
+state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
+efficient.
+
+The time@which IDLE2 becomes more energy efficient than IDLE1 (and other
+shallower states in a system with multiple idle states) is defined
+IDLE2-min-residency and corresponds to the time when energy consumption of
+IDLE1 and IDLE2 states breaks even.
+
+The definitions provided in this section underpin the idle states
+properties specification that is the subject of the following sections.
+
+===========================================
+3 - idle-states node
+===========================================
+
+ARM processor idle states are defined within the idle-states node, which is
+a direct child of the cpus node [1] and provides a container where the
+processor idle states, defined as device tree nodes, are listed.
+
+- idle-states node
+
+ Usage: Optional - On ARM systems, it is a container of processor idle
+ states nodes. If the system does not provide CPU
+ power management capabilities or the processor just
+ supports idle_standby an idle-states node is not
+ required.
+
+ Description: idle-states node is a container node, where its
+ subnodes describe the CPU idle states.
+
+ Node name must be "idle-states".
+
+ The idle-states node's parent node must be the cpus node.
+
+ The idle-states node's child nodes can be:
+
+ - one or more state nodes
+
+ Any other configuration is considered invalid.
+
+ An idle-states node defines the following properties:
+
+ - entry-method
+ Value type: <stringlist>
+ Usage and definition depend on ARM architecture version.
+ # On ARM v8 64-bit this property is required and must
+ be one of:
+ - "psci" (see bindings in [2])
+ # On ARM 32-bit systems this property is optional
+
+The nodes describing the idle states (state) can only be defined within the
+idle-states node, any other configuration is considered invalid and therefore
+must be ignored.
+
+===========================================
+4 - state node
+===========================================
+
+A state node represents an idle state description and must be defined as
+follows:
+
+- state node
+
+ Description: must be child of the idle-states node
+
+ The state node name shall follow standard device tree naming
+ rules ([5], 2.2.1 "Node names"), in particular state nodes which
+ are siblings within a single common parent must be given a unique name.
+
+ The idle state entered by executing the wfi instruction (idle_standby
+ SBSA,[3][4]) is considered standard on all ARM platforms and therefore
+ must not be listed.
+
+ With the definitions provided above, the following list represents
+ the valid properties for a state node:
+
+ - compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must be "arm,idle-state".
+
+ - local-timer-stop
+ Usage: See definition
+ Value type: <none>
+ Definition: if present the CPU local timer control logic is
+ lost on state entry, otherwise it is retained.
+
+ - entry-latency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency in
+ microseconds required to enter the idle state.
+ The exit-latency-us duration may be guaranteed
+ only after entry-latency-us has passed.
+
+ - exit-latency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency
+ in microseconds required to exit the idle state.
+
+ - min-residency-us
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing minimum residency duration
+ in microseconds, inclusive of preparation and
+ entry, for this idle state to be considered
+ worthwhile energy wise (refer to section 2 of
+ this document for a complete description).
+
+ - wakeup-latency-us:
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing maximum delay between the
+ signaling of a wake-up event and the CPU being
+ able to execute normal code again. If omitted,
+ this is assumed to be equal to:
+
+ entry-latency-us + exit-latency-us
+
+ It is important to supply this value on systems
+ where the duration of PREP phase (see diagram 1,
+ section 2) is non-neglibigle.
+ In such systems entry-latency-us + exit-latency-us
+ will exceed wakeup-latency-us by this duration.
+
+ In addition to the properties listed above, a state node may require
+ additional properties specifics to the entry-method defined in the
+ idle-states node, please refer to the entry-method bindings
+ documentation for properties definitions.
+
+===========================================
+4 - Examples
+===========================================
+
+Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU2: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU3: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU4: cpu at 10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU5: cpu at 10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU6: cpu at 10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU7: cpu at 10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU8: cpu at 100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x0>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU9: cpu at 100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x1>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU10: cpu at 100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU11: cpu at 100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU12: cpu at 100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU13: cpu at 100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU14: cpu at 100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU15: cpu at 100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_RETENTION_0_0: cpu-retention-0-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <80>;
+ };
+
+ CLUSTER_RETENTION_0: cluster-retention-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <250>;
+ wakeup-latency-us = <130>;
+ };
+
+ CPU_SLEEP_0_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <250>;
+ exit-latency-us = <500>;
+ min-residency-us = <950>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <600>;
+ exit-latency-us = <1100>;
+ min-residency-us = <2700>;
+ wakeup-latency-us = <1500>;
+ };
+
+ CPU_RETENTION_1_0: cpu-retention-1-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <20>;
+ exit-latency-us = <40>;
+ min-residency-us = <90>;
+ };
+
+ CLUSTER_RETENTION_1: cluster-retention-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <50>;
+ exit-latency-us = <100>;
+ min-residency-us = <270>;
+ wakeup-latency-us = <100>;
+ };
+
+ CPU_SLEEP_1_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <70>;
+ exit-latency-us = <100>;
+ min-residency-us = <300>;
+ wakeup-latency-us = <150>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x1010000>;
+ entry-latency-us = <500>;
+ exit-latency-us = <1200>;
+ min-residency-us = <3500>;
+ wakeup-latency-us = <1300>;
+ };
+ };
+
+};
+
+Example 2 (ARM 32-bit, 8-cpu system, two clusters):
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ CPU0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x3>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ };
+
+ CPU4: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU5: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU6: cpu at 102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ CPU7: cpu at 103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ };
+
+ idle-states {
+ CPU_SLEEP_0_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <200>;
+ exit-latency-us = <100>;
+ min-residency-us = <400>;
+ wakeup-latency-us = <250>;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <500>;
+ exit-latency-us = <1500>;
+ min-residency-us = <2500>;
+ wakeup-latency-us = <1700>;
+ };
+
+ CPU_SLEEP_1_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <500>;
+ min-residency-us = <900>;
+ wakeup-latency-us = <600>;
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <800>;
+ exit-latency-us = <2000>;
+ min-residency-us = <6500>;
+ wakeup-latency-us = <2300>;
+ };
+ };
+
+};
+
+===========================================
+5 - References
+===========================================
+
+[1] ARM Linux Kernel documentation - CPUs bindings
+ Documentation/devicetree/bindings/arm/cpus.txt
+
+[2] ARM Linux Kernel documentation - PSCI bindings
+ Documentation/devicetree/bindings/arm/psci.txt
+
+[3] ARM Server Base System Architecture (SBSA)
+ http://infocenter.arm.com/help/index.jsp
+
+[4] ARM Architecture Reference Manuals
+ http://infocenter.arm.com/help/index.jsp
+
+[5] ePAPR standard
+ https://www.power.org/documentation/epapr-version-1-1/
diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
index b4a58f3..5aa40ed 100644
--- a/Documentation/devicetree/bindings/arm/psci.txt
+++ b/Documentation/devicetree/bindings/arm/psci.txt
@@ -50,6 +50,16 @@ Main node optional properties:
- migrate : Function ID for MIGRATE operation
+Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
+state nodes, as per bindings in [1]) must specify the following properties:
+
+- arm,psci-suspend-param
+ Usage: Required for state nodes[1] if the corresponding
+ idle-states node entry-method property is set
+ to "psci".
+ Value type: <u32>
+ Definition: power_state parameter to pass to the PSCI
+ suspend call.
Example:
@@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
migrate = <0x95c10003>;
};
-
Case 2: PSCI v0.2 only
psci {
@@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
...
};
+
+[1] Kernel documentation - ARM idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel, linux-pm
Cc: devicetree, Lorenzo Pieralisi, Mark Rutland, Sudeep Holla,
Catalin Marinas, Charles Garcia Tobin, Nicolas Pitre,
Rob Herring, Grant Likely, Peter De Schrijver, Santosh Shilimkar,
Daniel Lezcano, Amit Kucheria, Vincent Guittot, Antti Miettinen,
Stephen Boyd, Kevin Hilman, Sebastian Capella, Tomasz Figa,
Mark Brown, Paul Walmsley, Chander Kashyap, Geoff
On most common ARM systems, the low-power states a CPU can be put into are
not discoverable in HW and require device tree bindings to describe
power down suspend operations and idle states parameters.
In order to enable DT based idle states and configure idle drivers, this
patch implements the bulk infrastructure required to parse the device tree
idle states bindings and initialize the corresponding CPUidle driver states
data.
The parsing API accepts a start index that defines the first idle state
that should be initialized by the parsing code in order to give new and
legacy driver flexibility over which states should be parsed using the
new DT mechanism.
The idle states list is obtained from the first cpu in the driver
cpumask, which implicitly means the parsing code expects idle states
(and related list of phandles) to be the same for all CPUs in the
CPUidle driver mask. The kernel does not check this assumption, it must
be enforced by the bootloader to ensure correct system behaviour.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
drivers/cpuidle/Kconfig | 8 +++
drivers/cpuidle/Makefile | 1 +
drivers/cpuidle/dt_idle_states.c | 138 +++++++++++++++++++++++++++++++++++++++
drivers/cpuidle/dt_idle_states.h | 5 ++
4 files changed, 152 insertions(+)
create mode 100644 drivers/cpuidle/dt_idle_states.c
create mode 100644 drivers/cpuidle/dt_idle_states.h
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index 1b96fb9..414e7a96 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -30,6 +30,14 @@ config CPU_IDLE_GOV_MENU
bool "Menu governor (for tickless system)"
default y
+config DT_IDLE_STATES
+ bool "Idle states DT support"
+ depends on ARM || ARM64
+ help
+ Allows the CPU idle framework to initialize CPU idle drivers
+ state data by using DT provided nodes compliant with idle states
+ device tree bindings.
+
menu "ARM CPU Idle Drivers"
depends on ARM
source "drivers/cpuidle/Kconfig.arm"
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index d8bb1ff..b27a062 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -4,6 +4,7 @@
obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
+obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
##################################################################################
# ARM SoC drivers
diff --git a/drivers/cpuidle/dt_idle_states.c b/drivers/cpuidle/dt_idle_states.c
new file mode 100644
index 0000000..5413132
--- /dev/null
+++ b/drivers/cpuidle/dt_idle_states.c
@@ -0,0 +1,138 @@
+/*
+ * DT idle states parsing code.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "DT idle-states: " fmt
+
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+#include "dt_idle_states.h"
+
+static int init_state_node(struct cpuidle_state *idle_state,
+ struct device_node *state_node)
+{
+ int err;
+
+ err = of_property_read_u32(state_node, "wakeup-latency-us",
+ &idle_state->exit_latency);
+ if (err) {
+ u32 entry_latency, exit_latency;
+
+ err = of_property_read_u32(state_node, "entry-latency-us",
+ &entry_latency);
+ if (err) {
+ pr_debug(" * %s missing entry-latency-us property\n",
+ state_node->full_name);
+ return -EINVAL;
+ }
+
+ err = of_property_read_u32(state_node, "exit-latency-us",
+ &exit_latency);
+ if (err) {
+ pr_debug(" * %s missing exit-latency-us property\n",
+ state_node->full_name);
+ return -EINVAL;
+ }
+ /*
+ * If wakeup-latency-us is missing, default to entry+exit
+ * latencies as defined in idle states bindings
+ */
+ idle_state->exit_latency = entry_latency + exit_latency;
+ }
+
+ err = of_property_read_u32(state_node, "min-residency-us",
+ &idle_state->target_residency);
+ if (err) {
+ pr_debug(" * %s missing min-residency-us property\n",
+ state_node->full_name);
+ return -EINVAL;
+ }
+
+ idle_state->flags = CPUIDLE_FLAG_TIME_VALID;
+ if (of_property_read_bool(state_node, "local-timer-stop"))
+ idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP;
+ /*
+ * TODO:
+ * replace with kstrdup and pointer assignment when name
+ * and desc become string pointers
+ */
+ strncpy(idle_state->name, state_node->name, CPUIDLE_NAME_LEN - 1);
+ strncpy(idle_state->desc, state_node->name, CPUIDLE_DESC_LEN - 1);
+ return 0;
+}
+
+/**
+ * dt_init_idle_driver() - Parse the DT idle states and initialize the
+ * idle driver states array
+ *
+ * @drv: Pointer to CPU idle driver to be initialized
+ * @start_idx: First idle state index to be initialized
+ *
+ * On success the states array in the cpuidle driver contains
+ * initialized entries in the states array, starting from index start_idx.
+ *
+ * Return:
+ * 0 on success
+ * <0 on failure
+ */
+int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
+{
+ unsigned int i, state_idx = start_idx;
+ struct cpuidle_state *idle_state;
+ struct device_node *state_node, *cpu_node;
+
+
+ if (state_idx >= CPUIDLE_STATE_MAX)
+ return -EINVAL;
+ /*
+ * We get the idle states for the first logical cpu in the
+ * driver mask. The kernel does not check idle states on all
+ * cpus in the driver mask, they are assumed to be the same
+ * by default.
+ */
+ cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
+
+ for (i = 0; ; i++) {
+ int err;
+
+ state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+ if (!state_node)
+ break;
+
+ if (state_idx == CPUIDLE_STATE_MAX) {
+ pr_warn("State index reached static CPU idle driver states array size\n");
+ break;
+ }
+
+ idle_state = &drv->states[state_idx++];
+ err = init_state_node(idle_state, state_node);
+ if (err)
+ return err;
+ }
+
+ /*
+ * If no idle states are detected, return an error and let the idle
+ * driver initialization fail accordingly since initializing a driver
+ * with simple WFI as an idle state is equivalent to letting the
+ * kernel run the default idle loop.
+ */
+ if (!i)
+ return -ENODATA;
+
+ drv->state_count = state_idx;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dt_init_idle_driver);
diff --git a/drivers/cpuidle/dt_idle_states.h b/drivers/cpuidle/dt_idle_states.h
new file mode 100644
index 0000000..728c37c
--- /dev/null
+++ b/drivers/cpuidle/dt_idle_states.h
@@ -0,0 +1,5 @@
+#ifndef __DT_IDLE_STATES
+#define __DT_IDLE_STATES
+
+int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx);
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
On most common ARM systems, the low-power states a CPU can be put into are
not discoverable in HW and require device tree bindings to describe
power down suspend operations and idle states parameters.
In order to enable DT based idle states and configure idle drivers, this
patch implements the bulk infrastructure required to parse the device tree
idle states bindings and initialize the corresponding CPUidle driver states
data.
The parsing API accepts a start index that defines the first idle state
that should be initialized by the parsing code in order to give new and
legacy driver flexibility over which states should be parsed using the
new DT mechanism.
The idle states list is obtained from the first cpu in the driver
cpumask, which implicitly means the parsing code expects idle states
(and related list of phandles) to be the same for all CPUs in the
CPUidle driver mask. The kernel does not check this assumption, it must
be enforced by the bootloader to ensure correct system behaviour.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
drivers/cpuidle/Kconfig | 8 +++
drivers/cpuidle/Makefile | 1 +
drivers/cpuidle/dt_idle_states.c | 138 +++++++++++++++++++++++++++++++++++++++
drivers/cpuidle/dt_idle_states.h | 5 ++
4 files changed, 152 insertions(+)
create mode 100644 drivers/cpuidle/dt_idle_states.c
create mode 100644 drivers/cpuidle/dt_idle_states.h
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index 1b96fb9..414e7a96 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -30,6 +30,14 @@ config CPU_IDLE_GOV_MENU
bool "Menu governor (for tickless system)"
default y
+config DT_IDLE_STATES
+ bool "Idle states DT support"
+ depends on ARM || ARM64
+ help
+ Allows the CPU idle framework to initialize CPU idle drivers
+ state data by using DT provided nodes compliant with idle states
+ device tree bindings.
+
menu "ARM CPU Idle Drivers"
depends on ARM
source "drivers/cpuidle/Kconfig.arm"
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index d8bb1ff..b27a062 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -4,6 +4,7 @@
obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
+obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
##################################################################################
# ARM SoC drivers
diff --git a/drivers/cpuidle/dt_idle_states.c b/drivers/cpuidle/dt_idle_states.c
new file mode 100644
index 0000000..5413132
--- /dev/null
+++ b/drivers/cpuidle/dt_idle_states.c
@@ -0,0 +1,138 @@
+/*
+ * DT idle states parsing code.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "DT idle-states: " fmt
+
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+
+#include "dt_idle_states.h"
+
+static int init_state_node(struct cpuidle_state *idle_state,
+ struct device_node *state_node)
+{
+ int err;
+
+ err = of_property_read_u32(state_node, "wakeup-latency-us",
+ &idle_state->exit_latency);
+ if (err) {
+ u32 entry_latency, exit_latency;
+
+ err = of_property_read_u32(state_node, "entry-latency-us",
+ &entry_latency);
+ if (err) {
+ pr_debug(" * %s missing entry-latency-us property\n",
+ state_node->full_name);
+ return -EINVAL;
+ }
+
+ err = of_property_read_u32(state_node, "exit-latency-us",
+ &exit_latency);
+ if (err) {
+ pr_debug(" * %s missing exit-latency-us property\n",
+ state_node->full_name);
+ return -EINVAL;
+ }
+ /*
+ * If wakeup-latency-us is missing, default to entry+exit
+ * latencies as defined in idle states bindings
+ */
+ idle_state->exit_latency = entry_latency + exit_latency;
+ }
+
+ err = of_property_read_u32(state_node, "min-residency-us",
+ &idle_state->target_residency);
+ if (err) {
+ pr_debug(" * %s missing min-residency-us property\n",
+ state_node->full_name);
+ return -EINVAL;
+ }
+
+ idle_state->flags = CPUIDLE_FLAG_TIME_VALID;
+ if (of_property_read_bool(state_node, "local-timer-stop"))
+ idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP;
+ /*
+ * TODO:
+ * replace with kstrdup and pointer assignment when name
+ * and desc become string pointers
+ */
+ strncpy(idle_state->name, state_node->name, CPUIDLE_NAME_LEN - 1);
+ strncpy(idle_state->desc, state_node->name, CPUIDLE_DESC_LEN - 1);
+ return 0;
+}
+
+/**
+ * dt_init_idle_driver() - Parse the DT idle states and initialize the
+ * idle driver states array
+ *
+ * @drv: Pointer to CPU idle driver to be initialized
+ * @start_idx: First idle state index to be initialized
+ *
+ * On success the states array in the cpuidle driver contains
+ * initialized entries in the states array, starting from index start_idx.
+ *
+ * Return:
+ * 0 on success
+ * <0 on failure
+ */
+int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
+{
+ unsigned int i, state_idx = start_idx;
+ struct cpuidle_state *idle_state;
+ struct device_node *state_node, *cpu_node;
+
+
+ if (state_idx >= CPUIDLE_STATE_MAX)
+ return -EINVAL;
+ /*
+ * We get the idle states for the first logical cpu in the
+ * driver mask. The kernel does not check idle states on all
+ * cpus in the driver mask, they are assumed to be the same
+ * by default.
+ */
+ cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
+
+ for (i = 0; ; i++) {
+ int err;
+
+ state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+ if (!state_node)
+ break;
+
+ if (state_idx == CPUIDLE_STATE_MAX) {
+ pr_warn("State index reached static CPU idle driver states array size\n");
+ break;
+ }
+
+ idle_state = &drv->states[state_idx++];
+ err = init_state_node(idle_state, state_node);
+ if (err)
+ return err;
+ }
+
+ /*
+ * If no idle states are detected, return an error and let the idle
+ * driver initialization fail accordingly since initializing a driver
+ * with simple WFI as an idle state is equivalent to letting the
+ * kernel run the default idle loop.
+ */
+ if (!i)
+ return -ENODATA;
+
+ drv->state_count = state_idx;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dt_init_idle_driver);
diff --git a/drivers/cpuidle/dt_idle_states.h b/drivers/cpuidle/dt_idle_states.h
new file mode 100644
index 0000000..728c37c
--- /dev/null
+++ b/drivers/cpuidle/dt_idle_states.h
@@ -0,0 +1,5 @@
+#ifndef __DT_IDLE_STATES
+#define __DT_IDLE_STATES
+
+int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx);
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 3/7] arm64: kernel: introduce cpu_init_idle CPU operation
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel, linux-pm
Cc: devicetree, Lorenzo Pieralisi, Mark Rutland, Sudeep Holla,
Catalin Marinas, Charles Garcia Tobin, Nicolas Pitre,
Rob Herring, Grant Likely, Peter De Schrijver, Santosh Shilimkar,
Daniel Lezcano, Amit Kucheria, Vincent Guittot, Antti Miettinen,
Stephen Boyd, Kevin Hilman, Sebastian Capella, Tomasz Figa,
Mark Brown, Paul Walmsley, Chander Kashyap, Geoff
The CPUidle subsystem on ARM64 machines requires the idle states
implementation back-end to initialize idle states parameter upon
boot. This patch adds a hook in the CPU operations structure that
should be initialized by the CPU operations back-end in order to
provide a function that initializes cpu idle states.
This patch also adds the infrastructure to arm64 kernel required
to export the CPU operations based initialization interface, so
that drivers (ie CPUidle) can use it when they are initialized
at probe time.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/cpuidle.h | 13 +++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/cpuidle.c | 27 +++++++++++++++++++++++++++
4 files changed, 42 insertions(+)
create mode 100644 arch/arm64/include/asm/cpuidle.h
create mode 100644 arch/arm64/kernel/cpuidle.c
diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index d7b4b38..c156498 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -47,6 +47,7 @@ struct device_node;
struct cpu_operations {
const char *name;
int (*cpu_init)(struct device_node *, unsigned int);
+ int (*cpu_init_idle)(struct device_node *, unsigned int);
int (*cpu_prepare)(unsigned int);
int (*cpu_boot)(unsigned int);
void (*cpu_postboot)(void);
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
new file mode 100644
index 0000000..b52a993
--- /dev/null
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_CPUIDLE_H
+#define __ASM_CPUIDLE_H
+
+#ifdef CONFIG_CPU_IDLE
+extern int cpu_init_idle(unsigned int cpu);
+#else
+static inline int cpu_init_idle(unsigned int cpu)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index cdaedad..7b0c068 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -26,6 +26,7 @@ arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o
+arm64-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
arm64-obj-$(CONFIG_KGDB) += kgdb.o
arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o
diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
new file mode 100644
index 0000000..46eb3ea
--- /dev/null
+++ b/arch/arm64/kernel/cpuidle.c
@@ -0,0 +1,27 @@
+/*
+ * ARM64 CPU idle arch support
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <asm/cpu_ops.h>
+
+int cpu_init_idle(unsigned int cpu)
+{
+ struct device_node *cpu_node = of_cpu_device_node_get(cpu);
+
+ if (!cpu_node)
+ return -ENODEV;
+
+ if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_init_idle)
+ return cpu_ops[cpu]->cpu_init_idle(cpu_node, cpu);
+
+ return -EOPNOTSUPP;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 3/7] arm64: kernel: introduce cpu_init_idle CPU operation
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
The CPUidle subsystem on ARM64 machines requires the idle states
implementation back-end to initialize idle states parameter upon
boot. This patch adds a hook in the CPU operations structure that
should be initialized by the CPU operations back-end in order to
provide a function that initializes cpu idle states.
This patch also adds the infrastructure to arm64 kernel required
to export the CPU operations based initialization interface, so
that drivers (ie CPUidle) can use it when they are initialized
at probe time.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm64/include/asm/cpu_ops.h | 1 +
arch/arm64/include/asm/cpuidle.h | 13 +++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/cpuidle.c | 27 +++++++++++++++++++++++++++
4 files changed, 42 insertions(+)
create mode 100644 arch/arm64/include/asm/cpuidle.h
create mode 100644 arch/arm64/kernel/cpuidle.c
diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
index d7b4b38..c156498 100644
--- a/arch/arm64/include/asm/cpu_ops.h
+++ b/arch/arm64/include/asm/cpu_ops.h
@@ -47,6 +47,7 @@ struct device_node;
struct cpu_operations {
const char *name;
int (*cpu_init)(struct device_node *, unsigned int);
+ int (*cpu_init_idle)(struct device_node *, unsigned int);
int (*cpu_prepare)(unsigned int);
int (*cpu_boot)(unsigned int);
void (*cpu_postboot)(void);
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
new file mode 100644
index 0000000..b52a993
--- /dev/null
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_CPUIDLE_H
+#define __ASM_CPUIDLE_H
+
+#ifdef CONFIG_CPU_IDLE
+extern int cpu_init_idle(unsigned int cpu);
+#else
+static inline int cpu_init_idle(unsigned int cpu)
+{
+ return -EOPNOTSUPP;
+}
+#endif
+
+#endif
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index cdaedad..7b0c068 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -26,6 +26,7 @@ arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
arm64-obj-$(CONFIG_ARM64_CPU_SUSPEND) += sleep.o suspend.o
+arm64-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
arm64-obj-$(CONFIG_KGDB) += kgdb.o
arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o
diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
new file mode 100644
index 0000000..46eb3ea
--- /dev/null
+++ b/arch/arm64/kernel/cpuidle.c
@@ -0,0 +1,27 @@
+/*
+ * ARM64 CPU idle arch support
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <asm/cpu_ops.h>
+
+int cpu_init_idle(unsigned int cpu)
+{
+ struct device_node *cpu_node = of_cpu_device_node_get(cpu);
+
+ if (!cpu_node)
+ return -ENODEV;
+
+ if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_init_idle)
+ return cpu_ops[cpu]->cpu_init_idle(cpu_node, cpu);
+
+ return -EOPNOTSUPP;
+}
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 4/7] arm64: add PSCI CPU_SUSPEND based cpu_suspend support
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-pm-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Lorenzo Pieralisi,
Mark Rutland, Sudeep Holla, Catalin Marinas,
Charles Garcia Tobin, Nicolas Pitre, Rob Herring, Grant Likely,
Peter De Schrijver, Santosh Shilimkar, Daniel Lezcano,
Amit Kucheria, Vincent Guittot, Antti Miettinen, Stephen Boyd,
Kevin Hilman, Sebastian Capella, Tomasz Figa, Mark Brown,
Paul Walmsley, Chander Kashyap, Geoff
This patch implements the cpu_suspend cpu operations method through
the PSCI CPU SUSPEND API. The PSCI implementation translates the idle state
index passed by the cpu_suspend core call into a valid PSCI state according to
the PSCI states initialized at boot through the cpu_init_idle() CPU
operations hook.
Entry point is set to cpu_resume physical address, that represents the
default kernel execution address following a CPU reset; for standby
states the entry point address is useless and will therefore be ignored
by the PSCI implementation.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
---
arch/arm64/kernel/psci.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index a623c44..bbdf41d 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -21,6 +21,7 @@
#include <linux/reboot.h>
#include <linux/pm.h>
#include <linux/delay.h>
+#include <linux/slab.h>
#include <uapi/linux/psci.h>
#include <asm/compiler.h>
@@ -28,6 +29,7 @@
#include <asm/errno.h>
#include <asm/psci.h>
#include <asm/smp_plat.h>
+#include <asm/suspend.h>
#include <asm/system_misc.h>
#define PSCI_POWER_STATE_TYPE_STANDBY 0
@@ -65,6 +67,8 @@ enum psci_function {
PSCI_FN_MAX,
};
+static DEFINE_PER_CPU_READ_MOSTLY(struct psci_power_state *, psci_power_state);
+
static u32 psci_function_id[PSCI_FN_MAX];
static int psci_to_linux_errno(int errno)
@@ -93,6 +97,18 @@ static u32 psci_power_state_pack(struct psci_power_state state)
& PSCI_0_2_POWER_STATE_AFFL_MASK);
}
+static void psci_power_state_unpack(u32 power_state,
+ struct psci_power_state *state)
+{
+ state->id = (power_state & PSCI_0_2_POWER_STATE_ID_MASK) >>
+ PSCI_0_2_POWER_STATE_ID_SHIFT;
+ state->type = (power_state & PSCI_0_2_POWER_STATE_TYPE_MASK) >>
+ PSCI_0_2_POWER_STATE_TYPE_SHIFT;
+ state->affinity_level =
+ (power_state & PSCI_0_2_POWER_STATE_AFFL_MASK) >>
+ PSCI_0_2_POWER_STATE_AFFL_SHIFT;
+}
+
/*
* The following two functions are invoked via the invoke_psci_fn pointer
* and will not be inlined, allowing us to piggyback on the AAPCS.
@@ -199,6 +215,61 @@ static int psci_migrate_info_type(void)
return err;
}
+static int cpu_psci_cpu_init_idle(struct device_node *cpu_node,
+ unsigned int cpu)
+{
+ int i, ret, count = 0;
+ struct psci_power_state *psci_states;
+ struct device_node *state_node;
+
+ /*
+ * If the PSCI cpu_suspend function hook has not been initialized
+ * idle states must not be enabled, so bail out
+ */
+ if (!psci_ops.cpu_suspend)
+ return -EOPNOTSUPP;
+
+ /* Count idle states */
+ while ((state_node = of_parse_phandle(cpu_node, "cpu-idle-states",
+ count)))
+ count++;
+
+ if (!count)
+ return -ENODEV;
+
+ psci_states = kcalloc(count, sizeof(*psci_states), GFP_KERNEL);
+ if (!psci_states) {
+ pr_warn("idle state psci_state allocation failed\n");
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < count; i++) {
+ u32 psci_power_state;
+
+ state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+
+ ret = of_property_read_u32(state_node,
+ "arm,psci-suspend-param",
+ &psci_power_state);
+ if (ret) {
+ pr_warn(" * %s missing arm,psci-suspend-param property\n",
+ state_node->full_name);
+ goto free_mem;
+ }
+
+ pr_debug("psci-power-state %#x index %d\n", psci_power_state,
+ i);
+ psci_power_state_unpack(psci_power_state, &psci_states[i]);
+ }
+ /* Idle states parsed correctly, initialize per-cpu pointer */
+ per_cpu(psci_power_state, cpu) = psci_states;
+ return 0;
+
+free_mem:
+ kfree(psci_states);
+ return ret;
+}
+
static int get_set_conduit_method(struct device_node *np)
{
const char *method;
@@ -436,8 +507,23 @@ static int cpu_psci_cpu_kill(unsigned int cpu)
#endif
#endif
+static int __maybe_unused cpu_psci_cpu_suspend(unsigned long index)
+{
+ struct psci_power_state *state = __get_cpu_var(psci_power_state);
+ /*
+ * idle state index 0 corresponds to wfi, should never be called
+ * from the cpu_suspend operations
+ */
+ if (WARN_ON_ONCE(!index))
+ return -EINVAL;
+
+ return psci_ops.cpu_suspend(state[index - 1],
+ virt_to_phys(cpu_resume));
+}
+
const struct cpu_operations cpu_psci_ops = {
.name = "psci",
+ .cpu_init_idle = cpu_psci_cpu_init_idle,
#ifdef CONFIG_SMP
.cpu_init = cpu_psci_cpu_init,
.cpu_prepare = cpu_psci_cpu_prepare,
@@ -448,5 +534,8 @@ const struct cpu_operations cpu_psci_ops = {
.cpu_kill = cpu_psci_cpu_kill,
#endif
#endif
+#ifdef CONFIG_ARM64_CPU_SUSPEND
+ .cpu_suspend = cpu_psci_cpu_suspend,
+#endif
};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 4/7] arm64: add PSCI CPU_SUSPEND based cpu_suspend support
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
This patch implements the cpu_suspend cpu operations method through
the PSCI CPU SUSPEND API. The PSCI implementation translates the idle state
index passed by the cpu_suspend core call into a valid PSCI state according to
the PSCI states initialized at boot through the cpu_init_idle() CPU
operations hook.
Entry point is set to cpu_resume physical address, that represents the
default kernel execution address following a CPU reset; for standby
states the entry point address is useless and will therefore be ignored
by the PSCI implementation.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm64/kernel/psci.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index a623c44..bbdf41d 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -21,6 +21,7 @@
#include <linux/reboot.h>
#include <linux/pm.h>
#include <linux/delay.h>
+#include <linux/slab.h>
#include <uapi/linux/psci.h>
#include <asm/compiler.h>
@@ -28,6 +29,7 @@
#include <asm/errno.h>
#include <asm/psci.h>
#include <asm/smp_plat.h>
+#include <asm/suspend.h>
#include <asm/system_misc.h>
#define PSCI_POWER_STATE_TYPE_STANDBY 0
@@ -65,6 +67,8 @@ enum psci_function {
PSCI_FN_MAX,
};
+static DEFINE_PER_CPU_READ_MOSTLY(struct psci_power_state *, psci_power_state);
+
static u32 psci_function_id[PSCI_FN_MAX];
static int psci_to_linux_errno(int errno)
@@ -93,6 +97,18 @@ static u32 psci_power_state_pack(struct psci_power_state state)
& PSCI_0_2_POWER_STATE_AFFL_MASK);
}
+static void psci_power_state_unpack(u32 power_state,
+ struct psci_power_state *state)
+{
+ state->id = (power_state & PSCI_0_2_POWER_STATE_ID_MASK) >>
+ PSCI_0_2_POWER_STATE_ID_SHIFT;
+ state->type = (power_state & PSCI_0_2_POWER_STATE_TYPE_MASK) >>
+ PSCI_0_2_POWER_STATE_TYPE_SHIFT;
+ state->affinity_level =
+ (power_state & PSCI_0_2_POWER_STATE_AFFL_MASK) >>
+ PSCI_0_2_POWER_STATE_AFFL_SHIFT;
+}
+
/*
* The following two functions are invoked via the invoke_psci_fn pointer
* and will not be inlined, allowing us to piggyback on the AAPCS.
@@ -199,6 +215,61 @@ static int psci_migrate_info_type(void)
return err;
}
+static int cpu_psci_cpu_init_idle(struct device_node *cpu_node,
+ unsigned int cpu)
+{
+ int i, ret, count = 0;
+ struct psci_power_state *psci_states;
+ struct device_node *state_node;
+
+ /*
+ * If the PSCI cpu_suspend function hook has not been initialized
+ * idle states must not be enabled, so bail out
+ */
+ if (!psci_ops.cpu_suspend)
+ return -EOPNOTSUPP;
+
+ /* Count idle states */
+ while ((state_node = of_parse_phandle(cpu_node, "cpu-idle-states",
+ count)))
+ count++;
+
+ if (!count)
+ return -ENODEV;
+
+ psci_states = kcalloc(count, sizeof(*psci_states), GFP_KERNEL);
+ if (!psci_states) {
+ pr_warn("idle state psci_state allocation failed\n");
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < count; i++) {
+ u32 psci_power_state;
+
+ state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
+
+ ret = of_property_read_u32(state_node,
+ "arm,psci-suspend-param",
+ &psci_power_state);
+ if (ret) {
+ pr_warn(" * %s missing arm,psci-suspend-param property\n",
+ state_node->full_name);
+ goto free_mem;
+ }
+
+ pr_debug("psci-power-state %#x index %d\n", psci_power_state,
+ i);
+ psci_power_state_unpack(psci_power_state, &psci_states[i]);
+ }
+ /* Idle states parsed correctly, initialize per-cpu pointer */
+ per_cpu(psci_power_state, cpu) = psci_states;
+ return 0;
+
+free_mem:
+ kfree(psci_states);
+ return ret;
+}
+
static int get_set_conduit_method(struct device_node *np)
{
const char *method;
@@ -436,8 +507,23 @@ static int cpu_psci_cpu_kill(unsigned int cpu)
#endif
#endif
+static int __maybe_unused cpu_psci_cpu_suspend(unsigned long index)
+{
+ struct psci_power_state *state = __get_cpu_var(psci_power_state);
+ /*
+ * idle state index 0 corresponds to wfi, should never be called
+ * from the cpu_suspend operations
+ */
+ if (WARN_ON_ONCE(!index))
+ return -EINVAL;
+
+ return psci_ops.cpu_suspend(state[index - 1],
+ virt_to_phys(cpu_resume));
+}
+
const struct cpu_operations cpu_psci_ops = {
.name = "psci",
+ .cpu_init_idle = cpu_psci_cpu_init_idle,
#ifdef CONFIG_SMP
.cpu_init = cpu_psci_cpu_init,
.cpu_prepare = cpu_psci_cpu_prepare,
@@ -448,5 +534,8 @@ const struct cpu_operations cpu_psci_ops = {
.cpu_kill = cpu_psci_cpu_kill,
#endif
#endif
+#ifdef CONFIG_ARM64_CPU_SUSPEND
+ .cpu_suspend = cpu_psci_cpu_suspend,
+#endif
};
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 5/7] drivers: cpuidle: CPU idle ARM64 driver
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel, linux-pm
Cc: devicetree, Lorenzo Pieralisi, Mark Rutland, Sudeep Holla,
Catalin Marinas, Charles Garcia Tobin, Nicolas Pitre,
Rob Herring, Grant Likely, Peter De Schrijver, Santosh Shilimkar,
Daniel Lezcano, Amit Kucheria, Vincent Guittot, Antti Miettinen,
Stephen Boyd, Kevin Hilman, Sebastian Capella, Tomasz Figa,
Mark Brown, Paul Walmsley, Chander Kashyap, Geoff
This patch implements a generic CPU idle driver for ARM64 machines.
It relies on the DT idle states infrastructure to initialize idle
states count and respective parameters. Current code assumes the driver
is managing idle states on all possible CPUs but can be easily
generalized to support heterogenous systems and build cpumasks at
runtime using MIDRs or DT cpu nodes compatible properties.
The driver relies on the arm64 CPU operations to call the idle
initialization hook used to parse and save suspend back-end specific
idle states information upon probing.
Idle state index 0 is always initialized as a simple wfi state, ie always
considered present and functional on all ARM64 platforms.
Idle state indices higher than 0 trigger idle state entry by calling
the cpu_suspend function, that does save the CPU context and executes
the CPU operations suspend back-end hook. cpu_suspend passes the idle
state index as a parameter so that the CPU operations suspend back-end
can retrieve the required idle state data by using the idle state
index to execute a look-up on its internal data structures.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
drivers/cpuidle/Kconfig | 5 ++
drivers/cpuidle/Kconfig.arm64 | 14 +++++
drivers/cpuidle/Makefile | 4 ++
drivers/cpuidle/cpuidle-arm64.c | 128 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 151 insertions(+)
create mode 100644 drivers/cpuidle/Kconfig.arm64
create mode 100644 drivers/cpuidle/cpuidle-arm64.c
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index 414e7a96..ebf0c2e 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -43,6 +43,11 @@ depends on ARM
source "drivers/cpuidle/Kconfig.arm"
endmenu
+menu "ARM64 CPU Idle Drivers"
+depends on ARM64
+source "drivers/cpuidle/Kconfig.arm64"
+endmenu
+
menu "MIPS CPU Idle Drivers"
depends on MIPS
source "drivers/cpuidle/Kconfig.mips"
diff --git a/drivers/cpuidle/Kconfig.arm64 b/drivers/cpuidle/Kconfig.arm64
new file mode 100644
index 0000000..d0a08ed
--- /dev/null
+++ b/drivers/cpuidle/Kconfig.arm64
@@ -0,0 +1,14 @@
+#
+# ARM64 CPU Idle drivers
+#
+
+config ARM64_CPUIDLE
+ bool "Generic ARM64 CPU idle Driver"
+ select ARM64_CPU_SUSPEND
+ select DT_IDLE_STATES
+ help
+ Select this to enable generic cpuidle driver for ARM64.
+ It provides a generic idle driver whose idle states are configured
+ at run-time through DT nodes. The CPUidle suspend backend is
+ initialized by calling the CPU operations init idle hook
+ provided by architecture code.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index b27a062..706cb7f 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -23,6 +23,10 @@ obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o
obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o
###############################################################################
+# ARM64 drivers
+obj-$(CONFIG_ARM64_CPUIDLE) += cpuidle-arm64.o
+
+###############################################################################
# POWERPC drivers
obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o
obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o
diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
new file mode 100644
index 0000000..1aeb426
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-arm64.c
@@ -0,0 +1,128 @@
+/*
+ * ARM64 generic CPU idle driver.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "CPUidle arm64: " fmt
+
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/cpu_pm.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include <asm/cpuidle.h>
+#include <asm/suspend.h>
+
+#include "dt_idle_states.h"
+
+/*
+ * arm_enter_idle_state - Programs CPU to enter the specified state
+ *
+ * dev: cpuidle device
+ * drv: cpuidle driver
+ * idx: state index
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified target state selected by the governor.
+ */
+static int arm_enter_idle_state(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int idx)
+{
+ int ret;
+
+ if (!idx) {
+ cpu_do_idle();
+ return idx;
+ }
+
+ ret = cpu_pm_enter();
+ if (!ret) {
+ /*
+ * Pass idle state index to cpu_suspend which in turn will
+ * call the CPU ops suspend protocol with idle index as a
+ * parameter.
+ */
+ ret = cpu_suspend(idx);
+
+ cpu_pm_exit();
+ }
+
+ return ret ? -1 : idx;
+}
+
+struct cpuidle_driver arm64_idle_driver = {
+ .name = "arm64_idle",
+ .owner = THIS_MODULE,
+ /*
+ * State at index 0 is standby wfi and considered standard
+ * on all ARM platforms. If in some platforms simple wfi
+ * can't be used as "state 0", DT bindings must be implemented
+ * to work around this issue and allow installing a special
+ * handler for idle state index 0.
+ */
+ .states[0] = {
+ .enter = arm_enter_idle_state,
+ .exit_latency = 1,
+ .target_residency = 1,
+ .power_usage = UINT_MAX,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = "WFI",
+ .desc = "ARM64 WFI",
+ }
+};
+
+/*
+ * arm64_idle_init
+ *
+ * Registers the arm64 specific cpuidle driver with the cpuidle
+ * framework. It relies on core code to parse the idle states
+ * and initialize them using driver data structures accordingly.
+ */
+static int __init arm64_idle_init(void)
+{
+ int i, ret;
+ struct cpuidle_driver *drv = &arm64_idle_driver;
+
+ drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+ if (!drv->cpumask)
+ return -ENOMEM;
+
+ cpumask_copy(drv->cpumask, cpu_possible_mask);
+ /*
+ * Start at index 1, request idle state nodes to be filled
+ */
+ ret = dt_init_idle_driver(drv, 1);
+ if (ret)
+ goto free_mem;
+ /*
+ * Call arch CPU operations in order to initialize
+ * idle states suspend back-end specific data
+ */
+ for_each_cpu(i, drv->cpumask) {
+ ret = cpu_init_idle(i);
+ if (ret)
+ goto free_mem;
+ }
+
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = arm_enter_idle_state;
+
+ ret = cpuidle_register(drv, NULL);
+ if (ret)
+ goto free_mem;
+
+ return 0;
+free_mem:
+ kfree(drv->cpumask);
+ return ret;
+}
+device_initcall(arm64_idle_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 5/7] drivers: cpuidle: CPU idle ARM64 driver
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
This patch implements a generic CPU idle driver for ARM64 machines.
It relies on the DT idle states infrastructure to initialize idle
states count and respective parameters. Current code assumes the driver
is managing idle states on all possible CPUs but can be easily
generalized to support heterogenous systems and build cpumasks at
runtime using MIDRs or DT cpu nodes compatible properties.
The driver relies on the arm64 CPU operations to call the idle
initialization hook used to parse and save suspend back-end specific
idle states information upon probing.
Idle state index 0 is always initialized as a simple wfi state, ie always
considered present and functional on all ARM64 platforms.
Idle state indices higher than 0 trigger idle state entry by calling
the cpu_suspend function, that does save the CPU context and executes
the CPU operations suspend back-end hook. cpu_suspend passes the idle
state index as a parameter so that the CPU operations suspend back-end
can retrieve the required idle state data by using the idle state
index to execute a look-up on its internal data structures.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
drivers/cpuidle/Kconfig | 5 ++
drivers/cpuidle/Kconfig.arm64 | 14 +++++
drivers/cpuidle/Makefile | 4 ++
drivers/cpuidle/cpuidle-arm64.c | 128 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 151 insertions(+)
create mode 100644 drivers/cpuidle/Kconfig.arm64
create mode 100644 drivers/cpuidle/cpuidle-arm64.c
diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
index 414e7a96..ebf0c2e 100644
--- a/drivers/cpuidle/Kconfig
+++ b/drivers/cpuidle/Kconfig
@@ -43,6 +43,11 @@ depends on ARM
source "drivers/cpuidle/Kconfig.arm"
endmenu
+menu "ARM64 CPU Idle Drivers"
+depends on ARM64
+source "drivers/cpuidle/Kconfig.arm64"
+endmenu
+
menu "MIPS CPU Idle Drivers"
depends on MIPS
source "drivers/cpuidle/Kconfig.mips"
diff --git a/drivers/cpuidle/Kconfig.arm64 b/drivers/cpuidle/Kconfig.arm64
new file mode 100644
index 0000000..d0a08ed
--- /dev/null
+++ b/drivers/cpuidle/Kconfig.arm64
@@ -0,0 +1,14 @@
+#
+# ARM64 CPU Idle drivers
+#
+
+config ARM64_CPUIDLE
+ bool "Generic ARM64 CPU idle Driver"
+ select ARM64_CPU_SUSPEND
+ select DT_IDLE_STATES
+ help
+ Select this to enable generic cpuidle driver for ARM64.
+ It provides a generic idle driver whose idle states are configured
+ at run-time through DT nodes. The CPUidle suspend backend is
+ initialized by calling the CPU operations init idle hook
+ provided by architecture code.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index b27a062..706cb7f 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -23,6 +23,10 @@ obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o
obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o
###############################################################################
+# ARM64 drivers
+obj-$(CONFIG_ARM64_CPUIDLE) += cpuidle-arm64.o
+
+###############################################################################
# POWERPC drivers
obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o
obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o
diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
new file mode 100644
index 0000000..1aeb426
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-arm64.c
@@ -0,0 +1,128 @@
+/*
+ * ARM64 generic CPU idle driver.
+ *
+ * Copyright (C) 2014 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define pr_fmt(fmt) "CPUidle arm64: " fmt
+
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/cpu_pm.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include <asm/cpuidle.h>
+#include <asm/suspend.h>
+
+#include "dt_idle_states.h"
+
+/*
+ * arm_enter_idle_state - Programs CPU to enter the specified state
+ *
+ * dev: cpuidle device
+ * drv: cpuidle driver
+ * idx: state index
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified target state selected by the governor.
+ */
+static int arm_enter_idle_state(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int idx)
+{
+ int ret;
+
+ if (!idx) {
+ cpu_do_idle();
+ return idx;
+ }
+
+ ret = cpu_pm_enter();
+ if (!ret) {
+ /*
+ * Pass idle state index to cpu_suspend which in turn will
+ * call the CPU ops suspend protocol with idle index as a
+ * parameter.
+ */
+ ret = cpu_suspend(idx);
+
+ cpu_pm_exit();
+ }
+
+ return ret ? -1 : idx;
+}
+
+struct cpuidle_driver arm64_idle_driver = {
+ .name = "arm64_idle",
+ .owner = THIS_MODULE,
+ /*
+ * State at index 0 is standby wfi and considered standard
+ * on all ARM platforms. If in some platforms simple wfi
+ * can't be used as "state 0", DT bindings must be implemented
+ * to work around this issue and allow installing a special
+ * handler for idle state index 0.
+ */
+ .states[0] = {
+ .enter = arm_enter_idle_state,
+ .exit_latency = 1,
+ .target_residency = 1,
+ .power_usage = UINT_MAX,
+ .flags = CPUIDLE_FLAG_TIME_VALID,
+ .name = "WFI",
+ .desc = "ARM64 WFI",
+ }
+};
+
+/*
+ * arm64_idle_init
+ *
+ * Registers the arm64 specific cpuidle driver with the cpuidle
+ * framework. It relies on core code to parse the idle states
+ * and initialize them using driver data structures accordingly.
+ */
+static int __init arm64_idle_init(void)
+{
+ int i, ret;
+ struct cpuidle_driver *drv = &arm64_idle_driver;
+
+ drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+ if (!drv->cpumask)
+ return -ENOMEM;
+
+ cpumask_copy(drv->cpumask, cpu_possible_mask);
+ /*
+ * Start at index 1, request idle state nodes to be filled
+ */
+ ret = dt_init_idle_driver(drv, 1);
+ if (ret)
+ goto free_mem;
+ /*
+ * Call arch CPU operations in order to initialize
+ * idle states suspend back-end specific data
+ */
+ for_each_cpu(i, drv->cpumask) {
+ ret = cpu_init_idle(i);
+ if (ret)
+ goto free_mem;
+ }
+
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = arm_enter_idle_state;
+
+ ret = cpuidle_register(drv, NULL);
+ if (ret)
+ goto free_mem;
+
+ return 0;
+free_mem:
+ kfree(drv->cpumask);
+ return ret;
+}
+device_initcall(arm64_idle_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 6/7] drivers: cpuidle: initialize big.LITTLE driver through DT
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel, linux-pm
Cc: devicetree, Lorenzo Pieralisi, Chander Kashyap, Mark Rutland,
Sudeep Holla, Catalin Marinas, Charles Garcia Tobin,
Nicolas Pitre, Rob Herring, Grant Likely, Peter De Schrijver,
Santosh Shilimkar, Daniel Lezcano, Amit Kucheria,
Vincent Guittot, Antti Miettinen, Stephen Boyd, Kevin Hilman,
Sebastian Capella, Tomasz Figa, Mark Brown, Paul Walmsley, Geoff
With the introduction of DT based idle states, CPUidle drivers for ARM
can now initialize idle states data through properties in the device tree.
This patch adds code to the big.LITTLE CPUidle driver to dynamically
initialize idle states data through the updated device tree source file.
Cc: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 23 ++++++++++++++++
drivers/cpuidle/Kconfig.arm | 1 +
drivers/cpuidle/cpuidle-big_little.c | 43 +++++++++++++++---------------
3 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index a25c262..d61da86 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -38,6 +38,7 @@
compatible = "arm,cortex-a15";
reg = <0>;
cci-control-port = <&cci_control1>;
+ cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
};
cpu1: cpu@1 {
@@ -45,6 +46,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
cci-control-port = <&cci_control1>;
+ cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
};
cpu2: cpu@2 {
@@ -52,6 +54,7 @@
compatible = "arm,cortex-a7";
reg = <0x100>;
cci-control-port = <&cci_control2>;
+ cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
};
cpu3: cpu@3 {
@@ -59,6 +62,7 @@
compatible = "arm,cortex-a7";
reg = <0x101>;
cci-control-port = <&cci_control2>;
+ cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
};
cpu4: cpu@4 {
@@ -66,6 +70,25 @@
compatible = "arm,cortex-a7";
reg = <0x102>;
cci-control-port = <&cci_control2>;
+ cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
+ };
+
+ idle-states {
+ CLUSTER_SLEEP_BIG: cluster-sleep-big {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <3500>;
+ };
+
+ CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <500>;
+ min-residency-us = <3000>;
+ };
};
};
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index b6d69e8..a9b089c 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -12,6 +12,7 @@ config ARM_BIG_LITTLE_CPUIDLE
depends on ARCH_VEXPRESS_TC2_PM
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
+ select DT_IDLE_STATES
help
Select this option to enable CPU idle driver for big.LITTLE based
ARM systems. Driver manages CPUs coordination through MCPM and
diff --git a/drivers/cpuidle/cpuidle-big_little.c b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..0a88480 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -24,6 +24,8 @@
#include <asm/smp_plat.h>
#include <asm/suspend.h>
+#include "dt_idle_states.h"
+
static int bl_enter_powerdown(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int idx);
@@ -61,32 +63,12 @@ static struct cpuidle_driver bl_idle_little_driver = {
.name = "little_idle",
.owner = THIS_MODULE,
.states[0] = ARM_CPUIDLE_WFI_STATE,
- .states[1] = {
- .enter = bl_enter_powerdown,
- .exit_latency = 700,
- .target_residency = 2500,
- .flags = CPUIDLE_FLAG_TIME_VALID |
- CPUIDLE_FLAG_TIMER_STOP,
- .name = "C1",
- .desc = "ARM little-cluster power down",
- },
- .state_count = 2,
};
static struct cpuidle_driver bl_idle_big_driver = {
.name = "big_idle",
.owner = THIS_MODULE,
.states[0] = ARM_CPUIDLE_WFI_STATE,
- .states[1] = {
- .enter = bl_enter_powerdown,
- .exit_latency = 500,
- .target_residency = 2000,
- .flags = CPUIDLE_FLAG_TIME_VALID |
- CPUIDLE_FLAG_TIMER_STOP,
- .name = "C1",
- .desc = "ARM big-cluster power down",
- },
- .state_count = 2,
};
/*
@@ -165,7 +147,8 @@ static int __init bl_idle_driver_init(struct cpuidle_driver *drv, int cpu_id)
static int __init bl_idle_init(void)
{
- int ret;
+ int ret, i;
+ struct cpuidle_driver *drv;
/*
* Initialize the driver just for a compliant set of machines
@@ -187,6 +170,24 @@ static int __init bl_idle_init(void)
if (ret)
goto out_uninit_little;
+ /* Start at index 1, index 0 standard WFI */
+ ret = dt_init_idle_driver(&bl_idle_big_driver, 1);
+ if (ret)
+ goto out_uninit_big;
+
+ /* Start at index 1, index 0 standard WFI */
+ ret = dt_init_idle_driver(&bl_idle_little_driver, 1);
+ if (ret)
+ goto out_uninit_big;
+
+ drv = &bl_idle_big_driver;
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = bl_enter_powerdown;
+
+ drv = &bl_idle_little_driver;
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = bl_enter_powerdown;
+
ret = cpuidle_register(&bl_idle_little_driver, NULL);
if (ret)
goto out_uninit_big;
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 6/7] drivers: cpuidle: initialize big.LITTLE driver through DT
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
With the introduction of DT based idle states, CPUidle drivers for ARM
can now initialize idle states data through properties in the device tree.
This patch adds code to the big.LITTLE CPUidle driver to dynamically
initialize idle states data through the updated device tree source file.
Cc: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 23 ++++++++++++++++
drivers/cpuidle/Kconfig.arm | 1 +
drivers/cpuidle/cpuidle-big_little.c | 43 +++++++++++++++---------------
3 files changed, 46 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index a25c262..d61da86 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -38,6 +38,7 @@
compatible = "arm,cortex-a15";
reg = <0>;
cci-control-port = <&cci_control1>;
+ cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
};
cpu1: cpu at 1 {
@@ -45,6 +46,7 @@
compatible = "arm,cortex-a15";
reg = <1>;
cci-control-port = <&cci_control1>;
+ cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
};
cpu2: cpu at 2 {
@@ -52,6 +54,7 @@
compatible = "arm,cortex-a7";
reg = <0x100>;
cci-control-port = <&cci_control2>;
+ cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
};
cpu3: cpu at 3 {
@@ -59,6 +62,7 @@
compatible = "arm,cortex-a7";
reg = <0x101>;
cci-control-port = <&cci_control2>;
+ cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
};
cpu4: cpu at 4 {
@@ -66,6 +70,25 @@
compatible = "arm,cortex-a7";
reg = <0x102>;
cci-control-port = <&cci_control2>;
+ cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
+ };
+
+ idle-states {
+ CLUSTER_SLEEP_BIG: cluster-sleep-big {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <3500>;
+ };
+
+ CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <500>;
+ min-residency-us = <3000>;
+ };
};
};
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index b6d69e8..a9b089c 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -12,6 +12,7 @@ config ARM_BIG_LITTLE_CPUIDLE
depends on ARCH_VEXPRESS_TC2_PM
select ARM_CPU_SUSPEND
select CPU_IDLE_MULTIPLE_DRIVERS
+ select DT_IDLE_STATES
help
Select this option to enable CPU idle driver for big.LITTLE based
ARM systems. Driver manages CPUs coordination through MCPM and
diff --git a/drivers/cpuidle/cpuidle-big_little.c b/drivers/cpuidle/cpuidle-big_little.c
index b45fc62..0a88480 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -24,6 +24,8 @@
#include <asm/smp_plat.h>
#include <asm/suspend.h>
+#include "dt_idle_states.h"
+
static int bl_enter_powerdown(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int idx);
@@ -61,32 +63,12 @@ static struct cpuidle_driver bl_idle_little_driver = {
.name = "little_idle",
.owner = THIS_MODULE,
.states[0] = ARM_CPUIDLE_WFI_STATE,
- .states[1] = {
- .enter = bl_enter_powerdown,
- .exit_latency = 700,
- .target_residency = 2500,
- .flags = CPUIDLE_FLAG_TIME_VALID |
- CPUIDLE_FLAG_TIMER_STOP,
- .name = "C1",
- .desc = "ARM little-cluster power down",
- },
- .state_count = 2,
};
static struct cpuidle_driver bl_idle_big_driver = {
.name = "big_idle",
.owner = THIS_MODULE,
.states[0] = ARM_CPUIDLE_WFI_STATE,
- .states[1] = {
- .enter = bl_enter_powerdown,
- .exit_latency = 500,
- .target_residency = 2000,
- .flags = CPUIDLE_FLAG_TIME_VALID |
- CPUIDLE_FLAG_TIMER_STOP,
- .name = "C1",
- .desc = "ARM big-cluster power down",
- },
- .state_count = 2,
};
/*
@@ -165,7 +147,8 @@ static int __init bl_idle_driver_init(struct cpuidle_driver *drv, int cpu_id)
static int __init bl_idle_init(void)
{
- int ret;
+ int ret, i;
+ struct cpuidle_driver *drv;
/*
* Initialize the driver just for a compliant set of machines
@@ -187,6 +170,24 @@ static int __init bl_idle_init(void)
if (ret)
goto out_uninit_little;
+ /* Start at index 1, index 0 standard WFI */
+ ret = dt_init_idle_driver(&bl_idle_big_driver, 1);
+ if (ret)
+ goto out_uninit_big;
+
+ /* Start at index 1, index 0 standard WFI */
+ ret = dt_init_idle_driver(&bl_idle_little_driver, 1);
+ if (ret)
+ goto out_uninit_big;
+
+ drv = &bl_idle_big_driver;
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = bl_enter_powerdown;
+
+ drv = &bl_idle_little_driver;
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = bl_enter_powerdown;
+
ret = cpuidle_register(&bl_idle_little_driver, NULL);
if (ret)
goto out_uninit_big;
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 7/7] drivers: cpuidle: initialize Exynos driver through DT
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel, linux-pm
Cc: devicetree, Lorenzo Pieralisi, Chander Kashyap, Kukjin Kim,
Tomasz Figa, Mark Rutland, Sudeep Holla, Catalin Marinas,
Charles Garcia Tobin, Nicolas Pitre, Rob Herring, Grant Likely,
Peter De Schrijver, Santosh Shilimkar, Daniel Lezcano,
Amit Kucheria, Vincent Guittot, Antti Miettinen, Stephen Boyd,
Kevin Hilman, Sebastian Capella, Mark Brown, Paul
With the introduction of DT based idle states, CPUidle drivers for
ARM can now initialize idle states data through properties in the device
tree.
This patch adds code to the Exynos CPUidle driver to dynamically
initialize idle states data through the updated device tree source
files.
Cc: Chander Kashyap <chander.kashyap@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 11 +++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 11 +++++++++++
drivers/cpuidle/Kconfig.arm | 1 +
drivers/cpuidle/cpuidle-exynos.c | 37 ++++++++++++++++++++++++-------------
4 files changed, 47 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index bc2b444..0270100 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -39,12 +39,23 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x900>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
};
cpu@901 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x901>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+
+ idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ entry-latency-us = <1000>;
+ exit-latency-us = <300>;
+ min-residency-us = <100000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..631906e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -63,12 +63,23 @@
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1700000000>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1700000000>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+
+ idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ entry-latency-us = <1000>;
+ exit-latency-us = <300>;
+ min-residency-us = <100000>;
+ };
};
};
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index a9b089c..d8a9cd2 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -60,5 +60,6 @@ config ARM_AT91_CPUIDLE
config ARM_EXYNOS_CPUIDLE
bool "Cpu Idle Driver for the Exynos processors"
depends on ARCH_EXYNOS
+ select DT_IDLE_STATES
help
Select this to enable cpuidle for Exynos processors
diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c
index 7c01512..097c21d 100644
--- a/drivers/cpuidle/cpuidle-exynos.c
+++ b/drivers/cpuidle/cpuidle-exynos.c
@@ -13,11 +13,14 @@
#include <linux/export.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/cpuidle.h>
+#include "dt_idle_states.h"
+
static void (*exynos_enter_aftr)(void);
static int idle_finisher(unsigned long flags)
@@ -60,32 +63,40 @@ static struct cpuidle_driver exynos_idle_driver = {
.owner = THIS_MODULE,
.states = {
[0] = ARM_CPUIDLE_WFI_STATE,
- [1] = {
- .enter = exynos_enter_lowpower,
- .exit_latency = 300,
- .target_residency = 100000,
- .flags = CPUIDLE_FLAG_TIME_VALID,
- .name = "C1",
- .desc = "ARM power down",
- },
},
- .state_count = 2,
- .safe_state_index = 0,
};
static int exynos_cpuidle_probe(struct platform_device *pdev)
{
- int ret;
+ int ret, i;
+ struct cpuidle_driver *drv = &exynos_idle_driver;
exynos_enter_aftr = (void *)(pdev->dev.platform_data);
- ret = cpuidle_register(&exynos_idle_driver, NULL);
+ drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+ if (!drv->cpumask)
+ return -ENOMEM;
+
+ /* Start at index 1, index 0 standard WFI */
+ ret = dt_init_idle_driver(drv, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to initialize idle states\n");
+ goto free_mem;
+ }
+
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = exynos_enter_lowpower;
+
+ ret = cpuidle_register(drv, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
- return ret;
+ goto free_mem;
}
return 0;
+free_mem:
+ kfree(drv->cpumask);
+ return ret;
}
static struct platform_driver exynos_cpuidle_driver = {
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* [PATCH v6 7/7] drivers: cpuidle: initialize Exynos driver through DT
@ 2014-07-21 16:06 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-21 16:06 UTC (permalink / raw)
To: linux-arm-kernel
With the introduction of DT based idle states, CPUidle drivers for
ARM can now initialize idle states data through properties in the device
tree.
This patch adds code to the Exynos CPUidle driver to dynamically
initialize idle states data through the updated device tree source
files.
Cc: Chander Kashyap <chander.kashyap@linaro.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 11 +++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 11 +++++++++++
drivers/cpuidle/Kconfig.arm | 1 +
drivers/cpuidle/cpuidle-exynos.c | 37 ++++++++++++++++++++++++-------------
4 files changed, 47 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index bc2b444..0270100 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -39,12 +39,23 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x900>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
};
cpu at 901 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x901>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+
+ idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ entry-latency-us = <1000>;
+ exit-latency-us = <300>;
+ min-residency-us = <100000>;
+ };
};
};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 834fb5a..631906e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -63,12 +63,23 @@
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1700000000>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
};
cpu at 1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1700000000>;
+ cpu-idle-states = <&CLUSTER_SLEEP_0>;
+ };
+
+ idle-states {
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ entry-latency-us = <1000>;
+ exit-latency-us = <300>;
+ min-residency-us = <100000>;
+ };
};
};
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index a9b089c..d8a9cd2 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -60,5 +60,6 @@ config ARM_AT91_CPUIDLE
config ARM_EXYNOS_CPUIDLE
bool "Cpu Idle Driver for the Exynos processors"
depends on ARCH_EXYNOS
+ select DT_IDLE_STATES
help
Select this to enable cpuidle for Exynos processors
diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c
index 7c01512..097c21d 100644
--- a/drivers/cpuidle/cpuidle-exynos.c
+++ b/drivers/cpuidle/cpuidle-exynos.c
@@ -13,11 +13,14 @@
#include <linux/export.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
#include <asm/proc-fns.h>
#include <asm/suspend.h>
#include <asm/cpuidle.h>
+#include "dt_idle_states.h"
+
static void (*exynos_enter_aftr)(void);
static int idle_finisher(unsigned long flags)
@@ -60,32 +63,40 @@ static struct cpuidle_driver exynos_idle_driver = {
.owner = THIS_MODULE,
.states = {
[0] = ARM_CPUIDLE_WFI_STATE,
- [1] = {
- .enter = exynos_enter_lowpower,
- .exit_latency = 300,
- .target_residency = 100000,
- .flags = CPUIDLE_FLAG_TIME_VALID,
- .name = "C1",
- .desc = "ARM power down",
- },
},
- .state_count = 2,
- .safe_state_index = 0,
};
static int exynos_cpuidle_probe(struct platform_device *pdev)
{
- int ret;
+ int ret, i;
+ struct cpuidle_driver *drv = &exynos_idle_driver;
exynos_enter_aftr = (void *)(pdev->dev.platform_data);
- ret = cpuidle_register(&exynos_idle_driver, NULL);
+ drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
+ if (!drv->cpumask)
+ return -ENOMEM;
+
+ /* Start at index 1, index 0 standard WFI */
+ ret = dt_init_idle_driver(drv, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to initialize idle states\n");
+ goto free_mem;
+ }
+
+ for (i = 1; i < drv->state_count; i++)
+ drv->states[i].enter = exynos_enter_lowpower;
+
+ ret = cpuidle_register(drv, NULL);
if (ret) {
dev_err(&pdev->dev, "failed to register cpuidle driver\n");
- return ret;
+ goto free_mem;
}
return 0;
+free_mem:
+ kfree(drv->cpumask);
+ return ret;
}
static struct platform_driver exynos_cpuidle_driver = {
--
1.9.1
^ permalink raw reply related [flat|nested] 44+ messages in thread
* Re: [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 22:40 ` Nicolas Pitre
-1 siblings, 0 replies; 44+ messages in thread
From: Nicolas Pitre @ 2014-07-21 22:40 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: linux-arm-kernel, linux-pm, devicetree, Mark Rutland,
Sudeep Holla, Catalin Marinas, Charles Garcia Tobin, Rob Herring,
Grant Likely, Peter De Schrijver, Santosh Shilimkar,
Daniel Lezcano, Amit Kucheria, Vincent Guittot, Antti Miettinen,
Stephen Boyd, Kevin Hilman, Sebastian Capella, Tomasz Figa,
Mark Brown, Paul Walmsley, Chander Kashyap, Geoff Levand
On Mon, 21 Jul 2014, Lorenzo Pieralisi wrote:
> ARM based platforms implement a variety of power management schemes that
> allow processors to enter idle states at run-time.
> The parameters defining these idle states vary on a per-platform basis forcing
> the OS to hardcode the state parameters in platform specific static tables
> whose size grows as the number of platforms supported in the kernel increases
> and hampers device drivers standardization.
>
> Therefore, this patch aims at standardizing idle state device tree bindings
> for ARM platforms. Bindings define idle state parameters inclusive of entry
> methods and state latencies, to allow operating systems to retrieve the
> configuration entries from the device tree and initialize the related power
> management drivers, paving the way for common code in the kernel to deal with
> idle states and removing the need for static data in current and previous
> kernel versions.
>
> ARM64 platforms require the DT to define an entry-method property
> for idle states.
>
> On system implementing PSCI as an enable-method to enter low-power
> states the PSCI CPU suspend method requires the power_state parameter to
> be passed to the PSCI CPU suspend function.
>
> This parameter is specific to a power state and platform specific,
> therefore must be provided by firmware to the OS in order to enable
> proper call sequence.
>
> Thus, this patch also adds a property in the PSCI bindings that
> describes how the PSCI CPU suspend power_state parameter should be
> defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 8 +
> .../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
> Documentation/devicetree/bindings/arm/psci.txt | 14 +-
> 3 files changed, 700 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 1fe72a0..a44d4fd 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
> Value type: <phandle>
> Definition: Specifies the ACC[2] node associated with this CPU.
>
> + - cpu-idle-states
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition:
> + # List of phandles to idle state nodes supported
> + by this cpu [3].
>
> Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> @@ -411,3 +417,5 @@ cpus {
> --
> [1] arm/msm/qcom,saw2.txt
> [2] arm/msm/qcom,kpss-acc.txt
> +[3] ARM Linux kernel documentation - idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
> new file mode 100644
> index 0000000..37375c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/idle-states.txt
> @@ -0,0 +1,679 @@
> +==========================================
> +ARM idle states binding description
> +==========================================
> +
> +==========================================
> +1 - Introduction
> +==========================================
> +
> +ARM systems contain HW capable of managing power consumption dynamically,
> +where cores can be put in different low-power states (ranging from simple
> +wfi to power gating) according to OS PM policies. The CPU states representing
> +the range of dynamic idle states that a processor can enter at run-time, can be
> +specified through device tree bindings representing the parameters required
> +to enter/exit specific idle states on a given processor.
> +
> +According to the Server Base System Architecture document (SBSA, [3]), the
> +power states an ARM CPU can be put into are identified by the following list:
> +
> +- Running
> +- Idle_standby
> +- Idle_retention
> +- Sleep
> +- Off
> +
> +The power states described in the SBSA document define the basic CPU states on
> +top of which ARM platforms implement power management schemes that allow an OS
> +PM implementation to put the processor in different idle states (which include
> +states listed above; "off" state is not an idle state since it does not have
> +wake-up capabilities, hence it is not considered in this document).
> +
> +Idle state parameters (eg entry latency) are platform specific and need to be
> +characterized with bindings that provide the required information to OS PM
> +code so that it can build the required tables and use them at runtime.
> +
> +The device tree binding definition for ARM idle states is the subject of this
> +document.
> +
> +===========================================
> +2 - idle-states definitions
> +===========================================
> +
> +Idle states are characterized for a specific system through a set of
> +timing and energy related properties, that underline the HW behaviour
> +triggered upon idle states entry and exit.
> +
> +The following diagram depicts the CPU execution phases and related timing
> +properties required to enter and exit an idle state:
> +
> +..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
> + | | | | |
> +
> + |<------ entry ------->|
> + | latency |
> + |<- exit ->|
> + | latency |
> + |<-------- min-residency -------->|
> + |<------- wakeup-latency ------->|
> +
> + Diagram 1: CPU idle state execution phases
> +
> +EXEC: Normal CPU execution.
> +
> +PREP: Preparation phase before committing the hardware to idle mode
> + like cache flushing. This is abortable on pending wake-up
> + event conditions. The abort latency is assumed to be negligible
> + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
> + goes back to EXEC. This phase is optional. If not abortable,
> + this should be included in the ENTRY phase instead.
> +
> +ENTRY: The hardware is committed to idle mode. This period must run
> + to completion up to IDLE before anything else can happen.
> +
> +IDLE: This is the actual energy-saving idle period. This may last
> + between 0 and infinite time, until a wake-up event occurs.
> +
> +EXIT: Period during which the CPU is brought back to operational
> + mode (EXEC).
> +
> +entry-latency: Worst case latency required to enter the idle state. The
> +exit-latency may be guaranteed only after entry-latency has passed.
> +
> +min-residency: Minimum period, including preparation and entry, for a given
> +idle state to be worthwhile energywise.
> +
> +wakeup-latency: Maximum delay between the signaling of a wake-up event and the
> +CPU being able to execute normal code again. If not specified, this is assumed
> +to be entry-latency + exit-latency.
> +
> +These timing parameters can be used by an OS in different circumstances.
> +
> +An idle CPU requires the expected min-residency time to select the most
> +appropriate idle state based on the expected expiry time of the next IRQ
> +(ie wake-up) that causes the CPU to return to the EXEC phase.
> +
> +An operating system scheduler may need to compute the shortest wake-up delay
> +for CPUs in the system by detecting how long will it take to get a CPU out
> +of an idle state, eg:
> +
> +wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
> +
> +In other words, the scheduler can make its scheduling decision by selecting
> +(eg waking-up) the CPU with the shortest wake-up latency.
> +The wake-up latency must take into account the entry latency if that period
> +has not expired. The abortable nature of the PREP period can be ignored
> +if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
> +the worst case since it depends on the CPU operating conditions, ie caches
> +state).
> +
> +An OS has to reliably probe the wakeup-latency since some devices can enforce
> +latency constraints guarantees to work properly, so the OS has to detect the
> +worst case wake-up latency it can incur if a CPU is allowed to enter an
> +idle state, and possibly to prevent that to guarantee reliable device
> +functioning.
> +
> +The min-residency time parameter deserves further explanation since it is
> +expressed in time units but must factor in energy consumption coefficients.
> +
> +The energy consumption of a cpu when it enters a power state can be roughly
> +characterised by the following graph:
> +
> + |
> + |
> + |
> + e |
> + n | /---
> + e | /------
> + r | /------
> + g | /-----
> + y | /------
> + | ----
> + | /|
> + | / |
> + | / |
> + | / |
> + | / |
> + | / |
> + |/ |
> + -----|-------+----------------------------------
> + 0| 1 time(ms)
> +
> + Graph 1: Energy vs time example
> +
> +The graph is split in two parts delimited by time 1ms on the X-axis.
> +The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
> +and denotes the energy costs incurred whilst entering and leaving the idle
> +state.
> +The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
> +shallower slope and essentially represents the energy consumption of the idle
> +state.
> +
> +min-residency is defined for a given idle state as the minimum expected
> +residency time for a state (inclusive of preparation and entry) after
> +which choosing that state become the most energy efficient option. A good
> +way to visualise this, is by taking the same graph above and comparing some
> +states energy consumptions plots.
> +
> +For sake of simplicity, let's consider a system with two idle states IDLE1,
> +and IDLE2:
> +
> + |
> + |
> + |
> + | /-- IDLE1
> + e | /---
> + n | /----
> + e | /---
> + r | /-----/--------- IDLE2
> + g | /-------/---------
> + y | ------------ /---|
> + | / /---- |
> + | / /--- |
> + | / /---- |
> + | / /--- |
> + | --- |
> + | / |
> + | / |
> + |/ | time
> + ---/----------------------------+------------------------
> + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
> + |
> + IDLE2-min-residency
> +
> + Graph 2: idle states min-residency example
> +
> +In graph 2 above, that takes into account idle states entry/exit energy
> +costs, it is clear that if the idle state residency time (ie time till next
> +wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
> +choice energywise.
> +
> +This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
> +than IDLE2.
> +
> +However, the lower power consumption (ie shallower energy curve slope) of idle
> +state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
> +efficient.
> +
> +The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
> +shallower states in a system with multiple idle states) is defined
> +IDLE2-min-residency and corresponds to the time when energy consumption of
> +IDLE1 and IDLE2 states breaks even.
> +
> +The definitions provided in this section underpin the idle states
> +properties specification that is the subject of the following sections.
> +
> +===========================================
> +3 - idle-states node
> +===========================================
> +
> +ARM processor idle states are defined within the idle-states node, which is
> +a direct child of the cpus node [1] and provides a container where the
> +processor idle states, defined as device tree nodes, are listed.
> +
> +- idle-states node
> +
> + Usage: Optional - On ARM systems, it is a container of processor idle
> + states nodes. If the system does not provide CPU
> + power management capabilities or the processor just
> + supports idle_standby an idle-states node is not
> + required.
> +
> + Description: idle-states node is a container node, where its
> + subnodes describe the CPU idle states.
> +
> + Node name must be "idle-states".
> +
> + The idle-states node's parent node must be the cpus node.
> +
> + The idle-states node's child nodes can be:
> +
> + - one or more state nodes
> +
> + Any other configuration is considered invalid.
> +
> + An idle-states node defines the following properties:
> +
> + - entry-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version.
> + # On ARM v8 64-bit this property is required and must
> + be one of:
> + - "psci" (see bindings in [2])
> + # On ARM 32-bit systems this property is optional
> +
> +The nodes describing the idle states (state) can only be defined within the
> +idle-states node, any other configuration is considered invalid and therefore
> +must be ignored.
> +
> +===========================================
> +4 - state node
> +===========================================
> +
> +A state node represents an idle state description and must be defined as
> +follows:
> +
> +- state node
> +
> + Description: must be child of the idle-states node
> +
> + The state node name shall follow standard device tree naming
> + rules ([5], 2.2.1 "Node names"), in particular state nodes which
> + are siblings within a single common parent must be given a unique name.
> +
> + The idle state entered by executing the wfi instruction (idle_standby
> + SBSA,[3][4]) is considered standard on all ARM platforms and therefore
> + must not be listed.
> +
> + With the definitions provided above, the following list represents
> + the valid properties for a state node:
> +
> + - compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must be "arm,idle-state".
> +
> + - local-timer-stop
> + Usage: See definition
> + Value type: <none>
> + Definition: if present the CPU local timer control logic is
> + lost on state entry, otherwise it is retained.
> +
> + - entry-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency in
> + microseconds required to enter the idle state.
> + The exit-latency-us duration may be guaranteed
> + only after entry-latency-us has passed.
> +
> + - exit-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency
> + in microseconds required to exit the idle state.
> +
> + - min-residency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing minimum residency duration
> + in microseconds, inclusive of preparation and
> + entry, for this idle state to be considered
> + worthwhile energy wise (refer to section 2 of
> + this document for a complete description).
> +
> + - wakeup-latency-us:
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing maximum delay between the
> + signaling of a wake-up event and the CPU being
> + able to execute normal code again. If omitted,
> + this is assumed to be equal to:
> +
> + entry-latency-us + exit-latency-us
> +
> + It is important to supply this value on systems
> + where the duration of PREP phase (see diagram 1,
> + section 2) is non-neglibigle.
> + In such systems entry-latency-us + exit-latency-us
> + will exceed wakeup-latency-us by this duration.
> +
> + In addition to the properties listed above, a state node may require
> + additional properties specifics to the entry-method defined in the
> + idle-states node, please refer to the entry-method bindings
> + documentation for properties definitions.
> +
> +===========================================
> +4 - Examples
> +===========================================
> +
> +Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu@10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU5: cpu@10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU6: cpu@10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU7: cpu@10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU8: cpu@100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU9: cpu@100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU10: cpu@100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU11: cpu@100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU12: cpu@100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU13: cpu@100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU14: cpu@100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU15: cpu@100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_RETENTION_0_0: cpu-retention-0-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <80>;
> + };
> +
> + CLUSTER_RETENTION_0: cluster-retention-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <250>;
> + wakeup-latency-us = <130>;
> + };
> +
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <250>;
> + exit-latency-us = <500>;
> + min-residency-us = <950>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <600>;
> + exit-latency-us = <1100>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> +
> + CPU_RETENTION_1_0: cpu-retention-1-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <90>;
> + };
> +
> + CLUSTER_RETENTION_1: cluster-retention-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <270>;
> + wakeup-latency-us = <100>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <100>;
> + min-residency-us = <300>;
> + wakeup-latency-us = <150>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <500>;
> + exit-latency-us = <1200>;
> + min-residency-us = <3500>;
> + wakeup-latency-us = <1300>;
> + };
> + };
> +
> +};
> +
> +Example 2 (ARM 32-bit, 8-cpu system, two clusters):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x0>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x1>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x2>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x3>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <200>;
> + exit-latency-us = <100>;
> + min-residency-us = <400>;
> + wakeup-latency-us = <250>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <500>;
> + exit-latency-us = <1500>;
> + min-residency-us = <2500>;
> + wakeup-latency-us = <1700>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <500>;
> + min-residency-us = <900>;
> + wakeup-latency-us = <600>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <800>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6500>;
> + wakeup-latency-us = <2300>;
> + };
> + };
> +
> +};
> +
> +===========================================
> +5 - References
> +===========================================
> +
> +[1] ARM Linux Kernel documentation - CPUs bindings
> + Documentation/devicetree/bindings/arm/cpus.txt
> +
> +[2] ARM Linux Kernel documentation - PSCI bindings
> + Documentation/devicetree/bindings/arm/psci.txt
> +
> +[3] ARM Server Base System Architecture (SBSA)
> + http://infocenter.arm.com/help/index.jsp
> +
> +[4] ARM Architecture Reference Manuals
> + http://infocenter.arm.com/help/index.jsp
> +
> +[5] ePAPR standard
> + https://www.power.org/documentation/epapr-version-1-1/
> diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
> index b4a58f3..5aa40ed 100644
> --- a/Documentation/devicetree/bindings/arm/psci.txt
> +++ b/Documentation/devicetree/bindings/arm/psci.txt
> @@ -50,6 +50,16 @@ Main node optional properties:
>
> - migrate : Function ID for MIGRATE operation
>
> +Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
> +state nodes, as per bindings in [1]) must specify the following properties:
> +
> +- arm,psci-suspend-param
> + Usage: Required for state nodes[1] if the corresponding
> + idle-states node entry-method property is set
> + to "psci".
> + Value type: <u32>
> + Definition: power_state parameter to pass to the PSCI
> + suspend call.
>
> Example:
>
> @@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
> migrate = <0x95c10003>;
> };
>
> -
> Case 2: PSCI v0.2 only
>
> psci {
> @@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
>
> ...
> };
> +
> +[1] Kernel documentation - ARM idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> --
> 1.9.1
>
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
@ 2014-07-21 22:40 ` Nicolas Pitre
0 siblings, 0 replies; 44+ messages in thread
From: Nicolas Pitre @ 2014-07-21 22:40 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, 21 Jul 2014, Lorenzo Pieralisi wrote:
> ARM based platforms implement a variety of power management schemes that
> allow processors to enter idle states at run-time.
> The parameters defining these idle states vary on a per-platform basis forcing
> the OS to hardcode the state parameters in platform specific static tables
> whose size grows as the number of platforms supported in the kernel increases
> and hampers device drivers standardization.
>
> Therefore, this patch aims at standardizing idle state device tree bindings
> for ARM platforms. Bindings define idle state parameters inclusive of entry
> methods and state latencies, to allow operating systems to retrieve the
> configuration entries from the device tree and initialize the related power
> management drivers, paving the way for common code in the kernel to deal with
> idle states and removing the need for static data in current and previous
> kernel versions.
>
> ARM64 platforms require the DT to define an entry-method property
> for idle states.
>
> On system implementing PSCI as an enable-method to enter low-power
> states the PSCI CPU suspend method requires the power_state parameter to
> be passed to the PSCI CPU suspend function.
>
> This parameter is specific to a power state and platform specific,
> therefore must be provided by firmware to the OS in order to enable
> proper call sequence.
>
> Thus, this patch also adds a property in the PSCI bindings that
> describes how the PSCI CPU suspend power_state parameter should be
> defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 8 +
> .../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
> Documentation/devicetree/bindings/arm/psci.txt | 14 +-
> 3 files changed, 700 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 1fe72a0..a44d4fd 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
> Value type: <phandle>
> Definition: Specifies the ACC[2] node associated with this CPU.
>
> + - cpu-idle-states
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition:
> + # List of phandles to idle state nodes supported
> + by this cpu [3].
>
> Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> @@ -411,3 +417,5 @@ cpus {
> --
> [1] arm/msm/qcom,saw2.txt
> [2] arm/msm/qcom,kpss-acc.txt
> +[3] ARM Linux kernel documentation - idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
> new file mode 100644
> index 0000000..37375c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/idle-states.txt
> @@ -0,0 +1,679 @@
> +==========================================
> +ARM idle states binding description
> +==========================================
> +
> +==========================================
> +1 - Introduction
> +==========================================
> +
> +ARM systems contain HW capable of managing power consumption dynamically,
> +where cores can be put in different low-power states (ranging from simple
> +wfi to power gating) according to OS PM policies. The CPU states representing
> +the range of dynamic idle states that a processor can enter at run-time, can be
> +specified through device tree bindings representing the parameters required
> +to enter/exit specific idle states on a given processor.
> +
> +According to the Server Base System Architecture document (SBSA, [3]), the
> +power states an ARM CPU can be put into are identified by the following list:
> +
> +- Running
> +- Idle_standby
> +- Idle_retention
> +- Sleep
> +- Off
> +
> +The power states described in the SBSA document define the basic CPU states on
> +top of which ARM platforms implement power management schemes that allow an OS
> +PM implementation to put the processor in different idle states (which include
> +states listed above; "off" state is not an idle state since it does not have
> +wake-up capabilities, hence it is not considered in this document).
> +
> +Idle state parameters (eg entry latency) are platform specific and need to be
> +characterized with bindings that provide the required information to OS PM
> +code so that it can build the required tables and use them at runtime.
> +
> +The device tree binding definition for ARM idle states is the subject of this
> +document.
> +
> +===========================================
> +2 - idle-states definitions
> +===========================================
> +
> +Idle states are characterized for a specific system through a set of
> +timing and energy related properties, that underline the HW behaviour
> +triggered upon idle states entry and exit.
> +
> +The following diagram depicts the CPU execution phases and related timing
> +properties required to enter and exit an idle state:
> +
> +..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
> + | | | | |
> +
> + |<------ entry ------->|
> + | latency |
> + |<- exit ->|
> + | latency |
> + |<-------- min-residency -------->|
> + |<------- wakeup-latency ------->|
> +
> + Diagram 1: CPU idle state execution phases
> +
> +EXEC: Normal CPU execution.
> +
> +PREP: Preparation phase before committing the hardware to idle mode
> + like cache flushing. This is abortable on pending wake-up
> + event conditions. The abort latency is assumed to be negligible
> + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
> + goes back to EXEC. This phase is optional. If not abortable,
> + this should be included in the ENTRY phase instead.
> +
> +ENTRY: The hardware is committed to idle mode. This period must run
> + to completion up to IDLE before anything else can happen.
> +
> +IDLE: This is the actual energy-saving idle period. This may last
> + between 0 and infinite time, until a wake-up event occurs.
> +
> +EXIT: Period during which the CPU is brought back to operational
> + mode (EXEC).
> +
> +entry-latency: Worst case latency required to enter the idle state. The
> +exit-latency may be guaranteed only after entry-latency has passed.
> +
> +min-residency: Minimum period, including preparation and entry, for a given
> +idle state to be worthwhile energywise.
> +
> +wakeup-latency: Maximum delay between the signaling of a wake-up event and the
> +CPU being able to execute normal code again. If not specified, this is assumed
> +to be entry-latency + exit-latency.
> +
> +These timing parameters can be used by an OS in different circumstances.
> +
> +An idle CPU requires the expected min-residency time to select the most
> +appropriate idle state based on the expected expiry time of the next IRQ
> +(ie wake-up) that causes the CPU to return to the EXEC phase.
> +
> +An operating system scheduler may need to compute the shortest wake-up delay
> +for CPUs in the system by detecting how long will it take to get a CPU out
> +of an idle state, eg:
> +
> +wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
> +
> +In other words, the scheduler can make its scheduling decision by selecting
> +(eg waking-up) the CPU with the shortest wake-up latency.
> +The wake-up latency must take into account the entry latency if that period
> +has not expired. The abortable nature of the PREP period can be ignored
> +if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
> +the worst case since it depends on the CPU operating conditions, ie caches
> +state).
> +
> +An OS has to reliably probe the wakeup-latency since some devices can enforce
> +latency constraints guarantees to work properly, so the OS has to detect the
> +worst case wake-up latency it can incur if a CPU is allowed to enter an
> +idle state, and possibly to prevent that to guarantee reliable device
> +functioning.
> +
> +The min-residency time parameter deserves further explanation since it is
> +expressed in time units but must factor in energy consumption coefficients.
> +
> +The energy consumption of a cpu when it enters a power state can be roughly
> +characterised by the following graph:
> +
> + |
> + |
> + |
> + e |
> + n | /---
> + e | /------
> + r | /------
> + g | /-----
> + y | /------
> + | ----
> + | /|
> + | / |
> + | / |
> + | / |
> + | / |
> + | / |
> + |/ |
> + -----|-------+----------------------------------
> + 0| 1 time(ms)
> +
> + Graph 1: Energy vs time example
> +
> +The graph is split in two parts delimited by time 1ms on the X-axis.
> +The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
> +and denotes the energy costs incurred whilst entering and leaving the idle
> +state.
> +The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
> +shallower slope and essentially represents the energy consumption of the idle
> +state.
> +
> +min-residency is defined for a given idle state as the minimum expected
> +residency time for a state (inclusive of preparation and entry) after
> +which choosing that state become the most energy efficient option. A good
> +way to visualise this, is by taking the same graph above and comparing some
> +states energy consumptions plots.
> +
> +For sake of simplicity, let's consider a system with two idle states IDLE1,
> +and IDLE2:
> +
> + |
> + |
> + |
> + | /-- IDLE1
> + e | /---
> + n | /----
> + e | /---
> + r | /-----/--------- IDLE2
> + g | /-------/---------
> + y | ------------ /---|
> + | / /---- |
> + | / /--- |
> + | / /---- |
> + | / /--- |
> + | --- |
> + | / |
> + | / |
> + |/ | time
> + ---/----------------------------+------------------------
> + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
> + |
> + IDLE2-min-residency
> +
> + Graph 2: idle states min-residency example
> +
> +In graph 2 above, that takes into account idle states entry/exit energy
> +costs, it is clear that if the idle state residency time (ie time till next
> +wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
> +choice energywise.
> +
> +This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
> +than IDLE2.
> +
> +However, the lower power consumption (ie shallower energy curve slope) of idle
> +state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
> +efficient.
> +
> +The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
> +shallower states in a system with multiple idle states) is defined
> +IDLE2-min-residency and corresponds to the time when energy consumption of
> +IDLE1 and IDLE2 states breaks even.
> +
> +The definitions provided in this section underpin the idle states
> +properties specification that is the subject of the following sections.
> +
> +===========================================
> +3 - idle-states node
> +===========================================
> +
> +ARM processor idle states are defined within the idle-states node, which is
> +a direct child of the cpus node [1] and provides a container where the
> +processor idle states, defined as device tree nodes, are listed.
> +
> +- idle-states node
> +
> + Usage: Optional - On ARM systems, it is a container of processor idle
> + states nodes. If the system does not provide CPU
> + power management capabilities or the processor just
> + supports idle_standby an idle-states node is not
> + required.
> +
> + Description: idle-states node is a container node, where its
> + subnodes describe the CPU idle states.
> +
> + Node name must be "idle-states".
> +
> + The idle-states node's parent node must be the cpus node.
> +
> + The idle-states node's child nodes can be:
> +
> + - one or more state nodes
> +
> + Any other configuration is considered invalid.
> +
> + An idle-states node defines the following properties:
> +
> + - entry-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version.
> + # On ARM v8 64-bit this property is required and must
> + be one of:
> + - "psci" (see bindings in [2])
> + # On ARM 32-bit systems this property is optional
> +
> +The nodes describing the idle states (state) can only be defined within the
> +idle-states node, any other configuration is considered invalid and therefore
> +must be ignored.
> +
> +===========================================
> +4 - state node
> +===========================================
> +
> +A state node represents an idle state description and must be defined as
> +follows:
> +
> +- state node
> +
> + Description: must be child of the idle-states node
> +
> + The state node name shall follow standard device tree naming
> + rules ([5], 2.2.1 "Node names"), in particular state nodes which
> + are siblings within a single common parent must be given a unique name.
> +
> + The idle state entered by executing the wfi instruction (idle_standby
> + SBSA,[3][4]) is considered standard on all ARM platforms and therefore
> + must not be listed.
> +
> + With the definitions provided above, the following list represents
> + the valid properties for a state node:
> +
> + - compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must be "arm,idle-state".
> +
> + - local-timer-stop
> + Usage: See definition
> + Value type: <none>
> + Definition: if present the CPU local timer control logic is
> + lost on state entry, otherwise it is retained.
> +
> + - entry-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency in
> + microseconds required to enter the idle state.
> + The exit-latency-us duration may be guaranteed
> + only after entry-latency-us has passed.
> +
> + - exit-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency
> + in microseconds required to exit the idle state.
> +
> + - min-residency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing minimum residency duration
> + in microseconds, inclusive of preparation and
> + entry, for this idle state to be considered
> + worthwhile energy wise (refer to section 2 of
> + this document for a complete description).
> +
> + - wakeup-latency-us:
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing maximum delay between the
> + signaling of a wake-up event and the CPU being
> + able to execute normal code again. If omitted,
> + this is assumed to be equal to:
> +
> + entry-latency-us + exit-latency-us
> +
> + It is important to supply this value on systems
> + where the duration of PREP phase (see diagram 1,
> + section 2) is non-neglibigle.
> + In such systems entry-latency-us + exit-latency-us
> + will exceed wakeup-latency-us by this duration.
> +
> + In addition to the properties listed above, a state node may require
> + additional properties specifics to the entry-method defined in the
> + idle-states node, please refer to the entry-method bindings
> + documentation for properties definitions.
> +
> +===========================================
> +4 - Examples
> +===========================================
> +
> +Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu at 10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU5: cpu at 10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU6: cpu at 10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU7: cpu at 10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU8: cpu at 100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU9: cpu at 100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU10: cpu at 100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU11: cpu at 100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU12: cpu at 100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU13: cpu at 100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU14: cpu at 100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU15: cpu at 100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_RETENTION_0_0: cpu-retention-0-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <80>;
> + };
> +
> + CLUSTER_RETENTION_0: cluster-retention-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <250>;
> + wakeup-latency-us = <130>;
> + };
> +
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <250>;
> + exit-latency-us = <500>;
> + min-residency-us = <950>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <600>;
> + exit-latency-us = <1100>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> +
> + CPU_RETENTION_1_0: cpu-retention-1-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <90>;
> + };
> +
> + CLUSTER_RETENTION_1: cluster-retention-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <270>;
> + wakeup-latency-us = <100>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <100>;
> + min-residency-us = <300>;
> + wakeup-latency-us = <150>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <500>;
> + exit-latency-us = <1200>;
> + min-residency-us = <3500>;
> + wakeup-latency-us = <1300>;
> + };
> + };
> +
> +};
> +
> +Example 2 (ARM 32-bit, 8-cpu system, two clusters):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x0>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x1>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x2>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x3>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU5: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU6: cpu at 102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU7: cpu at 103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <200>;
> + exit-latency-us = <100>;
> + min-residency-us = <400>;
> + wakeup-latency-us = <250>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <500>;
> + exit-latency-us = <1500>;
> + min-residency-us = <2500>;
> + wakeup-latency-us = <1700>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <500>;
> + min-residency-us = <900>;
> + wakeup-latency-us = <600>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <800>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6500>;
> + wakeup-latency-us = <2300>;
> + };
> + };
> +
> +};
> +
> +===========================================
> +5 - References
> +===========================================
> +
> +[1] ARM Linux Kernel documentation - CPUs bindings
> + Documentation/devicetree/bindings/arm/cpus.txt
> +
> +[2] ARM Linux Kernel documentation - PSCI bindings
> + Documentation/devicetree/bindings/arm/psci.txt
> +
> +[3] ARM Server Base System Architecture (SBSA)
> + http://infocenter.arm.com/help/index.jsp
> +
> +[4] ARM Architecture Reference Manuals
> + http://infocenter.arm.com/help/index.jsp
> +
> +[5] ePAPR standard
> + https://www.power.org/documentation/epapr-version-1-1/
> diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
> index b4a58f3..5aa40ed 100644
> --- a/Documentation/devicetree/bindings/arm/psci.txt
> +++ b/Documentation/devicetree/bindings/arm/psci.txt
> @@ -50,6 +50,16 @@ Main node optional properties:
>
> - migrate : Function ID for MIGRATE operation
>
> +Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
> +state nodes, as per bindings in [1]) must specify the following properties:
> +
> +- arm,psci-suspend-param
> + Usage: Required for state nodes[1] if the corresponding
> + idle-states node entry-method property is set
> + to "psci".
> + Value type: <u32>
> + Definition: power_state parameter to pass to the PSCI
> + suspend call.
>
> Example:
>
> @@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
> migrate = <0x95c10003>;
> };
>
> -
> Case 2: PSCI v0.2 only
>
> psci {
> @@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
>
> ...
> };
> +
> +[1] Kernel documentation - ARM idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> --
> 1.9.1
>
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 3/7] arm64: kernel: introduce cpu_init_idle CPU operation
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-21 22:55 ` Stephen Boyd
-1 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2014-07-21 22:55 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: linux-arm-kernel, linux-pm, devicetree, Mark Rutland,
Sudeep Holla, Catalin Marinas, Charles Garcia Tobin,
Nicolas Pitre, Rob Herring, Grant Likely, Peter De Schrijver,
Santosh Shilimkar, Daniel Lezcano, Amit Kucheria,
Vincent Guittot, Antti Miettinen, Kevin Hilman,
Sebastian Capella, Tomasz Figa, Mark Brown, Paul Walmsley,
Chander Kashyap, Geoff Levand
On 07/21/14 09:06, Lorenzo Pieralisi wrote:
> diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
> new file mode 100644
> index 0000000..46eb3ea
> --- /dev/null
> +++ b/arch/arm64/kernel/cpuidle.c
> @@ -0,0 +1,27 @@
> +/*
> + * ARM64 CPU idle arch support
> + *
> + * Copyright (C) 2014 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <asm/cpu_ops.h>
> +
> +int cpu_init_idle(unsigned int cpu)
sparse will probably complain here unless we include <asm/cpuidle.h> right?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 3/7] arm64: kernel: introduce cpu_init_idle CPU operation
@ 2014-07-21 22:55 ` Stephen Boyd
0 siblings, 0 replies; 44+ messages in thread
From: Stephen Boyd @ 2014-07-21 22:55 UTC (permalink / raw)
To: linux-arm-kernel
On 07/21/14 09:06, Lorenzo Pieralisi wrote:
> diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
> new file mode 100644
> index 0000000..46eb3ea
> --- /dev/null
> +++ b/arch/arm64/kernel/cpuidle.c
> @@ -0,0 +1,27 @@
> +/*
> + * ARM64 CPU idle arch support
> + *
> + * Copyright (C) 2014 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <asm/cpu_ops.h>
> +
> +int cpu_init_idle(unsigned int cpu)
sparse will probably complain here unless we include <asm/cpuidle.h> right?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 3/7] arm64: kernel: introduce cpu_init_idle CPU operation
2014-07-21 22:55 ` Stephen Boyd
@ 2014-07-22 9:12 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-22 9:12 UTC (permalink / raw)
To: Stephen Boyd
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Daniel Lezcano, linux-arm-kernel,
grant.likely, Charles Garcia-Tobin, devicetree, Kevin Hilman,
linux-pm, Sebastian Capella, Mark Brown, Antti Miettinen,
Paul Walmsley, Geoff Levand, Peter De Schrijver, Amit Kucheria
On Mon, Jul 21, 2014 at 11:55:15PM +0100, Stephen Boyd wrote:
> On 07/21/14 09:06, Lorenzo Pieralisi wrote:
> > diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
> > new file mode 100644
> > index 0000000..46eb3ea
> > --- /dev/null
> > +++ b/arch/arm64/kernel/cpuidle.c
> > @@ -0,0 +1,27 @@
> > +/*
> > + * ARM64 CPU idle arch support
> > + *
> > + * Copyright (C) 2014 ARM Ltd.
> > + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <asm/cpu_ops.h>
> > +
> > +int cpu_init_idle(unsigned int cpu)
>
> sparse will probably complain here unless we include <asm/cpuidle.h> right?
Yes, I missed that, now fixed, thanks a lot.
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 3/7] arm64: kernel: introduce cpu_init_idle CPU operation
@ 2014-07-22 9:12 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-22 9:12 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 21, 2014 at 11:55:15PM +0100, Stephen Boyd wrote:
> On 07/21/14 09:06, Lorenzo Pieralisi wrote:
> > diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c
> > new file mode 100644
> > index 0000000..46eb3ea
> > --- /dev/null
> > +++ b/arch/arm64/kernel/cpuidle.c
> > @@ -0,0 +1,27 @@
> > +/*
> > + * ARM64 CPU idle arch support
> > + *
> > + * Copyright (C) 2014 ARM Ltd.
> > + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <asm/cpu_ops.h>
> > +
> > +int cpu_init_idle(unsigned int cpu)
>
> sparse will probably complain here unless we include <asm/cpuidle.h> right?
Yes, I missed that, now fixed, thanks a lot.
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-22 12:38 ` Rob Herring
-1 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2014-07-22 12:38 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Daniel Lezcano, linux-arm-kernel,
Grant Likely, Charles Garcia Tobin, devicetree, Kevin Hilman,
linux-pm, Sebastian Capella, Mark Brown, Antti Miettinen,
Paul Walmsley, Geoff Levand, Peter De Schrijver, Stephen Boyd,
Amit Kucheria
On Mon, Jul 21, 2014 at 11:06 AM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> ARM based platforms implement a variety of power management schemes that
> allow processors to enter idle states at run-time.
> The parameters defining these idle states vary on a per-platform basis forcing
> the OS to hardcode the state parameters in platform specific static tables
> whose size grows as the number of platforms supported in the kernel increases
> and hampers device drivers standardization.
>
> Therefore, this patch aims at standardizing idle state device tree bindings
> for ARM platforms. Bindings define idle state parameters inclusive of entry
> methods and state latencies, to allow operating systems to retrieve the
> configuration entries from the device tree and initialize the related power
> management drivers, paving the way for common code in the kernel to deal with
> idle states and removing the need for static data in current and previous
> kernel versions.
>
> ARM64 platforms require the DT to define an entry-method property
> for idle states.
>
> On system implementing PSCI as an enable-method to enter low-power
> states the PSCI CPU suspend method requires the power_state parameter to
> be passed to the PSCI CPU suspend function.
>
> This parameter is specific to a power state and platform specific,
> therefore must be provided by firmware to the OS in order to enable
> proper call sequence.
>
> Thus, this patch also adds a property in the PSCI bindings that
> describes how the PSCI CPU suspend power_state parameter should be
> defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Rob
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 8 +
> .../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
> Documentation/devicetree/bindings/arm/psci.txt | 14 +-
> 3 files changed, 700 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 1fe72a0..a44d4fd 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
> Value type: <phandle>
> Definition: Specifies the ACC[2] node associated with this CPU.
>
> + - cpu-idle-states
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition:
> + # List of phandles to idle state nodes supported
> + by this cpu [3].
>
> Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> @@ -411,3 +417,5 @@ cpus {
> --
> [1] arm/msm/qcom,saw2.txt
> [2] arm/msm/qcom,kpss-acc.txt
> +[3] ARM Linux kernel documentation - idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
> new file mode 100644
> index 0000000..37375c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/idle-states.txt
> @@ -0,0 +1,679 @@
> +==========================================
> +ARM idle states binding description
> +==========================================
> +
> +==========================================
> +1 - Introduction
> +==========================================
> +
> +ARM systems contain HW capable of managing power consumption dynamically,
> +where cores can be put in different low-power states (ranging from simple
> +wfi to power gating) according to OS PM policies. The CPU states representing
> +the range of dynamic idle states that a processor can enter at run-time, can be
> +specified through device tree bindings representing the parameters required
> +to enter/exit specific idle states on a given processor.
> +
> +According to the Server Base System Architecture document (SBSA, [3]), the
> +power states an ARM CPU can be put into are identified by the following list:
> +
> +- Running
> +- Idle_standby
> +- Idle_retention
> +- Sleep
> +- Off
> +
> +The power states described in the SBSA document define the basic CPU states on
> +top of which ARM platforms implement power management schemes that allow an OS
> +PM implementation to put the processor in different idle states (which include
> +states listed above; "off" state is not an idle state since it does not have
> +wake-up capabilities, hence it is not considered in this document).
> +
> +Idle state parameters (eg entry latency) are platform specific and need to be
> +characterized with bindings that provide the required information to OS PM
> +code so that it can build the required tables and use them at runtime.
> +
> +The device tree binding definition for ARM idle states is the subject of this
> +document.
> +
> +===========================================
> +2 - idle-states definitions
> +===========================================
> +
> +Idle states are characterized for a specific system through a set of
> +timing and energy related properties, that underline the HW behaviour
> +triggered upon idle states entry and exit.
> +
> +The following diagram depicts the CPU execution phases and related timing
> +properties required to enter and exit an idle state:
> +
> +..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
> + | | | | |
> +
> + |<------ entry ------->|
> + | latency |
> + |<- exit ->|
> + | latency |
> + |<-------- min-residency -------->|
> + |<------- wakeup-latency ------->|
> +
> + Diagram 1: CPU idle state execution phases
> +
> +EXEC: Normal CPU execution.
> +
> +PREP: Preparation phase before committing the hardware to idle mode
> + like cache flushing. This is abortable on pending wake-up
> + event conditions. The abort latency is assumed to be negligible
> + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
> + goes back to EXEC. This phase is optional. If not abortable,
> + this should be included in the ENTRY phase instead.
> +
> +ENTRY: The hardware is committed to idle mode. This period must run
> + to completion up to IDLE before anything else can happen.
> +
> +IDLE: This is the actual energy-saving idle period. This may last
> + between 0 and infinite time, until a wake-up event occurs.
> +
> +EXIT: Period during which the CPU is brought back to operational
> + mode (EXEC).
> +
> +entry-latency: Worst case latency required to enter the idle state. The
> +exit-latency may be guaranteed only after entry-latency has passed.
> +
> +min-residency: Minimum period, including preparation and entry, for a given
> +idle state to be worthwhile energywise.
> +
> +wakeup-latency: Maximum delay between the signaling of a wake-up event and the
> +CPU being able to execute normal code again. If not specified, this is assumed
> +to be entry-latency + exit-latency.
> +
> +These timing parameters can be used by an OS in different circumstances.
> +
> +An idle CPU requires the expected min-residency time to select the most
> +appropriate idle state based on the expected expiry time of the next IRQ
> +(ie wake-up) that causes the CPU to return to the EXEC phase.
> +
> +An operating system scheduler may need to compute the shortest wake-up delay
> +for CPUs in the system by detecting how long will it take to get a CPU out
> +of an idle state, eg:
> +
> +wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
> +
> +In other words, the scheduler can make its scheduling decision by selecting
> +(eg waking-up) the CPU with the shortest wake-up latency.
> +The wake-up latency must take into account the entry latency if that period
> +has not expired. The abortable nature of the PREP period can be ignored
> +if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
> +the worst case since it depends on the CPU operating conditions, ie caches
> +state).
> +
> +An OS has to reliably probe the wakeup-latency since some devices can enforce
> +latency constraints guarantees to work properly, so the OS has to detect the
> +worst case wake-up latency it can incur if a CPU is allowed to enter an
> +idle state, and possibly to prevent that to guarantee reliable device
> +functioning.
> +
> +The min-residency time parameter deserves further explanation since it is
> +expressed in time units but must factor in energy consumption coefficients.
> +
> +The energy consumption of a cpu when it enters a power state can be roughly
> +characterised by the following graph:
> +
> + |
> + |
> + |
> + e |
> + n | /---
> + e | /------
> + r | /------
> + g | /-----
> + y | /------
> + | ----
> + | /|
> + | / |
> + | / |
> + | / |
> + | / |
> + | / |
> + |/ |
> + -----|-------+----------------------------------
> + 0| 1 time(ms)
> +
> + Graph 1: Energy vs time example
> +
> +The graph is split in two parts delimited by time 1ms on the X-axis.
> +The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
> +and denotes the energy costs incurred whilst entering and leaving the idle
> +state.
> +The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
> +shallower slope and essentially represents the energy consumption of the idle
> +state.
> +
> +min-residency is defined for a given idle state as the minimum expected
> +residency time for a state (inclusive of preparation and entry) after
> +which choosing that state become the most energy efficient option. A good
> +way to visualise this, is by taking the same graph above and comparing some
> +states energy consumptions plots.
> +
> +For sake of simplicity, let's consider a system with two idle states IDLE1,
> +and IDLE2:
> +
> + |
> + |
> + |
> + | /-- IDLE1
> + e | /---
> + n | /----
> + e | /---
> + r | /-----/--------- IDLE2
> + g | /-------/---------
> + y | ------------ /---|
> + | / /---- |
> + | / /--- |
> + | / /---- |
> + | / /--- |
> + | --- |
> + | / |
> + | / |
> + |/ | time
> + ---/----------------------------+------------------------
> + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
> + |
> + IDLE2-min-residency
> +
> + Graph 2: idle states min-residency example
> +
> +In graph 2 above, that takes into account idle states entry/exit energy
> +costs, it is clear that if the idle state residency time (ie time till next
> +wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
> +choice energywise.
> +
> +This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
> +than IDLE2.
> +
> +However, the lower power consumption (ie shallower energy curve slope) of idle
> +state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
> +efficient.
> +
> +The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
> +shallower states in a system with multiple idle states) is defined
> +IDLE2-min-residency and corresponds to the time when energy consumption of
> +IDLE1 and IDLE2 states breaks even.
> +
> +The definitions provided in this section underpin the idle states
> +properties specification that is the subject of the following sections.
> +
> +===========================================
> +3 - idle-states node
> +===========================================
> +
> +ARM processor idle states are defined within the idle-states node, which is
> +a direct child of the cpus node [1] and provides a container where the
> +processor idle states, defined as device tree nodes, are listed.
> +
> +- idle-states node
> +
> + Usage: Optional - On ARM systems, it is a container of processor idle
> + states nodes. If the system does not provide CPU
> + power management capabilities or the processor just
> + supports idle_standby an idle-states node is not
> + required.
> +
> + Description: idle-states node is a container node, where its
> + subnodes describe the CPU idle states.
> +
> + Node name must be "idle-states".
> +
> + The idle-states node's parent node must be the cpus node.
> +
> + The idle-states node's child nodes can be:
> +
> + - one or more state nodes
> +
> + Any other configuration is considered invalid.
> +
> + An idle-states node defines the following properties:
> +
> + - entry-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version.
> + # On ARM v8 64-bit this property is required and must
> + be one of:
> + - "psci" (see bindings in [2])
> + # On ARM 32-bit systems this property is optional
> +
> +The nodes describing the idle states (state) can only be defined within the
> +idle-states node, any other configuration is considered invalid and therefore
> +must be ignored.
> +
> +===========================================
> +4 - state node
> +===========================================
> +
> +A state node represents an idle state description and must be defined as
> +follows:
> +
> +- state node
> +
> + Description: must be child of the idle-states node
> +
> + The state node name shall follow standard device tree naming
> + rules ([5], 2.2.1 "Node names"), in particular state nodes which
> + are siblings within a single common parent must be given a unique name.
> +
> + The idle state entered by executing the wfi instruction (idle_standby
> + SBSA,[3][4]) is considered standard on all ARM platforms and therefore
> + must not be listed.
> +
> + With the definitions provided above, the following list represents
> + the valid properties for a state node:
> +
> + - compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must be "arm,idle-state".
> +
> + - local-timer-stop
> + Usage: See definition
> + Value type: <none>
> + Definition: if present the CPU local timer control logic is
> + lost on state entry, otherwise it is retained.
> +
> + - entry-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency in
> + microseconds required to enter the idle state.
> + The exit-latency-us duration may be guaranteed
> + only after entry-latency-us has passed.
> +
> + - exit-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency
> + in microseconds required to exit the idle state.
> +
> + - min-residency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing minimum residency duration
> + in microseconds, inclusive of preparation and
> + entry, for this idle state to be considered
> + worthwhile energy wise (refer to section 2 of
> + this document for a complete description).
> +
> + - wakeup-latency-us:
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing maximum delay between the
> + signaling of a wake-up event and the CPU being
> + able to execute normal code again. If omitted,
> + this is assumed to be equal to:
> +
> + entry-latency-us + exit-latency-us
> +
> + It is important to supply this value on systems
> + where the duration of PREP phase (see diagram 1,
> + section 2) is non-neglibigle.
> + In such systems entry-latency-us + exit-latency-us
> + will exceed wakeup-latency-us by this duration.
> +
> + In addition to the properties listed above, a state node may require
> + additional properties specifics to the entry-method defined in the
> + idle-states node, please refer to the entry-method bindings
> + documentation for properties definitions.
> +
> +===========================================
> +4 - Examples
> +===========================================
> +
> +Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu@10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU5: cpu@10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU6: cpu@10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU7: cpu@10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU8: cpu@100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU9: cpu@100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU10: cpu@100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU11: cpu@100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU12: cpu@100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU13: cpu@100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU14: cpu@100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU15: cpu@100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_RETENTION_0_0: cpu-retention-0-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <80>;
> + };
> +
> + CLUSTER_RETENTION_0: cluster-retention-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <250>;
> + wakeup-latency-us = <130>;
> + };
> +
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <250>;
> + exit-latency-us = <500>;
> + min-residency-us = <950>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <600>;
> + exit-latency-us = <1100>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> +
> + CPU_RETENTION_1_0: cpu-retention-1-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <90>;
> + };
> +
> + CLUSTER_RETENTION_1: cluster-retention-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <270>;
> + wakeup-latency-us = <100>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <100>;
> + min-residency-us = <300>;
> + wakeup-latency-us = <150>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <500>;
> + exit-latency-us = <1200>;
> + min-residency-us = <3500>;
> + wakeup-latency-us = <1300>;
> + };
> + };
> +
> +};
> +
> +Example 2 (ARM 32-bit, 8-cpu system, two clusters):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x0>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x1>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x2>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x3>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <200>;
> + exit-latency-us = <100>;
> + min-residency-us = <400>;
> + wakeup-latency-us = <250>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <500>;
> + exit-latency-us = <1500>;
> + min-residency-us = <2500>;
> + wakeup-latency-us = <1700>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <500>;
> + min-residency-us = <900>;
> + wakeup-latency-us = <600>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <800>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6500>;
> + wakeup-latency-us = <2300>;
> + };
> + };
> +
> +};
> +
> +===========================================
> +5 - References
> +===========================================
> +
> +[1] ARM Linux Kernel documentation - CPUs bindings
> + Documentation/devicetree/bindings/arm/cpus.txt
> +
> +[2] ARM Linux Kernel documentation - PSCI bindings
> + Documentation/devicetree/bindings/arm/psci.txt
> +
> +[3] ARM Server Base System Architecture (SBSA)
> + http://infocenter.arm.com/help/index.jsp
> +
> +[4] ARM Architecture Reference Manuals
> + http://infocenter.arm.com/help/index.jsp
> +
> +[5] ePAPR standard
> + https://www.power.org/documentation/epapr-version-1-1/
> diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
> index b4a58f3..5aa40ed 100644
> --- a/Documentation/devicetree/bindings/arm/psci.txt
> +++ b/Documentation/devicetree/bindings/arm/psci.txt
> @@ -50,6 +50,16 @@ Main node optional properties:
>
> - migrate : Function ID for MIGRATE operation
>
> +Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
> +state nodes, as per bindings in [1]) must specify the following properties:
> +
> +- arm,psci-suspend-param
> + Usage: Required for state nodes[1] if the corresponding
> + idle-states node entry-method property is set
> + to "psci".
> + Value type: <u32>
> + Definition: power_state parameter to pass to the PSCI
> + suspend call.
>
> Example:
>
> @@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
> migrate = <0x95c10003>;
> };
>
> -
> Case 2: PSCI v0.2 only
>
> psci {
> @@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
>
> ...
> };
> +
> +[1] Kernel documentation - ARM idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
@ 2014-07-22 12:38 ` Rob Herring
0 siblings, 0 replies; 44+ messages in thread
From: Rob Herring @ 2014-07-22 12:38 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 21, 2014 at 11:06 AM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> ARM based platforms implement a variety of power management schemes that
> allow processors to enter idle states at run-time.
> The parameters defining these idle states vary on a per-platform basis forcing
> the OS to hardcode the state parameters in platform specific static tables
> whose size grows as the number of platforms supported in the kernel increases
> and hampers device drivers standardization.
>
> Therefore, this patch aims at standardizing idle state device tree bindings
> for ARM platforms. Bindings define idle state parameters inclusive of entry
> methods and state latencies, to allow operating systems to retrieve the
> configuration entries from the device tree and initialize the related power
> management drivers, paving the way for common code in the kernel to deal with
> idle states and removing the need for static data in current and previous
> kernel versions.
>
> ARM64 platforms require the DT to define an entry-method property
> for idle states.
>
> On system implementing PSCI as an enable-method to enter low-power
> states the PSCI CPU suspend method requires the power_state parameter to
> be passed to the PSCI CPU suspend function.
>
> This parameter is specific to a power state and platform specific,
> therefore must be provided by firmware to the OS in order to enable
> proper call sequence.
>
> Thus, this patch also adds a property in the PSCI bindings that
> describes how the PSCI CPU suspend power_state parameter should be
> defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Rob
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 8 +
> .../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
> Documentation/devicetree/bindings/arm/psci.txt | 14 +-
> 3 files changed, 700 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 1fe72a0..a44d4fd 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
> Value type: <phandle>
> Definition: Specifies the ACC[2] node associated with this CPU.
>
> + - cpu-idle-states
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition:
> + # List of phandles to idle state nodes supported
> + by this cpu [3].
>
> Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> @@ -411,3 +417,5 @@ cpus {
> --
> [1] arm/msm/qcom,saw2.txt
> [2] arm/msm/qcom,kpss-acc.txt
> +[3] ARM Linux kernel documentation - idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
> new file mode 100644
> index 0000000..37375c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/idle-states.txt
> @@ -0,0 +1,679 @@
> +==========================================
> +ARM idle states binding description
> +==========================================
> +
> +==========================================
> +1 - Introduction
> +==========================================
> +
> +ARM systems contain HW capable of managing power consumption dynamically,
> +where cores can be put in different low-power states (ranging from simple
> +wfi to power gating) according to OS PM policies. The CPU states representing
> +the range of dynamic idle states that a processor can enter at run-time, can be
> +specified through device tree bindings representing the parameters required
> +to enter/exit specific idle states on a given processor.
> +
> +According to the Server Base System Architecture document (SBSA, [3]), the
> +power states an ARM CPU can be put into are identified by the following list:
> +
> +- Running
> +- Idle_standby
> +- Idle_retention
> +- Sleep
> +- Off
> +
> +The power states described in the SBSA document define the basic CPU states on
> +top of which ARM platforms implement power management schemes that allow an OS
> +PM implementation to put the processor in different idle states (which include
> +states listed above; "off" state is not an idle state since it does not have
> +wake-up capabilities, hence it is not considered in this document).
> +
> +Idle state parameters (eg entry latency) are platform specific and need to be
> +characterized with bindings that provide the required information to OS PM
> +code so that it can build the required tables and use them at runtime.
> +
> +The device tree binding definition for ARM idle states is the subject of this
> +document.
> +
> +===========================================
> +2 - idle-states definitions
> +===========================================
> +
> +Idle states are characterized for a specific system through a set of
> +timing and energy related properties, that underline the HW behaviour
> +triggered upon idle states entry and exit.
> +
> +The following diagram depicts the CPU execution phases and related timing
> +properties required to enter and exit an idle state:
> +
> +..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
> + | | | | |
> +
> + |<------ entry ------->|
> + | latency |
> + |<- exit ->|
> + | latency |
> + |<-------- min-residency -------->|
> + |<------- wakeup-latency ------->|
> +
> + Diagram 1: CPU idle state execution phases
> +
> +EXEC: Normal CPU execution.
> +
> +PREP: Preparation phase before committing the hardware to idle mode
> + like cache flushing. This is abortable on pending wake-up
> + event conditions. The abort latency is assumed to be negligible
> + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
> + goes back to EXEC. This phase is optional. If not abortable,
> + this should be included in the ENTRY phase instead.
> +
> +ENTRY: The hardware is committed to idle mode. This period must run
> + to completion up to IDLE before anything else can happen.
> +
> +IDLE: This is the actual energy-saving idle period. This may last
> + between 0 and infinite time, until a wake-up event occurs.
> +
> +EXIT: Period during which the CPU is brought back to operational
> + mode (EXEC).
> +
> +entry-latency: Worst case latency required to enter the idle state. The
> +exit-latency may be guaranteed only after entry-latency has passed.
> +
> +min-residency: Minimum period, including preparation and entry, for a given
> +idle state to be worthwhile energywise.
> +
> +wakeup-latency: Maximum delay between the signaling of a wake-up event and the
> +CPU being able to execute normal code again. If not specified, this is assumed
> +to be entry-latency + exit-latency.
> +
> +These timing parameters can be used by an OS in different circumstances.
> +
> +An idle CPU requires the expected min-residency time to select the most
> +appropriate idle state based on the expected expiry time of the next IRQ
> +(ie wake-up) that causes the CPU to return to the EXEC phase.
> +
> +An operating system scheduler may need to compute the shortest wake-up delay
> +for CPUs in the system by detecting how long will it take to get a CPU out
> +of an idle state, eg:
> +
> +wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
> +
> +In other words, the scheduler can make its scheduling decision by selecting
> +(eg waking-up) the CPU with the shortest wake-up latency.
> +The wake-up latency must take into account the entry latency if that period
> +has not expired. The abortable nature of the PREP period can be ignored
> +if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
> +the worst case since it depends on the CPU operating conditions, ie caches
> +state).
> +
> +An OS has to reliably probe the wakeup-latency since some devices can enforce
> +latency constraints guarantees to work properly, so the OS has to detect the
> +worst case wake-up latency it can incur if a CPU is allowed to enter an
> +idle state, and possibly to prevent that to guarantee reliable device
> +functioning.
> +
> +The min-residency time parameter deserves further explanation since it is
> +expressed in time units but must factor in energy consumption coefficients.
> +
> +The energy consumption of a cpu when it enters a power state can be roughly
> +characterised by the following graph:
> +
> + |
> + |
> + |
> + e |
> + n | /---
> + e | /------
> + r | /------
> + g | /-----
> + y | /------
> + | ----
> + | /|
> + | / |
> + | / |
> + | / |
> + | / |
> + | / |
> + |/ |
> + -----|-------+----------------------------------
> + 0| 1 time(ms)
> +
> + Graph 1: Energy vs time example
> +
> +The graph is split in two parts delimited by time 1ms on the X-axis.
> +The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
> +and denotes the energy costs incurred whilst entering and leaving the idle
> +state.
> +The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
> +shallower slope and essentially represents the energy consumption of the idle
> +state.
> +
> +min-residency is defined for a given idle state as the minimum expected
> +residency time for a state (inclusive of preparation and entry) after
> +which choosing that state become the most energy efficient option. A good
> +way to visualise this, is by taking the same graph above and comparing some
> +states energy consumptions plots.
> +
> +For sake of simplicity, let's consider a system with two idle states IDLE1,
> +and IDLE2:
> +
> + |
> + |
> + |
> + | /-- IDLE1
> + e | /---
> + n | /----
> + e | /---
> + r | /-----/--------- IDLE2
> + g | /-------/---------
> + y | ------------ /---|
> + | / /---- |
> + | / /--- |
> + | / /---- |
> + | / /--- |
> + | --- |
> + | / |
> + | / |
> + |/ | time
> + ---/----------------------------+------------------------
> + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
> + |
> + IDLE2-min-residency
> +
> + Graph 2: idle states min-residency example
> +
> +In graph 2 above, that takes into account idle states entry/exit energy
> +costs, it is clear that if the idle state residency time (ie time till next
> +wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
> +choice energywise.
> +
> +This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
> +than IDLE2.
> +
> +However, the lower power consumption (ie shallower energy curve slope) of idle
> +state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
> +efficient.
> +
> +The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
> +shallower states in a system with multiple idle states) is defined
> +IDLE2-min-residency and corresponds to the time when energy consumption of
> +IDLE1 and IDLE2 states breaks even.
> +
> +The definitions provided in this section underpin the idle states
> +properties specification that is the subject of the following sections.
> +
> +===========================================
> +3 - idle-states node
> +===========================================
> +
> +ARM processor idle states are defined within the idle-states node, which is
> +a direct child of the cpus node [1] and provides a container where the
> +processor idle states, defined as device tree nodes, are listed.
> +
> +- idle-states node
> +
> + Usage: Optional - On ARM systems, it is a container of processor idle
> + states nodes. If the system does not provide CPU
> + power management capabilities or the processor just
> + supports idle_standby an idle-states node is not
> + required.
> +
> + Description: idle-states node is a container node, where its
> + subnodes describe the CPU idle states.
> +
> + Node name must be "idle-states".
> +
> + The idle-states node's parent node must be the cpus node.
> +
> + The idle-states node's child nodes can be:
> +
> + - one or more state nodes
> +
> + Any other configuration is considered invalid.
> +
> + An idle-states node defines the following properties:
> +
> + - entry-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version.
> + # On ARM v8 64-bit this property is required and must
> + be one of:
> + - "psci" (see bindings in [2])
> + # On ARM 32-bit systems this property is optional
> +
> +The nodes describing the idle states (state) can only be defined within the
> +idle-states node, any other configuration is considered invalid and therefore
> +must be ignored.
> +
> +===========================================
> +4 - state node
> +===========================================
> +
> +A state node represents an idle state description and must be defined as
> +follows:
> +
> +- state node
> +
> + Description: must be child of the idle-states node
> +
> + The state node name shall follow standard device tree naming
> + rules ([5], 2.2.1 "Node names"), in particular state nodes which
> + are siblings within a single common parent must be given a unique name.
> +
> + The idle state entered by executing the wfi instruction (idle_standby
> + SBSA,[3][4]) is considered standard on all ARM platforms and therefore
> + must not be listed.
> +
> + With the definitions provided above, the following list represents
> + the valid properties for a state node:
> +
> + - compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must be "arm,idle-state".
> +
> + - local-timer-stop
> + Usage: See definition
> + Value type: <none>
> + Definition: if present the CPU local timer control logic is
> + lost on state entry, otherwise it is retained.
> +
> + - entry-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency in
> + microseconds required to enter the idle state.
> + The exit-latency-us duration may be guaranteed
> + only after entry-latency-us has passed.
> +
> + - exit-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency
> + in microseconds required to exit the idle state.
> +
> + - min-residency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing minimum residency duration
> + in microseconds, inclusive of preparation and
> + entry, for this idle state to be considered
> + worthwhile energy wise (refer to section 2 of
> + this document for a complete description).
> +
> + - wakeup-latency-us:
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing maximum delay between the
> + signaling of a wake-up event and the CPU being
> + able to execute normal code again. If omitted,
> + this is assumed to be equal to:
> +
> + entry-latency-us + exit-latency-us
> +
> + It is important to supply this value on systems
> + where the duration of PREP phase (see diagram 1,
> + section 2) is non-neglibigle.
> + In such systems entry-latency-us + exit-latency-us
> + will exceed wakeup-latency-us by this duration.
> +
> + In addition to the properties listed above, a state node may require
> + additional properties specifics to the entry-method defined in the
> + idle-states node, please refer to the entry-method bindings
> + documentation for properties definitions.
> +
> +===========================================
> +4 - Examples
> +===========================================
> +
> +Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu at 10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU5: cpu at 10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU6: cpu at 10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU7: cpu at 10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU8: cpu at 100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU9: cpu at 100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU10: cpu at 100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU11: cpu at 100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU12: cpu at 100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU13: cpu at 100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU14: cpu at 100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU15: cpu at 100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_RETENTION_0_0: cpu-retention-0-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <80>;
> + };
> +
> + CLUSTER_RETENTION_0: cluster-retention-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <250>;
> + wakeup-latency-us = <130>;
> + };
> +
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <250>;
> + exit-latency-us = <500>;
> + min-residency-us = <950>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <600>;
> + exit-latency-us = <1100>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> +
> + CPU_RETENTION_1_0: cpu-retention-1-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <90>;
> + };
> +
> + CLUSTER_RETENTION_1: cluster-retention-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <270>;
> + wakeup-latency-us = <100>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <100>;
> + min-residency-us = <300>;
> + wakeup-latency-us = <150>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <500>;
> + exit-latency-us = <1200>;
> + min-residency-us = <3500>;
> + wakeup-latency-us = <1300>;
> + };
> + };
> +
> +};
> +
> +Example 2 (ARM 32-bit, 8-cpu system, two clusters):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x0>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x1>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x2>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x3>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU5: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU6: cpu at 102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU7: cpu at 103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <200>;
> + exit-latency-us = <100>;
> + min-residency-us = <400>;
> + wakeup-latency-us = <250>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <500>;
> + exit-latency-us = <1500>;
> + min-residency-us = <2500>;
> + wakeup-latency-us = <1700>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <500>;
> + min-residency-us = <900>;
> + wakeup-latency-us = <600>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <800>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6500>;
> + wakeup-latency-us = <2300>;
> + };
> + };
> +
> +};
> +
> +===========================================
> +5 - References
> +===========================================
> +
> +[1] ARM Linux Kernel documentation - CPUs bindings
> + Documentation/devicetree/bindings/arm/cpus.txt
> +
> +[2] ARM Linux Kernel documentation - PSCI bindings
> + Documentation/devicetree/bindings/arm/psci.txt
> +
> +[3] ARM Server Base System Architecture (SBSA)
> + http://infocenter.arm.com/help/index.jsp
> +
> +[4] ARM Architecture Reference Manuals
> + http://infocenter.arm.com/help/index.jsp
> +
> +[5] ePAPR standard
> + https://www.power.org/documentation/epapr-version-1-1/
> diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
> index b4a58f3..5aa40ed 100644
> --- a/Documentation/devicetree/bindings/arm/psci.txt
> +++ b/Documentation/devicetree/bindings/arm/psci.txt
> @@ -50,6 +50,16 @@ Main node optional properties:
>
> - migrate : Function ID for MIGRATE operation
>
> +Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
> +state nodes, as per bindings in [1]) must specify the following properties:
> +
> +- arm,psci-suspend-param
> + Usage: Required for state nodes[1] if the corresponding
> + idle-states node entry-method property is set
> + to "psci".
> + Value type: <u32>
> + Definition: power_state parameter to pass to the PSCI
> + suspend call.
>
> Example:
>
> @@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
> migrate = <0x95c10003>;
> };
>
> -
> Case 2: PSCI v0.2 only
>
> psci {
> @@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
>
> ...
> };
> +
> +[1] Kernel documentation - ARM idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-23 15:52 ` Daniel Lezcano
-1 siblings, 0 replies; 44+ messages in thread
From: Daniel Lezcano @ 2014-07-23 15:52 UTC (permalink / raw)
To: Lorenzo Pieralisi, linux-arm-kernel, linux-pm
Cc: devicetree, Mark Rutland, Sudeep Holla, Catalin Marinas,
Charles Garcia Tobin, Nicolas Pitre, Rob Herring, Grant Likely,
Peter De Schrijver, Santosh Shilimkar, Amit Kucheria,
Vincent Guittot, Antti Miettinen, Stephen Boyd, Kevin Hilman,
Sebastian Capella, Tomasz Figa, Mark Brown, Paul Walmsley,
Chander Kashyap, Geoff Levand, Bartlomiej Zolnierkiewicz
On 07/21/2014 06:06 PM, Lorenzo Pieralisi wrote:
> ARM based platforms implement a variety of power management schemes that
> allow processors to enter idle states at run-time.
> The parameters defining these idle states vary on a per-platform basis forcing
> the OS to hardcode the state parameters in platform specific static tables
> whose size grows as the number of platforms supported in the kernel increases
> and hampers device drivers standardization.
>
> Therefore, this patch aims at standardizing idle state device tree bindings
> for ARM platforms. Bindings define idle state parameters inclusive of entry
> methods and state latencies, to allow operating systems to retrieve the
> configuration entries from the device tree and initialize the related power
> management drivers, paving the way for common code in the kernel to deal with
> idle states and removing the need for static data in current and previous
> kernel versions.
>
> ARM64 platforms require the DT to define an entry-method property
> for idle states.
>
> On system implementing PSCI as an enable-method to enter low-power
> states the PSCI CPU suspend method requires the power_state parameter to
> be passed to the PSCI CPU suspend function.
>
> This parameter is specific to a power state and platform specific,
> therefore must be provided by firmware to the OS in order to enable
> proper call sequence.
>
> Thus, this patch also adds a property in the PSCI bindings that
> describes how the PSCI CPU suspend power_state parameter should be
> defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 8 +
> .../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
> Documentation/devicetree/bindings/arm/psci.txt | 14 +-
> 3 files changed, 700 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 1fe72a0..a44d4fd 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
> Value type: <phandle>
> Definition: Specifies the ACC[2] node associated with this CPU.
>
> + - cpu-idle-states
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition:
> + # List of phandles to idle state nodes supported
> + by this cpu [3].
>
> Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> @@ -411,3 +417,5 @@ cpus {
> --
> [1] arm/msm/qcom,saw2.txt
> [2] arm/msm/qcom,kpss-acc.txt
> +[3] ARM Linux kernel documentation - idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
> new file mode 100644
> index 0000000..37375c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/idle-states.txt
> @@ -0,0 +1,679 @@
> +==========================================
> +ARM idle states binding description
> +==========================================
> +
> +==========================================
> +1 - Introduction
> +==========================================
> +
> +ARM systems contain HW capable of managing power consumption dynamically,
> +where cores can be put in different low-power states (ranging from simple
> +wfi to power gating) according to OS PM policies. The CPU states representing
> +the range of dynamic idle states that a processor can enter at run-time, can be
> +specified through device tree bindings representing the parameters required
> +to enter/exit specific idle states on a given processor.
> +
> +According to the Server Base System Architecture document (SBSA, [3]), the
> +power states an ARM CPU can be put into are identified by the following list:
> +
> +- Running
> +- Idle_standby
> +- Idle_retention
> +- Sleep
> +- Off
> +
> +The power states described in the SBSA document define the basic CPU states on
> +top of which ARM platforms implement power management schemes that allow an OS
> +PM implementation to put the processor in different idle states (which include
> +states listed above; "off" state is not an idle state since it does not have
> +wake-up capabilities, hence it is not considered in this document).
> +
> +Idle state parameters (eg entry latency) are platform specific and need to be
> +characterized with bindings that provide the required information to OS PM
> +code so that it can build the required tables and use them at runtime.
> +
> +The device tree binding definition for ARM idle states is the subject of this
> +document.
> +
> +===========================================
> +2 - idle-states definitions
> +===========================================
> +
> +Idle states are characterized for a specific system through a set of
> +timing and energy related properties, that underline the HW behaviour
> +triggered upon idle states entry and exit.
> +
> +The following diagram depicts the CPU execution phases and related timing
> +properties required to enter and exit an idle state:
> +
> +..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
> + | | | | |
> +
> + |<------ entry ------->|
> + | latency |
> + |<- exit ->|
> + | latency |
> + |<-------- min-residency -------->|
> + |<------- wakeup-latency ------->|
> +
> + Diagram 1: CPU idle state execution phases
> +
> +EXEC: Normal CPU execution.
> +
> +PREP: Preparation phase before committing the hardware to idle mode
> + like cache flushing. This is abortable on pending wake-up
> + event conditions. The abort latency is assumed to be negligible
> + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
> + goes back to EXEC. This phase is optional. If not abortable,
> + this should be included in the ENTRY phase instead.
> +
> +ENTRY: The hardware is committed to idle mode. This period must run
> + to completion up to IDLE before anything else can happen.
> +
> +IDLE: This is the actual energy-saving idle period. This may last
> + between 0 and infinite time, until a wake-up event occurs.
> +
> +EXIT: Period during which the CPU is brought back to operational
> + mode (EXEC).
> +
> +entry-latency: Worst case latency required to enter the idle state. The
> +exit-latency may be guaranteed only after entry-latency has passed.
> +
> +min-residency: Minimum period, including preparation and entry, for a given
> +idle state to be worthwhile energywise.
> +
> +wakeup-latency: Maximum delay between the signaling of a wake-up event and the
> +CPU being able to execute normal code again. If not specified, this is assumed
> +to be entry-latency + exit-latency.
> +
> +These timing parameters can be used by an OS in different circumstances.
> +
> +An idle CPU requires the expected min-residency time to select the most
> +appropriate idle state based on the expected expiry time of the next IRQ
> +(ie wake-up) that causes the CPU to return to the EXEC phase.
> +
> +An operating system scheduler may need to compute the shortest wake-up delay
> +for CPUs in the system by detecting how long will it take to get a CPU out
> +of an idle state, eg:
> +
> +wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
> +
> +In other words, the scheduler can make its scheduling decision by selecting
> +(eg waking-up) the CPU with the shortest wake-up latency.
> +The wake-up latency must take into account the entry latency if that period
> +has not expired. The abortable nature of the PREP period can be ignored
> +if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
> +the worst case since it depends on the CPU operating conditions, ie caches
> +state).
> +
> +An OS has to reliably probe the wakeup-latency since some devices can enforce
> +latency constraints guarantees to work properly, so the OS has to detect the
> +worst case wake-up latency it can incur if a CPU is allowed to enter an
> +idle state, and possibly to prevent that to guarantee reliable device
> +functioning.
> +
> +The min-residency time parameter deserves further explanation since it is
> +expressed in time units but must factor in energy consumption coefficients.
> +
> +The energy consumption of a cpu when it enters a power state can be roughly
> +characterised by the following graph:
> +
> + |
> + |
> + |
> + e |
> + n | /---
> + e | /------
> + r | /------
> + g | /-----
> + y | /------
> + | ----
> + | /|
> + | / |
> + | / |
> + | / |
> + | / |
> + | / |
> + |/ |
> + -----|-------+----------------------------------
> + 0| 1 time(ms)
> +
> + Graph 1: Energy vs time example
> +
> +The graph is split in two parts delimited by time 1ms on the X-axis.
> +The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
> +and denotes the energy costs incurred whilst entering and leaving the idle
> +state.
> +The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
> +shallower slope and essentially represents the energy consumption of the idle
> +state.
> +
> +min-residency is defined for a given idle state as the minimum expected
> +residency time for a state (inclusive of preparation and entry) after
> +which choosing that state become the most energy efficient option. A good
> +way to visualise this, is by taking the same graph above and comparing some
> +states energy consumptions plots.
> +
> +For sake of simplicity, let's consider a system with two idle states IDLE1,
> +and IDLE2:
> +
> + |
> + |
> + |
> + | /-- IDLE1
> + e | /---
> + n | /----
> + e | /---
> + r | /-----/--------- IDLE2
> + g | /-------/---------
> + y | ------------ /---|
> + | / /---- |
> + | / /--- |
> + | / /---- |
> + | / /--- |
> + | --- |
> + | / |
> + | / |
> + |/ | time
> + ---/----------------------------+------------------------
> + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
> + |
> + IDLE2-min-residency
> +
> + Graph 2: idle states min-residency example
> +
> +In graph 2 above, that takes into account idle states entry/exit energy
> +costs, it is clear that if the idle state residency time (ie time till next
> +wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
> +choice energywise.
> +
> +This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
> +than IDLE2.
> +
> +However, the lower power consumption (ie shallower energy curve slope) of idle
> +state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
> +efficient.
> +
> +The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
> +shallower states in a system with multiple idle states) is defined
> +IDLE2-min-residency and corresponds to the time when energy consumption of
> +IDLE1 and IDLE2 states breaks even.
> +
> +The definitions provided in this section underpin the idle states
> +properties specification that is the subject of the following sections.
> +
> +===========================================
> +3 - idle-states node
> +===========================================
> +
> +ARM processor idle states are defined within the idle-states node, which is
> +a direct child of the cpus node [1] and provides a container where the
> +processor idle states, defined as device tree nodes, are listed.
> +
> +- idle-states node
> +
> + Usage: Optional - On ARM systems, it is a container of processor idle
> + states nodes. If the system does not provide CPU
> + power management capabilities or the processor just
> + supports idle_standby an idle-states node is not
> + required.
> +
> + Description: idle-states node is a container node, where its
> + subnodes describe the CPU idle states.
> +
> + Node name must be "idle-states".
> +
> + The idle-states node's parent node must be the cpus node.
> +
> + The idle-states node's child nodes can be:
> +
> + - one or more state nodes
> +
> + Any other configuration is considered invalid.
> +
> + An idle-states node defines the following properties:
> +
> + - entry-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version.
> + # On ARM v8 64-bit this property is required and must
> + be one of:
> + - "psci" (see bindings in [2])
> + # On ARM 32-bit systems this property is optional
> +
> +The nodes describing the idle states (state) can only be defined within the
> +idle-states node, any other configuration is considered invalid and therefore
> +must be ignored.
> +
> +===========================================
> +4 - state node
> +===========================================
> +
> +A state node represents an idle state description and must be defined as
> +follows:
> +
> +- state node
> +
> + Description: must be child of the idle-states node
> +
> + The state node name shall follow standard device tree naming
> + rules ([5], 2.2.1 "Node names"), in particular state nodes which
> + are siblings within a single common parent must be given a unique name.
> +
> + The idle state entered by executing the wfi instruction (idle_standby
> + SBSA,[3][4]) is considered standard on all ARM platforms and therefore
> + must not be listed.
> +
> + With the definitions provided above, the following list represents
> + the valid properties for a state node:
> +
> + - compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must be "arm,idle-state".
> +
> + - local-timer-stop
> + Usage: See definition
> + Value type: <none>
> + Definition: if present the CPU local timer control logic is
> + lost on state entry, otherwise it is retained.
> +
> + - entry-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency in
> + microseconds required to enter the idle state.
> + The exit-latency-us duration may be guaranteed
> + only after entry-latency-us has passed.
> +
> + - exit-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency
> + in microseconds required to exit the idle state.
> +
> + - min-residency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing minimum residency duration
> + in microseconds, inclusive of preparation and
> + entry, for this idle state to be considered
> + worthwhile energy wise (refer to section 2 of
> + this document for a complete description).
> +
> + - wakeup-latency-us:
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing maximum delay between the
> + signaling of a wake-up event and the CPU being
> + able to execute normal code again. If omitted,
> + this is assumed to be equal to:
> +
> + entry-latency-us + exit-latency-us
> +
> + It is important to supply this value on systems
> + where the duration of PREP phase (see diagram 1,
> + section 2) is non-neglibigle.
> + In such systems entry-latency-us + exit-latency-us
> + will exceed wakeup-latency-us by this duration.
> +
> + In addition to the properties listed above, a state node may require
> + additional properties specifics to the entry-method defined in the
> + idle-states node, please refer to the entry-method bindings
> + documentation for properties definitions.
> +
> +===========================================
> +4 - Examples
> +===========================================
> +
> +Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu@10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU5: cpu@10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU6: cpu@10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU7: cpu@10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU8: cpu@100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU9: cpu@100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU10: cpu@100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU11: cpu@100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU12: cpu@100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU13: cpu@100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU14: cpu@100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU15: cpu@100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_RETENTION_0_0: cpu-retention-0-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <80>;
> + };
> +
> + CLUSTER_RETENTION_0: cluster-retention-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <250>;
> + wakeup-latency-us = <130>;
> + };
> +
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <250>;
> + exit-latency-us = <500>;
> + min-residency-us = <950>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <600>;
> + exit-latency-us = <1100>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> +
> + CPU_RETENTION_1_0: cpu-retention-1-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <90>;
> + };
> +
> + CLUSTER_RETENTION_1: cluster-retention-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <270>;
> + wakeup-latency-us = <100>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <100>;
> + min-residency-us = <300>;
> + wakeup-latency-us = <150>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <500>;
> + exit-latency-us = <1200>;
> + min-residency-us = <3500>;
> + wakeup-latency-us = <1300>;
> + };
> + };
> +
> +};
> +
> +Example 2 (ARM 32-bit, 8-cpu system, two clusters):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x0>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x1>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x2>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x3>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <200>;
> + exit-latency-us = <100>;
> + min-residency-us = <400>;
> + wakeup-latency-us = <250>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <500>;
> + exit-latency-us = <1500>;
> + min-residency-us = <2500>;
> + wakeup-latency-us = <1700>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <500>;
> + min-residency-us = <900>;
> + wakeup-latency-us = <600>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <800>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6500>;
> + wakeup-latency-us = <2300>;
> + };
> + };
> +
> +};
> +
> +===========================================
> +5 - References
> +===========================================
> +
> +[1] ARM Linux Kernel documentation - CPUs bindings
> + Documentation/devicetree/bindings/arm/cpus.txt
> +
> +[2] ARM Linux Kernel documentation - PSCI bindings
> + Documentation/devicetree/bindings/arm/psci.txt
> +
> +[3] ARM Server Base System Architecture (SBSA)
> + http://infocenter.arm.com/help/index.jsp
> +
> +[4] ARM Architecture Reference Manuals
> + http://infocenter.arm.com/help/index.jsp
> +
> +[5] ePAPR standard
> + https://www.power.org/documentation/epapr-version-1-1/
> diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
> index b4a58f3..5aa40ed 100644
> --- a/Documentation/devicetree/bindings/arm/psci.txt
> +++ b/Documentation/devicetree/bindings/arm/psci.txt
> @@ -50,6 +50,16 @@ Main node optional properties:
>
> - migrate : Function ID for MIGRATE operation
>
> +Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
> +state nodes, as per bindings in [1]) must specify the following properties:
> +
> +- arm,psci-suspend-param
> + Usage: Required for state nodes[1] if the corresponding
> + idle-states node entry-method property is set
> + to "psci".
> + Value type: <u32>
> + Definition: power_state parameter to pass to the PSCI
> + suspend call.
>
> Example:
>
> @@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
> migrate = <0x95c10003>;
> };
>
> -
> Case 2: PSCI v0.2 only
>
> psci {
> @@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
>
> ...
> };
> +
> +[1] Kernel documentation - ARM idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
>
--
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^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 1/7] Documentation: arm: define DT idle states bindings
@ 2014-07-23 15:52 ` Daniel Lezcano
0 siblings, 0 replies; 44+ messages in thread
From: Daniel Lezcano @ 2014-07-23 15:52 UTC (permalink / raw)
To: linux-arm-kernel
On 07/21/2014 06:06 PM, Lorenzo Pieralisi wrote:
> ARM based platforms implement a variety of power management schemes that
> allow processors to enter idle states at run-time.
> The parameters defining these idle states vary on a per-platform basis forcing
> the OS to hardcode the state parameters in platform specific static tables
> whose size grows as the number of platforms supported in the kernel increases
> and hampers device drivers standardization.
>
> Therefore, this patch aims at standardizing idle state device tree bindings
> for ARM platforms. Bindings define idle state parameters inclusive of entry
> methods and state latencies, to allow operating systems to retrieve the
> configuration entries from the device tree and initialize the related power
> management drivers, paving the way for common code in the kernel to deal with
> idle states and removing the need for static data in current and previous
> kernel versions.
>
> ARM64 platforms require the DT to define an entry-method property
> for idle states.
>
> On system implementing PSCI as an enable-method to enter low-power
> states the PSCI CPU suspend method requires the power_state parameter to
> be passed to the PSCI CPU suspend function.
>
> This parameter is specific to a power state and platform specific,
> therefore must be provided by firmware to the OS in order to enable
> proper call sequence.
>
> Thus, this patch also adds a property in the PSCI bindings that
> describes how the PSCI CPU suspend power_state parameter should be
> defined in DT in all device nodes that rely on PSCI CPU suspend method usage.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.txt | 8 +
> .../devicetree/bindings/arm/idle-states.txt | 679 +++++++++++++++++++++
> Documentation/devicetree/bindings/arm/psci.txt | 14 +-
> 3 files changed, 700 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
> index 1fe72a0..a44d4fd 100644
> --- a/Documentation/devicetree/bindings/arm/cpus.txt
> +++ b/Documentation/devicetree/bindings/arm/cpus.txt
> @@ -215,6 +215,12 @@ nodes to be present and contain the properties described below.
> Value type: <phandle>
> Definition: Specifies the ACC[2] node associated with this CPU.
>
> + - cpu-idle-states
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition:
> + # List of phandles to idle state nodes supported
> + by this cpu [3].
>
> Example 1 (dual-cluster big.LITTLE system 32-bit):
>
> @@ -411,3 +417,5 @@ cpus {
> --
> [1] arm/msm/qcom,saw2.txt
> [2] arm/msm/qcom,kpss-acc.txt
> +[3] ARM Linux kernel documentation - idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
> diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
> new file mode 100644
> index 0000000..37375c7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/idle-states.txt
> @@ -0,0 +1,679 @@
> +==========================================
> +ARM idle states binding description
> +==========================================
> +
> +==========================================
> +1 - Introduction
> +==========================================
> +
> +ARM systems contain HW capable of managing power consumption dynamically,
> +where cores can be put in different low-power states (ranging from simple
> +wfi to power gating) according to OS PM policies. The CPU states representing
> +the range of dynamic idle states that a processor can enter at run-time, can be
> +specified through device tree bindings representing the parameters required
> +to enter/exit specific idle states on a given processor.
> +
> +According to the Server Base System Architecture document (SBSA, [3]), the
> +power states an ARM CPU can be put into are identified by the following list:
> +
> +- Running
> +- Idle_standby
> +- Idle_retention
> +- Sleep
> +- Off
> +
> +The power states described in the SBSA document define the basic CPU states on
> +top of which ARM platforms implement power management schemes that allow an OS
> +PM implementation to put the processor in different idle states (which include
> +states listed above; "off" state is not an idle state since it does not have
> +wake-up capabilities, hence it is not considered in this document).
> +
> +Idle state parameters (eg entry latency) are platform specific and need to be
> +characterized with bindings that provide the required information to OS PM
> +code so that it can build the required tables and use them at runtime.
> +
> +The device tree binding definition for ARM idle states is the subject of this
> +document.
> +
> +===========================================
> +2 - idle-states definitions
> +===========================================
> +
> +Idle states are characterized for a specific system through a set of
> +timing and energy related properties, that underline the HW behaviour
> +triggered upon idle states entry and exit.
> +
> +The following diagram depicts the CPU execution phases and related timing
> +properties required to enter and exit an idle state:
> +
> +..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
> + | | | | |
> +
> + |<------ entry ------->|
> + | latency |
> + |<- exit ->|
> + | latency |
> + |<-------- min-residency -------->|
> + |<------- wakeup-latency ------->|
> +
> + Diagram 1: CPU idle state execution phases
> +
> +EXEC: Normal CPU execution.
> +
> +PREP: Preparation phase before committing the hardware to idle mode
> + like cache flushing. This is abortable on pending wake-up
> + event conditions. The abort latency is assumed to be negligible
> + (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
> + goes back to EXEC. This phase is optional. If not abortable,
> + this should be included in the ENTRY phase instead.
> +
> +ENTRY: The hardware is committed to idle mode. This period must run
> + to completion up to IDLE before anything else can happen.
> +
> +IDLE: This is the actual energy-saving idle period. This may last
> + between 0 and infinite time, until a wake-up event occurs.
> +
> +EXIT: Period during which the CPU is brought back to operational
> + mode (EXEC).
> +
> +entry-latency: Worst case latency required to enter the idle state. The
> +exit-latency may be guaranteed only after entry-latency has passed.
> +
> +min-residency: Minimum period, including preparation and entry, for a given
> +idle state to be worthwhile energywise.
> +
> +wakeup-latency: Maximum delay between the signaling of a wake-up event and the
> +CPU being able to execute normal code again. If not specified, this is assumed
> +to be entry-latency + exit-latency.
> +
> +These timing parameters can be used by an OS in different circumstances.
> +
> +An idle CPU requires the expected min-residency time to select the most
> +appropriate idle state based on the expected expiry time of the next IRQ
> +(ie wake-up) that causes the CPU to return to the EXEC phase.
> +
> +An operating system scheduler may need to compute the shortest wake-up delay
> +for CPUs in the system by detecting how long will it take to get a CPU out
> +of an idle state, eg:
> +
> +wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
> +
> +In other words, the scheduler can make its scheduling decision by selecting
> +(eg waking-up) the CPU with the shortest wake-up latency.
> +The wake-up latency must take into account the entry latency if that period
> +has not expired. The abortable nature of the PREP period can be ignored
> +if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
> +the worst case since it depends on the CPU operating conditions, ie caches
> +state).
> +
> +An OS has to reliably probe the wakeup-latency since some devices can enforce
> +latency constraints guarantees to work properly, so the OS has to detect the
> +worst case wake-up latency it can incur if a CPU is allowed to enter an
> +idle state, and possibly to prevent that to guarantee reliable device
> +functioning.
> +
> +The min-residency time parameter deserves further explanation since it is
> +expressed in time units but must factor in energy consumption coefficients.
> +
> +The energy consumption of a cpu when it enters a power state can be roughly
> +characterised by the following graph:
> +
> + |
> + |
> + |
> + e |
> + n | /---
> + e | /------
> + r | /------
> + g | /-----
> + y | /------
> + | ----
> + | /|
> + | / |
> + | / |
> + | / |
> + | / |
> + | / |
> + |/ |
> + -----|-------+----------------------------------
> + 0| 1 time(ms)
> +
> + Graph 1: Energy vs time example
> +
> +The graph is split in two parts delimited by time 1ms on the X-axis.
> +The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
> +and denotes the energy costs incurred whilst entering and leaving the idle
> +state.
> +The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
> +shallower slope and essentially represents the energy consumption of the idle
> +state.
> +
> +min-residency is defined for a given idle state as the minimum expected
> +residency time for a state (inclusive of preparation and entry) after
> +which choosing that state become the most energy efficient option. A good
> +way to visualise this, is by taking the same graph above and comparing some
> +states energy consumptions plots.
> +
> +For sake of simplicity, let's consider a system with two idle states IDLE1,
> +and IDLE2:
> +
> + |
> + |
> + |
> + | /-- IDLE1
> + e | /---
> + n | /----
> + e | /---
> + r | /-----/--------- IDLE2
> + g | /-------/---------
> + y | ------------ /---|
> + | / /---- |
> + | / /--- |
> + | / /---- |
> + | / /--- |
> + | --- |
> + | / |
> + | / |
> + |/ | time
> + ---/----------------------------+------------------------
> + |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
> + |
> + IDLE2-min-residency
> +
> + Graph 2: idle states min-residency example
> +
> +In graph 2 above, that takes into account idle states entry/exit energy
> +costs, it is clear that if the idle state residency time (ie time till next
> +wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
> +choice energywise.
> +
> +This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
> +than IDLE2.
> +
> +However, the lower power consumption (ie shallower energy curve slope) of idle
> +state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
> +efficient.
> +
> +The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
> +shallower states in a system with multiple idle states) is defined
> +IDLE2-min-residency and corresponds to the time when energy consumption of
> +IDLE1 and IDLE2 states breaks even.
> +
> +The definitions provided in this section underpin the idle states
> +properties specification that is the subject of the following sections.
> +
> +===========================================
> +3 - idle-states node
> +===========================================
> +
> +ARM processor idle states are defined within the idle-states node, which is
> +a direct child of the cpus node [1] and provides a container where the
> +processor idle states, defined as device tree nodes, are listed.
> +
> +- idle-states node
> +
> + Usage: Optional - On ARM systems, it is a container of processor idle
> + states nodes. If the system does not provide CPU
> + power management capabilities or the processor just
> + supports idle_standby an idle-states node is not
> + required.
> +
> + Description: idle-states node is a container node, where its
> + subnodes describe the CPU idle states.
> +
> + Node name must be "idle-states".
> +
> + The idle-states node's parent node must be the cpus node.
> +
> + The idle-states node's child nodes can be:
> +
> + - one or more state nodes
> +
> + Any other configuration is considered invalid.
> +
> + An idle-states node defines the following properties:
> +
> + - entry-method
> + Value type: <stringlist>
> + Usage and definition depend on ARM architecture version.
> + # On ARM v8 64-bit this property is required and must
> + be one of:
> + - "psci" (see bindings in [2])
> + # On ARM 32-bit systems this property is optional
> +
> +The nodes describing the idle states (state) can only be defined within the
> +idle-states node, any other configuration is considered invalid and therefore
> +must be ignored.
> +
> +===========================================
> +4 - state node
> +===========================================
> +
> +A state node represents an idle state description and must be defined as
> +follows:
> +
> +- state node
> +
> + Description: must be child of the idle-states node
> +
> + The state node name shall follow standard device tree naming
> + rules ([5], 2.2.1 "Node names"), in particular state nodes which
> + are siblings within a single common parent must be given a unique name.
> +
> + The idle state entered by executing the wfi instruction (idle_standby
> + SBSA,[3][4]) is considered standard on all ARM platforms and therefore
> + must not be listed.
> +
> + With the definitions provided above, the following list represents
> + the valid properties for a state node:
> +
> + - compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must be "arm,idle-state".
> +
> + - local-timer-stop
> + Usage: See definition
> + Value type: <none>
> + Definition: if present the CPU local timer control logic is
> + lost on state entry, otherwise it is retained.
> +
> + - entry-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency in
> + microseconds required to enter the idle state.
> + The exit-latency-us duration may be guaranteed
> + only after entry-latency-us has passed.
> +
> + - exit-latency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing worst case latency
> + in microseconds required to exit the idle state.
> +
> + - min-residency-us
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing minimum residency duration
> + in microseconds, inclusive of preparation and
> + entry, for this idle state to be considered
> + worthwhile energy wise (refer to section 2 of
> + this document for a complete description).
> +
> + - wakeup-latency-us:
> + Usage: Optional
> + Value type: <prop-encoded-array>
> + Definition: u32 value representing maximum delay between the
> + signaling of a wake-up event and the CPU being
> + able to execute normal code again. If omitted,
> + this is assumed to be equal to:
> +
> + entry-latency-us + exit-latency-us
> +
> + It is important to supply this value on systems
> + where the duration of PREP phase (see diagram 1,
> + section 2) is non-neglibigle.
> + In such systems entry-latency-us + exit-latency-us
> + will exceed wakeup-latency-us by this duration.
> +
> + In addition to the properties listed above, a state node may require
> + additional properties specifics to the entry-method defined in the
> + idle-states node, please refer to the entry-method bindings
> + documentation for properties definitions.
> +
> +===========================================
> +4 - Examples
> +===========================================
> +
> +Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <2>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu at 10000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU5: cpu at 10001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU6: cpu at 10100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU7: cpu at 10101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
> + &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU8: cpu at 100000000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU9: cpu at 100000001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x1>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU10: cpu at 100000100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU11: cpu at 100000101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU12: cpu at 100010000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU13: cpu at 100010001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU14: cpu at 100010100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU15: cpu at 100010101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1 0x10101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
> + &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + entry-method = "arm,psci";
> +
> + CPU_RETENTION_0_0: cpu-retention-0-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <80>;
> + };
> +
> + CLUSTER_RETENTION_0: cluster-retention-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <250>;
> + wakeup-latency-us = <130>;
> + };
> +
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <250>;
> + exit-latency-us = <500>;
> + min-residency-us = <950>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <600>;
> + exit-latency-us = <1100>;
> + min-residency-us = <2700>;
> + wakeup-latency-us = <1500>;
> + };
> +
> + CPU_RETENTION_1_0: cpu-retention-1-0 {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <20>;
> + exit-latency-us = <40>;
> + min-residency-us = <90>;
> + };
> +
> + CLUSTER_RETENTION_1: cluster-retention-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <50>;
> + exit-latency-us = <100>;
> + min-residency-us = <270>;
> + wakeup-latency-us = <100>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x0010000>;
> + entry-latency-us = <70>;
> + exit-latency-us = <100>;
> + min-residency-us = <300>;
> + wakeup-latency-us = <150>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + arm,psci-suspend-param = <0x1010000>;
> + entry-latency-us = <500>;
> + exit-latency-us = <1200>;
> + min-residency-us = <3500>;
> + wakeup-latency-us = <1300>;
> + };
> + };
> +
> +};
> +
> +Example 2 (ARM 32-bit, 8-cpu system, two clusters):
> +
> +cpus {
> + #size-cells = <0>;
> + #address-cells = <1>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x0>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x1>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x2>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a15";
> + reg = <0x3>;
> + cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
> + };
> +
> + CPU4: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x100>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU5: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x101>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU6: cpu at 102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x102>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + CPU7: cpu at 103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0x103>;
> + cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
> + };
> +
> + idle-states {
> + CPU_SLEEP_0_0: cpu-sleep-0-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <200>;
> + exit-latency-us = <100>;
> + min-residency-us = <400>;
> + wakeup-latency-us = <250>;
> + };
> +
> + CLUSTER_SLEEP_0: cluster-sleep-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <500>;
> + exit-latency-us = <1500>;
> + min-residency-us = <2500>;
> + wakeup-latency-us = <1700>;
> + };
> +
> + CPU_SLEEP_1_0: cpu-sleep-1-0 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <300>;
> + exit-latency-us = <500>;
> + min-residency-us = <900>;
> + wakeup-latency-us = <600>;
> + };
> +
> + CLUSTER_SLEEP_1: cluster-sleep-1 {
> + compatible = "arm,idle-state";
> + local-timer-stop;
> + entry-latency-us = <800>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6500>;
> + wakeup-latency-us = <2300>;
> + };
> + };
> +
> +};
> +
> +===========================================
> +5 - References
> +===========================================
> +
> +[1] ARM Linux Kernel documentation - CPUs bindings
> + Documentation/devicetree/bindings/arm/cpus.txt
> +
> +[2] ARM Linux Kernel documentation - PSCI bindings
> + Documentation/devicetree/bindings/arm/psci.txt
> +
> +[3] ARM Server Base System Architecture (SBSA)
> + http://infocenter.arm.com/help/index.jsp
> +
> +[4] ARM Architecture Reference Manuals
> + http://infocenter.arm.com/help/index.jsp
> +
> +[5] ePAPR standard
> + https://www.power.org/documentation/epapr-version-1-1/
> diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
> index b4a58f3..5aa40ed 100644
> --- a/Documentation/devicetree/bindings/arm/psci.txt
> +++ b/Documentation/devicetree/bindings/arm/psci.txt
> @@ -50,6 +50,16 @@ Main node optional properties:
>
> - migrate : Function ID for MIGRATE operation
>
> +Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
> +state nodes, as per bindings in [1]) must specify the following properties:
> +
> +- arm,psci-suspend-param
> + Usage: Required for state nodes[1] if the corresponding
> + idle-states node entry-method property is set
> + to "psci".
> + Value type: <u32>
> + Definition: power_state parameter to pass to the PSCI
> + suspend call.
>
> Example:
>
> @@ -64,7 +74,6 @@ Case 1: PSCI v0.1 only.
> migrate = <0x95c10003>;
> };
>
> -
> Case 2: PSCI v0.2 only
>
> psci {
> @@ -88,3 +97,6 @@ Case 3: PSCI v0.2 and PSCI v0.1.
>
> ...
> };
> +
> +[1] Kernel documentation - ARM idle states bindings
> + Documentation/devicetree/bindings/arm/idle-states.txt
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
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^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-23 16:07 ` Daniel Lezcano
-1 siblings, 0 replies; 44+ messages in thread
From: Daniel Lezcano @ 2014-07-23 16:07 UTC (permalink / raw)
To: Lorenzo Pieralisi, linux-arm-kernel, linux-pm
Cc: devicetree, Mark Rutland, Sudeep Holla, Catalin Marinas,
Charles Garcia Tobin, Nicolas Pitre, Rob Herring, Grant Likely,
Peter De Schrijver, Santosh Shilimkar, Amit Kucheria,
Vincent Guittot, Antti Miettinen, Stephen Boyd, Kevin Hilman,
Sebastian Capella, Tomasz Figa, Mark Brown, Paul Walmsley,
Chander Kashyap, Geoff Levand, Bartlomiej Zolnierkiewicz
On 07/21/2014 06:06 PM, Lorenzo Pieralisi wrote:
> On most common ARM systems, the low-power states a CPU can be put into are
> not discoverable in HW and require device tree bindings to describe
> power down suspend operations and idle states parameters.
>
> In order to enable DT based idle states and configure idle drivers, this
> patch implements the bulk infrastructure required to parse the device tree
> idle states bindings and initialize the corresponding CPUidle driver states
> data.
>
> The parsing API accepts a start index that defines the first idle state
> that should be initialized by the parsing code in order to give new and
> legacy driver flexibility over which states should be parsed using the
> new DT mechanism.
>
> The idle states list is obtained from the first cpu in the driver
> cpumask, which implicitly means the parsing code expects idle states
> (and related list of phandles) to be the same for all CPUs in the
> CPUidle driver mask. The kernel does not check this assumption, it must
> be enforced by the bootloader to ensure correct system behaviour.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This patch looks good for me but I have a couple of questions below.
> ---
> drivers/cpuidle/Kconfig | 8 +++
> drivers/cpuidle/Makefile | 1 +
> drivers/cpuidle/dt_idle_states.c | 138 +++++++++++++++++++++++++++++++++++++++
> drivers/cpuidle/dt_idle_states.h | 5 ++
> 4 files changed, 152 insertions(+)
> create mode 100644 drivers/cpuidle/dt_idle_states.c
> create mode 100644 drivers/cpuidle/dt_idle_states.h
>
> diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> index 1b96fb9..414e7a96 100644
> --- a/drivers/cpuidle/Kconfig
> +++ b/drivers/cpuidle/Kconfig
> @@ -30,6 +30,14 @@ config CPU_IDLE_GOV_MENU
> bool "Menu governor (for tickless system)"
> default y
>
> +config DT_IDLE_STATES
> + bool "Idle states DT support"
> + depends on ARM || ARM64
> + help
> + Allows the CPU idle framework to initialize CPU idle drivers
> + state data by using DT provided nodes compliant with idle states
> + device tree bindings.
> +
Wouldn't make sense to make this as an hidden option and let the
different drivers to set DT_IDLE_STATES if they depend on it ?
> menu "ARM CPU Idle Drivers"
> depends on ARM
> source "drivers/cpuidle/Kconfig.arm"
> diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
> index d8bb1ff..b27a062 100644
> --- a/drivers/cpuidle/Makefile
> +++ b/drivers/cpuidle/Makefile
> @@ -4,6 +4,7 @@
>
> obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
> obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
> +obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
>
> ##################################################################################
> # ARM SoC drivers
> diff --git a/drivers/cpuidle/dt_idle_states.c b/drivers/cpuidle/dt_idle_states.c
> new file mode 100644
> index 0000000..5413132
> --- /dev/null
> +++ b/drivers/cpuidle/dt_idle_states.c
> @@ -0,0 +1,138 @@
> +/*
> + * DT idle states parsing code.
> + *
> + * Copyright (C) 2014 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define pr_fmt(fmt) "DT idle-states: " fmt
> +
> +#include <linux/cpuidle.h>
> +#include <linux/cpumask.h>
> +#include <linux/errno.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +
> +#include "dt_idle_states.h"
> +
> +static int init_state_node(struct cpuidle_state *idle_state,
> + struct device_node *state_node)
> +{
> + int err;
> +
> + err = of_property_read_u32(state_node, "wakeup-latency-us",
> + &idle_state->exit_latency);
> + if (err) {
> + u32 entry_latency, exit_latency;
> +
> + err = of_property_read_u32(state_node, "entry-latency-us",
> + &entry_latency);
> + if (err) {
> + pr_debug(" * %s missing entry-latency-us property\n",
> + state_node->full_name);
> + return -EINVAL;
> + }
> +
> + err = of_property_read_u32(state_node, "exit-latency-us",
> + &exit_latency);
> + if (err) {
> + pr_debug(" * %s missing exit-latency-us property\n",
> + state_node->full_name);
> + return -EINVAL;
> + }
> + /*
> + * If wakeup-latency-us is missing, default to entry+exit
> + * latencies as defined in idle states bindings
> + */
> + idle_state->exit_latency = entry_latency + exit_latency;
> + }
> +
> + err = of_property_read_u32(state_node, "min-residency-us",
> + &idle_state->target_residency);
> + if (err) {
> + pr_debug(" * %s missing min-residency-us property\n",
> + state_node->full_name);
> + return -EINVAL;
> + }
> +
> + idle_state->flags = CPUIDLE_FLAG_TIME_VALID;
> + if (of_property_read_bool(state_node, "local-timer-stop"))
> + idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP;
> + /*
> + * TODO:
> + * replace with kstrdup and pointer assignment when name
> + * and desc become string pointers
> + */
> + strncpy(idle_state->name, state_node->name, CPUIDLE_NAME_LEN - 1);
> + strncpy(idle_state->desc, state_node->name, CPUIDLE_DESC_LEN - 1);
> + return 0;
> +}
> +
> +/**
> + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> + * idle driver states array
> + *
> + * @drv: Pointer to CPU idle driver to be initialized
> + * @start_idx: First idle state index to be initialized
> + *
> + * On success the states array in the cpuidle driver contains
> + * initialized entries in the states array, starting from index start_idx.
> + *
> + * Return:
> + * 0 on success
> + * <0 on failure
> + */
> +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> +{
> + unsigned int i, state_idx = start_idx;
> + struct cpuidle_state *idle_state;
> + struct device_node *state_node, *cpu_node;
> +
> +
> + if (state_idx >= CPUIDLE_STATE_MAX)
> + return -EINVAL;
> + /*
> + * We get the idle states for the first logical cpu in the
> + * driver mask. The kernel does not check idle states on all
> + * cpus in the driver mask, they are assumed to be the same
> + * by default.
> + */
> + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
> +
> + for (i = 0; ; i++) {
> + int err;
> +
> + state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> + if (!state_node)
> + break;
> +
> + if (state_idx == CPUIDLE_STATE_MAX) {
> + pr_warn("State index reached static CPU idle driver states array size\n");
> + break;
> + }
> +
> + idle_state = &drv->states[state_idx++];
> + err = init_state_node(idle_state, state_node);
> + if (err)
As the init_state_node error traces are in pr_debug level, a pr_err
would help here IMO.
> + return err;
> + }
> +
> + /*
> + * If no idle states are detected, return an error and let the idle
> + * driver initialization fail accordingly since initializing a driver
> + * with simple WFI as an idle state is equivalent to letting the
> + * kernel run the default idle loop.
> + */
> + if (!i)
> + return -ENODATA;
> +
> + drv->state_count = state_idx;
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(dt_init_idle_driver);
> diff --git a/drivers/cpuidle/dt_idle_states.h b/drivers/cpuidle/dt_idle_states.h
> new file mode 100644
> index 0000000..728c37c
> --- /dev/null
> +++ b/drivers/cpuidle/dt_idle_states.h
> @@ -0,0 +1,5 @@
> +#ifndef __DT_IDLE_STATES
> +#define __DT_IDLE_STATES
> +
> +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx);
> +#endif
>
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
@ 2014-07-23 16:07 ` Daniel Lezcano
0 siblings, 0 replies; 44+ messages in thread
From: Daniel Lezcano @ 2014-07-23 16:07 UTC (permalink / raw)
To: linux-arm-kernel
On 07/21/2014 06:06 PM, Lorenzo Pieralisi wrote:
> On most common ARM systems, the low-power states a CPU can be put into are
> not discoverable in HW and require device tree bindings to describe
> power down suspend operations and idle states parameters.
>
> In order to enable DT based idle states and configure idle drivers, this
> patch implements the bulk infrastructure required to parse the device tree
> idle states bindings and initialize the corresponding CPUidle driver states
> data.
>
> The parsing API accepts a start index that defines the first idle state
> that should be initialized by the parsing code in order to give new and
> legacy driver flexibility over which states should be parsed using the
> new DT mechanism.
>
> The idle states list is obtained from the first cpu in the driver
> cpumask, which implicitly means the parsing code expects idle states
> (and related list of phandles) to be the same for all CPUs in the
> CPUidle driver mask. The kernel does not check this assumption, it must
> be enforced by the bootloader to ensure correct system behaviour.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
This patch looks good for me but I have a couple of questions below.
> ---
> drivers/cpuidle/Kconfig | 8 +++
> drivers/cpuidle/Makefile | 1 +
> drivers/cpuidle/dt_idle_states.c | 138 +++++++++++++++++++++++++++++++++++++++
> drivers/cpuidle/dt_idle_states.h | 5 ++
> 4 files changed, 152 insertions(+)
> create mode 100644 drivers/cpuidle/dt_idle_states.c
> create mode 100644 drivers/cpuidle/dt_idle_states.h
>
> diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> index 1b96fb9..414e7a96 100644
> --- a/drivers/cpuidle/Kconfig
> +++ b/drivers/cpuidle/Kconfig
> @@ -30,6 +30,14 @@ config CPU_IDLE_GOV_MENU
> bool "Menu governor (for tickless system)"
> default y
>
> +config DT_IDLE_STATES
> + bool "Idle states DT support"
> + depends on ARM || ARM64
> + help
> + Allows the CPU idle framework to initialize CPU idle drivers
> + state data by using DT provided nodes compliant with idle states
> + device tree bindings.
> +
Wouldn't make sense to make this as an hidden option and let the
different drivers to set DT_IDLE_STATES if they depend on it ?
> menu "ARM CPU Idle Drivers"
> depends on ARM
> source "drivers/cpuidle/Kconfig.arm"
> diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
> index d8bb1ff..b27a062 100644
> --- a/drivers/cpuidle/Makefile
> +++ b/drivers/cpuidle/Makefile
> @@ -4,6 +4,7 @@
>
> obj-y += cpuidle.o driver.o governor.o sysfs.o governors/
> obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
> +obj-$(CONFIG_DT_IDLE_STATES) += dt_idle_states.o
>
> ##################################################################################
> # ARM SoC drivers
> diff --git a/drivers/cpuidle/dt_idle_states.c b/drivers/cpuidle/dt_idle_states.c
> new file mode 100644
> index 0000000..5413132
> --- /dev/null
> +++ b/drivers/cpuidle/dt_idle_states.c
> @@ -0,0 +1,138 @@
> +/*
> + * DT idle states parsing code.
> + *
> + * Copyright (C) 2014 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define pr_fmt(fmt) "DT idle-states: " fmt
> +
> +#include <linux/cpuidle.h>
> +#include <linux/cpumask.h>
> +#include <linux/errno.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +
> +#include "dt_idle_states.h"
> +
> +static int init_state_node(struct cpuidle_state *idle_state,
> + struct device_node *state_node)
> +{
> + int err;
> +
> + err = of_property_read_u32(state_node, "wakeup-latency-us",
> + &idle_state->exit_latency);
> + if (err) {
> + u32 entry_latency, exit_latency;
> +
> + err = of_property_read_u32(state_node, "entry-latency-us",
> + &entry_latency);
> + if (err) {
> + pr_debug(" * %s missing entry-latency-us property\n",
> + state_node->full_name);
> + return -EINVAL;
> + }
> +
> + err = of_property_read_u32(state_node, "exit-latency-us",
> + &exit_latency);
> + if (err) {
> + pr_debug(" * %s missing exit-latency-us property\n",
> + state_node->full_name);
> + return -EINVAL;
> + }
> + /*
> + * If wakeup-latency-us is missing, default to entry+exit
> + * latencies as defined in idle states bindings
> + */
> + idle_state->exit_latency = entry_latency + exit_latency;
> + }
> +
> + err = of_property_read_u32(state_node, "min-residency-us",
> + &idle_state->target_residency);
> + if (err) {
> + pr_debug(" * %s missing min-residency-us property\n",
> + state_node->full_name);
> + return -EINVAL;
> + }
> +
> + idle_state->flags = CPUIDLE_FLAG_TIME_VALID;
> + if (of_property_read_bool(state_node, "local-timer-stop"))
> + idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP;
> + /*
> + * TODO:
> + * replace with kstrdup and pointer assignment when name
> + * and desc become string pointers
> + */
> + strncpy(idle_state->name, state_node->name, CPUIDLE_NAME_LEN - 1);
> + strncpy(idle_state->desc, state_node->name, CPUIDLE_DESC_LEN - 1);
> + return 0;
> +}
> +
> +/**
> + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> + * idle driver states array
> + *
> + * @drv: Pointer to CPU idle driver to be initialized
> + * @start_idx: First idle state index to be initialized
> + *
> + * On success the states array in the cpuidle driver contains
> + * initialized entries in the states array, starting from index start_idx.
> + *
> + * Return:
> + * 0 on success
> + * <0 on failure
> + */
> +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> +{
> + unsigned int i, state_idx = start_idx;
> + struct cpuidle_state *idle_state;
> + struct device_node *state_node, *cpu_node;
> +
> +
> + if (state_idx >= CPUIDLE_STATE_MAX)
> + return -EINVAL;
> + /*
> + * We get the idle states for the first logical cpu in the
> + * driver mask. The kernel does not check idle states on all
> + * cpus in the driver mask, they are assumed to be the same
> + * by default.
> + */
> + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
> +
> + for (i = 0; ; i++) {
> + int err;
> +
> + state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> + if (!state_node)
> + break;
> +
> + if (state_idx == CPUIDLE_STATE_MAX) {
> + pr_warn("State index reached static CPU idle driver states array size\n");
> + break;
> + }
> +
> + idle_state = &drv->states[state_idx++];
> + err = init_state_node(idle_state, state_node);
> + if (err)
As the init_state_node error traces are in pr_debug level, a pr_err
would help here IMO.
> + return err;
> + }
> +
> + /*
> + * If no idle states are detected, return an error and let the idle
> + * driver initialization fail accordingly since initializing a driver
> + * with simple WFI as an idle state is equivalent to letting the
> + * kernel run the default idle loop.
> + */
> + if (!i)
> + return -ENODATA;
> +
> + drv->state_count = state_idx;
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(dt_init_idle_driver);
> diff --git a/drivers/cpuidle/dt_idle_states.h b/drivers/cpuidle/dt_idle_states.h
> new file mode 100644
> index 0000000..728c37c
> --- /dev/null
> +++ b/drivers/cpuidle/dt_idle_states.h
> @@ -0,0 +1,5 @@
> +#ifndef __DT_IDLE_STATES
> +#define __DT_IDLE_STATES
> +
> +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx);
> +#endif
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 4/7] arm64: add PSCI CPU_SUSPEND based cpu_suspend support
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-23 16:15 ` Ashwin Chaugule
-1 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 16:15 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Daniel Lezcano, linux-arm-kernel,
Grant Likely, Charles Garcia Tobin, Devicetree List,
Kevin Hilman, linux-pm, Sebastian Capella, Rob Herring,
Antti Miettinen, Paul Walmsley, Geoff Levand, Peter De Schrijver,
Stephen Boyd, Amit Kucheria, Bartlomiej
On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> This patch implements the cpu_suspend cpu operations method through
> the PSCI CPU SUSPEND API. The PSCI implementation translates the idle state
> index passed by the cpu_suspend core call into a valid PSCI state according to
> the PSCI states initialized at boot through the cpu_init_idle() CPU
> operations hook.
>
> Entry point is set to cpu_resume physical address, that represents the
> default kernel execution address following a CPU reset; for standby
> states the entry point address is useless and will therefore be ignored
> by the PSCI implementation.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm64/kernel/psci.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
> index a623c44..bbdf41d 100644
> --- a/arch/arm64/kernel/psci.c
> +++ b/arch/arm64/kernel/psci.c
> @@ -21,6 +21,7 @@
> #include <linux/reboot.h>
> #include <linux/pm.h>
> #include <linux/delay.h>
> +#include <linux/slab.h>
> #include <uapi/linux/psci.h>
>
> #include <asm/compiler.h>
> @@ -28,6 +29,7 @@
> #include <asm/errno.h>
> #include <asm/psci.h>
> #include <asm/smp_plat.h>
> +#include <asm/suspend.h>
> #include <asm/system_misc.h>
>
> #define PSCI_POWER_STATE_TYPE_STANDBY 0
> @@ -65,6 +67,8 @@ enum psci_function {
> PSCI_FN_MAX,
> };
>
> +static DEFINE_PER_CPU_READ_MOSTLY(struct psci_power_state *, psci_power_state);
> +
> static u32 psci_function_id[PSCI_FN_MAX];
>
> static int psci_to_linux_errno(int errno)
> @@ -93,6 +97,18 @@ static u32 psci_power_state_pack(struct psci_power_state state)
> & PSCI_0_2_POWER_STATE_AFFL_MASK);
> }
>
> +static void psci_power_state_unpack(u32 power_state,
> + struct psci_power_state *state)
> +{
> + state->id = (power_state & PSCI_0_2_POWER_STATE_ID_MASK) >>
> + PSCI_0_2_POWER_STATE_ID_SHIFT;
> + state->type = (power_state & PSCI_0_2_POWER_STATE_TYPE_MASK) >>
> + PSCI_0_2_POWER_STATE_TYPE_SHIFT;
> + state->affinity_level =
> + (power_state & PSCI_0_2_POWER_STATE_AFFL_MASK) >>
> + PSCI_0_2_POWER_STATE_AFFL_SHIFT;
> +}
> +
> /*
> * The following two functions are invoked via the invoke_psci_fn pointer
> * and will not be inlined, allowing us to piggyback on the AAPCS.
> @@ -199,6 +215,61 @@ static int psci_migrate_info_type(void)
> return err;
> }
>
> +static int cpu_psci_cpu_init_idle(struct device_node *cpu_node,
> + unsigned int cpu)
> +{
> + int i, ret, count = 0;
> + struct psci_power_state *psci_states;
> + struct device_node *state_node;
> +
> + /*
> + * If the PSCI cpu_suspend function hook has not been initialized
> + * idle states must not be enabled, so bail out
> + */
> + if (!psci_ops.cpu_suspend)
> + return -EOPNOTSUPP;
> +
> + /* Count idle states */
> + while ((state_node = of_parse_phandle(cpu_node, "cpu-idle-states",
> + count)))
> + count++;
> +
> + if (!count)
> + return -ENODEV;
> +
> + psci_states = kcalloc(count, sizeof(*psci_states), GFP_KERNEL);
> + if (!psci_states) {
> + pr_warn("idle state psci_state allocation failed\n");
> + return -ENOMEM;
> + }
> +
> + for (i = 0; i < count; i++) {
> + u32 psci_power_state;
> +
> + state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> +
> + ret = of_property_read_u32(state_node,
> + "arm,psci-suspend-param",
> + &psci_power_state);
> + if (ret) {
> + pr_warn(" * %s missing arm,psci-suspend-param property\n",
> + state_node->full_name);
> + goto free_mem;
> + }
> +
> + pr_debug("psci-power-state %#x index %d\n", psci_power_state,
> + i);
> + psci_power_state_unpack(psci_power_state, &psci_states[i]);
> + }
> + /* Idle states parsed correctly, initialize per-cpu pointer */
> + per_cpu(psci_power_state, cpu) = psci_states;
> + return 0;
> +
> +free_mem:
> + kfree(psci_states);
> + return ret;
> +}
> +
> static int get_set_conduit_method(struct device_node *np)
> {
> const char *method;
> @@ -436,8 +507,23 @@ static int cpu_psci_cpu_kill(unsigned int cpu)
> #endif
> #endif
>
> +static int __maybe_unused cpu_psci_cpu_suspend(unsigned long index)
> +{
> + struct psci_power_state *state = __get_cpu_var(psci_power_state);
> + /*
> + * idle state index 0 corresponds to wfi, should never be called
> + * from the cpu_suspend operations
> + */
> + if (WARN_ON_ONCE(!index))
> + return -EINVAL;
> +
> + return psci_ops.cpu_suspend(state[index - 1],
> + virt_to_phys(cpu_resume));
> +}
> +
> const struct cpu_operations cpu_psci_ops = {
> .name = "psci",
> + .cpu_init_idle = cpu_psci_cpu_init_idle,
> #ifdef CONFIG_SMP
> .cpu_init = cpu_psci_cpu_init,
> .cpu_prepare = cpu_psci_cpu_prepare,
> @@ -448,5 +534,8 @@ const struct cpu_operations cpu_psci_ops = {
> .cpu_kill = cpu_psci_cpu_kill,
> #endif
> #endif
> +#ifdef CONFIG_ARM64_CPU_SUSPEND
> + .cpu_suspend = cpu_psci_cpu_suspend,
> +#endif
> };
>
> --
> 1.9.1
Reviewed-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 4/7] arm64: add PSCI CPU_SUSPEND based cpu_suspend support
@ 2014-07-23 16:15 ` Ashwin Chaugule
0 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 16:15 UTC (permalink / raw)
To: linux-arm-kernel
On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> This patch implements the cpu_suspend cpu operations method through
> the PSCI CPU SUSPEND API. The PSCI implementation translates the idle state
> index passed by the cpu_suspend core call into a valid PSCI state according to
> the PSCI states initialized at boot through the cpu_init_idle() CPU
> operations hook.
>
> Entry point is set to cpu_resume physical address, that represents the
> default kernel execution address following a CPU reset; for standby
> states the entry point address is useless and will therefore be ignored
> by the PSCI implementation.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> arch/arm64/kernel/psci.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
> index a623c44..bbdf41d 100644
> --- a/arch/arm64/kernel/psci.c
> +++ b/arch/arm64/kernel/psci.c
> @@ -21,6 +21,7 @@
> #include <linux/reboot.h>
> #include <linux/pm.h>
> #include <linux/delay.h>
> +#include <linux/slab.h>
> #include <uapi/linux/psci.h>
>
> #include <asm/compiler.h>
> @@ -28,6 +29,7 @@
> #include <asm/errno.h>
> #include <asm/psci.h>
> #include <asm/smp_plat.h>
> +#include <asm/suspend.h>
> #include <asm/system_misc.h>
>
> #define PSCI_POWER_STATE_TYPE_STANDBY 0
> @@ -65,6 +67,8 @@ enum psci_function {
> PSCI_FN_MAX,
> };
>
> +static DEFINE_PER_CPU_READ_MOSTLY(struct psci_power_state *, psci_power_state);
> +
> static u32 psci_function_id[PSCI_FN_MAX];
>
> static int psci_to_linux_errno(int errno)
> @@ -93,6 +97,18 @@ static u32 psci_power_state_pack(struct psci_power_state state)
> & PSCI_0_2_POWER_STATE_AFFL_MASK);
> }
>
> +static void psci_power_state_unpack(u32 power_state,
> + struct psci_power_state *state)
> +{
> + state->id = (power_state & PSCI_0_2_POWER_STATE_ID_MASK) >>
> + PSCI_0_2_POWER_STATE_ID_SHIFT;
> + state->type = (power_state & PSCI_0_2_POWER_STATE_TYPE_MASK) >>
> + PSCI_0_2_POWER_STATE_TYPE_SHIFT;
> + state->affinity_level =
> + (power_state & PSCI_0_2_POWER_STATE_AFFL_MASK) >>
> + PSCI_0_2_POWER_STATE_AFFL_SHIFT;
> +}
> +
> /*
> * The following two functions are invoked via the invoke_psci_fn pointer
> * and will not be inlined, allowing us to piggyback on the AAPCS.
> @@ -199,6 +215,61 @@ static int psci_migrate_info_type(void)
> return err;
> }
>
> +static int cpu_psci_cpu_init_idle(struct device_node *cpu_node,
> + unsigned int cpu)
> +{
> + int i, ret, count = 0;
> + struct psci_power_state *psci_states;
> + struct device_node *state_node;
> +
> + /*
> + * If the PSCI cpu_suspend function hook has not been initialized
> + * idle states must not be enabled, so bail out
> + */
> + if (!psci_ops.cpu_suspend)
> + return -EOPNOTSUPP;
> +
> + /* Count idle states */
> + while ((state_node = of_parse_phandle(cpu_node, "cpu-idle-states",
> + count)))
> + count++;
> +
> + if (!count)
> + return -ENODEV;
> +
> + psci_states = kcalloc(count, sizeof(*psci_states), GFP_KERNEL);
> + if (!psci_states) {
> + pr_warn("idle state psci_state allocation failed\n");
> + return -ENOMEM;
> + }
> +
> + for (i = 0; i < count; i++) {
> + u32 psci_power_state;
> +
> + state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> +
> + ret = of_property_read_u32(state_node,
> + "arm,psci-suspend-param",
> + &psci_power_state);
> + if (ret) {
> + pr_warn(" * %s missing arm,psci-suspend-param property\n",
> + state_node->full_name);
> + goto free_mem;
> + }
> +
> + pr_debug("psci-power-state %#x index %d\n", psci_power_state,
> + i);
> + psci_power_state_unpack(psci_power_state, &psci_states[i]);
> + }
> + /* Idle states parsed correctly, initialize per-cpu pointer */
> + per_cpu(psci_power_state, cpu) = psci_states;
> + return 0;
> +
> +free_mem:
> + kfree(psci_states);
> + return ret;
> +}
> +
> static int get_set_conduit_method(struct device_node *np)
> {
> const char *method;
> @@ -436,8 +507,23 @@ static int cpu_psci_cpu_kill(unsigned int cpu)
> #endif
> #endif
>
> +static int __maybe_unused cpu_psci_cpu_suspend(unsigned long index)
> +{
> + struct psci_power_state *state = __get_cpu_var(psci_power_state);
> + /*
> + * idle state index 0 corresponds to wfi, should never be called
> + * from the cpu_suspend operations
> + */
> + if (WARN_ON_ONCE(!index))
> + return -EINVAL;
> +
> + return psci_ops.cpu_suspend(state[index - 1],
> + virt_to_phys(cpu_resume));
> +}
> +
> const struct cpu_operations cpu_psci_ops = {
> .name = "psci",
> + .cpu_init_idle = cpu_psci_cpu_init_idle,
> #ifdef CONFIG_SMP
> .cpu_init = cpu_psci_cpu_init,
> .cpu_prepare = cpu_psci_cpu_prepare,
> @@ -448,5 +534,8 @@ const struct cpu_operations cpu_psci_ops = {
> .cpu_kill = cpu_psci_cpu_kill,
> #endif
> #endif
> +#ifdef CONFIG_ARM64_CPU_SUSPEND
> + .cpu_suspend = cpu_psci_cpu_suspend,
> +#endif
> };
>
> --
> 1.9.1
Reviewed-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 6/7] drivers: cpuidle: initialize big.LITTLE driver through DT
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-23 16:26 ` Catalin Marinas
-1 siblings, 0 replies; 44+ messages in thread
From: Catalin Marinas @ 2014-07-23 16:26 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Tomasz Figa, Chander Kashyap, Vincent Guittot,
Nicolas Pitre, Daniel Lezcano, linux-arm-kernel, grant.likely,
Charles Garcia-Tobin, devicetree, Kevin Hilman, linux-pm,
Sebastian Capella, Mark Brown, Antti Miettinen, Paul Walmsley,
Geoff Levand, Peter De Schrijver, Stephen Boyd, Amit Kucheria,
Bartlomi
On Mon, Jul 21, 2014 at 05:06:25PM +0100, Lorenzo Pieralisi wrote:
> With the introduction of DT based idle states, CPUidle drivers for ARM
> can now initialize idle states data through properties in the device tree.
>
> This patch adds code to the big.LITTLE CPUidle driver to dynamically
> initialize idle states data through the updated device tree source file.
>
> Cc: Chander Kashyap <chander.kashyap@linaro.org>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
I think for this patch (and the exynos one) we should still allow the
driver to work fine with old DT. Basically if the information is not in
DT, fall back to the original static definitions.
--
Catalin
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 6/7] drivers: cpuidle: initialize big.LITTLE driver through DT
@ 2014-07-23 16:26 ` Catalin Marinas
0 siblings, 0 replies; 44+ messages in thread
From: Catalin Marinas @ 2014-07-23 16:26 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 21, 2014 at 05:06:25PM +0100, Lorenzo Pieralisi wrote:
> With the introduction of DT based idle states, CPUidle drivers for ARM
> can now initialize idle states data through properties in the device tree.
>
> This patch adds code to the big.LITTLE CPUidle driver to dynamically
> initialize idle states data through the updated device tree source file.
>
> Cc: Chander Kashyap <chander.kashyap@linaro.org>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
I think for this patch (and the exynos one) we should still allow the
driver to work fine with old DT. Basically if the information is not in
DT, fall back to the original static definitions.
--
Catalin
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-23 16:34 ` Ashwin Chaugule
-1 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 16:34 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Daniel Lezcano, linux-arm-kernel,
Grant Likely, Charles Garcia Tobin, Devicetree List,
Kevin Hilman, linux-pm, Sebastian Capella, Rob Herring,
Antti Miettinen, Paul Walmsley, Geoff Levand, Peter De Schrijver,
Stephen Boyd, Amit Kucheria, Bartlomiej
Hi Lorenzo,
On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> +/**
> + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> + * idle driver states array
> + *
> + * @drv: Pointer to CPU idle driver to be initialized
> + * @start_idx: First idle state index to be initialized
> + *
> + * On success the states array in the cpuidle driver contains
> + * initialized entries in the states array, starting from index start_idx.
> + *
> + * Return:
> + * 0 on success
> + * <0 on failure
> + */
> +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> +{
> + unsigned int i, state_idx = start_idx;
> + struct cpuidle_state *idle_state;
> + struct device_node *state_node, *cpu_node;
> +
> +
> + if (state_idx >= CPUIDLE_STATE_MAX)
> + return -EINVAL;
> + /*
> + * We get the idle states for the first logical cpu in the
> + * driver mask. The kernel does not check idle states on all
> + * cpus in the driver mask, they are assumed to be the same
> + * by default.
> + */
> + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
Is this an assumption for the short term? My understanding from the
corresponding ACPI discussions is that the order of idle states may
not necessarily be same for all CPUs, even for big.Little?
Cheers,
Ashwin
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
@ 2014-07-23 16:34 ` Ashwin Chaugule
0 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 16:34 UTC (permalink / raw)
To: linux-arm-kernel
Hi Lorenzo,
On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> +/**
> + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> + * idle driver states array
> + *
> + * @drv: Pointer to CPU idle driver to be initialized
> + * @start_idx: First idle state index to be initialized
> + *
> + * On success the states array in the cpuidle driver contains
> + * initialized entries in the states array, starting from index start_idx.
> + *
> + * Return:
> + * 0 on success
> + * <0 on failure
> + */
> +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> +{
> + unsigned int i, state_idx = start_idx;
> + struct cpuidle_state *idle_state;
> + struct device_node *state_node, *cpu_node;
> +
> +
> + if (state_idx >= CPUIDLE_STATE_MAX)
> + return -EINVAL;
> + /*
> + * We get the idle states for the first logical cpu in the
> + * driver mask. The kernel does not check idle states on all
> + * cpus in the driver mask, they are assumed to be the same
> + * by default.
> + */
> + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
Is this an assumption for the short term? My understanding from the
corresponding ACPI discussions is that the order of idle states may
not necessarily be same for all CPUs, even for big.Little?
Cheers,
Ashwin
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 5/7] drivers: cpuidle: CPU idle ARM64 driver
2014-07-21 16:06 ` Lorenzo Pieralisi
@ 2014-07-23 16:34 ` Ashwin Chaugule
-1 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 16:34 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Daniel Lezcano, linux-arm-kernel,
Grant Likely, Charles Garcia Tobin, Devicetree List,
Kevin Hilman, linux-pm, Sebastian Capella, Rob Herring,
Antti Miettinen, Paul Walmsley, Geoff Levand, Peter De Schrijver,
Stephen Boyd, Amit Kucheria, Bartlomiej
On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> This patch implements a generic CPU idle driver for ARM64 machines.
>
> It relies on the DT idle states infrastructure to initialize idle
> states count and respective parameters. Current code assumes the driver
> is managing idle states on all possible CPUs but can be easily
> generalized to support heterogenous systems and build cpumasks at
> runtime using MIDRs or DT cpu nodes compatible properties.
>
> The driver relies on the arm64 CPU operations to call the idle
> initialization hook used to parse and save suspend back-end specific
> idle states information upon probing.
>
> Idle state index 0 is always initialized as a simple wfi state, ie always
> considered present and functional on all ARM64 platforms.
>
> Idle state indices higher than 0 trigger idle state entry by calling
> the cpu_suspend function, that does save the CPU context and executes
> the CPU operations suspend back-end hook. cpu_suspend passes the idle
> state index as a parameter so that the CPU operations suspend back-end
> can retrieve the required idle state data by using the idle state
> index to execute a look-up on its internal data structures.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> drivers/cpuidle/Kconfig | 5 ++
> drivers/cpuidle/Kconfig.arm64 | 14 +++++
> drivers/cpuidle/Makefile | 4 ++
> drivers/cpuidle/cpuidle-arm64.c | 128 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 151 insertions(+)
> create mode 100644 drivers/cpuidle/Kconfig.arm64
> create mode 100644 drivers/cpuidle/cpuidle-arm64.c
>
> diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> index 414e7a96..ebf0c2e 100644
> --- a/drivers/cpuidle/Kconfig
> +++ b/drivers/cpuidle/Kconfig
> @@ -43,6 +43,11 @@ depends on ARM
> source "drivers/cpuidle/Kconfig.arm"
> endmenu
>
> +menu "ARM64 CPU Idle Drivers"
> +depends on ARM64
> +source "drivers/cpuidle/Kconfig.arm64"
> +endmenu
> +
> menu "MIPS CPU Idle Drivers"
> depends on MIPS
> source "drivers/cpuidle/Kconfig.mips"
> diff --git a/drivers/cpuidle/Kconfig.arm64 b/drivers/cpuidle/Kconfig.arm64
> new file mode 100644
> index 0000000..d0a08ed
> --- /dev/null
> +++ b/drivers/cpuidle/Kconfig.arm64
> @@ -0,0 +1,14 @@
> +#
> +# ARM64 CPU Idle drivers
> +#
> +
> +config ARM64_CPUIDLE
> + bool "Generic ARM64 CPU idle Driver"
> + select ARM64_CPU_SUSPEND
> + select DT_IDLE_STATES
> + help
> + Select this to enable generic cpuidle driver for ARM64.
> + It provides a generic idle driver whose idle states are configured
> + at run-time through DT nodes. The CPUidle suspend backend is
> + initialized by calling the CPU operations init idle hook
> + provided by architecture code.
> diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
> index b27a062..706cb7f 100644
> --- a/drivers/cpuidle/Makefile
> +++ b/drivers/cpuidle/Makefile
> @@ -23,6 +23,10 @@ obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o
> obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o
>
> ###############################################################################
> +# ARM64 drivers
> +obj-$(CONFIG_ARM64_CPUIDLE) += cpuidle-arm64.o
> +
> +###############################################################################
> # POWERPC drivers
> obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o
> obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o
> diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
> new file mode 100644
> index 0000000..1aeb426
> --- /dev/null
> +++ b/drivers/cpuidle/cpuidle-arm64.c
> @@ -0,0 +1,128 @@
> +/*
> + * ARM64 generic CPU idle driver.
> + *
> + * Copyright (C) 2014 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define pr_fmt(fmt) "CPUidle arm64: " fmt
> +
> +#include <linux/cpuidle.h>
> +#include <linux/cpumask.h>
> +#include <linux/cpu_pm.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/slab.h>
> +
> +#include <asm/cpuidle.h>
> +#include <asm/suspend.h>
> +
> +#include "dt_idle_states.h"
> +
> +/*
> + * arm_enter_idle_state - Programs CPU to enter the specified state
> + *
> + * dev: cpuidle device
> + * drv: cpuidle driver
> + * idx: state index
> + *
> + * Called from the CPUidle framework to program the device to the
> + * specified target state selected by the governor.
> + */
> +static int arm_enter_idle_state(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv, int idx)
> +{
> + int ret;
> +
> + if (!idx) {
> + cpu_do_idle();
> + return idx;
> + }
> +
> + ret = cpu_pm_enter();
> + if (!ret) {
> + /*
> + * Pass idle state index to cpu_suspend which in turn will
> + * call the CPU ops suspend protocol with idle index as a
> + * parameter.
> + */
> + ret = cpu_suspend(idx);
> +
> + cpu_pm_exit();
> + }
> +
> + return ret ? -1 : idx;
> +}
> +
> +struct cpuidle_driver arm64_idle_driver = {
> + .name = "arm64_idle",
> + .owner = THIS_MODULE,
> + /*
> + * State at index 0 is standby wfi and considered standard
> + * on all ARM platforms. If in some platforms simple wfi
> + * can't be used as "state 0", DT bindings must be implemented
> + * to work around this issue and allow installing a special
> + * handler for idle state index 0.
> + */
> + .states[0] = {
> + .enter = arm_enter_idle_state,
> + .exit_latency = 1,
> + .target_residency = 1,
> + .power_usage = UINT_MAX,
> + .flags = CPUIDLE_FLAG_TIME_VALID,
> + .name = "WFI",
> + .desc = "ARM64 WFI",
> + }
> +};
> +
> +/*
> + * arm64_idle_init
> + *
> + * Registers the arm64 specific cpuidle driver with the cpuidle
> + * framework. It relies on core code to parse the idle states
> + * and initialize them using driver data structures accordingly.
> + */
> +static int __init arm64_idle_init(void)
> +{
> + int i, ret;
> + struct cpuidle_driver *drv = &arm64_idle_driver;
> +
> + drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
> + if (!drv->cpumask)
> + return -ENOMEM;
> +
> + cpumask_copy(drv->cpumask, cpu_possible_mask);
> + /*
> + * Start at index 1, request idle state nodes to be filled
> + */
> + ret = dt_init_idle_driver(drv, 1);
> + if (ret)
> + goto free_mem;
> + /*
> + * Call arch CPU operations in order to initialize
> + * idle states suspend back-end specific data
> + */
> + for_each_cpu(i, drv->cpumask) {
> + ret = cpu_init_idle(i);
> + if (ret)
> + goto free_mem;
> + }
> +
> + for (i = 1; i < drv->state_count; i++)
> + drv->states[i].enter = arm_enter_idle_state;
> +
> + ret = cpuidle_register(drv, NULL);
> + if (ret)
> + goto free_mem;
> +
> + return 0;
> +free_mem:
> + kfree(drv->cpumask);
> + return ret;
> +}
> +device_initcall(arm64_idle_init);
> --
> 1.9.1
>
>
>
Reviewed-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 5/7] drivers: cpuidle: CPU idle ARM64 driver
@ 2014-07-23 16:34 ` Ashwin Chaugule
0 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 16:34 UTC (permalink / raw)
To: linux-arm-kernel
On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> This patch implements a generic CPU idle driver for ARM64 machines.
>
> It relies on the DT idle states infrastructure to initialize idle
> states count and respective parameters. Current code assumes the driver
> is managing idle states on all possible CPUs but can be easily
> generalized to support heterogenous systems and build cpumasks at
> runtime using MIDRs or DT cpu nodes compatible properties.
>
> The driver relies on the arm64 CPU operations to call the idle
> initialization hook used to parse and save suspend back-end specific
> idle states information upon probing.
>
> Idle state index 0 is always initialized as a simple wfi state, ie always
> considered present and functional on all ARM64 platforms.
>
> Idle state indices higher than 0 trigger idle state entry by calling
> the cpu_suspend function, that does save the CPU context and executes
> the CPU operations suspend back-end hook. cpu_suspend passes the idle
> state index as a parameter so that the CPU operations suspend back-end
> can retrieve the required idle state data by using the idle state
> index to execute a look-up on its internal data structures.
>
> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> ---
> drivers/cpuidle/Kconfig | 5 ++
> drivers/cpuidle/Kconfig.arm64 | 14 +++++
> drivers/cpuidle/Makefile | 4 ++
> drivers/cpuidle/cpuidle-arm64.c | 128 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 151 insertions(+)
> create mode 100644 drivers/cpuidle/Kconfig.arm64
> create mode 100644 drivers/cpuidle/cpuidle-arm64.c
>
> diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> index 414e7a96..ebf0c2e 100644
> --- a/drivers/cpuidle/Kconfig
> +++ b/drivers/cpuidle/Kconfig
> @@ -43,6 +43,11 @@ depends on ARM
> source "drivers/cpuidle/Kconfig.arm"
> endmenu
>
> +menu "ARM64 CPU Idle Drivers"
> +depends on ARM64
> +source "drivers/cpuidle/Kconfig.arm64"
> +endmenu
> +
> menu "MIPS CPU Idle Drivers"
> depends on MIPS
> source "drivers/cpuidle/Kconfig.mips"
> diff --git a/drivers/cpuidle/Kconfig.arm64 b/drivers/cpuidle/Kconfig.arm64
> new file mode 100644
> index 0000000..d0a08ed
> --- /dev/null
> +++ b/drivers/cpuidle/Kconfig.arm64
> @@ -0,0 +1,14 @@
> +#
> +# ARM64 CPU Idle drivers
> +#
> +
> +config ARM64_CPUIDLE
> + bool "Generic ARM64 CPU idle Driver"
> + select ARM64_CPU_SUSPEND
> + select DT_IDLE_STATES
> + help
> + Select this to enable generic cpuidle driver for ARM64.
> + It provides a generic idle driver whose idle states are configured
> + at run-time through DT nodes. The CPUidle suspend backend is
> + initialized by calling the CPU operations init idle hook
> + provided by architecture code.
> diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
> index b27a062..706cb7f 100644
> --- a/drivers/cpuidle/Makefile
> +++ b/drivers/cpuidle/Makefile
> @@ -23,6 +23,10 @@ obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o
> obj-$(CONFIG_MIPS_CPS_CPUIDLE) += cpuidle-cps.o
>
> ###############################################################################
> +# ARM64 drivers
> +obj-$(CONFIG_ARM64_CPUIDLE) += cpuidle-arm64.o
> +
> +###############################################################################
> # POWERPC drivers
> obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o
> obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o
> diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
> new file mode 100644
> index 0000000..1aeb426
> --- /dev/null
> +++ b/drivers/cpuidle/cpuidle-arm64.c
> @@ -0,0 +1,128 @@
> +/*
> + * ARM64 generic CPU idle driver.
> + *
> + * Copyright (C) 2014 ARM Ltd.
> + * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define pr_fmt(fmt) "CPUidle arm64: " fmt
> +
> +#include <linux/cpuidle.h>
> +#include <linux/cpumask.h>
> +#include <linux/cpu_pm.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/slab.h>
> +
> +#include <asm/cpuidle.h>
> +#include <asm/suspend.h>
> +
> +#include "dt_idle_states.h"
> +
> +/*
> + * arm_enter_idle_state - Programs CPU to enter the specified state
> + *
> + * dev: cpuidle device
> + * drv: cpuidle driver
> + * idx: state index
> + *
> + * Called from the CPUidle framework to program the device to the
> + * specified target state selected by the governor.
> + */
> +static int arm_enter_idle_state(struct cpuidle_device *dev,
> + struct cpuidle_driver *drv, int idx)
> +{
> + int ret;
> +
> + if (!idx) {
> + cpu_do_idle();
> + return idx;
> + }
> +
> + ret = cpu_pm_enter();
> + if (!ret) {
> + /*
> + * Pass idle state index to cpu_suspend which in turn will
> + * call the CPU ops suspend protocol with idle index as a
> + * parameter.
> + */
> + ret = cpu_suspend(idx);
> +
> + cpu_pm_exit();
> + }
> +
> + return ret ? -1 : idx;
> +}
> +
> +struct cpuidle_driver arm64_idle_driver = {
> + .name = "arm64_idle",
> + .owner = THIS_MODULE,
> + /*
> + * State at index 0 is standby wfi and considered standard
> + * on all ARM platforms. If in some platforms simple wfi
> + * can't be used as "state 0", DT bindings must be implemented
> + * to work around this issue and allow installing a special
> + * handler for idle state index 0.
> + */
> + .states[0] = {
> + .enter = arm_enter_idle_state,
> + .exit_latency = 1,
> + .target_residency = 1,
> + .power_usage = UINT_MAX,
> + .flags = CPUIDLE_FLAG_TIME_VALID,
> + .name = "WFI",
> + .desc = "ARM64 WFI",
> + }
> +};
> +
> +/*
> + * arm64_idle_init
> + *
> + * Registers the arm64 specific cpuidle driver with the cpuidle
> + * framework. It relies on core code to parse the idle states
> + * and initialize them using driver data structures accordingly.
> + */
> +static int __init arm64_idle_init(void)
> +{
> + int i, ret;
> + struct cpuidle_driver *drv = &arm64_idle_driver;
> +
> + drv->cpumask = kzalloc(cpumask_size(), GFP_KERNEL);
> + if (!drv->cpumask)
> + return -ENOMEM;
> +
> + cpumask_copy(drv->cpumask, cpu_possible_mask);
> + /*
> + * Start at index 1, request idle state nodes to be filled
> + */
> + ret = dt_init_idle_driver(drv, 1);
> + if (ret)
> + goto free_mem;
> + /*
> + * Call arch CPU operations in order to initialize
> + * idle states suspend back-end specific data
> + */
> + for_each_cpu(i, drv->cpumask) {
> + ret = cpu_init_idle(i);
> + if (ret)
> + goto free_mem;
> + }
> +
> + for (i = 1; i < drv->state_count; i++)
> + drv->states[i].enter = arm_enter_idle_state;
> +
> + ret = cpuidle_register(drv, NULL);
> + if (ret)
> + goto free_mem;
> +
> + return 0;
> +free_mem:
> + kfree(drv->cpumask);
> + return ret;
> +}
> +device_initcall(arm64_idle_init);
> --
> 1.9.1
>
>
>
Reviewed-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
2014-07-23 16:07 ` Daniel Lezcano
@ 2014-07-23 17:19 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-23 17:19 UTC (permalink / raw)
To: Daniel Lezcano
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Bartlomiej Zolnierkiewicz,
linux-arm-kernel, grant.likely, Charles Garcia-Tobin, devicetree,
Kevin Hilman, linux-pm, Sebastian Capella, Mark Brown,
Antti Miettinen, Paul Walmsley, Geoff Levand, Peter De Schrijver,
Stephen Boyd
On Wed, Jul 23, 2014 at 05:07:45PM +0100, Daniel Lezcano wrote:
> On 07/21/2014 06:06 PM, Lorenzo Pieralisi wrote:
> > On most common ARM systems, the low-power states a CPU can be put into are
> > not discoverable in HW and require device tree bindings to describe
> > power down suspend operations and idle states parameters.
> >
> > In order to enable DT based idle states and configure idle drivers, this
> > patch implements the bulk infrastructure required to parse the device tree
> > idle states bindings and initialize the corresponding CPUidle driver states
> > data.
> >
> > The parsing API accepts a start index that defines the first idle state
> > that should be initialized by the parsing code in order to give new and
> > legacy driver flexibility over which states should be parsed using the
> > new DT mechanism.
> >
> > The idle states list is obtained from the first cpu in the driver
> > cpumask, which implicitly means the parsing code expects idle states
> > (and related list of phandles) to be the same for all CPUs in the
> > CPUidle driver mask. The kernel does not check this assumption, it must
> > be enforced by the bootloader to ensure correct system behaviour.
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
> This patch looks good for me but I have a couple of questions below.
>
> > ---
> > drivers/cpuidle/Kconfig | 8 +++
> > drivers/cpuidle/Makefile | 1 +
> > drivers/cpuidle/dt_idle_states.c | 138 +++++++++++++++++++++++++++++++++++++++
> > drivers/cpuidle/dt_idle_states.h | 5 ++
> > 4 files changed, 152 insertions(+)
> > create mode 100644 drivers/cpuidle/dt_idle_states.c
> > create mode 100644 drivers/cpuidle/dt_idle_states.h
> >
> > diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> > index 1b96fb9..414e7a96 100644
> > --- a/drivers/cpuidle/Kconfig
> > +++ b/drivers/cpuidle/Kconfig
> > @@ -30,6 +30,14 @@ config CPU_IDLE_GOV_MENU
> > bool "Menu governor (for tickless system)"
> > default y
> >
> > +config DT_IDLE_STATES
> > + bool "Idle states DT support"
> > + depends on ARM || ARM64
> > + help
> > + Allows the CPU idle framework to initialize CPU idle drivers
> > + state data by using DT provided nodes compliant with idle states
> > + device tree bindings.
> > +
>
> Wouldn't make sense to make this as an hidden option and let the
> different drivers to set DT_IDLE_STATES if they depend on it ?
Yes, it would :)
[...]
> > +/**
> > + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> > + * idle driver states array
> > + *
> > + * @drv: Pointer to CPU idle driver to be initialized
> > + * @start_idx: First idle state index to be initialized
> > + *
> > + * On success the states array in the cpuidle driver contains
> > + * initialized entries in the states array, starting from index start_idx.
> > + *
> > + * Return:
> > + * 0 on success
> > + * <0 on failure
> > + */
> > +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> > +{
> > + unsigned int i, state_idx = start_idx;
> > + struct cpuidle_state *idle_state;
> > + struct device_node *state_node, *cpu_node;
> > +
> > +
> > + if (state_idx >= CPUIDLE_STATE_MAX)
> > + return -EINVAL;
> > + /*
> > + * We get the idle states for the first logical cpu in the
> > + * driver mask. The kernel does not check idle states on all
> > + * cpus in the driver mask, they are assumed to be the same
> > + * by default.
> > + */
> > + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
> > +
> > + for (i = 0; ; i++) {
> > + int err;
> > +
> > + state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> > + if (!state_node)
> > + break;
> > +
> > + if (state_idx == CPUIDLE_STATE_MAX) {
> > + pr_warn("State index reached static CPU idle driver states array size\n");
> > + break;
> > + }
> > +
> > + idle_state = &drv->states[state_idx++];
> > + err = init_state_node(idle_state, state_node);
> > + if (err)
>
> As the init_state_node error traces are in pr_debug level, a pr_err
> would help here IMO.
I think I agree, since at this point we have an idle state phandle and
we verified that the node it points at contains invalid bindings, so it is
fair to flag this up.
I will add it.
Thanks !
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
@ 2014-07-23 17:19 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-23 17:19 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 23, 2014 at 05:07:45PM +0100, Daniel Lezcano wrote:
> On 07/21/2014 06:06 PM, Lorenzo Pieralisi wrote:
> > On most common ARM systems, the low-power states a CPU can be put into are
> > not discoverable in HW and require device tree bindings to describe
> > power down suspend operations and idle states parameters.
> >
> > In order to enable DT based idle states and configure idle drivers, this
> > patch implements the bulk infrastructure required to parse the device tree
> > idle states bindings and initialize the corresponding CPUidle driver states
> > data.
> >
> > The parsing API accepts a start index that defines the first idle state
> > that should be initialized by the parsing code in order to give new and
> > legacy driver flexibility over which states should be parsed using the
> > new DT mechanism.
> >
> > The idle states list is obtained from the first cpu in the driver
> > cpumask, which implicitly means the parsing code expects idle states
> > (and related list of phandles) to be the same for all CPUs in the
> > CPUidle driver mask. The kernel does not check this assumption, it must
> > be enforced by the bootloader to ensure correct system behaviour.
> >
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
> This patch looks good for me but I have a couple of questions below.
>
> > ---
> > drivers/cpuidle/Kconfig | 8 +++
> > drivers/cpuidle/Makefile | 1 +
> > drivers/cpuidle/dt_idle_states.c | 138 +++++++++++++++++++++++++++++++++++++++
> > drivers/cpuidle/dt_idle_states.h | 5 ++
> > 4 files changed, 152 insertions(+)
> > create mode 100644 drivers/cpuidle/dt_idle_states.c
> > create mode 100644 drivers/cpuidle/dt_idle_states.h
> >
> > diff --git a/drivers/cpuidle/Kconfig b/drivers/cpuidle/Kconfig
> > index 1b96fb9..414e7a96 100644
> > --- a/drivers/cpuidle/Kconfig
> > +++ b/drivers/cpuidle/Kconfig
> > @@ -30,6 +30,14 @@ config CPU_IDLE_GOV_MENU
> > bool "Menu governor (for tickless system)"
> > default y
> >
> > +config DT_IDLE_STATES
> > + bool "Idle states DT support"
> > + depends on ARM || ARM64
> > + help
> > + Allows the CPU idle framework to initialize CPU idle drivers
> > + state data by using DT provided nodes compliant with idle states
> > + device tree bindings.
> > +
>
> Wouldn't make sense to make this as an hidden option and let the
> different drivers to set DT_IDLE_STATES if they depend on it ?
Yes, it would :)
[...]
> > +/**
> > + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> > + * idle driver states array
> > + *
> > + * @drv: Pointer to CPU idle driver to be initialized
> > + * @start_idx: First idle state index to be initialized
> > + *
> > + * On success the states array in the cpuidle driver contains
> > + * initialized entries in the states array, starting from index start_idx.
> > + *
> > + * Return:
> > + * 0 on success
> > + * <0 on failure
> > + */
> > +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> > +{
> > + unsigned int i, state_idx = start_idx;
> > + struct cpuidle_state *idle_state;
> > + struct device_node *state_node, *cpu_node;
> > +
> > +
> > + if (state_idx >= CPUIDLE_STATE_MAX)
> > + return -EINVAL;
> > + /*
> > + * We get the idle states for the first logical cpu in the
> > + * driver mask. The kernel does not check idle states on all
> > + * cpus in the driver mask, they are assumed to be the same
> > + * by default.
> > + */
> > + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
> > +
> > + for (i = 0; ; i++) {
> > + int err;
> > +
> > + state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
> > + if (!state_node)
> > + break;
> > +
> > + if (state_idx == CPUIDLE_STATE_MAX) {
> > + pr_warn("State index reached static CPU idle driver states array size\n");
> > + break;
> > + }
> > +
> > + idle_state = &drv->states[state_idx++];
> > + err = init_state_node(idle_state, state_node);
> > + if (err)
>
> As the init_state_node error traces are in pr_debug level, a pr_err
> would help here IMO.
I think I agree, since at this point we have an idle state phandle and
we verified that the node it points at contains invalid bindings, so it is
fair to flag this up.
I will add it.
Thanks !
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
2014-07-23 16:34 ` Ashwin Chaugule
@ 2014-07-23 17:32 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-23 17:32 UTC (permalink / raw)
To: Ashwin Chaugule
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Daniel Lezcano, linux-arm-kernel,
grant.likely, Charles Garcia-Tobin, Devicetree List,
Kevin Hilman, linux-pm, Sebastian Capella, Rob Herring,
Antti Miettinen, Paul Walmsley, Geoff Levand, Peter De Schrijver,
Stephen Boyd, Amit Kucheria
Hi Ashwin,
On Wed, Jul 23, 2014 at 05:34:16PM +0100, Ashwin Chaugule wrote:
> Hi Lorenzo,
>
> On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> > +/**
> > + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> > + * idle driver states array
> > + *
> > + * @drv: Pointer to CPU idle driver to be initialized
> > + * @start_idx: First idle state index to be initialized
> > + *
> > + * On success the states array in the cpuidle driver contains
> > + * initialized entries in the states array, starting from index start_idx.
> > + *
> > + * Return:
> > + * 0 on success
> > + * <0 on failure
> > + */
> > +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> > +{
> > + unsigned int i, state_idx = start_idx;
> > + struct cpuidle_state *idle_state;
> > + struct device_node *state_node, *cpu_node;
> > +
> > +
> > + if (state_idx >= CPUIDLE_STATE_MAX)
> > + return -EINVAL;
> > + /*
> > + * We get the idle states for the first logical cpu in the
> > + * driver mask. The kernel does not check idle states on all
> > + * cpus in the driver mask, they are assumed to be the same
> > + * by default.
> > + */
> > + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
>
> Is this an assumption for the short term? My understanding from the
> corresponding ACPI discussions is that the order of idle states may
> not necessarily be same for all CPUs, even for big.Little?
Well, it is more of a problem of the CPUidle infrastructure than related
to this specific patchset. The idle states for a specific cpumask (ie CPUidle
driver) are expected to be all the same, same order same data.
Current driver can be used on homegeneous ARM64 SMP systems, but I am fairly
confident we can extend it for big.LITTLE and also other funky SMP
configurations, the parsing code only expects all cpus in the mask
to have the same set of idle states (and so does the CPUidle core), if that's
not the case, the cpus belong in different CPUidle drivers (ie a CPUidle
driver is a set of states valid on a cpumask).
So my answer is yes, it is a proper assumption and not only for the
short term, but in general.
HTH,
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
@ 2014-07-23 17:32 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-07-23 17:32 UTC (permalink / raw)
To: linux-arm-kernel
Hi Ashwin,
On Wed, Jul 23, 2014 at 05:34:16PM +0100, Ashwin Chaugule wrote:
> Hi Lorenzo,
>
> On 21 July 2014 12:06, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
> > +/**
> > + * dt_init_idle_driver() - Parse the DT idle states and initialize the
> > + * idle driver states array
> > + *
> > + * @drv: Pointer to CPU idle driver to be initialized
> > + * @start_idx: First idle state index to be initialized
> > + *
> > + * On success the states array in the cpuidle driver contains
> > + * initialized entries in the states array, starting from index start_idx.
> > + *
> > + * Return:
> > + * 0 on success
> > + * <0 on failure
> > + */
> > +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
> > +{
> > + unsigned int i, state_idx = start_idx;
> > + struct cpuidle_state *idle_state;
> > + struct device_node *state_node, *cpu_node;
> > +
> > +
> > + if (state_idx >= CPUIDLE_STATE_MAX)
> > + return -EINVAL;
> > + /*
> > + * We get the idle states for the first logical cpu in the
> > + * driver mask. The kernel does not check idle states on all
> > + * cpus in the driver mask, they are assumed to be the same
> > + * by default.
> > + */
> > + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
>
> Is this an assumption for the short term? My understanding from the
> corresponding ACPI discussions is that the order of idle states may
> not necessarily be same for all CPUs, even for big.Little?
Well, it is more of a problem of the CPUidle infrastructure than related
to this specific patchset. The idle states for a specific cpumask (ie CPUidle
driver) are expected to be all the same, same order same data.
Current driver can be used on homegeneous ARM64 SMP systems, but I am fairly
confident we can extend it for big.LITTLE and also other funky SMP
configurations, the parsing code only expects all cpus in the mask
to have the same set of idle states (and so does the CPUidle core), if that's
not the case, the cpus belong in different CPUidle drivers (ie a CPUidle
driver is a set of states valid on a cpumask).
So my answer is yes, it is a proper assumption and not only for the
short term, but in general.
HTH,
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
2014-07-23 17:32 ` Lorenzo Pieralisi
@ 2014-07-23 19:08 ` Ashwin Chaugule
-1 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 19:08 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Catalin Marinas, Tomasz Figa, Chander Kashyap,
Vincent Guittot, Nicolas Pitre, Daniel Lezcano, linux-arm-kernel,
grant.likely, Charles Garcia-Tobin, Devicetree List,
Kevin Hilman, linux-pm, Sebastian Capella, Rob Herring,
Antti Miettinen, Paul Walmsley, Geoff Levand, Peter De Schrijver,
Stephen Boyd, Amit Kucheria
Hi Lorenzo,
On 23 July 2014 13:32, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
>> > +/**
>> > + * dt_init_idle_driver() - Parse the DT idle states and initialize the
>> > + * idle driver states array
>> > + *
>> > + * @drv: Pointer to CPU idle driver to be initialized
>> > + * @start_idx: First idle state index to be initialized
>> > + *
>> > + * On success the states array in the cpuidle driver contains
>> > + * initialized entries in the states array, starting from index start_idx.
>> > + *
>> > + * Return:
>> > + * 0 on success
>> > + * <0 on failure
>> > + */
>> > +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
>> > +{
>> > + unsigned int i, state_idx = start_idx;
>> > + struct cpuidle_state *idle_state;
>> > + struct device_node *state_node, *cpu_node;
>> > +
>> > +
>> > + if (state_idx >= CPUIDLE_STATE_MAX)
>> > + return -EINVAL;
>> > + /*
>> > + * We get the idle states for the first logical cpu in the
>> > + * driver mask. The kernel does not check idle states on all
>> > + * cpus in the driver mask, they are assumed to be the same
>> > + * by default.
>> > + */
>> > + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
>>
>> Is this an assumption for the short term? My understanding from the
>> corresponding ACPI discussions is that the order of idle states may
>> not necessarily be same for all CPUs, even for big.Little?
>
> Well, it is more of a problem of the CPUidle infrastructure than related
> to this specific patchset. The idle states for a specific cpumask (ie CPUidle
> driver) are expected to be all the same, same order same data.
>
> Current driver can be used on homegeneous ARM64 SMP systems, but I am fairly
> confident we can extend it for big.LITTLE and also other funky SMP
> configurations, the parsing code only expects all cpus in the mask
> to have the same set of idle states (and so does the CPUidle core), if that's
> not the case, the cpus belong in different CPUidle drivers (ie a CPUidle
> driver is a set of states valid on a cpumask).
>
> So my answer is yes, it is a proper assumption and not only for the
> short term, but in general.
>
> HTH,
> Lorenzo
Ok. Thanks for the explanation. I just had a look at
drivers/cpuidle/cpuidle-big_little.c. So, you'll need another call to
cpuidle_register() should there be another cpumask with a different
set of idle states.
Cheers,
Ashwin
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure
@ 2014-07-23 19:08 ` Ashwin Chaugule
0 siblings, 0 replies; 44+ messages in thread
From: Ashwin Chaugule @ 2014-07-23 19:08 UTC (permalink / raw)
To: linux-arm-kernel
Hi Lorenzo,
On 23 July 2014 13:32, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
>> > +/**
>> > + * dt_init_idle_driver() - Parse the DT idle states and initialize the
>> > + * idle driver states array
>> > + *
>> > + * @drv: Pointer to CPU idle driver to be initialized
>> > + * @start_idx: First idle state index to be initialized
>> > + *
>> > + * On success the states array in the cpuidle driver contains
>> > + * initialized entries in the states array, starting from index start_idx.
>> > + *
>> > + * Return:
>> > + * 0 on success
>> > + * <0 on failure
>> > + */
>> > +int dt_init_idle_driver(struct cpuidle_driver *drv, unsigned int start_idx)
>> > +{
>> > + unsigned int i, state_idx = start_idx;
>> > + struct cpuidle_state *idle_state;
>> > + struct device_node *state_node, *cpu_node;
>> > +
>> > +
>> > + if (state_idx >= CPUIDLE_STATE_MAX)
>> > + return -EINVAL;
>> > + /*
>> > + * We get the idle states for the first logical cpu in the
>> > + * driver mask. The kernel does not check idle states on all
>> > + * cpus in the driver mask, they are assumed to be the same
>> > + * by default.
>> > + */
>> > + cpu_node = of_cpu_device_node_get(cpumask_first(drv->cpumask));
>>
>> Is this an assumption for the short term? My understanding from the
>> corresponding ACPI discussions is that the order of idle states may
>> not necessarily be same for all CPUs, even for big.Little?
>
> Well, it is more of a problem of the CPUidle infrastructure than related
> to this specific patchset. The idle states for a specific cpumask (ie CPUidle
> driver) are expected to be all the same, same order same data.
>
> Current driver can be used on homegeneous ARM64 SMP systems, but I am fairly
> confident we can extend it for big.LITTLE and also other funky SMP
> configurations, the parsing code only expects all cpus in the mask
> to have the same set of idle states (and so does the CPUidle core), if that's
> not the case, the cpus belong in different CPUidle drivers (ie a CPUidle
> driver is a set of states valid on a cpumask).
>
> So my answer is yes, it is a proper assumption and not only for the
> short term, but in general.
>
> HTH,
> Lorenzo
Ok. Thanks for the explanation. I just had a look at
drivers/cpuidle/cpuidle-big_little.c. So, you'll need another call to
cpuidle_register() should there be another cpumask with a different
set of idle states.
Cheers,
Ashwin
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH v6 6/7] drivers: cpuidle: initialize big.LITTLE driver through DT
2014-07-23 16:26 ` Catalin Marinas
@ 2014-08-06 9:02 ` Lorenzo Pieralisi
-1 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-08-06 9:02 UTC (permalink / raw)
To: Catalin Marinas
Cc: Mark Rutland, Tomasz Figa, Chander Kashyap, Vincent Guittot,
Nicolas Pitre, Daniel Lezcano, linux-arm-kernel, grant.likely,
Charles Garcia-Tobin, devicetree, Kevin Hilman, linux-pm,
Sebastian Capella, Mark Brown, Antti Miettinen, Paul Walmsley,
Geoff Levand, Peter De Schrijver, Stephen Boyd, Amit Kucheria,
Bartlomi
On Wed, Jul 23, 2014 at 05:26:26PM +0100, Catalin Marinas wrote:
> On Mon, Jul 21, 2014 at 05:06:25PM +0100, Lorenzo Pieralisi wrote:
> > With the introduction of DT based idle states, CPUidle drivers for ARM
> > can now initialize idle states data through properties in the device tree.
> >
> > This patch adds code to the big.LITTLE CPUidle driver to dynamically
> > initialize idle states data through the updated device tree source file.
> >
> > Cc: Chander Kashyap <chander.kashyap@linaro.org>
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
> I think for this patch (and the exynos one) we should still allow the
> driver to work fine with old DT. Basically if the information is not in
> DT, fall back to the original static definitions.
Yes, this makes sense, I will implement the fall-back mechanism on v7,
that should be final. If in the meanwhile Samsung guys have time to
test the Exynos patch that would be very appreciated.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH v6 6/7] drivers: cpuidle: initialize big.LITTLE driver through DT
@ 2014-08-06 9:02 ` Lorenzo Pieralisi
0 siblings, 0 replies; 44+ messages in thread
From: Lorenzo Pieralisi @ 2014-08-06 9:02 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 23, 2014 at 05:26:26PM +0100, Catalin Marinas wrote:
> On Mon, Jul 21, 2014 at 05:06:25PM +0100, Lorenzo Pieralisi wrote:
> > With the introduction of DT based idle states, CPUidle drivers for ARM
> > can now initialize idle states data through properties in the device tree.
> >
> > This patch adds code to the big.LITTLE CPUidle driver to dynamically
> > initialize idle states data through the updated device tree source file.
> >
> > Cc: Chander Kashyap <chander.kashyap@linaro.org>
> > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
> I think for this patch (and the exynos one) we should still allow the
> driver to work fine with old DT. Basically if the information is not in
> DT, fall back to the original static definitions.
Yes, this makes sense, I will implement the fall-back mechanism on v7,
that should be final. If in the meanwhile Samsung guys have time to
test the Exynos patch that would be very appreciated.
Thanks,
Lorenzo
^ permalink raw reply [flat|nested] 44+ messages in thread
end of thread, other threads:[~2014-08-06 9:02 UTC | newest]
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2014-07-21 16:06 [PATCH v6 0/7] ARM generic idle states Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
2014-07-21 16:06 ` [PATCH v6 1/7] Documentation: arm: define DT idle states bindings Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
2014-07-21 22:40 ` Nicolas Pitre
2014-07-21 22:40 ` Nicolas Pitre
2014-07-22 12:38 ` Rob Herring
2014-07-22 12:38 ` Rob Herring
2014-07-23 15:52 ` Daniel Lezcano
2014-07-23 15:52 ` Daniel Lezcano
2014-07-21 16:06 ` [PATCH v6 2/7] drivers: cpuidle: implement DT based idle states infrastructure Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
2014-07-23 16:07 ` Daniel Lezcano
2014-07-23 16:07 ` Daniel Lezcano
2014-07-23 17:19 ` Lorenzo Pieralisi
2014-07-23 17:19 ` Lorenzo Pieralisi
2014-07-23 16:34 ` Ashwin Chaugule
2014-07-23 16:34 ` Ashwin Chaugule
2014-07-23 17:32 ` Lorenzo Pieralisi
2014-07-23 17:32 ` Lorenzo Pieralisi
2014-07-23 19:08 ` Ashwin Chaugule
2014-07-23 19:08 ` Ashwin Chaugule
2014-07-21 16:06 ` [PATCH v6 3/7] arm64: kernel: introduce cpu_init_idle CPU operation Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
2014-07-21 22:55 ` Stephen Boyd
2014-07-21 22:55 ` Stephen Boyd
2014-07-22 9:12 ` Lorenzo Pieralisi
2014-07-22 9:12 ` Lorenzo Pieralisi
[not found] ` <1405958786-17243-1-git-send-email-lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org>
2014-07-21 16:06 ` [PATCH v6 4/7] arm64: add PSCI CPU_SUSPEND based cpu_suspend support Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
2014-07-23 16:15 ` Ashwin Chaugule
2014-07-23 16:15 ` Ashwin Chaugule
2014-07-21 16:06 ` [PATCH v6 5/7] drivers: cpuidle: CPU idle ARM64 driver Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
2014-07-23 16:34 ` Ashwin Chaugule
2014-07-23 16:34 ` Ashwin Chaugule
2014-07-21 16:06 ` [PATCH v6 6/7] drivers: cpuidle: initialize big.LITTLE driver through DT Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
2014-07-23 16:26 ` Catalin Marinas
2014-07-23 16:26 ` Catalin Marinas
2014-08-06 9:02 ` Lorenzo Pieralisi
2014-08-06 9:02 ` Lorenzo Pieralisi
2014-07-21 16:06 ` [PATCH v6 7/7] drivers: cpuidle: initialize Exynos " Lorenzo Pieralisi
2014-07-21 16:06 ` Lorenzo Pieralisi
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