From: Evan Green <evan@rivosinc.com> To: Samuel Ortiz <sameo@rivosinc.com> Cc: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, linux-riscv@lists.infradead.org, "Hongren (Zenithal) Zheng" <i@zenithal.me>, linux@rivosinc.com, "Conor Dooley" <conor.dooley@microchip.com>, "Andrew Jones" <ajones@ventanamicro.com>, "Heiko Stuebner" <heiko.stuebner@vrull.eu>, "Anup Patel" <apatel@ventanamicro.com>, linux-kernel@vger.kernel.org, "Guo Ren" <guoren@kernel.org>, "Atish Patra" <atishp@rivosinc.com>, "Björn Töpel" <bjorn@rivosinc.com>, "Jiatai He" <jiatai2021@iscas.ac.cn> Subject: Re: [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT Date: Tue, 27 Jun 2023 11:14:30 -0700 [thread overview] Message-ID: <CALs-HssMkVikspnEi-Ek2t=ABvFvgptAhsBjk1+aLuVjiP7P7w@mail.gmail.com> (raw) In-Reply-To: <20230627143747.1599218-2-sameo@rivosinc.com> On Tue, Jun 27, 2023 at 7:38 AM Samuel Ortiz <sameo@rivosinc.com> wrote: > > From: "Hongren (Zenithal) Zheng" <i@zenithal.me> > > This patch parses Zb/Zk related string from DT and > output them in cpuinfo > > One thing worth noting is that if DT provides zk, > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > Note that zk is a valid extension name and the current > DT binding spec allows this. > > This patch also changes the logical id of > existing multi-letter extensions and adds a statement > that instead of logical id compatibility, the order > is needed. > > There currently lacks a mechanism to merge them when > producing cpuinfo. Namely if you provide a riscv,isa > "rv64imafdc_zk_zks", the cpuinfo output would be > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > _zksh_zkt" > > Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > --- > arch/riscv/include/asm/hwcap.h | 11 +++++++++++ > arch/riscv/kernel/cpu.c | 11 +++++++++++ > arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ > 3 files changed, 52 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index f041bfa7f6a0..b80ca6e77088 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -53,6 +53,17 @@ > #define RISCV_ISA_EXT_ZICSR 40 > #define RISCV_ISA_EXT_ZIFENCEI 41 > #define RISCV_ISA_EXT_ZIHPM 42 > +#define RISCV_ISA_EXT_ZBC 43 > +#define RISCV_ISA_EXT_ZBKB 44 > +#define RISCV_ISA_EXT_ZBKC 45 > +#define RISCV_ISA_EXT_ZBKX 46 > +#define RISCV_ISA_EXT_ZKND 47 > +#define RISCV_ISA_EXT_ZKNE 48 > +#define RISCV_ISA_EXT_ZKNH 49 > +#define RISCV_ISA_EXT_ZKR 50 > +#define RISCV_ISA_EXT_ZKSED 51 > +#define RISCV_ISA_EXT_ZKSH 52 > +#define RISCV_ISA_EXT_ZKT 53 > > #define RISCV_ISA_EXT_MAX 64 > #define RISCV_ISA_EXT_NAME_LEN_MAX 32 > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index a2fc952318e9..10524322a4c0 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -215,7 +215,18 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), > + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), > + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), > __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), > + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), > + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), > + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), > + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), > + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), > + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index bdcf460ea53d..447f853a5a4c 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -309,10 +309,40 @@ void __init riscv_fill_hwcap(void) > SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); > SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); > SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); > + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC); > SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); > + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zbks", RISCV_ISA_EXT_ZBKX); Should "zbks" be "zbkx"? > SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); > SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); > SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED); > + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH); > + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR); > + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKX); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKND); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNE); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNH); > + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND); > + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE); > + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKX); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSED); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSH); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKX); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKND); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNE); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNH); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKR); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKT); It would be nice to consolidate the ones together that search for a single string and set multiple bits, though I don't have any super elegant ideas for how off the top of my head.
WARNING: multiple messages have this Message-ID (diff)
From: Evan Green <evan@rivosinc.com> To: Samuel Ortiz <sameo@rivosinc.com> Cc: "Paul Walmsley" <paul.walmsley@sifive.com>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, linux-riscv@lists.infradead.org, "Hongren (Zenithal) Zheng" <i@zenithal.me>, linux@rivosinc.com, "Conor Dooley" <conor.dooley@microchip.com>, "Andrew Jones" <ajones@ventanamicro.com>, "Heiko Stuebner" <heiko.stuebner@vrull.eu>, "Anup Patel" <apatel@ventanamicro.com>, linux-kernel@vger.kernel.org, "Guo Ren" <guoren@kernel.org>, "Atish Patra" <atishp@rivosinc.com>, "Björn Töpel" <bjorn@rivosinc.com>, "Jiatai He" <jiatai2021@iscas.ac.cn> Subject: Re: [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT Date: Tue, 27 Jun 2023 11:14:30 -0700 [thread overview] Message-ID: <CALs-HssMkVikspnEi-Ek2t=ABvFvgptAhsBjk1+aLuVjiP7P7w@mail.gmail.com> (raw) In-Reply-To: <20230627143747.1599218-2-sameo@rivosinc.com> On Tue, Jun 27, 2023 at 7:38 AM Samuel Ortiz <sameo@rivosinc.com> wrote: > > From: "Hongren (Zenithal) Zheng" <i@zenithal.me> > > This patch parses Zb/Zk related string from DT and > output them in cpuinfo > > One thing worth noting is that if DT provides zk, > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > Note that zk is a valid extension name and the current > DT binding spec allows this. > > This patch also changes the logical id of > existing multi-letter extensions and adds a statement > that instead of logical id compatibility, the order > is needed. > > There currently lacks a mechanism to merge them when > producing cpuinfo. Namely if you provide a riscv,isa > "rv64imafdc_zk_zks", the cpuinfo output would be > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > _zksh_zkt" > > Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > --- > arch/riscv/include/asm/hwcap.h | 11 +++++++++++ > arch/riscv/kernel/cpu.c | 11 +++++++++++ > arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ > 3 files changed, 52 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index f041bfa7f6a0..b80ca6e77088 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -53,6 +53,17 @@ > #define RISCV_ISA_EXT_ZICSR 40 > #define RISCV_ISA_EXT_ZIFENCEI 41 > #define RISCV_ISA_EXT_ZIHPM 42 > +#define RISCV_ISA_EXT_ZBC 43 > +#define RISCV_ISA_EXT_ZBKB 44 > +#define RISCV_ISA_EXT_ZBKC 45 > +#define RISCV_ISA_EXT_ZBKX 46 > +#define RISCV_ISA_EXT_ZKND 47 > +#define RISCV_ISA_EXT_ZKNE 48 > +#define RISCV_ISA_EXT_ZKNH 49 > +#define RISCV_ISA_EXT_ZKR 50 > +#define RISCV_ISA_EXT_ZKSED 51 > +#define RISCV_ISA_EXT_ZKSH 52 > +#define RISCV_ISA_EXT_ZKT 53 > > #define RISCV_ISA_EXT_MAX 64 > #define RISCV_ISA_EXT_NAME_LEN_MAX 32 > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index a2fc952318e9..10524322a4c0 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -215,7 +215,18 @@ static struct riscv_isa_ext_data isa_ext_arr[] = { > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), > + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), > + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), > __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), > + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), > + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), > + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), > + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), > + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), > + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index bdcf460ea53d..447f853a5a4c 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -309,10 +309,40 @@ void __init riscv_fill_hwcap(void) > SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); > SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA); > SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); > + SET_ISA_EXT_MAP("zbc", RISCV_ISA_EXT_ZBC); > SET_ISA_EXT_MAP("zbs", RISCV_ISA_EXT_ZBS); > + SET_ISA_EXT_MAP("zbkb", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zbkc", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zbks", RISCV_ISA_EXT_ZBKX); Should "zbks" be "zbkx"? > SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); > SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); > SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > + SET_ISA_EXT_MAP("zksed", RISCV_ISA_EXT_ZKSED); > + SET_ISA_EXT_MAP("zksh", RISCV_ISA_EXT_ZKSH); > + SET_ISA_EXT_MAP("zkr", RISCV_ISA_EXT_ZKR); > + SET_ISA_EXT_MAP("zkt", RISCV_ISA_EXT_ZKT); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZBKX); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKND); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNE); > + SET_ISA_EXT_MAP("zkn", RISCV_ISA_EXT_ZKNH); > + SET_ISA_EXT_MAP("zknd", RISCV_ISA_EXT_ZKND); > + SET_ISA_EXT_MAP("zkne", RISCV_ISA_EXT_ZKNE); > + SET_ISA_EXT_MAP("zknh", RISCV_ISA_EXT_ZKNH); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZBKX); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSED); > + SET_ISA_EXT_MAP("zks", RISCV_ISA_EXT_ZKSH); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKB); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKC); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZBKX); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKND); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNE); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKNH); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKR); > + SET_ISA_EXT_MAP("zk", RISCV_ISA_EXT_ZKT); It would be nice to consolidate the ones together that search for a single string and set multiple bits, though I don't have any super elegant ideas for how off the top of my head. _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-06-27 18:16 UTC|newest] Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-06-27 14:37 [PATCH 0/3] RISC-V: archrandom support Samuel Ortiz 2023-06-27 14:37 ` Samuel Ortiz 2023-06-27 14:37 ` [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT Samuel Ortiz 2023-06-27 14:37 ` Samuel Ortiz 2023-06-27 18:14 ` Evan Green [this message] 2023-06-27 18:14 ` Evan Green 2023-06-27 18:44 ` Hongren (Zenithal) Zheng 2023-06-27 18:44 ` Hongren (Zenithal) Zheng 2023-06-27 18:48 ` Conor Dooley 2023-06-27 18:48 ` Conor Dooley 2023-06-27 19:03 ` Hongren (Zenithal) Zheng 2023-06-27 19:03 ` Hongren (Zenithal) Zheng 2023-06-27 19:18 ` Conor Dooley 2023-06-27 19:18 ` Conor Dooley 2023-06-28 9:59 ` Samuel Ortiz 2023-06-28 9:59 ` Samuel Ortiz 2023-06-28 10:01 ` Samuel Ortiz 2023-06-28 10:01 ` Samuel Ortiz 2023-06-28 11:10 ` Conor Dooley 2023-06-28 11:10 ` Conor Dooley 2023-06-28 12:30 ` Samuel Ortiz 2023-06-28 12:30 ` Samuel Ortiz 2023-06-28 16:49 ` Conor Dooley 2023-06-28 16:49 ` Conor Dooley 2023-06-28 17:18 ` Evan Green 2023-06-28 17:18 ` Evan Green 2023-06-28 17:24 ` Conor Dooley 2023-06-28 17:24 ` Conor Dooley 2023-07-03 17:39 ` Conor Dooley 2023-07-03 17:39 ` Conor Dooley 2023-06-28 11:21 ` Markus Elfring 2023-06-28 12:29 ` Samuel Ortiz 2023-06-28 12:29 ` Samuel Ortiz 2023-06-27 14:37 ` [PATCH 2/3] RISC-V: hwprobe: Expose Zbc and the scalar crypto extensions Samuel Ortiz 2023-06-27 14:37 ` Samuel Ortiz 2023-06-27 18:13 ` Evan Green 2023-06-27 18:13 ` Evan Green 2023-06-28 0:34 ` Stefan O'Rear 2023-06-28 0:34 ` Stefan O'Rear 2023-06-28 10:04 ` Samuel Ortiz 2023-06-28 10:04 ` Samuel Ortiz 2023-06-28 13:25 ` Stefan O'Rear 2023-06-28 13:25 ` Stefan O'Rear 2023-07-10 7:59 ` Samuel Ortiz 2023-07-10 7:59 ` Samuel Ortiz 2023-07-12 5:54 ` Stefan O'Rear 2023-07-12 5:54 ` Stefan O'Rear 2023-06-27 14:37 ` [PATCH 3/3] RISC-V: Implement archrandom when Zkr is available Samuel Ortiz 2023-06-27 14:37 ` Samuel Ortiz 2023-06-27 19:09 ` Conor Dooley 2023-06-27 19:09 ` Conor Dooley 2023-06-28 12:28 ` Samuel Ortiz 2023-06-28 12:28 ` Samuel Ortiz 2023-06-28 1:00 ` Stefan O'Rear 2023-06-28 1:00 ` Stefan O'Rear -- strict thread matches above, loose matches on Subject: below -- 2022-04-30 13:48 [PATCH 0/3] RISC-V: Add Bitmanip/Scalar Crypto HWCAP Hongren (Zenithal) Zheng 2022-04-30 13:50 ` [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT Hongren (Zenithal) Zheng 2022-04-30 13:50 ` Hongren (Zenithal) Zheng 2022-05-03 23:21 ` Heiko Stuebner 2022-05-03 23:21 ` Heiko Stuebner 2022-05-04 2:39 ` Hongren (Zenithal) Zheng 2022-05-04 2:39 ` Hongren (Zenithal) Zheng
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