[PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[c.tirumalesh-Re5JQEeQqe8AvxtiuMwx3w]

From: Tirumalesh Chalamarla <tchalamarla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>

This patch modifes output_mask calculation logic for stage 1 and allow
max possible value supported by SMMU implementaions for translations,
where stage 2 is bypassed.

Erlier it is not possible to access full supported PA address with stage 1,
even if it is supported by SMMU and stage 2 is bypass.

Signed-off-by: Tirumalesh Chalamarla <tchalamarla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
---
 drivers/iommu/arm-smmu.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a6b00bd..56cf42d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -707,6 +707,17 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 	struct arm_smmu_device *smmu = smmu_domain->smmu;
 	void __iomem *cb_base, *gr0_base, *gr1_base;
+	unsigned long s1_out_size;
+
+	if (cfg->cbar == CBAR_TYPE_S1_TRANS_S2_BYPASS) {
+		s1_out_size = smmu->s1_output_size;
+	} else {
+#ifdef CONFIG_64BIT
+		s1_out_size = min((unsigned long)VA_BITS, smmu->s1_output_size);
+#else
+		s1_out_size = min(32UL, smmu->s1_output_size);
+#endif
+	}
 
 	gr0_base = ARM_SMMU_GR0(smmu);
 	gr1_base = ARM_SMMU_GR1(smmu);
@@ -762,7 +773,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 			break;
 		}
 
-		switch (smmu->s1_output_size) {
+		switch (s1_out_size) {
 		case 32:
 			reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 			break;
@@ -808,7 +819,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 			reg = TTBCR_TG0_64K;
 
 		if (!stage1) {
-			reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
+			reg |= (64 - s1_out_size) << TTBCR_T0SZ_SHIFT;
 
 			switch (smmu->s2_output_size) {
 			case 32:
@@ -1411,9 +1422,17 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
 	if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
 		stage = 2;
 		output_mask = (1ULL << smmu->s2_output_size) - 1;
-	} else {
+	} else if (cfg->cbar == CBAR_TYPE_S1_TRANS_S2_BYPASS) {
 		stage = 1;
 		output_mask = (1ULL << smmu->s1_output_size) - 1;
+	} else {
+		stage = 1;
+#ifdef CONFIG_64BIT
+		output_mask = (1ULL << min((unsigned long)VA_BITS,
+					smmu->s1_output_size)) - 1;
+#else
+		output_mask = (1ULL << min(32UL, smmu->s1_output_size)) - 1;
+#endif
 	}
 
 	if (!pgd)
@@ -1777,11 +1796,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
 	 * Stage-1 output limited by stage-2 input size due to pgd
 	 * allocation (PTRS_PER_PGD).
 	 */
-#ifdef CONFIG_64BIT
-	smmu->s1_output_size = min((unsigned long)VA_BITS, size);
-#else
-	smmu->s1_output_size = min(32UL, size);
-#endif
+	smmu->s1_output_size = size;
 
 	/* The stage-2 output mask is also applied for bypass */
 	size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
-- 
1.9.3

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[PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[c.tirumalesh at gmail.com]

From: Tirumalesh Chalamarla <tchalamarla@cavium.com>

This patch modifes output_mask calculation logic for stage 1 and allow
max possible value supported by SMMU implementaions for translations,
where stage 2 is bypassed.

Erlier it is not possible to access full supported PA address with stage 1,
even if it is supported by SMMU and stage 2 is bypass.

Signed-off-by: Tirumalesh Chalamarla <tchalamarla@cavium.com>
---
 drivers/iommu/arm-smmu.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a6b00bd..56cf42d 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -707,6 +707,17 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
 	struct arm_smmu_device *smmu = smmu_domain->smmu;
 	void __iomem *cb_base, *gr0_base, *gr1_base;
+	unsigned long s1_out_size;
+
+	if (cfg->cbar == CBAR_TYPE_S1_TRANS_S2_BYPASS) {
+		s1_out_size = smmu->s1_output_size;
+	} else {
+#ifdef CONFIG_64BIT
+		s1_out_size = min((unsigned long)VA_BITS, smmu->s1_output_size);
+#else
+		s1_out_size = min(32UL, smmu->s1_output_size);
+#endif
+	}
 
 	gr0_base = ARM_SMMU_GR0(smmu);
 	gr1_base = ARM_SMMU_GR1(smmu);
@@ -762,7 +773,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 			break;
 		}
 
-		switch (smmu->s1_output_size) {
+		switch (s1_out_size) {
 		case 32:
 			reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
 			break;
@@ -808,7 +819,7 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 			reg = TTBCR_TG0_64K;
 
 		if (!stage1) {
-			reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
+			reg |= (64 - s1_out_size) << TTBCR_T0SZ_SHIFT;
 
 			switch (smmu->s2_output_size) {
 			case 32:
@@ -1411,9 +1422,17 @@ static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
 	if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
 		stage = 2;
 		output_mask = (1ULL << smmu->s2_output_size) - 1;
-	} else {
+	} else if (cfg->cbar == CBAR_TYPE_S1_TRANS_S2_BYPASS) {
 		stage = 1;
 		output_mask = (1ULL << smmu->s1_output_size) - 1;
+	} else {
+		stage = 1;
+#ifdef CONFIG_64BIT
+		output_mask = (1ULL << min((unsigned long)VA_BITS,
+					smmu->s1_output_size)) - 1;
+#else
+		output_mask = (1ULL << min(32UL, smmu->s1_output_size)) - 1;
+#endif
 	}
 
 	if (!pgd)
@@ -1777,11 +1796,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
 	 * Stage-1 output limited by stage-2 input size due to pgd
 	 * allocation (PTRS_PER_PGD).
 	 */
-#ifdef CONFIG_64BIT
-	smmu->s1_output_size = min((unsigned long)VA_BITS, size);
-#else
-	smmu->s1_output_size = min(32UL, size);
-#endif
+	smmu->s1_output_size = size;
 
 	/* The stage-2 output mask is also applied for bypass */
 	size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
-- 
1.9.3

Re: [PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[Will Deacon]

Hi Tirumalesh,

On Wed, Aug 27, 2014 at 07:02:21PM +0100, c.tirumalesh-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
> From: Tirumalesh Chalamarla <tchalamarla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> 
> This patch modifes output_mask calculation logic for stage 1 and allow
> max possible value supported by SMMU implementaions for translations,
> where stage 2 is bypassed.
> 
> Erlier it is not possible to access full supported PA address with stage 1,
> even if it is supported by SMMU and stage 2 is bypass.

I'm trying to understand what you're getting at here. Essentially, you want
to use the full stage-1 output range for a stage-1 only MMU, right?

The code is currently structured to truncate that to the stage-2 input size
for nested translation. However, I think that's better solved by faking the
ID registers in the virtual SMMU instead of posing these restrictions on the
host as well.

Assuming I understand the problem correctly, why not simply remove the
truncation from the existing code (untested patch below)? Does that not
work for you?

Will

--->8

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 2b1271658bfa..a02d05793a73 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1917,21 +1917,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
        /* ID2 */
        id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
        size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
-
-       /*
-        * Stage-1 output limited by stage-2 input size due to pgd
-        * allocation (PTRS_PER_PGD).
-        */
-       if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
-#ifdef CONFIG_64BIT
-               smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
-#else
-               smmu->s1_output_size = min(32UL, size);
-#endif
-       } else {
-               smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
-                                            size);
-       }
+       smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
 
        /* The stage-2 output mask is also applied for bypass */
        size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);

[PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[Will Deacon]

Hi Tirumalesh,

On Wed, Aug 27, 2014 at 07:02:21PM +0100, c.tirumalesh at gmail.com wrote:
> From: Tirumalesh Chalamarla <tchalamarla@cavium.com>
> 
> This patch modifes output_mask calculation logic for stage 1 and allow
> max possible value supported by SMMU implementaions for translations,
> where stage 2 is bypassed.
> 
> Erlier it is not possible to access full supported PA address with stage 1,
> even if it is supported by SMMU and stage 2 is bypass.

I'm trying to understand what you're getting at here. Essentially, you want
to use the full stage-1 output range for a stage-1 only MMU, right?

The code is currently structured to truncate that to the stage-2 input size
for nested translation. However, I think that's better solved by faking the
ID registers in the virtual SMMU instead of posing these restrictions on the
host as well.

Assuming I understand the problem correctly, why not simply remove the
truncation from the existing code (untested patch below)? Does that not
work for you?

Will

--->8

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 2b1271658bfa..a02d05793a73 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -1917,21 +1917,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
        /* ID2 */
        id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
        size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
-
-       /*
-        * Stage-1 output limited by stage-2 input size due to pgd
-        * allocation (PTRS_PER_PGD).
-        */
-       if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
-#ifdef CONFIG_64BIT
-               smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
-#else
-               smmu->s1_output_size = min(32UL, size);
-#endif
-       } else {
-               smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
-                                            size);
-       }
+       smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
 
        /* The stage-2 output mask is also applied for bypass */
        size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);

Re: [PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[tirumalesh chalamarla]

Hi Will,


On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:
> Hi Tirumalesh,
>
> On Wed, Aug 27, 2014 at 07:02:21PM +0100, c.tirumalesh-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:
>> From: Tirumalesh Chalamarla <tchalamarla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
>>
>> This patch modifes output_mask calculation logic for stage 1 and allow
>> max possible value supported by SMMU implementaions for translations,
>> where stage 2 is bypassed.
>>
>> Erlier it is not possible to access full supported PA address with stage 1,
>> even if it is supported by SMMU and stage 2 is bypass.
>
> I'm trying to understand what you're getting at here. Essentially, you want
> to use the full stage-1 output range for a stage-1 only MMU, right?
>

YES,  restrict stage 1 out put to VA_BITS only if stage 2 is needed
(i.e for NESTED_TRANSLATIONS).

> The code is currently structured to truncate that to the stage-2 input size
> for nested translation. However, I think that's better solved by faking the
> ID registers in the virtual SMMU instead of posing these restrictions on the
> host as well.
>

This sounds good, the only problem is, it is too much bound to virtual
SMMU. There is no harm in changing/checking the
stage 1 output mask, if stage 2 present, in host also.


> Assuming I understand the problem correctly, why not simply remove the
> truncation from the existing code (untested patch below)? Does that not
> work for you?
>

This will not restrict stage 1 out put to VA_BITS, even for two level
translations. this results in non debuggable problems
if we configure incorrectly.  there is no harm in checking the
condition for nested translations, as i did in my patch.


Regards,
Tirumalesh.

> Will
>
> --->8
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 2b1271658bfa..a02d05793a73 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -1917,21 +1917,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
>         /* ID2 */
>         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
>         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
> -
> -       /*
> -        * Stage-1 output limited by stage-2 input size due to pgd
> -        * allocation (PTRS_PER_PGD).
> -        */
> -       if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
> -#ifdef CONFIG_64BIT
> -               smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
> -#else
> -               smmu->s1_output_size = min(32UL, size);
> -#endif
> -       } else {
> -               smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
> -                                            size);
> -       }
> +       smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
>
>         /* The stage-2 output mask is also applied for bypass */
>         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
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[PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[tirumalesh chalamarla]

Hi Will,


On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon@arm.com> wrote:
> Hi Tirumalesh,
>
> On Wed, Aug 27, 2014 at 07:02:21PM +0100, c.tirumalesh at gmail.com wrote:
>> From: Tirumalesh Chalamarla <tchalamarla@cavium.com>
>>
>> This patch modifes output_mask calculation logic for stage 1 and allow
>> max possible value supported by SMMU implementaions for translations,
>> where stage 2 is bypassed.
>>
>> Erlier it is not possible to access full supported PA address with stage 1,
>> even if it is supported by SMMU and stage 2 is bypass.
>
> I'm trying to understand what you're getting at here. Essentially, you want
> to use the full stage-1 output range for a stage-1 only MMU, right?
>

YES,  restrict stage 1 out put to VA_BITS only if stage 2 is needed
(i.e for NESTED_TRANSLATIONS).

> The code is currently structured to truncate that to the stage-2 input size
> for nested translation. However, I think that's better solved by faking the
> ID registers in the virtual SMMU instead of posing these restrictions on the
> host as well.
>

This sounds good, the only problem is, it is too much bound to virtual
SMMU. There is no harm in changing/checking the
stage 1 output mask, if stage 2 present, in host also.


> Assuming I understand the problem correctly, why not simply remove the
> truncation from the existing code (untested patch below)? Does that not
> work for you?
>

This will not restrict stage 1 out put to VA_BITS, even for two level
translations. this results in non debuggable problems
if we configure incorrectly.  there is no harm in checking the
condition for nested translations, as i did in my patch.


Regards,
Tirumalesh.

> Will
>
> --->8
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 2b1271658bfa..a02d05793a73 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -1917,21 +1917,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
>         /* ID2 */
>         id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
>         size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
> -
> -       /*
> -        * Stage-1 output limited by stage-2 input size due to pgd
> -        * allocation (PTRS_PER_PGD).
> -        */
> -       if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
> -#ifdef CONFIG_64BIT
> -               smmu->s1_output_size = min_t(unsigned long, VA_BITS, size);
> -#else
> -               smmu->s1_output_size = min(32UL, size);
> -#endif
> -       } else {
> -               smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT,
> -                                            size);
> -       }
> +       smmu->s1_output_size = min_t(unsigned long, PHYS_MASK_SHIFT, size);
>
>         /* The stage-2 output mask is also applied for bypass */
>         size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);

Re: [PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[Will Deacon]

On Mon, Sep 01, 2014 at 02:49:58PM +0100, tirumalesh chalamarla wrote:
> On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:
> > Assuming I understand the problem correctly, why not simply remove the
> > truncation from the existing code (untested patch below)? Does that not
> > work for you?
> >
> 
> This will not restrict stage 1 out put to VA_BITS, even for two level
> translations. this results in non debuggable problems
> if we configure incorrectly.  there is no harm in checking the
> condition for nested translations, as i did in my patch.

Right, but restricting stage-1 output to VA_BITS doesn't make sense;
remember it's not the same kernel writing the stage-1 and stage-2 tables.

Will

[PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[Will Deacon]

On Mon, Sep 01, 2014 at 02:49:58PM +0100, tirumalesh chalamarla wrote:
> On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon@arm.com> wrote:
> > Assuming I understand the problem correctly, why not simply remove the
> > truncation from the existing code (untested patch below)? Does that not
> > work for you?
> >
> 
> This will not restrict stage 1 out put to VA_BITS, even for two level
> translations. this results in non debuggable problems
> if we configure incorrectly.  there is no harm in checking the
> condition for nested translations, as i did in my patch.

Right, but restricting stage-1 output to VA_BITS doesn't make sense;
remember it's not the same kernel writing the stage-1 and stage-2 tables.

Will

Re: [PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[tirumalesh chalamarla]

On Mon, Sep 1, 2014 at 8:12 AM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:
> On Mon, Sep 01, 2014 at 02:49:58PM +0100, tirumalesh chalamarla wrote:
>> On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:
>> > Assuming I understand the problem correctly, why not simply remove the
>> > truncation from the existing code (untested patch below)? Does that not
>> > work for you?
>> >
>>
>> This will not restrict stage 1 out put to VA_BITS, even for two level
>> translations. this results in non debuggable problems
>> if we configure incorrectly.  there is no harm in checking the
>> condition for nested translations, as i did in my patch.
>
> Right, but restricting stage-1 output to VA_BITS doesn't make sense;
> remember it's not the same kernel writing the stage-1 and stage-2 tables.
>

Yes, if we restrict driver by limiting either one and removing NESTED
altogether, i don't have a problem with this approach.

Regards,
Tirumalesh.

> Will

[PATCH] iommu/arm-smmu: Allow size of stage 1 output to max possible value for sateg 2 bypass

[tirumalesh chalamarla]

On Mon, Sep 1, 2014 at 8:12 AM, Will Deacon <will.deacon@arm.com> wrote:
> On Mon, Sep 01, 2014 at 02:49:58PM +0100, tirumalesh chalamarla wrote:
>> On Mon, Sep 1, 2014 at 4:42 AM, Will Deacon <will.deacon@arm.com> wrote:
>> > Assuming I understand the problem correctly, why not simply remove the
>> > truncation from the existing code (untested patch below)? Does that not
>> > work for you?
>> >
>>
>> This will not restrict stage 1 out put to VA_BITS, even for two level
>> translations. this results in non debuggable problems
>> if we configure incorrectly.  there is no harm in checking the
>> condition for nested translations, as i did in my patch.
>
> Right, but restricting stage-1 output to VA_BITS doesn't make sense;
> remember it's not the same kernel writing the stage-1 and stage-2 tables.
>

Yes, if we restrict driver by limiting either one and removing NESTED
altogether, i don't have a problem with this approach.

Regards,
Tirumalesh.

> Will